inst_queue.hh revision 8229
114184Sgabeblack@google.com/*
214184Sgabeblack@google.com * Copyright (c) 2011 ARM Limited
314184Sgabeblack@google.com * All rights reserved.
414184Sgabeblack@google.com *
514184Sgabeblack@google.com * The license below extends only to copyright in the software and shall
614184Sgabeblack@google.com * not be construed as granting a license to any other intellectual
714184Sgabeblack@google.com * property including but not limited to intellectual property relating
814184Sgabeblack@google.com * to a hardware implementation of the functionality of the software
914184Sgabeblack@google.com * licensed hereunder.  You may use the software subject to the license
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1114184Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software,
1214184Sgabeblack@google.com * modified or unmodified, in source code or in binary form.
1314184Sgabeblack@google.com *
1414184Sgabeblack@google.com * Copyright (c) 2004-2006 The Regents of The University of Michigan
1514184Sgabeblack@google.com * All rights reserved.
1614184Sgabeblack@google.com *
1714184Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without
1814184Sgabeblack@google.com * modification, are permitted provided that the following conditions are
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2014184Sgabeblack@google.com * notice, this list of conditions and the following disclaimer;
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2214184Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the
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2514184Sgabeblack@google.com * contributors may be used to endorse or promote products derived from
2614184Sgabeblack@google.com * this software without specific prior written permission.
2714184Sgabeblack@google.com *
2814184Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2914184Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3014184Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
3114184Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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3714184Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3814184Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3914184Sgabeblack@google.com *
4014184Sgabeblack@google.com * Authors: Kevin Lim
4114184Sgabeblack@google.com */
4214184Sgabeblack@google.com
4314184Sgabeblack@google.com#ifndef __CPU_O3_INST_QUEUE_HH__
4414184Sgabeblack@google.com#define __CPU_O3_INST_QUEUE_HH__
4514184Sgabeblack@google.com
4614184Sgabeblack@google.com#include <list>
4714184Sgabeblack@google.com#include <map>
4814184Sgabeblack@google.com#include <queue>
4914184Sgabeblack@google.com#include <vector>
5014184Sgabeblack@google.com
5114184Sgabeblack@google.com#include "base/statistics.hh"
5214184Sgabeblack@google.com#include "base/types.hh"
5314184Sgabeblack@google.com#include "cpu/o3/dep_graph.hh"
5414184Sgabeblack@google.com#include "cpu/inst_seq.hh"
5514184Sgabeblack@google.com#include "cpu/op_class.hh"
5614184Sgabeblack@google.com#include "cpu/timebuf.hh"
5714184Sgabeblack@google.com#include "sim/eventq.hh"
5814184Sgabeblack@google.com
5914184Sgabeblack@google.comclass DerivO3CPUParams;
6014184Sgabeblack@google.comclass FUPool;
6114184Sgabeblack@google.comclass MemInterface;
6214184Sgabeblack@google.com
6314184Sgabeblack@google.com/**
6414184Sgabeblack@google.com * A standard instruction queue class.  It holds ready instructions, in
6514184Sgabeblack@google.com * order, in seperate priority queues to facilitate the scheduling of
6614184Sgabeblack@google.com * instructions.  The IQ uses a separate linked list to track dependencies.
6714184Sgabeblack@google.com * Similar to the rename map and the free list, it expects that
6814184Sgabeblack@google.com * floating point registers have their indices start after the integer
6914184Sgabeblack@google.com * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
7014184Sgabeblack@google.com * and 96-191 are fp).  This remains true even for both logical and
7114184Sgabeblack@google.com * physical register indices. The IQ depends on the memory dependence unit to
7214184Sgabeblack@google.com * track when memory operations are ready in terms of ordering; register
7314184Sgabeblack@google.com * dependencies are tracked normally. Right now the IQ also handles the
7414184Sgabeblack@google.com * execution timing; this is mainly to allow back-to-back scheduling without
7514184Sgabeblack@google.com * requiring IEW to be able to peek into the IQ. At the end of the execution
7614184Sgabeblack@google.com * latency, the instruction is put into the queue to execute, where it will
7714184Sgabeblack@google.com * have the execute() function called on it.
7814184Sgabeblack@google.com * @todo: Make IQ able to handle multiple FU pools.
7914184Sgabeblack@google.com */
8014184Sgabeblack@google.comtemplate <class Impl>
8114184Sgabeblack@google.comclass InstructionQueue
8214184Sgabeblack@google.com{
8314184Sgabeblack@google.com  public:
8414184Sgabeblack@google.com    //Typedefs from the Impl.
8514184Sgabeblack@google.com    typedef typename Impl::O3CPU O3CPU;
8614184Sgabeblack@google.com    typedef typename Impl::DynInstPtr DynInstPtr;
8714184Sgabeblack@google.com
8814184Sgabeblack@google.com    typedef typename Impl::CPUPol::IEW IEW;
8914184Sgabeblack@google.com    typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
9014184Sgabeblack@google.com    typedef typename Impl::CPUPol::IssueStruct IssueStruct;
9114184Sgabeblack@google.com    typedef typename Impl::CPUPol::TimeStruct TimeStruct;
9214184Sgabeblack@google.com
9314184Sgabeblack@google.com    // Typedef of iterator through the list of instructions.
9414184Sgabeblack@google.com    typedef typename std::list<DynInstPtr>::iterator ListIt;
9514184Sgabeblack@google.com
9614184Sgabeblack@google.com    friend class Impl::O3CPU;
9714184Sgabeblack@google.com
9814184Sgabeblack@google.com    /** FU completion event class. */
9914184Sgabeblack@google.com    class FUCompletion : public Event {
10014184Sgabeblack@google.com      private:
10114184Sgabeblack@google.com        /** Executing instruction. */
10214184Sgabeblack@google.com        DynInstPtr inst;
10314184Sgabeblack@google.com
10414184Sgabeblack@google.com        /** Index of the FU used for executing. */
10514184Sgabeblack@google.com        int fuIdx;
10614184Sgabeblack@google.com
10714184Sgabeblack@google.com        /** Pointer back to the instruction queue. */
10814184Sgabeblack@google.com        InstructionQueue<Impl> *iqPtr;
10914184Sgabeblack@google.com
11014184Sgabeblack@google.com        /** Should the FU be added to the list to be freed upon
11114184Sgabeblack@google.com         * completing this event.
11214184Sgabeblack@google.com         */
11314184Sgabeblack@google.com        bool freeFU;
11414184Sgabeblack@google.com
11514184Sgabeblack@google.com      public:
11614184Sgabeblack@google.com        /** Construct a FU completion event. */
11714184Sgabeblack@google.com        FUCompletion(DynInstPtr &_inst, int fu_idx,
11814184Sgabeblack@google.com                     InstructionQueue<Impl> *iq_ptr);
11914184Sgabeblack@google.com
12014184Sgabeblack@google.com        virtual void process();
12114184Sgabeblack@google.com        virtual const char *description() const;
12214184Sgabeblack@google.com        void setFreeFU() { freeFU = true; }
12314184Sgabeblack@google.com    };
12414184Sgabeblack@google.com
12514184Sgabeblack@google.com    /** Constructs an IQ. */
12614184Sgabeblack@google.com    InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
12714184Sgabeblack@google.com
12814184Sgabeblack@google.com    /** Destructs the IQ. */
12914184Sgabeblack@google.com    ~InstructionQueue();
13014184Sgabeblack@google.com
13114184Sgabeblack@google.com    /** Returns the name of the IQ. */
13214184Sgabeblack@google.com    std::string name() const;
13314184Sgabeblack@google.com
13414184Sgabeblack@google.com    /** Registers statistics. */
13514184Sgabeblack@google.com    void regStats();
13614184Sgabeblack@google.com
13714184Sgabeblack@google.com    /** Resets all instruction queue state. */
13814184Sgabeblack@google.com    void resetState();
13914184Sgabeblack@google.com
14014184Sgabeblack@google.com    /** Sets active threads list. */
14114184Sgabeblack@google.com    void setActiveThreads(std::list<ThreadID> *at_ptr);
14214184Sgabeblack@google.com
14314184Sgabeblack@google.com    /** Sets the timer buffer between issue and execute. */
14414184Sgabeblack@google.com    void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
14514184Sgabeblack@google.com
14614184Sgabeblack@google.com    /** Sets the global time buffer. */
14714184Sgabeblack@google.com    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
14814184Sgabeblack@google.com
14914184Sgabeblack@google.com    /** Switches out the instruction queue. */
15014184Sgabeblack@google.com    void switchOut();
15114184Sgabeblack@google.com
15214184Sgabeblack@google.com    /** Takes over execution from another CPU's thread. */
15314184Sgabeblack@google.com    void takeOverFrom();
15414184Sgabeblack@google.com
15514184Sgabeblack@google.com    /** Returns if the IQ is switched out. */
15614184Sgabeblack@google.com    bool isSwitchedOut() { return switchedOut; }
15714184Sgabeblack@google.com
15814184Sgabeblack@google.com    /** Number of entries needed for given amount of threads. */
15914184Sgabeblack@google.com    int entryAmount(ThreadID num_threads);
16014184Sgabeblack@google.com
16114184Sgabeblack@google.com    /** Resets max entries for all threads. */
16214184Sgabeblack@google.com    void resetEntries();
16314184Sgabeblack@google.com
16414184Sgabeblack@google.com    /** Returns total number of free entries. */
16514184Sgabeblack@google.com    unsigned numFreeEntries();
16614184Sgabeblack@google.com
16714184Sgabeblack@google.com    /** Returns number of free entries for a thread. */
16814184Sgabeblack@google.com    unsigned numFreeEntries(ThreadID tid);
16914184Sgabeblack@google.com
17014184Sgabeblack@google.com    /** Returns whether or not the IQ is full. */
17114184Sgabeblack@google.com    bool isFull();
17214184Sgabeblack@google.com
17314184Sgabeblack@google.com    /** Returns whether or not the IQ is full for a specific thread. */
17414184Sgabeblack@google.com    bool isFull(ThreadID tid);
17514184Sgabeblack@google.com
17614184Sgabeblack@google.com    /** Returns if there are any ready instructions in the IQ. */
17714184Sgabeblack@google.com    bool hasReadyInsts();
17814184Sgabeblack@google.com
17914184Sgabeblack@google.com    /** Inserts a new instruction into the IQ. */
18014184Sgabeblack@google.com    void insert(DynInstPtr &new_inst);
18114184Sgabeblack@google.com
18214184Sgabeblack@google.com    /** Inserts a new, non-speculative instruction into the IQ. */
18314184Sgabeblack@google.com    void insertNonSpec(DynInstPtr &new_inst);
18414184Sgabeblack@google.com
18514184Sgabeblack@google.com    /** Inserts a memory or write barrier into the IQ to make sure
18614184Sgabeblack@google.com     *  loads and stores are ordered properly.
18714184Sgabeblack@google.com     */
18814184Sgabeblack@google.com    void insertBarrier(DynInstPtr &barr_inst);
18914184Sgabeblack@google.com
19014184Sgabeblack@google.com    /** Returns the oldest scheduled instruction, and removes it from
19114184Sgabeblack@google.com     * the list of instructions waiting to execute.
19214184Sgabeblack@google.com     */
19314184Sgabeblack@google.com    DynInstPtr getInstToExecute();
19414184Sgabeblack@google.com
19514184Sgabeblack@google.com    /** Returns a memory instruction that was referred due to a delayed DTB
19614184Sgabeblack@google.com     *  translation if it is now ready to execute.
19714184Sgabeblack@google.com     */
19814184Sgabeblack@google.com    DynInstPtr getDeferredMemInstToExecute();
19914184Sgabeblack@google.com
20014184Sgabeblack@google.com    /**
20114184Sgabeblack@google.com     * Records the instruction as the producer of a register without
20214184Sgabeblack@google.com     * adding it to the rest of the IQ.
20314184Sgabeblack@google.com     */
20414184Sgabeblack@google.com    void recordProducer(DynInstPtr &inst)
20514184Sgabeblack@google.com    { addToProducers(inst); }
20614184Sgabeblack@google.com
20714184Sgabeblack@google.com    /** Process FU completion event. */
20814184Sgabeblack@google.com    void processFUCompletion(DynInstPtr &inst, int fu_idx);
20914184Sgabeblack@google.com
21014184Sgabeblack@google.com    /**
21114184Sgabeblack@google.com     * Schedules ready instructions, adding the ready ones (oldest first) to
21214184Sgabeblack@google.com     * the queue to execute.
21314184Sgabeblack@google.com     */
21414184Sgabeblack@google.com    void scheduleReadyInsts();
21514184Sgabeblack@google.com
21614184Sgabeblack@google.com    /** Schedules a single specific non-speculative instruction. */
21714184Sgabeblack@google.com    void scheduleNonSpec(const InstSeqNum &inst);
21814184Sgabeblack@google.com
21914184Sgabeblack@google.com    /**
22014184Sgabeblack@google.com     * Commits all instructions up to and including the given sequence number,
22114184Sgabeblack@google.com     * for a specific thread.
22214184Sgabeblack@google.com     */
22314184Sgabeblack@google.com    void commit(const InstSeqNum &inst, ThreadID tid = 0);
22414184Sgabeblack@google.com
22514184Sgabeblack@google.com    /** Wakes all dependents of a completed instruction. */
22614184Sgabeblack@google.com    int wakeDependents(DynInstPtr &completed_inst);
22714184Sgabeblack@google.com
22814184Sgabeblack@google.com    /** Adds a ready memory instruction to the ready list. */
22914184Sgabeblack@google.com    void addReadyMemInst(DynInstPtr &ready_inst);
23014184Sgabeblack@google.com
23114184Sgabeblack@google.com    /**
23214184Sgabeblack@google.com     * Reschedules a memory instruction. It will be ready to issue once
23314184Sgabeblack@google.com     * replayMemInst() is called.
23414184Sgabeblack@google.com     */
23514184Sgabeblack@google.com    void rescheduleMemInst(DynInstPtr &resched_inst);
23614184Sgabeblack@google.com
23714184Sgabeblack@google.com    /** Replays a memory instruction. It must be rescheduled first. */
23814184Sgabeblack@google.com    void replayMemInst(DynInstPtr &replay_inst);
23914184Sgabeblack@google.com
24014184Sgabeblack@google.com    /** Completes a memory operation. */
24114184Sgabeblack@google.com    void completeMemInst(DynInstPtr &completed_inst);
24214184Sgabeblack@google.com
24314184Sgabeblack@google.com    /**
24414184Sgabeblack@google.com     * Defers a memory instruction when its DTB translation incurs a hw
24514184Sgabeblack@google.com     * page table walk.
24614184Sgabeblack@google.com     */
24714184Sgabeblack@google.com    void deferMemInst(DynInstPtr &deferred_inst);
24814184Sgabeblack@google.com
24914184Sgabeblack@google.com    /** Indicates an ordering violation between a store and a load. */
25014184Sgabeblack@google.com    void violation(DynInstPtr &store, DynInstPtr &faulting_load);
25114184Sgabeblack@google.com
25214184Sgabeblack@google.com    /**
25314184Sgabeblack@google.com     * Squashes instructions for a thread. Squashing information is obtained
25414184Sgabeblack@google.com     * from the time buffer.
25514184Sgabeblack@google.com     */
25614184Sgabeblack@google.com    void squash(ThreadID tid);
25714184Sgabeblack@google.com
25814184Sgabeblack@google.com    /** Returns the number of used entries for a thread. */
25914184Sgabeblack@google.com    unsigned getCount(ThreadID tid) { return count[tid]; };
26014184Sgabeblack@google.com
26114184Sgabeblack@google.com    /** Debug function to print all instructions. */
26214184Sgabeblack@google.com    void printInsts();
26314184Sgabeblack@google.com
26414184Sgabeblack@google.com  private:
26514184Sgabeblack@google.com    /** Does the actual squashing. */
26614184Sgabeblack@google.com    void doSquash(ThreadID tid);
26714184Sgabeblack@google.com
26814184Sgabeblack@google.com    /////////////////////////
26914184Sgabeblack@google.com    // Various pointers
27014184Sgabeblack@google.com    /////////////////////////
27114184Sgabeblack@google.com
27214184Sgabeblack@google.com    /** Pointer to the CPU. */
27314184Sgabeblack@google.com    O3CPU *cpu;
27414184Sgabeblack@google.com
27514184Sgabeblack@google.com    /** Cache interface. */
27614184Sgabeblack@google.com    MemInterface *dcacheInterface;
27714184Sgabeblack@google.com
27814184Sgabeblack@google.com    /** Pointer to IEW stage. */
27914184Sgabeblack@google.com    IEW *iewStage;
28014184Sgabeblack@google.com
28114184Sgabeblack@google.com    /** The memory dependence unit, which tracks/predicts memory dependences
28214184Sgabeblack@google.com     *  between instructions.
28314184Sgabeblack@google.com     */
28414184Sgabeblack@google.com    MemDepUnit memDepUnit[Impl::MaxThreads];
28514184Sgabeblack@google.com
28614184Sgabeblack@google.com    /** The queue to the execute stage.  Issued instructions will be written
28714184Sgabeblack@google.com     *  into it.
28814184Sgabeblack@google.com     */
28914184Sgabeblack@google.com    TimeBuffer<IssueStruct> *issueToExecuteQueue;
29014184Sgabeblack@google.com
29114184Sgabeblack@google.com    /** The backwards time buffer. */
29214184Sgabeblack@google.com    TimeBuffer<TimeStruct> *timeBuffer;
29314184Sgabeblack@google.com
29414184Sgabeblack@google.com    /** Wire to read information from timebuffer. */
29514184Sgabeblack@google.com    typename TimeBuffer<TimeStruct>::wire fromCommit;
29614184Sgabeblack@google.com
29714184Sgabeblack@google.com    /** Function unit pool. */
29814184Sgabeblack@google.com    FUPool *fuPool;
29914184Sgabeblack@google.com
30014184Sgabeblack@google.com    //////////////////////////////////////
30114184Sgabeblack@google.com    // Instruction lists, ready queues, and ordering
30214184Sgabeblack@google.com    //////////////////////////////////////
30314184Sgabeblack@google.com
30414184Sgabeblack@google.com    /** List of all the instructions in the IQ (some of which may be issued). */
30514184Sgabeblack@google.com    std::list<DynInstPtr> instList[Impl::MaxThreads];
30614184Sgabeblack@google.com
30714184Sgabeblack@google.com    /** List of instructions that are ready to be executed. */
30814184Sgabeblack@google.com    std::list<DynInstPtr> instsToExecute;
30914184Sgabeblack@google.com
31014184Sgabeblack@google.com    /** List of instructions waiting for their DTB translation to
31114184Sgabeblack@google.com     *  complete (hw page table walk in progress).
31214184Sgabeblack@google.com     */
31314184Sgabeblack@google.com    std::list<DynInstPtr> deferredMemInsts;
31414184Sgabeblack@google.com
31514184Sgabeblack@google.com    /**
31614184Sgabeblack@google.com     * Struct for comparing entries to be added to the priority queue.
31714184Sgabeblack@google.com     * This gives reverse ordering to the instructions in terms of
31814184Sgabeblack@google.com     * sequence numbers: the instructions with smaller sequence
31914184Sgabeblack@google.com     * numbers (and hence are older) will be at the top of the
32014184Sgabeblack@google.com     * priority queue.
32114184Sgabeblack@google.com     */
32214184Sgabeblack@google.com    struct pqCompare {
32314184Sgabeblack@google.com        bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
32414184Sgabeblack@google.com        {
32514184Sgabeblack@google.com            return lhs->seqNum > rhs->seqNum;
32614184Sgabeblack@google.com        }
32714184Sgabeblack@google.com    };
32814184Sgabeblack@google.com
32914184Sgabeblack@google.com    typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
33014184Sgabeblack@google.com    ReadyInstQueue;
33114184Sgabeblack@google.com
33214184Sgabeblack@google.com    /** List of ready instructions, per op class.  They are separated by op
33314184Sgabeblack@google.com     *  class to allow for easy mapping to FUs.
33414184Sgabeblack@google.com     */
33514184Sgabeblack@google.com    ReadyInstQueue readyInsts[Num_OpClasses];
33614184Sgabeblack@google.com
33714184Sgabeblack@google.com    /** List of non-speculative instructions that will be scheduled
33814184Sgabeblack@google.com     *  once the IQ gets a signal from commit.  While it's redundant to
33914184Sgabeblack@google.com     *  have the key be a part of the value (the sequence number is stored
34014184Sgabeblack@google.com     *  inside of DynInst), when these instructions are woken up only
34114184Sgabeblack@google.com     *  the sequence number will be available.  Thus it is most efficient to be
34214184Sgabeblack@google.com     *  able to search by the sequence number alone.
34314184Sgabeblack@google.com     */
34414184Sgabeblack@google.com    std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
34514184Sgabeblack@google.com
34614184Sgabeblack@google.com    typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
34714184Sgabeblack@google.com
34814184Sgabeblack@google.com    /** Entry for the list age ordering by op class. */
34914184Sgabeblack@google.com    struct ListOrderEntry {
35014184Sgabeblack@google.com        OpClass queueType;
35114184Sgabeblack@google.com        InstSeqNum oldestInst;
35214184Sgabeblack@google.com    };
35314184Sgabeblack@google.com
35414184Sgabeblack@google.com    /** List that contains the age order of the oldest instruction of each
35514184Sgabeblack@google.com     *  ready queue.  Used to select the oldest instruction available
35614184Sgabeblack@google.com     *  among op classes.
35714184Sgabeblack@google.com     *  @todo: Might be better to just move these entries around instead
35814184Sgabeblack@google.com     *  of creating new ones every time the position changes due to an
35914184Sgabeblack@google.com     *  instruction issuing.  Not sure std::list supports this.
36014184Sgabeblack@google.com     */
36114184Sgabeblack@google.com    std::list<ListOrderEntry> listOrder;
36214184Sgabeblack@google.com
36314184Sgabeblack@google.com    typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
36414184Sgabeblack@google.com
36514184Sgabeblack@google.com    /** Tracks if each ready queue is on the age order list. */
36614184Sgabeblack@google.com    bool queueOnList[Num_OpClasses];
36714184Sgabeblack@google.com
36814184Sgabeblack@google.com    /** Iterators of each ready queue.  Points to their spot in the age order
36914184Sgabeblack@google.com     *  list.
37014184Sgabeblack@google.com     */
37114184Sgabeblack@google.com    ListOrderIt readyIt[Num_OpClasses];
37214184Sgabeblack@google.com
37314184Sgabeblack@google.com    /** Add an op class to the age order list. */
37414184Sgabeblack@google.com    void addToOrderList(OpClass op_class);
37514184Sgabeblack@google.com
37614184Sgabeblack@google.com    /**
37714184Sgabeblack@google.com     * Called when the oldest instruction has been removed from a ready queue;
37814184Sgabeblack@google.com     * this places that ready queue into the proper spot in the age order list.
37914184Sgabeblack@google.com     */
38014184Sgabeblack@google.com    void moveToYoungerInst(ListOrderIt age_order_it);
38114184Sgabeblack@google.com
38214184Sgabeblack@google.com    DependencyGraph<DynInstPtr> dependGraph;
38314184Sgabeblack@google.com
38414184Sgabeblack@google.com    //////////////////////////////////////
38514184Sgabeblack@google.com    // Various parameters
38614184Sgabeblack@google.com    //////////////////////////////////////
38714184Sgabeblack@google.com
38814184Sgabeblack@google.com    /** IQ Resource Sharing Policy */
38914184Sgabeblack@google.com    enum IQPolicy {
39014184Sgabeblack@google.com        Dynamic,
39114184Sgabeblack@google.com        Partitioned,
39214184Sgabeblack@google.com        Threshold
39314184Sgabeblack@google.com    };
39414184Sgabeblack@google.com
39514184Sgabeblack@google.com    /** IQ sharing policy for SMT. */
39614184Sgabeblack@google.com    IQPolicy iqPolicy;
39714184Sgabeblack@google.com
39814184Sgabeblack@google.com    /** Number of Total Threads*/
39914184Sgabeblack@google.com    ThreadID numThreads;
40014184Sgabeblack@google.com
40114184Sgabeblack@google.com    /** Pointer to list of active threads. */
40214184Sgabeblack@google.com    std::list<ThreadID> *activeThreads;
40314184Sgabeblack@google.com
40414184Sgabeblack@google.com    /** Per Thread IQ count */
40514184Sgabeblack@google.com    unsigned count[Impl::MaxThreads];
40614184Sgabeblack@google.com
40714184Sgabeblack@google.com    /** Max IQ Entries Per Thread */
40814184Sgabeblack@google.com    unsigned maxEntries[Impl::MaxThreads];
40914184Sgabeblack@google.com
41014184Sgabeblack@google.com    /** Number of free IQ entries left. */
41114184Sgabeblack@google.com    unsigned freeEntries;
41214184Sgabeblack@google.com
41314184Sgabeblack@google.com    /** The number of entries in the instruction queue. */
41414184Sgabeblack@google.com    unsigned numEntries;
41514184Sgabeblack@google.com
41614184Sgabeblack@google.com    /** The total number of instructions that can be issued in one cycle. */
41714184Sgabeblack@google.com    unsigned totalWidth;
41814184Sgabeblack@google.com
41914184Sgabeblack@google.com    /** The number of physical registers in the CPU. */
42014184Sgabeblack@google.com    unsigned numPhysRegs;
42114184Sgabeblack@google.com
42214184Sgabeblack@google.com    /** The number of physical integer registers in the CPU. */
42314184Sgabeblack@google.com    unsigned numPhysIntRegs;
42414184Sgabeblack@google.com
42514184Sgabeblack@google.com    /** The number of floating point registers in the CPU. */
42614184Sgabeblack@google.com    unsigned numPhysFloatRegs;
42714184Sgabeblack@google.com
42814184Sgabeblack@google.com    /** Delay between commit stage and the IQ.
42914184Sgabeblack@google.com     *  @todo: Make there be a distinction between the delays within IEW.
43014184Sgabeblack@google.com     */
43114184Sgabeblack@google.com    unsigned commitToIEWDelay;
43214184Sgabeblack@google.com
43314184Sgabeblack@google.com    /** Is the IQ switched out. */
43414184Sgabeblack@google.com    bool switchedOut;
43514184Sgabeblack@google.com
43614184Sgabeblack@google.com    /** The sequence number of the squashed instruction. */
43714184Sgabeblack@google.com    InstSeqNum squashedSeqNum[Impl::MaxThreads];
43814184Sgabeblack@google.com
43914184Sgabeblack@google.com    /** A cache of the recently woken registers.  It is 1 if the register
44014184Sgabeblack@google.com     *  has been woken up recently, and 0 if the register has been added
44114184Sgabeblack@google.com     *  to the dependency graph and has not yet received its value.  It
44214184Sgabeblack@google.com     *  is basically a secondary scoreboard, and should pretty much mirror
44314184Sgabeblack@google.com     *  the scoreboard that exists in the rename map.
44414184Sgabeblack@google.com     */
44514184Sgabeblack@google.com    std::vector<bool> regScoreboard;
44614184Sgabeblack@google.com
44714184Sgabeblack@google.com    /** Adds an instruction to the dependency graph, as a consumer. */
44814184Sgabeblack@google.com    bool addToDependents(DynInstPtr &new_inst);
44914184Sgabeblack@google.com
45014184Sgabeblack@google.com    /** Adds an instruction to the dependency graph, as a producer. */
45114184Sgabeblack@google.com    void addToProducers(DynInstPtr &new_inst);
45214184Sgabeblack@google.com
45314184Sgabeblack@google.com    /** Moves an instruction to the ready queue if it is ready. */
45414184Sgabeblack@google.com    void addIfReady(DynInstPtr &inst);
45514184Sgabeblack@google.com
45614184Sgabeblack@google.com    /** Debugging function to count how many entries are in the IQ.  It does
45714184Sgabeblack@google.com     *  a linear walk through the instructions, so do not call this function
45814184Sgabeblack@google.com     *  during normal execution.
45914184Sgabeblack@google.com     */
46014184Sgabeblack@google.com    int countInsts();
46114184Sgabeblack@google.com
46214184Sgabeblack@google.com    /** Debugging function to dump all the list sizes, as well as print
46314184Sgabeblack@google.com     *  out the list of nonspeculative instructions.  Should not be used
46414184Sgabeblack@google.com     *  in any other capacity, but it has no harmful sideaffects.
46514184Sgabeblack@google.com     */
46614184Sgabeblack@google.com    void dumpLists();
46714184Sgabeblack@google.com
46814184Sgabeblack@google.com    /** Debugging function to dump out all instructions that are in the
46914184Sgabeblack@google.com     *  IQ.
47014184Sgabeblack@google.com     */
47114184Sgabeblack@google.com    void dumpInsts();
47214184Sgabeblack@google.com
47314184Sgabeblack@google.com    /** Stat for number of instructions added. */
47414184Sgabeblack@google.com    Stats::Scalar iqInstsAdded;
47514184Sgabeblack@google.com    /** Stat for number of non-speculative instructions added. */
47614184Sgabeblack@google.com    Stats::Scalar iqNonSpecInstsAdded;
47714184Sgabeblack@google.com
47814184Sgabeblack@google.com    Stats::Scalar iqInstsIssued;
47914184Sgabeblack@google.com    /** Stat for number of integer instructions issued. */
48014184Sgabeblack@google.com    Stats::Scalar iqIntInstsIssued;
48114184Sgabeblack@google.com    /** Stat for number of floating point instructions issued. */
48214184Sgabeblack@google.com    Stats::Scalar iqFloatInstsIssued;
48314184Sgabeblack@google.com    /** Stat for number of branch instructions issued. */
48414184Sgabeblack@google.com    Stats::Scalar iqBranchInstsIssued;
48514184Sgabeblack@google.com    /** Stat for number of memory instructions issued. */
48614184Sgabeblack@google.com    Stats::Scalar iqMemInstsIssued;
48714184Sgabeblack@google.com    /** Stat for number of miscellaneous instructions issued. */
48814184Sgabeblack@google.com    Stats::Scalar iqMiscInstsIssued;
48914184Sgabeblack@google.com    /** Stat for number of squashed instructions that were ready to issue. */
49014184Sgabeblack@google.com    Stats::Scalar iqSquashedInstsIssued;
49114184Sgabeblack@google.com    /** Stat for number of squashed instructions examined when squashing. */
49214184Sgabeblack@google.com    Stats::Scalar iqSquashedInstsExamined;
49314184Sgabeblack@google.com    /** Stat for number of squashed instruction operands examined when
49414184Sgabeblack@google.com     * squashing.
49514184Sgabeblack@google.com     */
49614184Sgabeblack@google.com    Stats::Scalar iqSquashedOperandsExamined;
49714184Sgabeblack@google.com    /** Stat for number of non-speculative instructions removed due to a squash.
49814184Sgabeblack@google.com     */
49914184Sgabeblack@google.com    Stats::Scalar iqSquashedNonSpecRemoved;
50014184Sgabeblack@google.com    // Also include number of instructions rescheduled and replayed.
50114184Sgabeblack@google.com
50214184Sgabeblack@google.com    /** Distribution of number of instructions in the queue.
50314184Sgabeblack@google.com     * @todo: Need to create struct to track the entry time for each
50414184Sgabeblack@google.com     * instruction. */
50514184Sgabeblack@google.com//    Stats::VectorDistribution queueResDist;
50614184Sgabeblack@google.com    /** Distribution of the number of instructions issued. */
50714184Sgabeblack@google.com    Stats::Distribution numIssuedDist;
50814184Sgabeblack@google.com    /** Distribution of the cycles it takes to issue an instruction.
50914184Sgabeblack@google.com     * @todo: Need to create struct to track the ready time for each
51014184Sgabeblack@google.com     * instruction. */
51114184Sgabeblack@google.com//    Stats::VectorDistribution issueDelayDist;
51214184Sgabeblack@google.com
51314184Sgabeblack@google.com    /** Number of times an instruction could not be issued because a
51414184Sgabeblack@google.com     * FU was busy.
51514184Sgabeblack@google.com     */
51614184Sgabeblack@google.com    Stats::Vector statFuBusy;
51714184Sgabeblack@google.com//    Stats::Vector dist_unissued;
51814184Sgabeblack@google.com    /** Stat for total number issued for each instruction type. */
51914184Sgabeblack@google.com    Stats::Vector2d statIssuedInstType;
52014184Sgabeblack@google.com
52114184Sgabeblack@google.com    /** Number of instructions issued per cycle. */
52214184Sgabeblack@google.com    Stats::Formula issueRate;
52314184Sgabeblack@google.com
52414184Sgabeblack@google.com    /** Number of times the FU was busy. */
52514184Sgabeblack@google.com    Stats::Vector fuBusy;
52614184Sgabeblack@google.com    /** Number of times the FU was busy per instruction issued. */
52714184Sgabeblack@google.com    Stats::Formula fuBusyRate;
52814184Sgabeblack@google.com   public:
52914184Sgabeblack@google.com    Stats::Scalar intInstQueueReads;
53014184Sgabeblack@google.com    Stats::Scalar intInstQueueWrites;
53114184Sgabeblack@google.com    Stats::Scalar intInstQueueWakeupAccesses;
53214184Sgabeblack@google.com    Stats::Scalar fpInstQueueReads;
53314184Sgabeblack@google.com    Stats::Scalar fpInstQueueWrites;
53414184Sgabeblack@google.com    Stats::Scalar fpInstQueueWakeupQccesses;
53514184Sgabeblack@google.com
53614184Sgabeblack@google.com    Stats::Scalar intAluAccesses;
53714184Sgabeblack@google.com    Stats::Scalar fpAluAccesses;
53814184Sgabeblack@google.com};
53914184Sgabeblack@google.com
54014184Sgabeblack@google.com#endif //__CPU_O3_INST_QUEUE_HH__
54114184Sgabeblack@google.com