inst_queue.hh revision 2669:f2b336e89d2a
12929Sktlim@umich.edu/* 22929Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32932Sktlim@umich.edu * All rights reserved. 42929Sktlim@umich.edu * 52929Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62929Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72929Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82929Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92929Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102929Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112929Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122929Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132929Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142929Sktlim@umich.edu * this software without specific prior written permission. 152929Sktlim@umich.edu * 162929Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172929Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182929Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192929Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202929Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212929Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222929Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232929Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242929Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252929Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262929Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272929Sktlim@umich.edu */ 282932Sktlim@umich.edu 292932Sktlim@umich.edu#ifndef __CPU_O3_INST_QUEUE_HH__ 302932Sktlim@umich.edu#define __CPU_O3_INST_QUEUE_HH__ 312929Sktlim@umich.edu 326007Ssteve.reinhardt@amd.com#include <list> 332929Sktlim@umich.edu#include <map> 342929Sktlim@umich.edu#include <queue> 352929Sktlim@umich.edu#include <vector> 362929Sktlim@umich.edu 372929Sktlim@umich.edu#include "base/statistics.hh" 382929Sktlim@umich.edu#include "base/timebuf.hh" 392929Sktlim@umich.edu#include "cpu/inst_seq.hh" 402929Sktlim@umich.edu#include "cpu/o3/dep_graph.hh" 412929Sktlim@umich.edu#include "cpu/op_class.hh" 422929Sktlim@umich.edu#include "sim/host.hh" 432929Sktlim@umich.edu 442929Sktlim@umich.educlass FUPool; 452929Sktlim@umich.educlass MemInterface; 462929Sktlim@umich.edu 476007Ssteve.reinhardt@amd.com/** 486007Ssteve.reinhardt@amd.com * A standard instruction queue class. It holds ready instructions, in 496007Ssteve.reinhardt@amd.com * order, in seperate priority queues to facilitate the scheduling of 506007Ssteve.reinhardt@amd.com * instructions. The IQ uses a separate linked list to track dependencies. 516007Ssteve.reinhardt@amd.com * Similar to the rename map and the free list, it expects that 526007Ssteve.reinhardt@amd.com * floating point registers have their indices start after the integer 536007Ssteve.reinhardt@amd.com * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer 546007Ssteve.reinhardt@amd.com * and 96-191 are fp). This remains true even for both logical and 556007Ssteve.reinhardt@amd.com * physical register indices. The IQ depends on the memory dependence unit to 566007Ssteve.reinhardt@amd.com * track when memory operations are ready in terms of ordering; register 576007Ssteve.reinhardt@amd.com * dependencies are tracked normally. Right now the IQ also handles the 586007Ssteve.reinhardt@amd.com * execution timing; this is mainly to allow back-to-back scheduling without 596007Ssteve.reinhardt@amd.com * requiring IEW to be able to peek into the IQ. At the end of the execution 606007Ssteve.reinhardt@amd.com * latency, the instruction is put into the queue to execute, where it will 616007Ssteve.reinhardt@amd.com * have the execute() function called on it. 626007Ssteve.reinhardt@amd.com * @todo: Make IQ able to handle multiple FU pools. 636007Ssteve.reinhardt@amd.com */ 646007Ssteve.reinhardt@amd.comtemplate <class Impl> 656007Ssteve.reinhardt@amd.comclass InstructionQueue 666007Ssteve.reinhardt@amd.com{ 676007Ssteve.reinhardt@amd.com public: 686007Ssteve.reinhardt@amd.com //Typedefs from the Impl. 696007Ssteve.reinhardt@amd.com typedef typename Impl::FullCPU FullCPU; 706007Ssteve.reinhardt@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 716007Ssteve.reinhardt@amd.com typedef typename Impl::Params Params; 726007Ssteve.reinhardt@amd.com 736007Ssteve.reinhardt@amd.com typedef typename Impl::CPUPol::IEW IEW; 746007Ssteve.reinhardt@amd.com typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; 756007Ssteve.reinhardt@amd.com typedef typename Impl::CPUPol::IssueStruct IssueStruct; 762929Sktlim@umich.edu typedef typename Impl::CPUPol::TimeStruct TimeStruct; 772929Sktlim@umich.edu 782929Sktlim@umich.edu // Typedef of iterator through the list of instructions. 796007Ssteve.reinhardt@amd.com typedef typename std::list<DynInstPtr>::iterator ListIt; 806007Ssteve.reinhardt@amd.com 816007Ssteve.reinhardt@amd.com friend class Impl::FullCPU; 826007Ssteve.reinhardt@amd.com 836007Ssteve.reinhardt@amd.com /** FU completion event class. */ 846007Ssteve.reinhardt@amd.com class FUCompletion : public Event { 852929Sktlim@umich.edu private: 862929Sktlim@umich.edu /** Executing instruction. */ 872929Sktlim@umich.edu DynInstPtr inst; 882929Sktlim@umich.edu 892929Sktlim@umich.edu /** Index of the FU used for executing. */ 906011Ssteve.reinhardt@amd.com int fuIdx; 916007Ssteve.reinhardt@amd.com 926007Ssteve.reinhardt@amd.com /** Pointer back to the instruction queue. */ 936007Ssteve.reinhardt@amd.com InstructionQueue<Impl> *iqPtr; 946007Ssteve.reinhardt@amd.com 956007Ssteve.reinhardt@amd.com bool freeFU; 966007Ssteve.reinhardt@amd.com 976007Ssteve.reinhardt@amd.com public: 986007Ssteve.reinhardt@amd.com /** Construct a FU completion event. */ 996007Ssteve.reinhardt@amd.com FUCompletion(DynInstPtr &_inst, int fu_idx, 1006007Ssteve.reinhardt@amd.com InstructionQueue<Impl> *iq_ptr); 1016007Ssteve.reinhardt@amd.com 1026007Ssteve.reinhardt@amd.com virtual void process(); 1036007Ssteve.reinhardt@amd.com virtual const char *description(); 1046007Ssteve.reinhardt@amd.com void setFreeFU() { freeFU = true; } 1056011Ssteve.reinhardt@amd.com }; 1066007Ssteve.reinhardt@amd.com 1076007Ssteve.reinhardt@amd.com /** Constructs an IQ. */ 1086007Ssteve.reinhardt@amd.com InstructionQueue(Params *params); 1096007Ssteve.reinhardt@amd.com 1106007Ssteve.reinhardt@amd.com /** Destructs the IQ. */ 1116007Ssteve.reinhardt@amd.com ~InstructionQueue(); 1126007Ssteve.reinhardt@amd.com 1136011Ssteve.reinhardt@amd.com /** Returns the name of the IQ. */ 1146007Ssteve.reinhardt@amd.com std::string name() const; 1156007Ssteve.reinhardt@amd.com 1166007Ssteve.reinhardt@amd.com /** Registers statistics. */ 1176007Ssteve.reinhardt@amd.com void regStats(); 1186007Ssteve.reinhardt@amd.com 1196007Ssteve.reinhardt@amd.com void resetState(); 1206007Ssteve.reinhardt@amd.com 1216011Ssteve.reinhardt@amd.com /** Sets CPU pointer. */ 1226007Ssteve.reinhardt@amd.com void setCPU(FullCPU *_cpu) { cpu = _cpu; } 1236007Ssteve.reinhardt@amd.com 1246007Ssteve.reinhardt@amd.com /** Sets active threads list. */ 1256007Ssteve.reinhardt@amd.com void setActiveThreads(std::list<unsigned> *at_ptr); 1266007Ssteve.reinhardt@amd.com 1276008Ssteve.reinhardt@amd.com /** Sets the IEW pointer. */ 1286007Ssteve.reinhardt@amd.com void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; } 1296008Ssteve.reinhardt@amd.com 1306008Ssteve.reinhardt@amd.com /** Sets the timer buffer between issue and execute. */ 1316008Ssteve.reinhardt@amd.com void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue); 1326008Ssteve.reinhardt@amd.com 1336008Ssteve.reinhardt@amd.com /** Sets the global time buffer. */ 1346008Ssteve.reinhardt@amd.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1356008Ssteve.reinhardt@amd.com 1366007Ssteve.reinhardt@amd.com void switchOut(); 1376007Ssteve.reinhardt@amd.com 1386007Ssteve.reinhardt@amd.com void takeOverFrom(); 1396007Ssteve.reinhardt@amd.com 1406007Ssteve.reinhardt@amd.com bool isSwitchedOut() { return switchedOut; } 1412929Sktlim@umich.edu 1422929Sktlim@umich.edu /** Number of entries needed for given amount of threads. */ 1432929Sktlim@umich.edu int entryAmount(int num_threads); 1442929Sktlim@umich.edu 1456007Ssteve.reinhardt@amd.com /** Resets max entries for all threads. */ 1466007Ssteve.reinhardt@amd.com void resetEntries(); 1472929Sktlim@umich.edu 1482929Sktlim@umich.edu /** Returns total number of free entries. */ 1492929Sktlim@umich.edu unsigned numFreeEntries(); 1502929Sktlim@umich.edu 1516007Ssteve.reinhardt@amd.com /** Returns number of free entries for a thread. */ 1526007Ssteve.reinhardt@amd.com unsigned numFreeEntries(unsigned tid); 1532929Sktlim@umich.edu 1542929Sktlim@umich.edu /** Returns whether or not the IQ is full. */ 1556007Ssteve.reinhardt@amd.com bool isFull(); 1562929Sktlim@umich.edu 1572929Sktlim@umich.edu /** Returns whether or not the IQ is full for a specific thread. */ 1582929Sktlim@umich.edu bool isFull(unsigned tid); 1592929Sktlim@umich.edu 1602929Sktlim@umich.edu /** Returns if there are any ready instructions in the IQ. */ 1612929Sktlim@umich.edu bool hasReadyInsts(); 1622929Sktlim@umich.edu 1634937Sstever@gmail.com /** Inserts a new instruction into the IQ. */ 1644937Sstever@gmail.com void insert(DynInstPtr &new_inst); 1654937Sstever@gmail.com 1664937Sstever@gmail.com /** Inserts a new, non-speculative instruction into the IQ. */ 1674937Sstever@gmail.com void insertNonSpec(DynInstPtr &new_inst); 1684937Sstever@gmail.com 1694937Sstever@gmail.com /** Inserts a memory or write barrier into the IQ to make sure 1704937Sstever@gmail.com * loads and stores are ordered properly. 1714937Sstever@gmail.com */ 1725773Snate@binkert.org void insertBarrier(DynInstPtr &barr_inst); 1734937Sstever@gmail.com 1744937Sstever@gmail.com DynInstPtr getInstToExecute(); 1754937Sstever@gmail.com 1762929Sktlim@umich.edu /** 1772929Sktlim@umich.edu * Records the instruction as the producer of a register without 1782929Sktlim@umich.edu * adding it to the rest of the IQ. 1795773Snate@binkert.org */ 1802929Sktlim@umich.edu void recordProducer(DynInstPtr &inst) 1812929Sktlim@umich.edu { addToProducers(inst); } 1822929Sktlim@umich.edu 1832929Sktlim@umich.edu /** Process FU completion event. */ 1842929Sktlim@umich.edu void processFUCompletion(DynInstPtr &inst, int fu_idx); 1852929Sktlim@umich.edu 1864937Sstever@gmail.com /** 1874937Sstever@gmail.com * Schedules ready instructions, adding the ready ones (oldest first) to 1884937Sstever@gmail.com * the queue to execute. 1894937Sstever@gmail.com */ 1904937Sstever@gmail.com void scheduleReadyInsts(); 1914937Sstever@gmail.com 1924937Sstever@gmail.com /** Schedules a single specific non-speculative instruction. */ 1934937Sstever@gmail.com void scheduleNonSpec(const InstSeqNum &inst); 1944937Sstever@gmail.com 1954937Sstever@gmail.com /** 1964937Sstever@gmail.com * Commits all instructions up to and including the given sequence number, 1974937Sstever@gmail.com * for a specific thread. 1984937Sstever@gmail.com */ 1994937Sstever@gmail.com void commit(const InstSeqNum &inst, unsigned tid = 0); 2004937Sstever@gmail.com 2012929Sktlim@umich.edu /** Wakes all dependents of a completed instruction. */ 2022929Sktlim@umich.edu int wakeDependents(DynInstPtr &completed_inst); 2032929Sktlim@umich.edu 2042929Sktlim@umich.edu /** Adds a ready memory instruction to the ready list. */ 2052929Sktlim@umich.edu void addReadyMemInst(DynInstPtr &ready_inst); 2062929Sktlim@umich.edu 2072929Sktlim@umich.edu /** 2086011Ssteve.reinhardt@amd.com * Reschedules a memory instruction. It will be ready to issue once 2092929Sktlim@umich.edu * replayMemInst() is called. 2102929Sktlim@umich.edu */ 2112929Sktlim@umich.edu void rescheduleMemInst(DynInstPtr &resched_inst); 2122929Sktlim@umich.edu 2132929Sktlim@umich.edu /** Replays a memory instruction. It must be rescheduled first. */ 2142929Sktlim@umich.edu void replayMemInst(DynInstPtr &replay_inst); 2152929Sktlim@umich.edu 2162929Sktlim@umich.edu /** Completes a memory operation. */ 2172997Sstever@eecs.umich.edu void completeMemInst(DynInstPtr &completed_inst); 2182997Sstever@eecs.umich.edu 2192929Sktlim@umich.edu /** Indicates an ordering violation between a store and a load. */ 2202997Sstever@eecs.umich.edu void violation(DynInstPtr &store, DynInstPtr &faulting_load); 2212997Sstever@eecs.umich.edu 2222929Sktlim@umich.edu /** 2232997Sstever@eecs.umich.edu * Squashes instructions for a thread. Squashing information is obtained 2242997Sstever@eecs.umich.edu * from the time buffer. 2252997Sstever@eecs.umich.edu */ 2262929Sktlim@umich.edu void squash(unsigned tid); 2272997Sstever@eecs.umich.edu 2282997Sstever@eecs.umich.edu /** Returns the number of used entries for a thread. */ 2292997Sstever@eecs.umich.edu unsigned getCount(unsigned tid) { return count[tid]; }; 2302997Sstever@eecs.umich.edu 2315773Snate@binkert.org /** Debug function to print all instructions. */ 2325773Snate@binkert.org void printInsts(); 2332997Sstever@eecs.umich.edu 2342997Sstever@eecs.umich.edu private: 2356007Ssteve.reinhardt@amd.com /** Does the actual squashing. */ 2366007Ssteve.reinhardt@amd.com void doSquash(unsigned tid); 2372997Sstever@eecs.umich.edu 2382929Sktlim@umich.edu ///////////////////////// 2392997Sstever@eecs.umich.edu // Various pointers 2402997Sstever@eecs.umich.edu ///////////////////////// 2412997Sstever@eecs.umich.edu 2422997Sstever@eecs.umich.edu /** Pointer to the CPU. */ 2432997Sstever@eecs.umich.edu FullCPU *cpu; 2442997Sstever@eecs.umich.edu 2452997Sstever@eecs.umich.edu /** Cache interface. */ 2462929Sktlim@umich.edu MemInterface *dcacheInterface; 2472997Sstever@eecs.umich.edu 2482929Sktlim@umich.edu /** Pointer to IEW stage. */ 2492929Sktlim@umich.edu IEW *iewStage; 2503005Sstever@eecs.umich.edu 2513005Sstever@eecs.umich.edu /** The memory dependence unit, which tracks/predicts memory dependences 2523005Sstever@eecs.umich.edu * between instructions. 2533005Sstever@eecs.umich.edu */ 2546025Snate@binkert.org MemDepUnit memDepUnit[Impl::MaxThreads]; 2556025Snate@binkert.org 2566025Snate@binkert.org /** The queue to the execute stage. Issued instructions will be written 2576025Snate@binkert.org * into it. 2586025Snate@binkert.org */ 2596025Snate@binkert.org TimeBuffer<IssueStruct> *issueToExecuteQueue; 2604130Ssaidi@eecs.umich.edu 2614130Ssaidi@eecs.umich.edu /** The backwards time buffer. */ 2624130Ssaidi@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 2633691Shsul@eecs.umich.edu 2643005Sstever@eecs.umich.edu /** Wire to read information from timebuffer. */ 2655721Shsul@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire fromCommit; 2666112Ssteve.reinhardt@amd.com 2673005Sstever@eecs.umich.edu /** Function unit pool. */ 2682929Sktlim@umich.edu FUPool *fuPool; 2692929Sktlim@umich.edu 2703005Sstever@eecs.umich.edu ////////////////////////////////////// 2712997Sstever@eecs.umich.edu // Instruction lists, ready queues, and ordering 2722997Sstever@eecs.umich.edu ////////////////////////////////////// 2732997Sstever@eecs.umich.edu 2742929Sktlim@umich.edu /** List of all the instructions in the IQ (some of which may be issued). */ 275 std::list<DynInstPtr> instList[Impl::MaxThreads]; 276 277 std::list<DynInstPtr> instsToExecute; 278 279 /** 280 * Struct for comparing entries to be added to the priority queue. This 281 * gives reverse ordering to the instructions in terms of sequence 282 * numbers: the instructions with smaller sequence numbers (and hence 283 * are older) will be at the top of the priority queue. 284 */ 285 struct pqCompare { 286 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const 287 { 288 return lhs->seqNum > rhs->seqNum; 289 } 290 }; 291 292 typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> 293 ReadyInstQueue; 294 295 /** List of ready instructions, per op class. They are separated by op 296 * class to allow for easy mapping to FUs. 297 */ 298 ReadyInstQueue readyInsts[Num_OpClasses]; 299 300 /** List of non-speculative instructions that will be scheduled 301 * once the IQ gets a signal from commit. While it's redundant to 302 * have the key be a part of the value (the sequence number is stored 303 * inside of DynInst), when these instructions are woken up only 304 * the sequence number will be available. Thus it is most efficient to be 305 * able to search by the sequence number alone. 306 */ 307 std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 308 309 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 310 311 /** Entry for the list age ordering by op class. */ 312 struct ListOrderEntry { 313 OpClass queueType; 314 InstSeqNum oldestInst; 315 }; 316 317 /** List that contains the age order of the oldest instruction of each 318 * ready queue. Used to select the oldest instruction available 319 * among op classes. 320 * @todo: Might be better to just move these entries around instead 321 * of creating new ones every time the position changes due to an 322 * instruction issuing. Not sure std::list supports this. 323 */ 324 std::list<ListOrderEntry> listOrder; 325 326 typedef typename std::list<ListOrderEntry>::iterator ListOrderIt; 327 328 /** Tracks if each ready queue is on the age order list. */ 329 bool queueOnList[Num_OpClasses]; 330 331 /** Iterators of each ready queue. Points to their spot in the age order 332 * list. 333 */ 334 ListOrderIt readyIt[Num_OpClasses]; 335 336 /** Add an op class to the age order list. */ 337 void addToOrderList(OpClass op_class); 338 339 /** 340 * Called when the oldest instruction has been removed from a ready queue; 341 * this places that ready queue into the proper spot in the age order list. 342 */ 343 void moveToYoungerInst(ListOrderIt age_order_it); 344 345 DependencyGraph<DynInstPtr> dependGraph; 346 347 ////////////////////////////////////// 348 // Various parameters 349 ////////////////////////////////////// 350 351 /** IQ Resource Sharing Policy */ 352 enum IQPolicy { 353 Dynamic, 354 Partitioned, 355 Threshold 356 }; 357 358 /** IQ sharing policy for SMT. */ 359 IQPolicy iqPolicy; 360 361 /** Number of Total Threads*/ 362 unsigned numThreads; 363 364 /** Pointer to list of active threads. */ 365 std::list<unsigned> *activeThreads; 366 367 /** Per Thread IQ count */ 368 unsigned count[Impl::MaxThreads]; 369 370 /** Max IQ Entries Per Thread */ 371 unsigned maxEntries[Impl::MaxThreads]; 372 373 /** Number of free IQ entries left. */ 374 unsigned freeEntries; 375 376 /** The number of entries in the instruction queue. */ 377 unsigned numEntries; 378 379 /** The total number of instructions that can be issued in one cycle. */ 380 unsigned totalWidth; 381 382 /** The number of physical registers in the CPU. */ 383 unsigned numPhysRegs; 384 385 /** The number of physical integer registers in the CPU. */ 386 unsigned numPhysIntRegs; 387 388 /** The number of floating point registers in the CPU. */ 389 unsigned numPhysFloatRegs; 390 391 /** Delay between commit stage and the IQ. 392 * @todo: Make there be a distinction between the delays within IEW. 393 */ 394 unsigned commitToIEWDelay; 395 396 bool switchedOut; 397 398 /** The sequence number of the squashed instruction. */ 399 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 400 401 /** A cache of the recently woken registers. It is 1 if the register 402 * has been woken up recently, and 0 if the register has been added 403 * to the dependency graph and has not yet received its value. It 404 * is basically a secondary scoreboard, and should pretty much mirror 405 * the scoreboard that exists in the rename map. 406 */ 407 std::vector<bool> regScoreboard; 408 409 /** Adds an instruction to the dependency graph, as a consumer. */ 410 bool addToDependents(DynInstPtr &new_inst); 411 412 /** Adds an instruction to the dependency graph, as a producer. */ 413 void addToProducers(DynInstPtr &new_inst); 414 415 /** Moves an instruction to the ready queue if it is ready. */ 416 void addIfReady(DynInstPtr &inst); 417 418 /** Debugging function to count how many entries are in the IQ. It does 419 * a linear walk through the instructions, so do not call this function 420 * during normal execution. 421 */ 422 int countInsts(); 423 424 /** Debugging function to dump all the list sizes, as well as print 425 * out the list of nonspeculative instructions. Should not be used 426 * in any other capacity, but it has no harmful sideaffects. 427 */ 428 void dumpLists(); 429 430 /** Debugging function to dump out all instructions that are in the 431 * IQ. 432 */ 433 void dumpInsts(); 434 435 /** Stat for number of instructions added. */ 436 Stats::Scalar<> iqInstsAdded; 437 /** Stat for number of non-speculative instructions added. */ 438 Stats::Scalar<> iqNonSpecInstsAdded; 439 440 Stats::Scalar<> iqInstsIssued; 441 /** Stat for number of integer instructions issued. */ 442 Stats::Scalar<> iqIntInstsIssued; 443 /** Stat for number of floating point instructions issued. */ 444 Stats::Scalar<> iqFloatInstsIssued; 445 /** Stat for number of branch instructions issued. */ 446 Stats::Scalar<> iqBranchInstsIssued; 447 /** Stat for number of memory instructions issued. */ 448 Stats::Scalar<> iqMemInstsIssued; 449 /** Stat for number of miscellaneous instructions issued. */ 450 Stats::Scalar<> iqMiscInstsIssued; 451 /** Stat for number of squashed instructions that were ready to issue. */ 452 Stats::Scalar<> iqSquashedInstsIssued; 453 /** Stat for number of squashed instructions examined when squashing. */ 454 Stats::Scalar<> iqSquashedInstsExamined; 455 /** Stat for number of squashed instruction operands examined when 456 * squashing. 457 */ 458 Stats::Scalar<> iqSquashedOperandsExamined; 459 /** Stat for number of non-speculative instructions removed due to a squash. 460 */ 461 Stats::Scalar<> iqSquashedNonSpecRemoved; 462 463 Stats::VectorDistribution<> queueResDist; 464 Stats::Distribution<> numIssuedDist; 465 Stats::VectorDistribution<> issueDelayDist; 466 467 Stats::Vector<> statFuBusy; 468// Stats::Vector<> dist_unissued; 469 Stats::Vector2d<> statIssuedInstType; 470 471 Stats::Formula issueRate; 472// Stats::Formula issue_stores; 473// Stats::Formula issue_op_rate; 474 Stats::Vector<> fuBusy; //cumulative fu busy 475 476 Stats::Formula fuBusyRate; 477}; 478 479#endif //__CPU_O3_INST_QUEUE_HH__ 480