inst_queue.hh revision 2361
16019Shines@cs.fsu.edu/* 27399SAli.Saidi@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37399SAli.Saidi@ARM.com * All rights reserved. 47399SAli.Saidi@ARM.com * 57399SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67399SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77399SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97399SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117399SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127399SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137399SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu */ 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.edu#ifndef __CPU_O3_INST_QUEUE_HH__ 306019Shines@cs.fsu.edu#define __CPU_O3_INST_QUEUE_HH__ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include <list> 336019Shines@cs.fsu.edu#include <map> 346019Shines@cs.fsu.edu#include <queue> 356019Shines@cs.fsu.edu#include <vector> 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edu#include "base/statistics.hh" 386019Shines@cs.fsu.edu#include "base/timebuf.hh" 396019Shines@cs.fsu.edu#include "cpu/inst_seq.hh" 407399SAli.Saidi@ARM.com#include "cpu/o3/dep_graph.hh" 416019Shines@cs.fsu.edu#include "encumbered/cpu/full/op_class.hh" 426019Shines@cs.fsu.edu#include "sim/host.hh" 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.educlass FUPool; 456019Shines@cs.fsu.educlass MemInterface; 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu/** 486019Shines@cs.fsu.edu * A standard instruction queue class. It holds ready instructions, in 496019Shines@cs.fsu.edu * order, in seperate priority queues to facilitate the scheduling of 506019Shines@cs.fsu.edu * instructions. The IQ uses a separate linked list to track dependencies. 516019Shines@cs.fsu.edu * Similar to the rename map and the free list, it expects that 526019Shines@cs.fsu.edu * floating point registers have their indices start after the integer 536019Shines@cs.fsu.edu * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer 546116Snate@binkert.org * and 96-191 are fp). This remains true even for both logical and 556019Shines@cs.fsu.edu * physical register indices. The IQ depends on the memory dependence unit to 566019Shines@cs.fsu.edu * track when memory operations are ready in terms of ordering; register 576019Shines@cs.fsu.edu * dependencies are tracked normally. Right now the IQ also handles the 586019Shines@cs.fsu.edu * execution timing; this is mainly to allow back-to-back scheduling without 596019Shines@cs.fsu.edu * requiring IEW to be able to peek into the IQ. At the end of the execution 606019Shines@cs.fsu.edu * latency, the instruction is put into the queue to execute, where it will 616019Shines@cs.fsu.edu * have the execute() function called on it. 627404SAli.Saidi@ARM.com * @todo: Make IQ able to handle multiple FU pools. 637404SAli.Saidi@ARM.com */ 646019Shines@cs.fsu.edutemplate <class Impl> 656019Shines@cs.fsu.educlass InstructionQueue 667294Sgblack@eecs.umich.edu{ 677294Sgblack@eecs.umich.edu public: 687639Sgblack@eecs.umich.edu //Typedefs from the Impl. 697294Sgblack@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 707294Sgblack@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 717294Sgblack@eecs.umich.edu typedef typename Impl::Params Params; 727294Sgblack@eecs.umich.edu 737294Sgblack@eecs.umich.edu typedef typename Impl::CPUPol::IEW IEW; 747639Sgblack@eecs.umich.edu typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; 757639Sgblack@eecs.umich.edu typedef typename Impl::CPUPol::IssueStruct IssueStruct; 767294Sgblack@eecs.umich.edu typedef typename Impl::CPUPol::TimeStruct TimeStruct; 777639Sgblack@eecs.umich.edu 787404SAli.Saidi@ARM.com // Typedef of iterator through the list of instructions. 797639Sgblack@eecs.umich.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 807294Sgblack@eecs.umich.edu 817294Sgblack@eecs.umich.edu friend class Impl::FullCPU; 827294Sgblack@eecs.umich.edu 837639Sgblack@eecs.umich.edu /** FU completion event class. */ 847294Sgblack@eecs.umich.edu class FUCompletion : public Event { 856019Shines@cs.fsu.edu private: 866019Shines@cs.fsu.edu /** Executing instruction. */ 876019Shines@cs.fsu.edu DynInstPtr inst; 886019Shines@cs.fsu.edu 897404SAli.Saidi@ARM.com /** Index of the FU used for executing. */ 906019Shines@cs.fsu.edu int fuIdx; 916019Shines@cs.fsu.edu 927406SAli.Saidi@ARM.com /** Pointer back to the instruction queue. */ 937436Sdam.sunwoo@arm.com InstructionQueue<Impl> *iqPtr; 947436Sdam.sunwoo@arm.com 957406SAli.Saidi@ARM.com /** Should the FU be added to the list to be freed upon 967404SAli.Saidi@ARM.com * completing this event. 977406SAli.Saidi@ARM.com */ 986019Shines@cs.fsu.edu bool freeFU; 996019Shines@cs.fsu.edu 1007404SAli.Saidi@ARM.com public: 1016019Shines@cs.fsu.edu /** Construct a FU completion event. */ 1027399SAli.Saidi@ARM.com FUCompletion(DynInstPtr &_inst, int fu_idx, 1036020Sgblack@eecs.umich.edu InstructionQueue<Impl> *iq_ptr); 1046020Sgblack@eecs.umich.edu 1056020Sgblack@eecs.umich.edu virtual void process(); 1066020Sgblack@eecs.umich.edu virtual const char *description(); 1076020Sgblack@eecs.umich.edu void setFreeFU() { freeFU = true; } 1086020Sgblack@eecs.umich.edu }; 1096020Sgblack@eecs.umich.edu 1106020Sgblack@eecs.umich.edu /** Constructs an IQ. */ 1116019Shines@cs.fsu.edu InstructionQueue(Params *params); 1126019Shines@cs.fsu.edu 1136019Shines@cs.fsu.edu /** Destructs the IQ. */ 1146019Shines@cs.fsu.edu ~InstructionQueue(); 1157404SAli.Saidi@ARM.com 1166019Shines@cs.fsu.edu /** Returns the name of the IQ. */ 1176019Shines@cs.fsu.edu std::string name() const; 1186019Shines@cs.fsu.edu 1196019Shines@cs.fsu.edu /** Registers statistics. */ 1206019Shines@cs.fsu.edu void regStats(); 1216019Shines@cs.fsu.edu 1226019Shines@cs.fsu.edu /** Resets all instruction queue state. */ 1237404SAli.Saidi@ARM.com void resetState(); 1247404SAli.Saidi@ARM.com 1257404SAli.Saidi@ARM.com /** Sets CPU pointer. */ 1266019Shines@cs.fsu.edu void setCPU(FullCPU *_cpu) { cpu = _cpu; } 1277404SAli.Saidi@ARM.com 1287404SAli.Saidi@ARM.com /** Sets active threads list. */ 1297404SAli.Saidi@ARM.com void setActiveThreads(std::list<unsigned> *at_ptr); 1307404SAli.Saidi@ARM.com 1317404SAli.Saidi@ARM.com /** Sets the IEW pointer. */ 1327404SAli.Saidi@ARM.com void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; } 1337404SAli.Saidi@ARM.com 1347404SAli.Saidi@ARM.com /** Sets the timer buffer between issue and execute. */ 1357404SAli.Saidi@ARM.com void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue); 1367404SAli.Saidi@ARM.com 1377404SAli.Saidi@ARM.com /** Sets the global time buffer. */ 1387404SAli.Saidi@ARM.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1397404SAli.Saidi@ARM.com 1407404SAli.Saidi@ARM.com /** Switches out the instruction queue. */ 1417404SAli.Saidi@ARM.com void switchOut(); 1427404SAli.Saidi@ARM.com 1437404SAli.Saidi@ARM.com /** Takes over execution from another CPU's thread. */ 1447404SAli.Saidi@ARM.com void takeOverFrom(); 1457406SAli.Saidi@ARM.com 1467406SAli.Saidi@ARM.com /** Returns if the IQ is switched out. */ 1477404SAli.Saidi@ARM.com bool isSwitchedOut() { return switchedOut; } 1487404SAli.Saidi@ARM.com 1497404SAli.Saidi@ARM.com /** Number of entries needed for given amount of threads. */ 1506019Shines@cs.fsu.edu int entryAmount(int num_threads); 1516019Shines@cs.fsu.edu 1527404SAli.Saidi@ARM.com /** Resets max entries for all threads. */ 1536019Shines@cs.fsu.edu void resetEntries(); 1546019Shines@cs.fsu.edu 1556019Shines@cs.fsu.edu /** Returns total number of free entries. */ 1566019Shines@cs.fsu.edu unsigned numFreeEntries(); 1577436Sdam.sunwoo@arm.com 1587436Sdam.sunwoo@arm.com /** Returns number of free entries for a thread. */ 1597436Sdam.sunwoo@arm.com unsigned numFreeEntries(unsigned tid); 1607436Sdam.sunwoo@arm.com 1617436Sdam.sunwoo@arm.com /** Returns whether or not the IQ is full. */ 1627436Sdam.sunwoo@arm.com bool isFull(); 1637436Sdam.sunwoo@arm.com 1647436Sdam.sunwoo@arm.com /** Returns whether or not the IQ is full for a specific thread. */ 1657436Sdam.sunwoo@arm.com bool isFull(unsigned tid); 1667436Sdam.sunwoo@arm.com 1677436Sdam.sunwoo@arm.com /** Returns if there are any ready instructions in the IQ. */ 1687436Sdam.sunwoo@arm.com bool hasReadyInsts(); 1697436Sdam.sunwoo@arm.com 1707404SAli.Saidi@ARM.com /** Inserts a new instruction into the IQ. */ 1717404SAli.Saidi@ARM.com void insert(DynInstPtr &new_inst); 1727404SAli.Saidi@ARM.com 1737404SAli.Saidi@ARM.com /** Inserts a new, non-speculative instruction into the IQ. */ 1747404SAli.Saidi@ARM.com void insertNonSpec(DynInstPtr &new_inst); 1757404SAli.Saidi@ARM.com 1767404SAli.Saidi@ARM.com /** Inserts a memory or write barrier into the IQ to make sure 1776116Snate@binkert.org * loads and stores are ordered properly. 1787404SAli.Saidi@ARM.com */ 1796116Snate@binkert.org void insertBarrier(DynInstPtr &barr_inst); 1806116Snate@binkert.org 1816019Shines@cs.fsu.edu /** Returns the oldest scheduled instruction, and removes it from 1826019Shines@cs.fsu.edu * the list of instructions waiting to execute. 1836019Shines@cs.fsu.edu */ 1846019Shines@cs.fsu.edu DynInstPtr getInstToExecute(); 1856019Shines@cs.fsu.edu 1866019Shines@cs.fsu.edu /** 1876019Shines@cs.fsu.edu * Records the instruction as the producer of a register without 1886116Snate@binkert.org * adding it to the rest of the IQ. 1896019Shines@cs.fsu.edu */ 1906019Shines@cs.fsu.edu void recordProducer(DynInstPtr &inst) 191 { addToProducers(inst); } 192 193 /** Process FU completion event. */ 194 void processFUCompletion(DynInstPtr &inst, int fu_idx); 195 196 /** 197 * Schedules ready instructions, adding the ready ones (oldest first) to 198 * the queue to execute. 199 */ 200 void scheduleReadyInsts(); 201 202 /** Schedules a single specific non-speculative instruction. */ 203 void scheduleNonSpec(const InstSeqNum &inst); 204 205 /** 206 * Commits all instructions up to and including the given sequence number, 207 * for a specific thread. 208 */ 209 void commit(const InstSeqNum &inst, unsigned tid = 0); 210 211 /** Wakes all dependents of a completed instruction. */ 212 int wakeDependents(DynInstPtr &completed_inst); 213 214 /** Adds a ready memory instruction to the ready list. */ 215 void addReadyMemInst(DynInstPtr &ready_inst); 216 217 /** 218 * Reschedules a memory instruction. It will be ready to issue once 219 * replayMemInst() is called. 220 */ 221 void rescheduleMemInst(DynInstPtr &resched_inst); 222 223 /** Replays a memory instruction. It must be rescheduled first. */ 224 void replayMemInst(DynInstPtr &replay_inst); 225 226 /** Completes a memory operation. */ 227 void completeMemInst(DynInstPtr &completed_inst); 228 229 /** Indicates an ordering violation between a store and a load. */ 230 void violation(DynInstPtr &store, DynInstPtr &faulting_load); 231 232 /** 233 * Squashes instructions for a thread. Squashing information is obtained 234 * from the time buffer. 235 */ 236 void squash(unsigned tid); 237 238 /** Returns the number of used entries for a thread. */ 239 unsigned getCount(unsigned tid) { return count[tid]; }; 240 241 /** Debug function to print all instructions. */ 242 void printInsts(); 243 244 private: 245 /** Does the actual squashing. */ 246 void doSquash(unsigned tid); 247 248 ///////////////////////// 249 // Various pointers 250 ///////////////////////// 251 252 /** Pointer to the CPU. */ 253 FullCPU *cpu; 254 255 /** Cache interface. */ 256 MemInterface *dcacheInterface; 257 258 /** Pointer to IEW stage. */ 259 IEW *iewStage; 260 261 /** The memory dependence unit, which tracks/predicts memory dependences 262 * between instructions. 263 */ 264 MemDepUnit memDepUnit[Impl::MaxThreads]; 265 266 /** The queue to the execute stage. Issued instructions will be written 267 * into it. 268 */ 269 TimeBuffer<IssueStruct> *issueToExecuteQueue; 270 271 /** The backwards time buffer. */ 272 TimeBuffer<TimeStruct> *timeBuffer; 273 274 /** Wire to read information from timebuffer. */ 275 typename TimeBuffer<TimeStruct>::wire fromCommit; 276 277 /** Function unit pool. */ 278 FUPool *fuPool; 279 280 ////////////////////////////////////// 281 // Instruction lists, ready queues, and ordering 282 ////////////////////////////////////// 283 284 /** List of all the instructions in the IQ (some of which may be issued). */ 285 std::list<DynInstPtr> instList[Impl::MaxThreads]; 286 287 /** List of instructions that are ready to be executed. */ 288 std::list<DynInstPtr> instsToExecute; 289 290 /** 291 * Struct for comparing entries to be added to the priority queue. 292 * This gives reverse ordering to the instructions in terms of 293 * sequence numbers: the instructions with smaller sequence 294 * numbers (and hence are older) will be at the top of the 295 * priority queue. 296 */ 297 struct pqCompare { 298 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const 299 { 300 return lhs->seqNum > rhs->seqNum; 301 } 302 }; 303 304 typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> 305 ReadyInstQueue; 306 307 /** List of ready instructions, per op class. They are separated by op 308 * class to allow for easy mapping to FUs. 309 */ 310 ReadyInstQueue readyInsts[Num_OpClasses]; 311 312 /** List of non-speculative instructions that will be scheduled 313 * once the IQ gets a signal from commit. While it's redundant to 314 * have the key be a part of the value (the sequence number is stored 315 * inside of DynInst), when these instructions are woken up only 316 * the sequence number will be available. Thus it is most efficient to be 317 * able to search by the sequence number alone. 318 */ 319 std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 320 321 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 322 323 /** Entry for the list age ordering by op class. */ 324 struct ListOrderEntry { 325 OpClass queueType; 326 InstSeqNum oldestInst; 327 }; 328 329 /** List that contains the age order of the oldest instruction of each 330 * ready queue. Used to select the oldest instruction available 331 * among op classes. 332 * @todo: Might be better to just move these entries around instead 333 * of creating new ones every time the position changes due to an 334 * instruction issuing. Not sure std::list supports this. 335 */ 336 std::list<ListOrderEntry> listOrder; 337 338 typedef typename std::list<ListOrderEntry>::iterator ListOrderIt; 339 340 /** Tracks if each ready queue is on the age order list. */ 341 bool queueOnList[Num_OpClasses]; 342 343 /** Iterators of each ready queue. Points to their spot in the age order 344 * list. 345 */ 346 ListOrderIt readyIt[Num_OpClasses]; 347 348 /** Add an op class to the age order list. */ 349 void addToOrderList(OpClass op_class); 350 351 /** 352 * Called when the oldest instruction has been removed from a ready queue; 353 * this places that ready queue into the proper spot in the age order list. 354 */ 355 void moveToYoungerInst(ListOrderIt age_order_it); 356 357 DependencyGraph<DynInstPtr> dependGraph; 358 359 ////////////////////////////////////// 360 // Various parameters 361 ////////////////////////////////////// 362 363 /** IQ Resource Sharing Policy */ 364 enum IQPolicy { 365 Dynamic, 366 Partitioned, 367 Threshold 368 }; 369 370 /** IQ sharing policy for SMT. */ 371 IQPolicy iqPolicy; 372 373 /** Number of Total Threads*/ 374 unsigned numThreads; 375 376 /** Pointer to list of active threads. */ 377 std::list<unsigned> *activeThreads; 378 379 /** Per Thread IQ count */ 380 unsigned count[Impl::MaxThreads]; 381 382 /** Max IQ Entries Per Thread */ 383 unsigned maxEntries[Impl::MaxThreads]; 384 385 /** Number of free IQ entries left. */ 386 unsigned freeEntries; 387 388 /** The number of entries in the instruction queue. */ 389 unsigned numEntries; 390 391 /** The total number of instructions that can be issued in one cycle. */ 392 unsigned totalWidth; 393 394 /** The number of physical registers in the CPU. */ 395 unsigned numPhysRegs; 396 397 /** The number of physical integer registers in the CPU. */ 398 unsigned numPhysIntRegs; 399 400 /** The number of floating point registers in the CPU. */ 401 unsigned numPhysFloatRegs; 402 403 /** Delay between commit stage and the IQ. 404 * @todo: Make there be a distinction between the delays within IEW. 405 */ 406 unsigned commitToIEWDelay; 407 408 /** Is the IQ switched out. */ 409 bool switchedOut; 410 411 /** The sequence number of the squashed instruction. */ 412 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 413 414 /** A cache of the recently woken registers. It is 1 if the register 415 * has been woken up recently, and 0 if the register has been added 416 * to the dependency graph and has not yet received its value. It 417 * is basically a secondary scoreboard, and should pretty much mirror 418 * the scoreboard that exists in the rename map. 419 */ 420 std::vector<bool> regScoreboard; 421 422 /** Adds an instruction to the dependency graph, as a consumer. */ 423 bool addToDependents(DynInstPtr &new_inst); 424 425 /** Adds an instruction to the dependency graph, as a producer. */ 426 void addToProducers(DynInstPtr &new_inst); 427 428 /** Moves an instruction to the ready queue if it is ready. */ 429 void addIfReady(DynInstPtr &inst); 430 431 /** Debugging function to count how many entries are in the IQ. It does 432 * a linear walk through the instructions, so do not call this function 433 * during normal execution. 434 */ 435 int countInsts(); 436 437 /** Debugging function to dump all the list sizes, as well as print 438 * out the list of nonspeculative instructions. Should not be used 439 * in any other capacity, but it has no harmful sideaffects. 440 */ 441 void dumpLists(); 442 443 /** Debugging function to dump out all instructions that are in the 444 * IQ. 445 */ 446 void dumpInsts(); 447 448 /** Stat for number of instructions added. */ 449 Stats::Scalar<> iqInstsAdded; 450 /** Stat for number of non-speculative instructions added. */ 451 Stats::Scalar<> iqNonSpecInstsAdded; 452 453 Stats::Scalar<> iqInstsIssued; 454 /** Stat for number of integer instructions issued. */ 455 Stats::Scalar<> iqIntInstsIssued; 456 /** Stat for number of floating point instructions issued. */ 457 Stats::Scalar<> iqFloatInstsIssued; 458 /** Stat for number of branch instructions issued. */ 459 Stats::Scalar<> iqBranchInstsIssued; 460 /** Stat for number of memory instructions issued. */ 461 Stats::Scalar<> iqMemInstsIssued; 462 /** Stat for number of miscellaneous instructions issued. */ 463 Stats::Scalar<> iqMiscInstsIssued; 464 /** Stat for number of squashed instructions that were ready to issue. */ 465 Stats::Scalar<> iqSquashedInstsIssued; 466 /** Stat for number of squashed instructions examined when squashing. */ 467 Stats::Scalar<> iqSquashedInstsExamined; 468 /** Stat for number of squashed instruction operands examined when 469 * squashing. 470 */ 471 Stats::Scalar<> iqSquashedOperandsExamined; 472 /** Stat for number of non-speculative instructions removed due to a squash. 473 */ 474 Stats::Scalar<> iqSquashedNonSpecRemoved; 475 476 /** Distribution of number of instructions in the queue. */ 477// Stats::VectorDistribution<> queueResDist; 478 /** Distribution of the number of instructions issued. */ 479 Stats::Distribution<> numIssuedDist; 480 /** Distribution of the cycles it takes to issue an instruction. */ 481// Stats::VectorDistribution<> issueDelayDist; 482 483 /** Number of times an instruction could not be issued because a 484 * FU was busy. 485 */ 486 Stats::Vector<> statFuBusy; 487// Stats::Vector<> dist_unissued; 488 /** Stat for total number issued for each instruction type. */ 489 Stats::Vector2d<> statIssuedInstType; 490 491 /** Number of instructions issued per cycle. */ 492 Stats::Formula issueRate; 493 /** Number of times the FU was busy. */ 494 Stats::Vector<> fuBusy; 495 /** Number of times the FU was busy per instruction issued. */ 496 Stats::Formula fuBusyRate; 497}; 498 499#endif //__CPU_O3_INST_QUEUE_HH__ 500