inst_queue.hh revision 2333
12623SN/A/*
22623SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282665Ssaidi@eecs.umich.edu
292623SN/A#ifndef __CPU_O3_INST_QUEUE_HH__
302623SN/A#define __CPU_O3_INST_QUEUE_HH__
313170Sstever@eecs.umich.edu
325103Ssaidi@eecs.umich.edu#include <list>
332623SN/A#include <map>
344040Ssaidi@eecs.umich.edu#include <queue>
356658Snate@binkert.org#include <vector>
362623SN/A
372623SN/A#include "base/statistics.hh"
383348Sbinkertn@umich.edu#include "base/timebuf.hh"
393348Sbinkertn@umich.edu#include "cpu/inst_seq.hh"
404762Snate@binkert.org#include "cpu/o3/dep_graph.hh"
412901Ssaidi@eecs.umich.edu#include "encumbered/cpu/full/op_class.hh"
422623SN/A#include "sim/host.hh"
432623SN/A
442623SN/Aclass FUPool;
452623SN/Aclass MemInterface;
462856Srdreslin@umich.edu
472856Srdreslin@umich.edu/**
482856Srdreslin@umich.edu * A standard instruction queue class.  It holds ready instructions, in
492856Srdreslin@umich.edu * order, in seperate priority queues to facilitate the scheduling of
502856Srdreslin@umich.edu * instructions.  The IQ uses a separate linked list to track dependencies.
512856Srdreslin@umich.edu * Similar to the rename map and the free list, it expects that
522856Srdreslin@umich.edu * floating point registers have their indices start after the integer
532856Srdreslin@umich.edu * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
542856Srdreslin@umich.edu * and 96-191 are fp).  This remains true even for both logical and
552856Srdreslin@umich.edu * physical register indices. The IQ depends on the memory dependence unit to
562623SN/A * track when memory operations are ready in terms of ordering; register
572623SN/A * dependencies are tracked normally. Right now the IQ also handles the
582623SN/A * execution timing; this is mainly to allow back-to-back scheduling without
592623SN/A * requiring IEW to be able to peek into the IQ. At the end of the execution
602623SN/A * latency, the instruction is put into the queue to execute, where it will
612623SN/A * have the execute() function called on it.
622680Sktlim@umich.edu * @todo: Make IQ able to handle multiple FU pools.
632680Sktlim@umich.edu */
642623SN/Atemplate <class Impl>
652623SN/Aclass InstructionQueue
665712Shsul@eecs.umich.edu{
672623SN/A  public:
682623SN/A    //Typedefs from the Impl.
692623SN/A    typedef typename Impl::FullCPU FullCPU;
702623SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
712623SN/A    typedef typename Impl::Params Params;
723349Sbinkertn@umich.edu
732623SN/A    typedef typename Impl::CPUPol::IEW IEW;
742623SN/A    typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
752623SN/A    typedef typename Impl::CPUPol::IssueStruct IssueStruct;
762623SN/A    typedef typename Impl::CPUPol::TimeStruct TimeStruct;
772623SN/A
782623SN/A    // Typedef of iterator through the list of instructions.
793349Sbinkertn@umich.edu    typedef typename std::list<DynInstPtr>::iterator ListIt;
802623SN/A
813184Srdreslin@umich.edu    friend class Impl::FullCPU;
823184Srdreslin@umich.edu
832623SN/A    /** FU completion event class. */
842623SN/A    class FUCompletion : public Event {
852623SN/A      private:
862623SN/A        /** Executing instruction. */
872623SN/A        DynInstPtr inst;
883647Srdreslin@umich.edu
893647Srdreslin@umich.edu        /** Index of the FU used for executing. */
903647Srdreslin@umich.edu        int fuIdx;
913647Srdreslin@umich.edu
923647Srdreslin@umich.edu        /** Pointer back to the instruction queue. */
932631SN/A        InstructionQueue<Impl> *iqPtr;
943647Srdreslin@umich.edu
952631SN/A        bool freeFU;
962623SN/A
972623SN/A      public:
982623SN/A        /** Construct a FU completion event. */
992948Ssaidi@eecs.umich.edu        FUCompletion(DynInstPtr &_inst, int fu_idx,
1002948Ssaidi@eecs.umich.edu                     InstructionQueue<Impl> *iq_ptr);
1013349Sbinkertn@umich.edu
1022948Ssaidi@eecs.umich.edu        virtual void process();
1032948Ssaidi@eecs.umich.edu        virtual const char *description();
1045606Snate@binkert.org        void setFreeFU() { freeFU = true; }
1052948Ssaidi@eecs.umich.edu    };
1062948Ssaidi@eecs.umich.edu
1075529Snate@binkert.org    /** Constructs an IQ. */
1085894Sgblack@eecs.umich.edu    InstructionQueue(Params *params);
1095894Sgblack@eecs.umich.edu
1102623SN/A    /** Destructs the IQ. */
1112623SN/A    ~InstructionQueue();
1123647Srdreslin@umich.edu
1133647Srdreslin@umich.edu    /** Returns the name of the IQ. */
1143647Srdreslin@umich.edu    std::string name() const;
1153647Srdreslin@umich.edu
1162623SN/A    /** Registers statistics. */
1172839Sktlim@umich.edu    void regStats();
1183222Sktlim@umich.edu
1192901Ssaidi@eecs.umich.edu    void resetState();
1202623SN/A
1212623SN/A    /** Sets CPU pointer. */
1222623SN/A    void setCPU(FullCPU *_cpu) { cpu = _cpu; }
1232623SN/A
1242623SN/A    /** Sets active threads list. */
1252623SN/A    void setActiveThreads(std::list<unsigned> *at_ptr);
1262623SN/A
1272623SN/A    /** Sets the IEW pointer. */
1282623SN/A    void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
1292623SN/A
1302915Sktlim@umich.edu    /** Sets the timer buffer between issue and execute. */
1312915Sktlim@umich.edu    void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
1322623SN/A
1332623SN/A    /** Sets the global time buffer. */
1342623SN/A    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
1352623SN/A
1362623SN/A    void switchOut();
1372623SN/A
1382915Sktlim@umich.edu    void takeOverFrom();
1392915Sktlim@umich.edu
1402623SN/A    bool isSwitchedOut() { return switchedOut; }
1412798Sktlim@umich.edu
1422798Sktlim@umich.edu    /** Number of entries needed for given amount of threads. */
1432901Ssaidi@eecs.umich.edu    int entryAmount(int num_threads);
1442839Sktlim@umich.edu
1452798Sktlim@umich.edu    /** Resets max entries for all threads. */
1462839Sktlim@umich.edu    void resetEntries();
1472798Sktlim@umich.edu
1485496Ssaidi@eecs.umich.edu    /** Returns total number of free entries. */
1492901Ssaidi@eecs.umich.edu    unsigned numFreeEntries();
1502901Ssaidi@eecs.umich.edu
1512798Sktlim@umich.edu    /** Returns number of free entries for a thread. */
1522839Sktlim@umich.edu    unsigned numFreeEntries(unsigned tid);
1532839Sktlim@umich.edu
1542901Ssaidi@eecs.umich.edu    /** Returns whether or not the IQ is full. */
1552798Sktlim@umich.edu    bool isFull();
1562623SN/A
1572623SN/A    /** Returns whether or not the IQ is full for a specific thread. */
1582623SN/A    bool isFull(unsigned tid);
1592798Sktlim@umich.edu
1602623SN/A    /** Returns if there are any ready instructions in the IQ. */
1615221Ssaidi@eecs.umich.edu    bool hasReadyInsts();
1622798Sktlim@umich.edu
1634762Snate@binkert.org    /** Inserts a new instruction into the IQ. */
1643201Shsul@eecs.umich.edu    void insert(DynInstPtr &new_inst);
1655710Scws3k@cs.virginia.edu
1665710Scws3k@cs.virginia.edu    /** Inserts a new, non-speculative instruction into the IQ. */
1672915Sktlim@umich.edu    void insertNonSpec(DynInstPtr &new_inst);
1685710Scws3k@cs.virginia.edu
1692623SN/A    /** Inserts a memory or write barrier into the IQ to make sure
1702798Sktlim@umich.edu     *  loads and stores are ordered properly.
1712901Ssaidi@eecs.umich.edu     */
1722798Sktlim@umich.edu    void insertBarrier(DynInstPtr &barr_inst);
1732798Sktlim@umich.edu
1742798Sktlim@umich.edu    DynInstPtr getInstToExecute();
1752798Sktlim@umich.edu
1762798Sktlim@umich.edu    /**
1775496Ssaidi@eecs.umich.edu     * Records the instruction as the producer of a register without
1782798Sktlim@umich.edu     * adding it to the rest of the IQ.
1795099Ssaidi@eecs.umich.edu     */
1802867Sktlim@umich.edu    void recordProducer(DynInstPtr &inst)
1812867Sktlim@umich.edu    { addToProducers(inst); }
1822867Sktlim@umich.edu
1835710Scws3k@cs.virginia.edu    /** Process FU completion event. */
1845606Snate@binkert.org    void processFUCompletion(DynInstPtr &inst, int fu_idx);
1852623SN/A
1862623SN/A    /**
1872623SN/A     * Schedules ready instructions, adding the ready ones (oldest first) to
1882623SN/A     * the queue to execute.
1892623SN/A     */
1902623SN/A    void scheduleReadyInsts();
1914192Sktlim@umich.edu
1922623SN/A    /** Schedules a single specific non-speculative instruction. */
1932680Sktlim@umich.edu    void scheduleNonSpec(const InstSeqNum &inst);
1942623SN/A
1952680Sktlim@umich.edu    /**
1962680Sktlim@umich.edu     * Commits all instructions up to and including the given sequence number,
1972680Sktlim@umich.edu     * for a specific thread.
1982623SN/A     */
1992623SN/A    void commit(const InstSeqNum &inst, unsigned tid = 0);
2002623SN/A
2012623SN/A    /** Wakes all dependents of a completed instruction. */
2023201Shsul@eecs.umich.edu    int wakeDependents(DynInstPtr &completed_inst);
2033201Shsul@eecs.umich.edu
2043201Shsul@eecs.umich.edu    /** Adds a ready memory instruction to the ready list. */
2053201Shsul@eecs.umich.edu    void addReadyMemInst(DynInstPtr &ready_inst);
2065169Ssaidi@eecs.umich.edu
2075101Ssaidi@eecs.umich.edu    /**
2082623SN/A     * Reschedules a memory instruction. It will be ready to issue once
2092623SN/A     * replayMemInst() is called.
2102623SN/A     */
2112623SN/A    void rescheduleMemInst(DynInstPtr &resched_inst);
2122623SN/A
2132623SN/A    /** Replays a memory instruction. It must be rescheduled first. */
2145221Ssaidi@eecs.umich.edu    void replayMemInst(DynInstPtr &replay_inst);
2155221Ssaidi@eecs.umich.edu
2162623SN/A    /** Completes a memory operation. */
2172683Sktlim@umich.edu    void completeMemInst(DynInstPtr &completed_inst);
2182623SN/A
2192623SN/A    /** Indicates an ordering violation between a store and a load. */
2202623SN/A    void violation(DynInstPtr &store, DynInstPtr &faulting_load);
2212623SN/A
2222623SN/A    /**
2233686Sktlim@umich.edu     * Squashes instructions for a thread. Squashing information is obtained
2242623SN/A     * from the time buffer.
2255606Snate@binkert.org     */
2262623SN/A    void squash(unsigned tid);
2272623SN/A
2282623SN/A    /** Returns the number of used entries for a thread. */
2292623SN/A    unsigned getCount(unsigned tid) { return count[tid]; };
2302623SN/A
2312623SN/A    /** Debug function to print all instructions. */
2325221Ssaidi@eecs.umich.edu    void printInsts();
2335221Ssaidi@eecs.umich.edu
2342623SN/A  private:
2352683Sktlim@umich.edu    /** Does the actual squashing. */
2362623SN/A    void doSquash(unsigned tid);
2376043Sgblack@eecs.umich.edu
2386043Sgblack@eecs.umich.edu    /////////////////////////
2396043Sgblack@eecs.umich.edu    // Various pointers
2402644Sstever@eecs.umich.edu    /////////////////////////
2412623SN/A
2422644Sstever@eecs.umich.edu    /** Pointer to the CPU. */
2432644Sstever@eecs.umich.edu    FullCPU *cpu;
2442623SN/A
2452623SN/A    /** Cache interface. */
2462623SN/A    MemInterface *dcacheInterface;
2472623SN/A
2482623SN/A    /** Pointer to IEW stage. */
2495728Sgblack@eecs.umich.edu    IEW *iewStage;
2505728Sgblack@eecs.umich.edu
2515728Sgblack@eecs.umich.edu    /** The memory dependence unit, which tracks/predicts memory dependences
2525728Sgblack@eecs.umich.edu     *  between instructions.
2535728Sgblack@eecs.umich.edu     */
2545728Sgblack@eecs.umich.edu    MemDepUnit memDepUnit[Impl::MaxThreads];
2555728Sgblack@eecs.umich.edu
2565728Sgblack@eecs.umich.edu    /** The queue to the execute stage.  Issued instructions will be written
2575728Sgblack@eecs.umich.edu     *  into it.
2585728Sgblack@eecs.umich.edu     */
2595728Sgblack@eecs.umich.edu    TimeBuffer<IssueStruct> *issueToExecuteQueue;
2605728Sgblack@eecs.umich.edu
2615728Sgblack@eecs.umich.edu    /** The backwards time buffer. */
2625728Sgblack@eecs.umich.edu    TimeBuffer<TimeStruct> *timeBuffer;
2635728Sgblack@eecs.umich.edu
2645728Sgblack@eecs.umich.edu    /** Wire to read information from timebuffer. */
2655728Sgblack@eecs.umich.edu    typename TimeBuffer<TimeStruct>::wire fromCommit;
2665728Sgblack@eecs.umich.edu
2675728Sgblack@eecs.umich.edu    /** Function unit pool. */
2685728Sgblack@eecs.umich.edu    FUPool *fuPool;
2692623SN/A
2705894Sgblack@eecs.umich.edu    //////////////////////////////////////
2715894Sgblack@eecs.umich.edu    // Instruction lists, ready queues, and ordering
2725894Sgblack@eecs.umich.edu    //////////////////////////////////////
2735744Sgblack@eecs.umich.edu
2745894Sgblack@eecs.umich.edu    /** List of all the instructions in the IQ (some of which may be issued). */
2755894Sgblack@eecs.umich.edu    std::list<DynInstPtr> instList[Impl::MaxThreads];
2765894Sgblack@eecs.umich.edu
2775894Sgblack@eecs.umich.edu    std::list<DynInstPtr> instsToExecute;
2785744Sgblack@eecs.umich.edu
2795894Sgblack@eecs.umich.edu    /**
2805894Sgblack@eecs.umich.edu     * Struct for comparing entries to be added to the priority queue.  This
2815894Sgblack@eecs.umich.edu     * gives reverse ordering to the instructions in terms of sequence
2825894Sgblack@eecs.umich.edu     * numbers: the instructions with smaller sequence numbers (and hence
2835894Sgblack@eecs.umich.edu     * are older) will be at the top of the priority queue.
2845894Sgblack@eecs.umich.edu     */
2855894Sgblack@eecs.umich.edu    struct pqCompare {
2865894Sgblack@eecs.umich.edu        bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
2875894Sgblack@eecs.umich.edu        {
2885894Sgblack@eecs.umich.edu            return lhs->seqNum > rhs->seqNum;
2895894Sgblack@eecs.umich.edu        }
2905894Sgblack@eecs.umich.edu    };
2915894Sgblack@eecs.umich.edu
2925894Sgblack@eecs.umich.edu    typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
2935894Sgblack@eecs.umich.edu    ReadyInstQueue;
2946102Sgblack@eecs.umich.edu
2955894Sgblack@eecs.umich.edu    /** List of ready instructions, per op class.  They are separated by op
2965894Sgblack@eecs.umich.edu     *  class to allow for easy mapping to FUs.
2975894Sgblack@eecs.umich.edu     */
2985894Sgblack@eecs.umich.edu    ReadyInstQueue readyInsts[Num_OpClasses];
2995894Sgblack@eecs.umich.edu
3005894Sgblack@eecs.umich.edu    /** List of non-speculative instructions that will be scheduled
3015894Sgblack@eecs.umich.edu     *  once the IQ gets a signal from commit.  While it's redundant to
3025894Sgblack@eecs.umich.edu     *  have the key be a part of the value (the sequence number is stored
3035894Sgblack@eecs.umich.edu     *  inside of DynInst), when these instructions are woken up only
3045894Sgblack@eecs.umich.edu     *  the sequence number will be available.  Thus it is most efficient to be
3055894Sgblack@eecs.umich.edu     *  able to search by the sequence number alone.
3065894Sgblack@eecs.umich.edu     */
3075894Sgblack@eecs.umich.edu    std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
3085894Sgblack@eecs.umich.edu
3095894Sgblack@eecs.umich.edu    typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
3105894Sgblack@eecs.umich.edu
3115894Sgblack@eecs.umich.edu    /** Entry for the list age ordering by op class. */
3125894Sgblack@eecs.umich.edu    struct ListOrderEntry {
3135894Sgblack@eecs.umich.edu        OpClass queueType;
3145894Sgblack@eecs.umich.edu        InstSeqNum oldestInst;
3155894Sgblack@eecs.umich.edu    };
3165894Sgblack@eecs.umich.edu
3175894Sgblack@eecs.umich.edu    /** List that contains the age order of the oldest instruction of each
3185894Sgblack@eecs.umich.edu     *  ready queue.  Used to select the oldest instruction available
3195890Sgblack@eecs.umich.edu     *  among op classes.
3205894Sgblack@eecs.umich.edu     *  @todo: Might be better to just move these entries around instead
3215894Sgblack@eecs.umich.edu     *  of creating new ones every time the position changes due to an
3225894Sgblack@eecs.umich.edu     *  instruction issuing.  Not sure std::list supports this.
3235894Sgblack@eecs.umich.edu     */
3245894Sgblack@eecs.umich.edu    std::list<ListOrderEntry> listOrder;
3255894Sgblack@eecs.umich.edu
3265894Sgblack@eecs.umich.edu    typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
3275894Sgblack@eecs.umich.edu
3285894Sgblack@eecs.umich.edu    /** Tracks if each ready queue is on the age order list. */
3295894Sgblack@eecs.umich.edu    bool queueOnList[Num_OpClasses];
3305894Sgblack@eecs.umich.edu
3315894Sgblack@eecs.umich.edu    /** Iterators of each ready queue.  Points to their spot in the age order
3325894Sgblack@eecs.umich.edu     *  list.
3335894Sgblack@eecs.umich.edu     */
3345894Sgblack@eecs.umich.edu    ListOrderIt readyIt[Num_OpClasses];
3355894Sgblack@eecs.umich.edu
3365894Sgblack@eecs.umich.edu    /** Add an op class to the age order list. */
3375894Sgblack@eecs.umich.edu    void addToOrderList(OpClass op_class);
3385894Sgblack@eecs.umich.edu
3395894Sgblack@eecs.umich.edu    /**
3405894Sgblack@eecs.umich.edu     * Called when the oldest instruction has been removed from a ready queue;
3415894Sgblack@eecs.umich.edu     * this places that ready queue into the proper spot in the age order list.
3425894Sgblack@eecs.umich.edu     */
3435894Sgblack@eecs.umich.edu    void moveToYoungerInst(ListOrderIt age_order_it);
3445894Sgblack@eecs.umich.edu
3455894Sgblack@eecs.umich.edu    DependencyGraph<DynInstPtr> dependGraph;
3465894Sgblack@eecs.umich.edu
3475894Sgblack@eecs.umich.edu    //////////////////////////////////////
3485894Sgblack@eecs.umich.edu    // Various parameters
3495894Sgblack@eecs.umich.edu    //////////////////////////////////////
3505894Sgblack@eecs.umich.edu
3515894Sgblack@eecs.umich.edu    /** IQ Resource Sharing Policy */
3525894Sgblack@eecs.umich.edu    enum IQPolicy {
3535894Sgblack@eecs.umich.edu        Dynamic,
3545894Sgblack@eecs.umich.edu        Partitioned,
3555894Sgblack@eecs.umich.edu        Threshold
3565894Sgblack@eecs.umich.edu    };
3575894Sgblack@eecs.umich.edu
3585894Sgblack@eecs.umich.edu    /** IQ sharing policy for SMT. */
3595894Sgblack@eecs.umich.edu    IQPolicy iqPolicy;
3605894Sgblack@eecs.umich.edu
3615894Sgblack@eecs.umich.edu    /** Number of Total Threads*/
3625894Sgblack@eecs.umich.edu    unsigned numThreads;
3635894Sgblack@eecs.umich.edu
3645894Sgblack@eecs.umich.edu    /** Pointer to list of active threads. */
3655894Sgblack@eecs.umich.edu    std::list<unsigned> *activeThreads;
3665894Sgblack@eecs.umich.edu
3675894Sgblack@eecs.umich.edu    /** Per Thread IQ count */
3685894Sgblack@eecs.umich.edu    unsigned count[Impl::MaxThreads];
3695894Sgblack@eecs.umich.edu
3705744Sgblack@eecs.umich.edu    /** Max IQ Entries Per Thread */
3715744Sgblack@eecs.umich.edu    unsigned maxEntries[Impl::MaxThreads];
3725894Sgblack@eecs.umich.edu
3735894Sgblack@eecs.umich.edu    /** Number of free IQ entries left. */
3745894Sgblack@eecs.umich.edu    unsigned freeEntries;
3755894Sgblack@eecs.umich.edu
3765894Sgblack@eecs.umich.edu    /** The number of entries in the instruction queue. */
3775894Sgblack@eecs.umich.edu    unsigned numEntries;
3785894Sgblack@eecs.umich.edu
3795894Sgblack@eecs.umich.edu    /** The total number of instructions that can be issued in one cycle. */
3805894Sgblack@eecs.umich.edu    unsigned totalWidth;
3815894Sgblack@eecs.umich.edu
3825894Sgblack@eecs.umich.edu    /** The number of physical registers in the CPU. */
3835894Sgblack@eecs.umich.edu    unsigned numPhysRegs;
3845894Sgblack@eecs.umich.edu
3855894Sgblack@eecs.umich.edu    /** The number of physical integer registers in the CPU. */
3865894Sgblack@eecs.umich.edu    unsigned numPhysIntRegs;
3875894Sgblack@eecs.umich.edu
3886102Sgblack@eecs.umich.edu    /** The number of floating point registers in the CPU. */
3895894Sgblack@eecs.umich.edu    unsigned numPhysFloatRegs;
3905894Sgblack@eecs.umich.edu
3915894Sgblack@eecs.umich.edu    /** Delay between commit stage and the IQ.
3926102Sgblack@eecs.umich.edu     *  @todo: Make there be a distinction between the delays within IEW.
3935894Sgblack@eecs.umich.edu     */
3945894Sgblack@eecs.umich.edu    unsigned commitToIEWDelay;
3955894Sgblack@eecs.umich.edu
3965894Sgblack@eecs.umich.edu    bool switchedOut;
3975894Sgblack@eecs.umich.edu
3985894Sgblack@eecs.umich.edu    /** The sequence number of the squashed instruction. */
3995894Sgblack@eecs.umich.edu    InstSeqNum squashedSeqNum[Impl::MaxThreads];
4005894Sgblack@eecs.umich.edu
4015894Sgblack@eecs.umich.edu    /** A cache of the recently woken registers.  It is 1 if the register
4025894Sgblack@eecs.umich.edu     *  has been woken up recently, and 0 if the register has been added
4035894Sgblack@eecs.umich.edu     *  to the dependency graph and has not yet received its value.  It
4045894Sgblack@eecs.umich.edu     *  is basically a secondary scoreboard, and should pretty much mirror
4055894Sgblack@eecs.umich.edu     *  the scoreboard that exists in the rename map.
4065894Sgblack@eecs.umich.edu     */
4075894Sgblack@eecs.umich.edu    std::vector<bool> regScoreboard;
4085744Sgblack@eecs.umich.edu
4095744Sgblack@eecs.umich.edu    /** Adds an instruction to the dependency graph, as a consumer. */
4105894Sgblack@eecs.umich.edu    bool addToDependents(DynInstPtr &new_inst);
4115894Sgblack@eecs.umich.edu
4125894Sgblack@eecs.umich.edu    /** Adds an instruction to the dependency graph, as a producer. */
4135894Sgblack@eecs.umich.edu    void addToProducers(DynInstPtr &new_inst);
4145894Sgblack@eecs.umich.edu
4155894Sgblack@eecs.umich.edu    /** Moves an instruction to the ready queue if it is ready. */
4165894Sgblack@eecs.umich.edu    void addIfReady(DynInstPtr &inst);
4175894Sgblack@eecs.umich.edu
4185744Sgblack@eecs.umich.edu    /** Debugging function to count how many entries are in the IQ.  It does
4195744Sgblack@eecs.umich.edu     *  a linear walk through the instructions, so do not call this function
4205744Sgblack@eecs.umich.edu     *  during normal execution.
4215744Sgblack@eecs.umich.edu     */
4225744Sgblack@eecs.umich.edu    int countInsts();
4235744Sgblack@eecs.umich.edu
4245744Sgblack@eecs.umich.edu    /** Debugging function to dump all the list sizes, as well as print
4255744Sgblack@eecs.umich.edu     *  out the list of nonspeculative instructions.  Should not be used
4265744Sgblack@eecs.umich.edu     *  in any other capacity, but it has no harmful sideaffects.
4275744Sgblack@eecs.umich.edu     */
4285744Sgblack@eecs.umich.edu    void dumpLists();
4295744Sgblack@eecs.umich.edu
4305744Sgblack@eecs.umich.edu    /** Debugging function to dump out all instructions that are in the
4315744Sgblack@eecs.umich.edu     *  IQ.
4325744Sgblack@eecs.umich.edu     */
4335744Sgblack@eecs.umich.edu    void dumpInsts();
4345744Sgblack@eecs.umich.edu
4352623SN/A    /** Stat for number of instructions added. */
4362623SN/A    Stats::Scalar<> iqInstsAdded;
4372623SN/A    /** Stat for number of non-speculative instructions added. */
4382623SN/A    Stats::Scalar<> iqNonSpecInstsAdded;
4395728Sgblack@eecs.umich.edu
4405728Sgblack@eecs.umich.edu    Stats::Scalar<> iqInstsIssued;
4416221Snate@binkert.org    /** Stat for number of integer instructions issued. */
4425728Sgblack@eecs.umich.edu    Stats::Scalar<> iqIntInstsIssued;
4436227Snate@binkert.org    /** Stat for number of floating point instructions issued. */
4445728Sgblack@eecs.umich.edu    Stats::Scalar<> iqFloatInstsIssued;
4452623SN/A    /** Stat for number of branch instructions issued. */
4465744Sgblack@eecs.umich.edu    Stats::Scalar<> iqBranchInstsIssued;
4476221Snate@binkert.org    /** Stat for number of memory instructions issued. */
4485728Sgblack@eecs.umich.edu    Stats::Scalar<> iqMemInstsIssued;
4495744Sgblack@eecs.umich.edu    /** Stat for number of miscellaneous instructions issued. */
4505744Sgblack@eecs.umich.edu    Stats::Scalar<> iqMiscInstsIssued;
4515728Sgblack@eecs.umich.edu    /** Stat for number of squashed instructions that were ready to issue. */
4525894Sgblack@eecs.umich.edu    Stats::Scalar<> iqSquashedInstsIssued;
4535894Sgblack@eecs.umich.edu    /** Stat for number of squashed instructions examined when squashing. */
4545744Sgblack@eecs.umich.edu    Stats::Scalar<> iqSquashedInstsExamined;
4555894Sgblack@eecs.umich.edu    /** Stat for number of squashed instruction operands examined when
4566102Sgblack@eecs.umich.edu     * squashing.
4575894Sgblack@eecs.umich.edu     */
4585894Sgblack@eecs.umich.edu    Stats::Scalar<> iqSquashedOperandsExamined;
4595894Sgblack@eecs.umich.edu    /** Stat for number of non-speculative instructions removed due to a squash.
4605894Sgblack@eecs.umich.edu     */
4616023Snate@binkert.org    Stats::Scalar<> iqSquashedNonSpecRemoved;
4625894Sgblack@eecs.umich.edu
4636023Snate@binkert.org    Stats::VectorDistribution<> queueResDist;
4645894Sgblack@eecs.umich.edu    Stats::Distribution<> numIssuedDist;
4656023Snate@binkert.org    Stats::VectorDistribution<> issueDelayDist;
4665744Sgblack@eecs.umich.edu
4676023Snate@binkert.org    Stats::Vector<> statFuBusy;
4686023Snate@binkert.org//    Stats::Vector<> dist_unissued;
4696023Snate@binkert.org    Stats::Vector2d<> statIssuedInstType;
4702623SN/A
4712623SN/A    Stats::Formula issueRate;
4725408Sgblack@eecs.umich.edu//    Stats::Formula issue_stores;
4735408Sgblack@eecs.umich.edu//    Stats::Formula issue_op_rate;
4745728Sgblack@eecs.umich.edu    Stats::Vector<> fuBusy;  //cumulative fu busy
4755408Sgblack@eecs.umich.edu
4765728Sgblack@eecs.umich.edu    Stats::Formula fuBusyRate;
4775728Sgblack@eecs.umich.edu};
4785728Sgblack@eecs.umich.edu
4795728Sgblack@eecs.umich.edu#endif //__CPU_O3_INST_QUEUE_HH__
4805728Sgblack@eecs.umich.edu