impl.hh revision 5595 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __CPU_O3_SPARC_IMPL_HH__
32#define __CPU_O3_SPARC_IMPL_HH__
33
34#include "arch/sparc/isa_traits.hh"
35
36#include "cpu/o3/cpu_policy.hh"
37
38
39// Forward declarations.
40template <class Impl>
41class SparcDynInst;
42
43template <class Impl>
44class FullO3CPU;
45
46/** Implementation specific struct that defines several key types to the
47 *  CPU, the stages within the CPU, the time buffers, and the DynInst.
48 *  The struct defines the ISA, the CPU policy, the specific DynInst, the
49 *  specific O3CPU, and all of the structs from the time buffers to do
50 *  communication.
51 *  This is one of the key things that must be defined for each hardware
52 *  specific CPU implementation.
53 */
54struct SparcSimpleImpl
55{
56    /** The type of MachInst. */
57    typedef TheISA::MachInst MachInst;
58
59    /** The CPU policy to be used, which defines all of the CPU stages. */
60    typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol;
61
62    /** The DynInst type to be used. */
63    typedef SparcDynInst<SparcSimpleImpl> DynInst;
64
65    /** The refcounted DynInst pointer to be used.  In most cases this is
66     *  what should be used, and not DynInst *.
67     */
68    typedef RefCountingPtr<DynInst> DynInstPtr;
69
70    /** The O3CPU type to be used. */
71    typedef FullO3CPU<SparcSimpleImpl> O3CPU;
72
73    /** Same typedef, but for CPUType.  BaseDynInst may not always use
74     * an O3 CPU, so it's clearer to call it CPUType instead in that
75     * case.
76     */
77    typedef O3CPU CPUType;
78
79    enum {
80      MaxWidth = 8,
81      MaxThreads = 4
82    };
83};
84
85/** The O3Impl to be used. */
86typedef SparcSimpleImpl O3CPUImpl;
87
88#endif // __CPU_O3_SPARC_IMPL_HH__
89