impl.hh revision 13429:a1e199fd8122
12SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
292665Ssaidi@eecs.umich.edu */
302SN/A
312SN/A#ifndef __CPU_O3_IMPL_HH__
322SN/A#define __CPU_O3_IMPL_HH__
332SN/A
342SN/A#include "arch/isa_traits.hh"
352SN/A#include "config/the_isa.hh"
362SN/A#include "cpu/o3/cpu_policy.hh"
372SN/A
382SN/A// Forward declarations.
392SN/Atemplate <class Impl>
402SN/Aclass BaseO3DynInst;
412SN/A
422SN/Atemplate <class Impl>
432SN/Aclass FullO3CPU;
444762Snate@binkert.org
4556SN/A/** Implementation specific struct that defines several key types to the
461127SN/A *  CPU, the stages within the CPU, the time buffers, and the DynInst.
472SN/A *  The struct defines the ISA, the CPU policy, the specific DynInst, the
482797Sktlim@umich.edu *  specific O3CPU, and all of the structs from the time buffers to do
492797Sktlim@umich.edu *  communication.
502609SN/A *  This is one of the key things that must be defined for each hardware
512SN/A *  specific CPU implementation.
522SN/A */
532SN/Astruct O3CPUImpl
542SN/A{
552SN/A    /** The type of MachInst. */
561127SN/A    typedef TheISA::MachInst MachInst;
572SN/A
581553SN/A    /** The CPU policy to be used, which defines all of the CPU stages. */
592797Sktlim@umich.edu    typedef SimpleCPUPolicy<O3CPUImpl> CPUPol;
602901Ssaidi@eecs.umich.edu
612839Sktlim@umich.edu    /** The DynInst type to be used. */
622901Ssaidi@eecs.umich.edu    typedef BaseO3DynInst<O3CPUImpl> DynInst;
632797Sktlim@umich.edu
643202Shsul@eecs.umich.edu    /** The refcounted DynInst pointer to be used.  In most cases this is
652901Ssaidi@eecs.umich.edu     *  what should be used, and not DynInst *.
662901Ssaidi@eecs.umich.edu     */
672797Sktlim@umich.edu    typedef RefCountingPtr<DynInst> DynInstPtr;
68265SN/A    typedef RefCountingPtr<const DynInst> DynInstConstPtr;
692797Sktlim@umich.edu
701553SN/A    /** The O3CPU type to be used. */
711553SN/A    typedef FullO3CPU<O3CPUImpl> O3CPU;
722797Sktlim@umich.edu
732797Sktlim@umich.edu    /** Same typedef, but for CPUType.  BaseDynInst may not always use
742SN/A     * an O3 CPU, so it's clearer to call it CPUType instead in that
752SN/A     * case.
762SN/A     */
772SN/A    typedef O3CPU CPUType;
782SN/A
792SN/A    enum {
804762Snate@binkert.org      MaxWidth = 8,
814762Snate@binkert.org      MaxThreads = 4
824762Snate@binkert.org    };
832SN/A};
844762Snate@binkert.org
854762Snate@binkert.org#endif // __CPU_O3_SPARC_IMPL_HH__
864762Snate@binkert.org