iew_impl.hh revision 9046 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "arch/utility.hh"
50#include "config/the_isa.hh"
51#include "cpu/checker/cpu.hh"
52#include "cpu/o3/fu_pool.hh"
53#include "cpu/o3/iew.hh"
54#include "cpu/timebuf.hh"
55#include "debug/Activity.hh"
56#include "debug/Decode.hh"
57#include "debug/IEW.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template<class Impl>
63DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
64    : issueToExecQueue(params->backComSize, params->forwardComSize),
65      cpu(_cpu),
66      instQueue(_cpu, this, params),
67      ldstQueue(_cpu, this, params),
68      fuPool(params->fuPool),
69      commitToIEWDelay(params->commitToIEWDelay),
70      renameToIEWDelay(params->renameToIEWDelay),
71      issueToExecuteDelay(params->issueToExecuteDelay),
72      dispatchWidth(params->dispatchWidth),
73      issueWidth(params->issueWidth),
74      wbOutstanding(0),
75      wbWidth(params->wbWidth),
76      numThreads(params->numThreads),
77      switchedOut(false)
78{
79    _status = Active;
80    exeStatus = Running;
81    wbStatus = Idle;
82
83    // Setup wire to read instructions coming from issue.
84    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
85
86    // Instruction queue needs the queue between issue and execute.
87    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
88
89    for (ThreadID tid = 0; tid < numThreads; tid++) {
90        dispatchStatus[tid] = Running;
91        stalls[tid].commit = false;
92        fetchRedirect[tid] = false;
93    }
94
95    wbMax = wbWidth * params->wbDepth;
96
97    updateLSQNextCycle = false;
98
99    ableToIssue = true;
100
101    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
102}
103
104template <class Impl>
105std::string
106DefaultIEW<Impl>::name() const
107{
108    return cpu->name() + ".iew";
109}
110
111template <class Impl>
112void
113DefaultIEW<Impl>::regStats()
114{
115    using namespace Stats;
116
117    instQueue.regStats();
118    ldstQueue.regStats();
119
120    iewIdleCycles
121        .name(name() + ".iewIdleCycles")
122        .desc("Number of cycles IEW is idle");
123
124    iewSquashCycles
125        .name(name() + ".iewSquashCycles")
126        .desc("Number of cycles IEW is squashing");
127
128    iewBlockCycles
129        .name(name() + ".iewBlockCycles")
130        .desc("Number of cycles IEW is blocking");
131
132    iewUnblockCycles
133        .name(name() + ".iewUnblockCycles")
134        .desc("Number of cycles IEW is unblocking");
135
136    iewDispatchedInsts
137        .name(name() + ".iewDispatchedInsts")
138        .desc("Number of instructions dispatched to IQ");
139
140    iewDispSquashedInsts
141        .name(name() + ".iewDispSquashedInsts")
142        .desc("Number of squashed instructions skipped by dispatch");
143
144    iewDispLoadInsts
145        .name(name() + ".iewDispLoadInsts")
146        .desc("Number of dispatched load instructions");
147
148    iewDispStoreInsts
149        .name(name() + ".iewDispStoreInsts")
150        .desc("Number of dispatched store instructions");
151
152    iewDispNonSpecInsts
153        .name(name() + ".iewDispNonSpecInsts")
154        .desc("Number of dispatched non-speculative instructions");
155
156    iewIQFullEvents
157        .name(name() + ".iewIQFullEvents")
158        .desc("Number of times the IQ has become full, causing a stall");
159
160    iewLSQFullEvents
161        .name(name() + ".iewLSQFullEvents")
162        .desc("Number of times the LSQ has become full, causing a stall");
163
164    memOrderViolationEvents
165        .name(name() + ".memOrderViolationEvents")
166        .desc("Number of memory order violations");
167
168    predictedTakenIncorrect
169        .name(name() + ".predictedTakenIncorrect")
170        .desc("Number of branches that were predicted taken incorrectly");
171
172    predictedNotTakenIncorrect
173        .name(name() + ".predictedNotTakenIncorrect")
174        .desc("Number of branches that were predicted not taken incorrectly");
175
176    branchMispredicts
177        .name(name() + ".branchMispredicts")
178        .desc("Number of branch mispredicts detected at execute");
179
180    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
181
182    iewExecutedInsts
183        .name(name() + ".iewExecutedInsts")
184        .desc("Number of executed instructions");
185
186    iewExecLoadInsts
187        .init(cpu->numThreads)
188        .name(name() + ".iewExecLoadInsts")
189        .desc("Number of load instructions executed")
190        .flags(total);
191
192    iewExecSquashedInsts
193        .name(name() + ".iewExecSquashedInsts")
194        .desc("Number of squashed instructions skipped in execute");
195
196    iewExecutedSwp
197        .init(cpu->numThreads)
198        .name(name() + ".exec_swp")
199        .desc("number of swp insts executed")
200        .flags(total);
201
202    iewExecutedNop
203        .init(cpu->numThreads)
204        .name(name() + ".exec_nop")
205        .desc("number of nop insts executed")
206        .flags(total);
207
208    iewExecutedRefs
209        .init(cpu->numThreads)
210        .name(name() + ".exec_refs")
211        .desc("number of memory reference insts executed")
212        .flags(total);
213
214    iewExecutedBranches
215        .init(cpu->numThreads)
216        .name(name() + ".exec_branches")
217        .desc("Number of branches executed")
218        .flags(total);
219
220    iewExecStoreInsts
221        .name(name() + ".exec_stores")
222        .desc("Number of stores executed")
223        .flags(total);
224    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
225
226    iewExecRate
227        .name(name() + ".exec_rate")
228        .desc("Inst execution rate")
229        .flags(total);
230
231    iewExecRate = iewExecutedInsts / cpu->numCycles;
232
233    iewInstsToCommit
234        .init(cpu->numThreads)
235        .name(name() + ".wb_sent")
236        .desc("cumulative count of insts sent to commit")
237        .flags(total);
238
239    writebackCount
240        .init(cpu->numThreads)
241        .name(name() + ".wb_count")
242        .desc("cumulative count of insts written-back")
243        .flags(total);
244
245    producerInst
246        .init(cpu->numThreads)
247        .name(name() + ".wb_producers")
248        .desc("num instructions producing a value")
249        .flags(total);
250
251    consumerInst
252        .init(cpu->numThreads)
253        .name(name() + ".wb_consumers")
254        .desc("num instructions consuming a value")
255        .flags(total);
256
257    wbPenalized
258        .init(cpu->numThreads)
259        .name(name() + ".wb_penalized")
260        .desc("number of instrctions required to write to 'other' IQ")
261        .flags(total);
262
263    wbPenalizedRate
264        .name(name() + ".wb_penalized_rate")
265        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
266        .flags(total);
267
268    wbPenalizedRate = wbPenalized / writebackCount;
269
270    wbFanout
271        .name(name() + ".wb_fanout")
272        .desc("average fanout of values written-back")
273        .flags(total);
274
275    wbFanout = producerInst / consumerInst;
276
277    wbRate
278        .name(name() + ".wb_rate")
279        .desc("insts written-back per cycle")
280        .flags(total);
281    wbRate = writebackCount / cpu->numCycles;
282}
283
284template<class Impl>
285void
286DefaultIEW<Impl>::initStage()
287{
288    for (ThreadID tid = 0; tid < numThreads; tid++) {
289        toRename->iewInfo[tid].usedIQ = true;
290        toRename->iewInfo[tid].freeIQEntries =
291            instQueue.numFreeEntries(tid);
292
293        toRename->iewInfo[tid].usedLSQ = true;
294        toRename->iewInfo[tid].freeLSQEntries =
295            ldstQueue.numFreeEntries(tid);
296    }
297
298    // Initialize the checker's dcache port here
299    if (cpu->checker) {
300        cpu->checker->setDcachePort(&cpu->getDataPort());
301    }
302
303    cpu->activateStage(O3CPU::IEWIdx);
304}
305
306template<class Impl>
307void
308DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
309{
310    timeBuffer = tb_ptr;
311
312    // Setup wire to read information from time buffer, from commit.
313    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
314
315    // Setup wire to write information back to previous stages.
316    toRename = timeBuffer->getWire(0);
317
318    toFetch = timeBuffer->getWire(0);
319
320    // Instruction queue also needs main time buffer.
321    instQueue.setTimeBuffer(tb_ptr);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
327{
328    renameQueue = rq_ptr;
329
330    // Setup wire to read information from rename queue.
331    fromRename = renameQueue->getWire(-renameToIEWDelay);
332}
333
334template<class Impl>
335void
336DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
337{
338    iewQueue = iq_ptr;
339
340    // Setup wire to write instructions to commit.
341    toCommit = iewQueue->getWire(0);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
347{
348    activeThreads = at_ptr;
349
350    ldstQueue.setActiveThreads(at_ptr);
351    instQueue.setActiveThreads(at_ptr);
352}
353
354template<class Impl>
355void
356DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
357{
358    scoreboard = sb_ptr;
359}
360
361template <class Impl>
362bool
363DefaultIEW<Impl>::drain()
364{
365    // IEW is ready to drain at any time.
366    cpu->signalDrained();
367    return true;
368}
369
370template <class Impl>
371void
372DefaultIEW<Impl>::resume()
373{
374}
375
376template <class Impl>
377void
378DefaultIEW<Impl>::switchOut()
379{
380    // Clear any state.
381    switchedOut = true;
382    assert(insts[0].empty());
383    assert(skidBuffer[0].empty());
384
385    instQueue.switchOut();
386    ldstQueue.switchOut();
387    fuPool->switchOut();
388
389    for (ThreadID tid = 0; tid < numThreads; tid++) {
390        while (!insts[tid].empty())
391            insts[tid].pop();
392        while (!skidBuffer[tid].empty())
393            skidBuffer[tid].pop();
394    }
395}
396
397template <class Impl>
398void
399DefaultIEW<Impl>::takeOverFrom()
400{
401    // Reset all state.
402    _status = Active;
403    exeStatus = Running;
404    wbStatus = Idle;
405    switchedOut = false;
406
407    instQueue.takeOverFrom();
408    ldstQueue.takeOverFrom();
409    fuPool->takeOver();
410
411    initStage();
412    cpu->activityThisCycle();
413
414    for (ThreadID tid = 0; tid < numThreads; tid++) {
415        dispatchStatus[tid] = Running;
416        stalls[tid].commit = false;
417        fetchRedirect[tid] = false;
418    }
419
420    updateLSQNextCycle = false;
421
422    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
423        issueToExecQueue.advance();
424    }
425}
426
427template<class Impl>
428void
429DefaultIEW<Impl>::squash(ThreadID tid)
430{
431    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
432
433    // Tell the IQ to start squashing.
434    instQueue.squash(tid);
435
436    // Tell the LDSTQ to start squashing.
437    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
438    updatedQueues = true;
439
440    // Clear the skid buffer in case it has any data in it.
441    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
442            tid, fromCommit->commitInfo[tid].doneSeqNum);
443
444    while (!skidBuffer[tid].empty()) {
445        if (skidBuffer[tid].front()->isLoad() ||
446            skidBuffer[tid].front()->isStore() ) {
447            toRename->iewInfo[tid].dispatchedToLSQ++;
448        }
449
450        toRename->iewInfo[tid].dispatched++;
451
452        skidBuffer[tid].pop();
453    }
454
455    emptyRenameInsts(tid);
456}
457
458template<class Impl>
459void
460DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
461{
462    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
463            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
464
465    if (toCommit->squash[tid] == false ||
466            inst->seqNum < toCommit->squashedSeqNum[tid]) {
467        toCommit->squash[tid] = true;
468        toCommit->squashedSeqNum[tid] = inst->seqNum;
469        toCommit->branchTaken[tid] = inst->pcState().branching();
470
471        TheISA::PCState pc = inst->pcState();
472        TheISA::advancePC(pc, inst->staticInst);
473
474        toCommit->pc[tid] = pc;
475        toCommit->mispredictInst[tid] = inst;
476        toCommit->includeSquashInst[tid] = false;
477
478        wroteToTimeBuffer = true;
479    }
480
481}
482
483template<class Impl>
484void
485DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
486{
487    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
488            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
489    // Need to include inst->seqNum in the following comparison to cover the
490    // corner case when a branch misprediction and a memory violation for the
491    // same instruction (e.g. load PC) are detected in the same cycle.  In this
492    // case the memory violator should take precedence over the branch
493    // misprediction because it requires the violator itself to be included in
494    // the squash.
495    if (toCommit->squash[tid] == false ||
496            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
497        toCommit->squash[tid] = true;
498
499        toCommit->squashedSeqNum[tid] = inst->seqNum;
500        toCommit->pc[tid] = inst->pcState();
501        toCommit->mispredictInst[tid] = NULL;
502
503        // Must include the memory violator in the squash.
504        toCommit->includeSquashInst[tid] = true;
505
506        wroteToTimeBuffer = true;
507    }
508}
509
510template<class Impl>
511void
512DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
513{
514    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
515            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
516    if (toCommit->squash[tid] == false ||
517            inst->seqNum < toCommit->squashedSeqNum[tid]) {
518        toCommit->squash[tid] = true;
519
520        toCommit->squashedSeqNum[tid] = inst->seqNum;
521        toCommit->pc[tid] = inst->pcState();
522        toCommit->mispredictInst[tid] = NULL;
523
524        // Must include the broadcasted SN in the squash.
525        toCommit->includeSquashInst[tid] = true;
526
527        ldstQueue.setLoadBlockedHandled(tid);
528
529        wroteToTimeBuffer = true;
530    }
531}
532
533template<class Impl>
534void
535DefaultIEW<Impl>::block(ThreadID tid)
536{
537    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
538
539    if (dispatchStatus[tid] != Blocked &&
540        dispatchStatus[tid] != Unblocking) {
541        toRename->iewBlock[tid] = true;
542        wroteToTimeBuffer = true;
543    }
544
545    // Add the current inputs to the skid buffer so they can be
546    // reprocessed when this stage unblocks.
547    skidInsert(tid);
548
549    dispatchStatus[tid] = Blocked;
550}
551
552template<class Impl>
553void
554DefaultIEW<Impl>::unblock(ThreadID tid)
555{
556    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
557            "buffer %u.\n",tid, tid);
558
559    // If the skid bufffer is empty, signal back to previous stages to unblock.
560    // Also switch status to running.
561    if (skidBuffer[tid].empty()) {
562        toRename->iewUnblock[tid] = true;
563        wroteToTimeBuffer = true;
564        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
565        dispatchStatus[tid] = Running;
566    }
567}
568
569template<class Impl>
570void
571DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
572{
573    instQueue.wakeDependents(inst);
574}
575
576template<class Impl>
577void
578DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
579{
580    instQueue.rescheduleMemInst(inst);
581}
582
583template<class Impl>
584void
585DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
586{
587    instQueue.replayMemInst(inst);
588}
589
590template<class Impl>
591void
592DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
593{
594    // This function should not be called after writebackInsts in a
595    // single cycle.  That will cause problems with an instruction
596    // being added to the queue to commit without being processed by
597    // writebackInsts prior to being sent to commit.
598
599    // First check the time slot that this instruction will write
600    // to.  If there are free write ports at the time, then go ahead
601    // and write the instruction to that time.  If there are not,
602    // keep looking back to see where's the first time there's a
603    // free slot.
604    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
605        ++wbNumInst;
606        if (wbNumInst == wbWidth) {
607            ++wbCycle;
608            wbNumInst = 0;
609        }
610
611        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
612    }
613
614    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
615            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
616    // Add finished instruction to queue to commit.
617    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
618    (*iewQueue)[wbCycle].size++;
619}
620
621template <class Impl>
622unsigned
623DefaultIEW<Impl>::validInstsFromRename()
624{
625    unsigned inst_count = 0;
626
627    for (int i=0; i<fromRename->size; i++) {
628        if (!fromRename->insts[i]->isSquashed())
629            inst_count++;
630    }
631
632    return inst_count;
633}
634
635template<class Impl>
636void
637DefaultIEW<Impl>::skidInsert(ThreadID tid)
638{
639    DynInstPtr inst = NULL;
640
641    while (!insts[tid].empty()) {
642        inst = insts[tid].front();
643
644        insts[tid].pop();
645
646        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
647                "dispatch skidBuffer %i\n",tid, inst->seqNum,
648                inst->pcState(),tid);
649
650        skidBuffer[tid].push(inst);
651    }
652
653    assert(skidBuffer[tid].size() <= skidBufferMax &&
654           "Skidbuffer Exceeded Max Size");
655}
656
657template<class Impl>
658int
659DefaultIEW<Impl>::skidCount()
660{
661    int max=0;
662
663    list<ThreadID>::iterator threads = activeThreads->begin();
664    list<ThreadID>::iterator end = activeThreads->end();
665
666    while (threads != end) {
667        ThreadID tid = *threads++;
668        unsigned thread_count = skidBuffer[tid].size();
669        if (max < thread_count)
670            max = thread_count;
671    }
672
673    return max;
674}
675
676template<class Impl>
677bool
678DefaultIEW<Impl>::skidsEmpty()
679{
680    list<ThreadID>::iterator threads = activeThreads->begin();
681    list<ThreadID>::iterator end = activeThreads->end();
682
683    while (threads != end) {
684        ThreadID tid = *threads++;
685
686        if (!skidBuffer[tid].empty())
687            return false;
688    }
689
690    return true;
691}
692
693template <class Impl>
694void
695DefaultIEW<Impl>::updateStatus()
696{
697    bool any_unblocking = false;
698
699    list<ThreadID>::iterator threads = activeThreads->begin();
700    list<ThreadID>::iterator end = activeThreads->end();
701
702    while (threads != end) {
703        ThreadID tid = *threads++;
704
705        if (dispatchStatus[tid] == Unblocking) {
706            any_unblocking = true;
707            break;
708        }
709    }
710
711    // If there are no ready instructions waiting to be scheduled by the IQ,
712    // and there's no stores waiting to write back, and dispatch is not
713    // unblocking, then there is no internal activity for the IEW stage.
714    instQueue.intInstQueueReads++;
715    if (_status == Active && !instQueue.hasReadyInsts() &&
716        !ldstQueue.willWB() && !any_unblocking) {
717        DPRINTF(IEW, "IEW switching to idle\n");
718
719        deactivateStage();
720
721        _status = Inactive;
722    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
723                                       ldstQueue.willWB() ||
724                                       any_unblocking)) {
725        // Otherwise there is internal activity.  Set to active.
726        DPRINTF(IEW, "IEW switching to active\n");
727
728        activateStage();
729
730        _status = Active;
731    }
732}
733
734template <class Impl>
735void
736DefaultIEW<Impl>::resetEntries()
737{
738    instQueue.resetEntries();
739    ldstQueue.resetEntries();
740}
741
742template <class Impl>
743void
744DefaultIEW<Impl>::readStallSignals(ThreadID tid)
745{
746    if (fromCommit->commitBlock[tid]) {
747        stalls[tid].commit = true;
748    }
749
750    if (fromCommit->commitUnblock[tid]) {
751        assert(stalls[tid].commit);
752        stalls[tid].commit = false;
753    }
754}
755
756template <class Impl>
757bool
758DefaultIEW<Impl>::checkStall(ThreadID tid)
759{
760    bool ret_val(false);
761
762    if (stalls[tid].commit) {
763        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
764        ret_val = true;
765    } else if (instQueue.isFull(tid)) {
766        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
767        ret_val = true;
768    } else if (ldstQueue.isFull(tid)) {
769        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
770
771        if (ldstQueue.numLoads(tid) > 0 ) {
772
773            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
774                    tid,ldstQueue.getLoadHeadSeqNum(tid));
775        }
776
777        if (ldstQueue.numStores(tid) > 0) {
778
779            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
780                    tid,ldstQueue.getStoreHeadSeqNum(tid));
781        }
782
783        ret_val = true;
784    } else if (ldstQueue.isStalled(tid)) {
785        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
786        ret_val = true;
787    }
788
789    return ret_val;
790}
791
792template <class Impl>
793void
794DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
795{
796    // Check if there's a squash signal, squash if there is
797    // Check stall signals, block if there is.
798    // If status was Blocked
799    //     if so then go to unblocking
800    // If status was Squashing
801    //     check if squashing is not high.  Switch to running this cycle.
802
803    readStallSignals(tid);
804
805    if (fromCommit->commitInfo[tid].squash) {
806        squash(tid);
807
808        if (dispatchStatus[tid] == Blocked ||
809            dispatchStatus[tid] == Unblocking) {
810            toRename->iewUnblock[tid] = true;
811            wroteToTimeBuffer = true;
812        }
813
814        dispatchStatus[tid] = Squashing;
815        fetchRedirect[tid] = false;
816        return;
817    }
818
819    if (fromCommit->commitInfo[tid].robSquashing) {
820        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
821
822        dispatchStatus[tid] = Squashing;
823        emptyRenameInsts(tid);
824        wroteToTimeBuffer = true;
825        return;
826    }
827
828    if (checkStall(tid)) {
829        block(tid);
830        dispatchStatus[tid] = Blocked;
831        return;
832    }
833
834    if (dispatchStatus[tid] == Blocked) {
835        // Status from previous cycle was blocked, but there are no more stall
836        // conditions.  Switch over to unblocking.
837        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
838                tid);
839
840        dispatchStatus[tid] = Unblocking;
841
842        unblock(tid);
843
844        return;
845    }
846
847    if (dispatchStatus[tid] == Squashing) {
848        // Switch status to running if rename isn't being told to block or
849        // squash this cycle.
850        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
851                tid);
852
853        dispatchStatus[tid] = Running;
854
855        return;
856    }
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::sortInsts()
862{
863    int insts_from_rename = fromRename->size;
864#ifdef DEBUG
865    for (ThreadID tid = 0; tid < numThreads; tid++)
866        assert(insts[tid].empty());
867#endif
868    for (int i = 0; i < insts_from_rename; ++i) {
869        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
870    }
871}
872
873template <class Impl>
874void
875DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
876{
877    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
878
879    while (!insts[tid].empty()) {
880
881        if (insts[tid].front()->isLoad() ||
882            insts[tid].front()->isStore() ) {
883            toRename->iewInfo[tid].dispatchedToLSQ++;
884        }
885
886        toRename->iewInfo[tid].dispatched++;
887
888        insts[tid].pop();
889    }
890}
891
892template <class Impl>
893void
894DefaultIEW<Impl>::wakeCPU()
895{
896    cpu->wakeCPU();
897}
898
899template <class Impl>
900void
901DefaultIEW<Impl>::activityThisCycle()
902{
903    DPRINTF(Activity, "Activity this cycle.\n");
904    cpu->activityThisCycle();
905}
906
907template <class Impl>
908inline void
909DefaultIEW<Impl>::activateStage()
910{
911    DPRINTF(Activity, "Activating stage.\n");
912    cpu->activateStage(O3CPU::IEWIdx);
913}
914
915template <class Impl>
916inline void
917DefaultIEW<Impl>::deactivateStage()
918{
919    DPRINTF(Activity, "Deactivating stage.\n");
920    cpu->deactivateStage(O3CPU::IEWIdx);
921}
922
923template<class Impl>
924void
925DefaultIEW<Impl>::dispatch(ThreadID tid)
926{
927    // If status is Running or idle,
928    //     call dispatchInsts()
929    // If status is Unblocking,
930    //     buffer any instructions coming from rename
931    //     continue trying to empty skid buffer
932    //     check if stall conditions have passed
933
934    if (dispatchStatus[tid] == Blocked) {
935        ++iewBlockCycles;
936
937    } else if (dispatchStatus[tid] == Squashing) {
938        ++iewSquashCycles;
939    }
940
941    // Dispatch should try to dispatch as many instructions as its bandwidth
942    // will allow, as long as it is not currently blocked.
943    if (dispatchStatus[tid] == Running ||
944        dispatchStatus[tid] == Idle) {
945        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
946                "dispatch.\n", tid);
947
948        dispatchInsts(tid);
949    } else if (dispatchStatus[tid] == Unblocking) {
950        // Make sure that the skid buffer has something in it if the
951        // status is unblocking.
952        assert(!skidsEmpty());
953
954        // If the status was unblocking, then instructions from the skid
955        // buffer were used.  Remove those instructions and handle
956        // the rest of unblocking.
957        dispatchInsts(tid);
958
959        ++iewUnblockCycles;
960
961        if (validInstsFromRename()) {
962            // Add the current inputs to the skid buffer so they can be
963            // reprocessed when this stage unblocks.
964            skidInsert(tid);
965        }
966
967        unblock(tid);
968    }
969}
970
971template <class Impl>
972void
973DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
974{
975    // Obtain instructions from skid buffer if unblocking, or queue from rename
976    // otherwise.
977    std::queue<DynInstPtr> &insts_to_dispatch =
978        dispatchStatus[tid] == Unblocking ?
979        skidBuffer[tid] : insts[tid];
980
981    int insts_to_add = insts_to_dispatch.size();
982
983    DynInstPtr inst;
984    bool add_to_iq = false;
985    int dis_num_inst = 0;
986
987    // Loop through the instructions, putting them in the instruction
988    // queue.
989    for ( ; dis_num_inst < insts_to_add &&
990              dis_num_inst < dispatchWidth;
991          ++dis_num_inst)
992    {
993        inst = insts_to_dispatch.front();
994
995        if (dispatchStatus[tid] == Unblocking) {
996            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
997                    "buffer\n", tid);
998        }
999
1000        // Make sure there's a valid instruction there.
1001        assert(inst);
1002
1003        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
1004                "IQ.\n",
1005                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1006
1007        // Be sure to mark these instructions as ready so that the
1008        // commit stage can go ahead and execute them, and mark
1009        // them as issued so the IQ doesn't reprocess them.
1010
1011        // Check for squashed instructions.
1012        if (inst->isSquashed()) {
1013            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1014                    "not adding to IQ.\n", tid);
1015
1016            ++iewDispSquashedInsts;
1017
1018            insts_to_dispatch.pop();
1019
1020            //Tell Rename That An Instruction has been processed
1021            if (inst->isLoad() || inst->isStore()) {
1022                toRename->iewInfo[tid].dispatchedToLSQ++;
1023            }
1024            toRename->iewInfo[tid].dispatched++;
1025
1026            continue;
1027        }
1028
1029        // Check for full conditions.
1030        if (instQueue.isFull(tid)) {
1031            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1032
1033            // Call function to start blocking.
1034            block(tid);
1035
1036            // Set unblock to false. Special case where we are using
1037            // skidbuffer (unblocking) instructions but then we still
1038            // get full in the IQ.
1039            toRename->iewUnblock[tid] = false;
1040
1041            ++iewIQFullEvents;
1042            break;
1043        } else if (ldstQueue.isFull(tid)) {
1044            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1045
1046            // Call function to start blocking.
1047            block(tid);
1048
1049            // Set unblock to false. Special case where we are using
1050            // skidbuffer (unblocking) instructions but then we still
1051            // get full in the IQ.
1052            toRename->iewUnblock[tid] = false;
1053
1054            ++iewLSQFullEvents;
1055            break;
1056        }
1057
1058        // Otherwise issue the instruction just fine.
1059        if (inst->isLoad()) {
1060            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1061                    "encountered, adding to LSQ.\n", tid);
1062
1063            // Reserve a spot in the load store queue for this
1064            // memory access.
1065            ldstQueue.insertLoad(inst);
1066
1067            ++iewDispLoadInsts;
1068
1069            add_to_iq = true;
1070
1071            toRename->iewInfo[tid].dispatchedToLSQ++;
1072        } else if (inst->isStore()) {
1073            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1074                    "encountered, adding to LSQ.\n", tid);
1075
1076            ldstQueue.insertStore(inst);
1077
1078            ++iewDispStoreInsts;
1079
1080            if (inst->isStoreConditional()) {
1081                // Store conditionals need to be set as "canCommit()"
1082                // so that commit can process them when they reach the
1083                // head of commit.
1084                // @todo: This is somewhat specific to Alpha.
1085                inst->setCanCommit();
1086                instQueue.insertNonSpec(inst);
1087                add_to_iq = false;
1088
1089                ++iewDispNonSpecInsts;
1090            } else {
1091                add_to_iq = true;
1092            }
1093
1094            toRename->iewInfo[tid].dispatchedToLSQ++;
1095        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1096            // Same as non-speculative stores.
1097            inst->setCanCommit();
1098            instQueue.insertBarrier(inst);
1099            add_to_iq = false;
1100        } else if (inst->isNop()) {
1101            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1102                    "skipping.\n", tid);
1103
1104            inst->setIssued();
1105            inst->setExecuted();
1106            inst->setCanCommit();
1107
1108            instQueue.recordProducer(inst);
1109
1110            iewExecutedNop[tid]++;
1111
1112            add_to_iq = false;
1113        } else if (inst->isExecuted()) {
1114            assert(0 && "Instruction shouldn't be executed.\n");
1115            DPRINTF(IEW, "Issue: Executed branch encountered, "
1116                    "skipping.\n");
1117
1118            inst->setIssued();
1119            inst->setCanCommit();
1120
1121            instQueue.recordProducer(inst);
1122
1123            add_to_iq = false;
1124        } else {
1125            add_to_iq = true;
1126        }
1127        if (inst->isNonSpeculative()) {
1128            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1129                    "encountered, skipping.\n", tid);
1130
1131            // Same as non-speculative stores.
1132            inst->setCanCommit();
1133
1134            // Specifically insert it as nonspeculative.
1135            instQueue.insertNonSpec(inst);
1136
1137            ++iewDispNonSpecInsts;
1138
1139            add_to_iq = false;
1140        }
1141
1142        // If the instruction queue is not full, then add the
1143        // instruction.
1144        if (add_to_iq) {
1145            instQueue.insert(inst);
1146        }
1147
1148        insts_to_dispatch.pop();
1149
1150        toRename->iewInfo[tid].dispatched++;
1151
1152        ++iewDispatchedInsts;
1153
1154#if TRACING_ON
1155        inst->dispatchTick = curTick() - inst->fetchTick;
1156#endif
1157    }
1158
1159    if (!insts_to_dispatch.empty()) {
1160        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1161        block(tid);
1162        toRename->iewUnblock[tid] = false;
1163    }
1164
1165    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1166        dispatchStatus[tid] = Running;
1167
1168        updatedQueues = true;
1169    }
1170
1171    dis_num_inst = 0;
1172}
1173
1174template <class Impl>
1175void
1176DefaultIEW<Impl>::printAvailableInsts()
1177{
1178    int inst = 0;
1179
1180    std::cout << "Available Instructions: ";
1181
1182    while (fromIssue->insts[inst]) {
1183
1184        if (inst%3==0) std::cout << "\n\t";
1185
1186        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1187             << " TN: " << fromIssue->insts[inst]->threadNumber
1188             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1189
1190        inst++;
1191
1192    }
1193
1194    std::cout << "\n";
1195}
1196
1197template <class Impl>
1198void
1199DefaultIEW<Impl>::executeInsts()
1200{
1201    wbNumInst = 0;
1202    wbCycle = 0;
1203
1204    list<ThreadID>::iterator threads = activeThreads->begin();
1205    list<ThreadID>::iterator end = activeThreads->end();
1206
1207    while (threads != end) {
1208        ThreadID tid = *threads++;
1209        fetchRedirect[tid] = false;
1210    }
1211
1212    // Uncomment this if you want to see all available instructions.
1213    // @todo This doesn't actually work anymore, we should fix it.
1214//    printAvailableInsts();
1215
1216    // Execute/writeback any instructions that are available.
1217    int insts_to_execute = fromIssue->size;
1218    int inst_num = 0;
1219    for (; inst_num < insts_to_execute;
1220          ++inst_num) {
1221
1222        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1223
1224        DynInstPtr inst = instQueue.getInstToExecute();
1225
1226        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1227                inst->pcState(), inst->threadNumber,inst->seqNum);
1228
1229        // Check if the instruction is squashed; if so then skip it
1230        if (inst->isSquashed()) {
1231            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1232                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1233                         inst->seqNum);
1234
1235            // Consider this instruction executed so that commit can go
1236            // ahead and retire the instruction.
1237            inst->setExecuted();
1238
1239            // Not sure if I should set this here or just let commit try to
1240            // commit any squashed instructions.  I like the latter a bit more.
1241            inst->setCanCommit();
1242
1243            ++iewExecSquashedInsts;
1244
1245            decrWb(inst->seqNum);
1246            continue;
1247        }
1248
1249        Fault fault = NoFault;
1250
1251        // Execute instruction.
1252        // Note that if the instruction faults, it will be handled
1253        // at the commit stage.
1254        if (inst->isMemRef()) {
1255            DPRINTF(IEW, "Execute: Calculating address for memory "
1256                    "reference.\n");
1257
1258            // Tell the LDSTQ to execute this instruction (if it is a load).
1259            if (inst->isLoad()) {
1260                // Loads will mark themselves as executed, and their writeback
1261                // event adds the instruction to the queue to commit
1262                fault = ldstQueue.executeLoad(inst);
1263
1264                if (inst->isTranslationDelayed() &&
1265                    fault == NoFault) {
1266                    // A hw page table walk is currently going on; the
1267                    // instruction must be deferred.
1268                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1269                            "load.\n");
1270                    instQueue.deferMemInst(inst);
1271                    continue;
1272                }
1273
1274                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1275                    inst->fault = NoFault;
1276                }
1277            } else if (inst->isStore()) {
1278                fault = ldstQueue.executeStore(inst);
1279
1280                if (inst->isTranslationDelayed() &&
1281                    fault == NoFault) {
1282                    // A hw page table walk is currently going on; the
1283                    // instruction must be deferred.
1284                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1285                            "store.\n");
1286                    instQueue.deferMemInst(inst);
1287                    continue;
1288                }
1289
1290                // If the store had a fault then it may not have a mem req
1291                if (fault != NoFault || inst->readPredicate() == false ||
1292                        !inst->isStoreConditional()) {
1293                    // If the instruction faulted, then we need to send it along
1294                    // to commit without the instruction completing.
1295                    // Send this instruction to commit, also make sure iew stage
1296                    // realizes there is activity.
1297                    inst->setExecuted();
1298                    instToCommit(inst);
1299                    activityThisCycle();
1300                }
1301
1302                // Store conditionals will mark themselves as
1303                // executed, and their writeback event will add the
1304                // instruction to the queue to commit.
1305            } else {
1306                panic("Unexpected memory type!\n");
1307            }
1308
1309        } else {
1310            // If the instruction has already faulted, then skip executing it.
1311            // Such case can happen when it faulted during ITLB translation.
1312            // If we execute the instruction (even if it's a nop) the fault
1313            // will be replaced and we will lose it.
1314            if (inst->getFault() == NoFault) {
1315                inst->execute();
1316                if (inst->readPredicate() == false)
1317                    inst->forwardOldRegs();
1318            }
1319
1320            inst->setExecuted();
1321
1322            instToCommit(inst);
1323        }
1324
1325        updateExeInstStats(inst);
1326
1327        // Check if branch prediction was correct, if not then we need
1328        // to tell commit to squash in flight instructions.  Only
1329        // handle this if there hasn't already been something that
1330        // redirects fetch in this group of instructions.
1331
1332        // This probably needs to prioritize the redirects if a different
1333        // scheduler is used.  Currently the scheduler schedules the oldest
1334        // instruction first, so the branch resolution order will be correct.
1335        ThreadID tid = inst->threadNumber;
1336
1337        if (!fetchRedirect[tid] ||
1338            !toCommit->squash[tid] ||
1339            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1340
1341            // Prevent testing for misprediction on load instructions,
1342            // that have not been executed.
1343            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1344
1345            if (inst->mispredicted() && !loadNotExecuted) {
1346                fetchRedirect[tid] = true;
1347
1348                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1349                DPRINTF(IEW, "Predicted target was PC: %s.\n",
1350                        inst->readPredTarg());
1351                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1352                        inst->pcState());
1353                // If incorrect, then signal the ROB that it must be squashed.
1354                squashDueToBranch(inst, tid);
1355
1356                if (inst->readPredTaken()) {
1357                    predictedTakenIncorrect++;
1358                } else {
1359                    predictedNotTakenIncorrect++;
1360                }
1361            } else if (ldstQueue.violation(tid)) {
1362                assert(inst->isMemRef());
1363                // If there was an ordering violation, then get the
1364                // DynInst that caused the violation.  Note that this
1365                // clears the violation signal.
1366                DynInstPtr violator;
1367                violator = ldstQueue.getMemDepViolator(tid);
1368
1369                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1370                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1371                        violator->pcState(), violator->seqNum,
1372                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1373
1374                fetchRedirect[tid] = true;
1375
1376                // Tell the instruction queue that a violation has occured.
1377                instQueue.violation(inst, violator);
1378
1379                // Squash.
1380                squashDueToMemOrder(violator, tid);
1381
1382                ++memOrderViolationEvents;
1383            } else if (ldstQueue.loadBlocked(tid) &&
1384                       !ldstQueue.isLoadBlockedHandled(tid)) {
1385                fetchRedirect[tid] = true;
1386
1387                DPRINTF(IEW, "Load operation couldn't execute because the "
1388                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1389                        inst->pcState(), inst->seqNum);
1390
1391                squashDueToMemBlocked(inst, tid);
1392            }
1393        } else {
1394            // Reset any state associated with redirects that will not
1395            // be used.
1396            if (ldstQueue.violation(tid)) {
1397                assert(inst->isMemRef());
1398
1399                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1400
1401                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1402                        "%s, inst PC: %s.  Addr is: %#x.\n",
1403                        violator->pcState(), inst->pcState(),
1404                        inst->physEffAddr);
1405                DPRINTF(IEW, "Violation will not be handled because "
1406                        "already squashing\n");
1407
1408                ++memOrderViolationEvents;
1409            }
1410            if (ldstQueue.loadBlocked(tid) &&
1411                !ldstQueue.isLoadBlockedHandled(tid)) {
1412                DPRINTF(IEW, "Load operation couldn't execute because the "
1413                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1414                        inst->pcState(), inst->seqNum);
1415                DPRINTF(IEW, "Blocked load will not be handled because "
1416                        "already squashing\n");
1417
1418                ldstQueue.setLoadBlockedHandled(tid);
1419            }
1420
1421        }
1422    }
1423
1424    // Update and record activity if we processed any instructions.
1425    if (inst_num) {
1426        if (exeStatus == Idle) {
1427            exeStatus = Running;
1428        }
1429
1430        updatedQueues = true;
1431
1432        cpu->activityThisCycle();
1433    }
1434
1435    // Need to reset this in case a writeback event needs to write into the
1436    // iew queue.  That way the writeback event will write into the correct
1437    // spot in the queue.
1438    wbNumInst = 0;
1439
1440}
1441
1442template <class Impl>
1443void
1444DefaultIEW<Impl>::writebackInsts()
1445{
1446    // Loop through the head of the time buffer and wake any
1447    // dependents.  These instructions are about to write back.  Also
1448    // mark scoreboard that this instruction is finally complete.
1449    // Either have IEW have direct access to scoreboard, or have this
1450    // as part of backwards communication.
1451    for (int inst_num = 0; inst_num < wbWidth &&
1452             toCommit->insts[inst_num]; inst_num++) {
1453        DynInstPtr inst = toCommit->insts[inst_num];
1454        ThreadID tid = inst->threadNumber;
1455
1456        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1457                inst->seqNum, inst->pcState());
1458
1459        iewInstsToCommit[tid]++;
1460
1461        // Some instructions will be sent to commit without having
1462        // executed because they need commit to handle them.
1463        // E.g. Uncached loads have not actually executed when they
1464        // are first sent to commit.  Instead commit must tell the LSQ
1465        // when it's ready to execute the uncached load.
1466        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1467            int dependents = instQueue.wakeDependents(inst);
1468
1469            for (int i = 0; i < inst->numDestRegs(); i++) {
1470                //mark as Ready
1471                DPRINTF(IEW,"Setting Destination Register %i\n",
1472                        inst->renamedDestRegIdx(i));
1473                scoreboard->setReg(inst->renamedDestRegIdx(i));
1474            }
1475
1476            if (dependents) {
1477                producerInst[tid]++;
1478                consumerInst[tid]+= dependents;
1479            }
1480            writebackCount[tid]++;
1481        }
1482
1483        decrWb(inst->seqNum);
1484    }
1485}
1486
1487template<class Impl>
1488void
1489DefaultIEW<Impl>::tick()
1490{
1491    wbNumInst = 0;
1492    wbCycle = 0;
1493
1494    wroteToTimeBuffer = false;
1495    updatedQueues = false;
1496
1497    sortInsts();
1498
1499    // Free function units marked as being freed this cycle.
1500    fuPool->processFreeUnits();
1501
1502    list<ThreadID>::iterator threads = activeThreads->begin();
1503    list<ThreadID>::iterator end = activeThreads->end();
1504
1505    // Check stall and squash signals, dispatch any instructions.
1506    while (threads != end) {
1507        ThreadID tid = *threads++;
1508
1509        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1510
1511        checkSignalsAndUpdate(tid);
1512        dispatch(tid);
1513    }
1514
1515    if (exeStatus != Squashing) {
1516        executeInsts();
1517
1518        writebackInsts();
1519
1520        // Have the instruction queue try to schedule any ready instructions.
1521        // (In actuality, this scheduling is for instructions that will
1522        // be executed next cycle.)
1523        instQueue.scheduleReadyInsts();
1524
1525        // Also should advance its own time buffers if the stage ran.
1526        // Not the best place for it, but this works (hopefully).
1527        issueToExecQueue.advance();
1528    }
1529
1530    bool broadcast_free_entries = false;
1531
1532    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1533        exeStatus = Idle;
1534        updateLSQNextCycle = false;
1535
1536        broadcast_free_entries = true;
1537    }
1538
1539    // Writeback any stores using any leftover bandwidth.
1540    ldstQueue.writebackStores();
1541
1542    // Check the committed load/store signals to see if there's a load
1543    // or store to commit.  Also check if it's being told to execute a
1544    // nonspeculative instruction.
1545    // This is pretty inefficient...
1546
1547    threads = activeThreads->begin();
1548    while (threads != end) {
1549        ThreadID tid = (*threads++);
1550
1551        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1552
1553        // Update structures based on instructions committed.
1554        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1555            !fromCommit->commitInfo[tid].squash &&
1556            !fromCommit->commitInfo[tid].robSquashing) {
1557
1558            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1559
1560            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1561
1562            updateLSQNextCycle = true;
1563            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1564        }
1565
1566        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1567
1568            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1569            if (fromCommit->commitInfo[tid].uncached) {
1570                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1571                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1572            } else {
1573                instQueue.scheduleNonSpec(
1574                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1575            }
1576        }
1577
1578        if (broadcast_free_entries) {
1579            toFetch->iewInfo[tid].iqCount =
1580                instQueue.getCount(tid);
1581            toFetch->iewInfo[tid].ldstqCount =
1582                ldstQueue.getCount(tid);
1583
1584            toRename->iewInfo[tid].usedIQ = true;
1585            toRename->iewInfo[tid].freeIQEntries =
1586                instQueue.numFreeEntries();
1587            toRename->iewInfo[tid].usedLSQ = true;
1588            toRename->iewInfo[tid].freeLSQEntries =
1589                ldstQueue.numFreeEntries(tid);
1590
1591            wroteToTimeBuffer = true;
1592        }
1593
1594        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1595                tid, toRename->iewInfo[tid].dispatched);
1596    }
1597
1598    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1599            "LSQ has %i free entries.\n",
1600            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1601            ldstQueue.numFreeEntries());
1602
1603    updateStatus();
1604
1605    if (wroteToTimeBuffer) {
1606        DPRINTF(Activity, "Activity this cycle.\n");
1607        cpu->activityThisCycle();
1608    }
1609}
1610
1611template <class Impl>
1612void
1613DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1614{
1615    ThreadID tid = inst->threadNumber;
1616
1617    iewExecutedInsts++;
1618
1619#if TRACING_ON
1620    inst->completeTick = curTick() - inst->fetchTick;
1621#endif
1622
1623    //
1624    //  Control operations
1625    //
1626    if (inst->isControl())
1627        iewExecutedBranches[tid]++;
1628
1629    //
1630    //  Memory operations
1631    //
1632    if (inst->isMemRef()) {
1633        iewExecutedRefs[tid]++;
1634
1635        if (inst->isLoad()) {
1636            iewExecLoadInsts[tid]++;
1637        }
1638    }
1639}
1640
1641template <class Impl>
1642void
1643DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1644{
1645    ThreadID tid = inst->threadNumber;
1646
1647    if (!fetchRedirect[tid] ||
1648        !toCommit->squash[tid] ||
1649        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1650
1651        if (inst->mispredicted()) {
1652            fetchRedirect[tid] = true;
1653
1654            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1655            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1656                    inst->predInstAddr(), inst->predNextInstAddr());
1657            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1658                    " NPC: %#x.\n", inst->nextInstAddr(),
1659                    inst->nextInstAddr());
1660            // If incorrect, then signal the ROB that it must be squashed.
1661            squashDueToBranch(inst, tid);
1662
1663            if (inst->readPredTaken()) {
1664                predictedTakenIncorrect++;
1665            } else {
1666                predictedNotTakenIncorrect++;
1667            }
1668        }
1669    }
1670}
1671