iew_impl.hh revision 8850 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "arch/utility.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/o3/fu_pool.hh"
53#include "cpu/o3/iew.hh"
54#include "cpu/timebuf.hh"
55#include "debug/Activity.hh"
56#include "debug/Decode.hh"
57#include "debug/IEW.hh"
58#include "params/DerivO3CPU.hh"
59
60#if USE_CHECKER
61#include "cpu/checker/cpu.hh"
62#endif // USE_CHECKER
63
64using namespace std;
65
66template<class Impl>
67DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
68    : issueToExecQueue(params->backComSize, params->forwardComSize),
69      cpu(_cpu),
70      instQueue(_cpu, this, params),
71      ldstQueue(_cpu, this, params),
72      fuPool(params->fuPool),
73      commitToIEWDelay(params->commitToIEWDelay),
74      renameToIEWDelay(params->renameToIEWDelay),
75      issueToExecuteDelay(params->issueToExecuteDelay),
76      dispatchWidth(params->dispatchWidth),
77      issueWidth(params->issueWidth),
78      wbOutstanding(0),
79      wbWidth(params->wbWidth),
80      numThreads(params->numThreads),
81      switchedOut(false)
82{
83    _status = Active;
84    exeStatus = Running;
85    wbStatus = Idle;
86
87    // Setup wire to read instructions coming from issue.
88    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
89
90    // Instruction queue needs the queue between issue and execute.
91    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
92
93    for (ThreadID tid = 0; tid < numThreads; tid++) {
94        dispatchStatus[tid] = Running;
95        stalls[tid].commit = false;
96        fetchRedirect[tid] = false;
97    }
98
99    wbMax = wbWidth * params->wbDepth;
100
101    updateLSQNextCycle = false;
102
103    ableToIssue = true;
104
105    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
106}
107
108template <class Impl>
109std::string
110DefaultIEW<Impl>::name() const
111{
112    return cpu->name() + ".iew";
113}
114
115template <class Impl>
116void
117DefaultIEW<Impl>::regStats()
118{
119    using namespace Stats;
120
121    instQueue.regStats();
122    ldstQueue.regStats();
123
124    iewIdleCycles
125        .name(name() + ".iewIdleCycles")
126        .desc("Number of cycles IEW is idle");
127
128    iewSquashCycles
129        .name(name() + ".iewSquashCycles")
130        .desc("Number of cycles IEW is squashing");
131
132    iewBlockCycles
133        .name(name() + ".iewBlockCycles")
134        .desc("Number of cycles IEW is blocking");
135
136    iewUnblockCycles
137        .name(name() + ".iewUnblockCycles")
138        .desc("Number of cycles IEW is unblocking");
139
140    iewDispatchedInsts
141        .name(name() + ".iewDispatchedInsts")
142        .desc("Number of instructions dispatched to IQ");
143
144    iewDispSquashedInsts
145        .name(name() + ".iewDispSquashedInsts")
146        .desc("Number of squashed instructions skipped by dispatch");
147
148    iewDispLoadInsts
149        .name(name() + ".iewDispLoadInsts")
150        .desc("Number of dispatched load instructions");
151
152    iewDispStoreInsts
153        .name(name() + ".iewDispStoreInsts")
154        .desc("Number of dispatched store instructions");
155
156    iewDispNonSpecInsts
157        .name(name() + ".iewDispNonSpecInsts")
158        .desc("Number of dispatched non-speculative instructions");
159
160    iewIQFullEvents
161        .name(name() + ".iewIQFullEvents")
162        .desc("Number of times the IQ has become full, causing a stall");
163
164    iewLSQFullEvents
165        .name(name() + ".iewLSQFullEvents")
166        .desc("Number of times the LSQ has become full, causing a stall");
167
168    memOrderViolationEvents
169        .name(name() + ".memOrderViolationEvents")
170        .desc("Number of memory order violations");
171
172    predictedTakenIncorrect
173        .name(name() + ".predictedTakenIncorrect")
174        .desc("Number of branches that were predicted taken incorrectly");
175
176    predictedNotTakenIncorrect
177        .name(name() + ".predictedNotTakenIncorrect")
178        .desc("Number of branches that were predicted not taken incorrectly");
179
180    branchMispredicts
181        .name(name() + ".branchMispredicts")
182        .desc("Number of branch mispredicts detected at execute");
183
184    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
185
186    iewExecutedInsts
187        .name(name() + ".iewExecutedInsts")
188        .desc("Number of executed instructions");
189
190    iewExecLoadInsts
191        .init(cpu->numThreads)
192        .name(name() + ".iewExecLoadInsts")
193        .desc("Number of load instructions executed")
194        .flags(total);
195
196    iewExecSquashedInsts
197        .name(name() + ".iewExecSquashedInsts")
198        .desc("Number of squashed instructions skipped in execute");
199
200    iewExecutedSwp
201        .init(cpu->numThreads)
202        .name(name() + ".exec_swp")
203        .desc("number of swp insts executed")
204        .flags(total);
205
206    iewExecutedNop
207        .init(cpu->numThreads)
208        .name(name() + ".exec_nop")
209        .desc("number of nop insts executed")
210        .flags(total);
211
212    iewExecutedRefs
213        .init(cpu->numThreads)
214        .name(name() + ".exec_refs")
215        .desc("number of memory reference insts executed")
216        .flags(total);
217
218    iewExecutedBranches
219        .init(cpu->numThreads)
220        .name(name() + ".exec_branches")
221        .desc("Number of branches executed")
222        .flags(total);
223
224    iewExecStoreInsts
225        .name(name() + ".exec_stores")
226        .desc("Number of stores executed")
227        .flags(total);
228    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
229
230    iewExecRate
231        .name(name() + ".exec_rate")
232        .desc("Inst execution rate")
233        .flags(total);
234
235    iewExecRate = iewExecutedInsts / cpu->numCycles;
236
237    iewInstsToCommit
238        .init(cpu->numThreads)
239        .name(name() + ".wb_sent")
240        .desc("cumulative count of insts sent to commit")
241        .flags(total);
242
243    writebackCount
244        .init(cpu->numThreads)
245        .name(name() + ".wb_count")
246        .desc("cumulative count of insts written-back")
247        .flags(total);
248
249    producerInst
250        .init(cpu->numThreads)
251        .name(name() + ".wb_producers")
252        .desc("num instructions producing a value")
253        .flags(total);
254
255    consumerInst
256        .init(cpu->numThreads)
257        .name(name() + ".wb_consumers")
258        .desc("num instructions consuming a value")
259        .flags(total);
260
261    wbPenalized
262        .init(cpu->numThreads)
263        .name(name() + ".wb_penalized")
264        .desc("number of instrctions required to write to 'other' IQ")
265        .flags(total);
266
267    wbPenalizedRate
268        .name(name() + ".wb_penalized_rate")
269        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
270        .flags(total);
271
272    wbPenalizedRate = wbPenalized / writebackCount;
273
274    wbFanout
275        .name(name() + ".wb_fanout")
276        .desc("average fanout of values written-back")
277        .flags(total);
278
279    wbFanout = producerInst / consumerInst;
280
281    wbRate
282        .name(name() + ".wb_rate")
283        .desc("insts written-back per cycle")
284        .flags(total);
285    wbRate = writebackCount / cpu->numCycles;
286}
287
288template<class Impl>
289void
290DefaultIEW<Impl>::initStage()
291{
292    for (ThreadID tid = 0; tid < numThreads; tid++) {
293        toRename->iewInfo[tid].usedIQ = true;
294        toRename->iewInfo[tid].freeIQEntries =
295            instQueue.numFreeEntries(tid);
296
297        toRename->iewInfo[tid].usedLSQ = true;
298        toRename->iewInfo[tid].freeLSQEntries =
299            ldstQueue.numFreeEntries(tid);
300    }
301
302// Initialize the checker's dcache port here
303#if USE_CHECKER
304    if (cpu->checker) {
305        cpu->checker->setDcachePort(&cpu->getDataPort());
306     }
307#endif
308
309    cpu->activateStage(O3CPU::IEWIdx);
310}
311
312template<class Impl>
313void
314DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
315{
316    timeBuffer = tb_ptr;
317
318    // Setup wire to read information from time buffer, from commit.
319    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
320
321    // Setup wire to write information back to previous stages.
322    toRename = timeBuffer->getWire(0);
323
324    toFetch = timeBuffer->getWire(0);
325
326    // Instruction queue also needs main time buffer.
327    instQueue.setTimeBuffer(tb_ptr);
328}
329
330template<class Impl>
331void
332DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
333{
334    renameQueue = rq_ptr;
335
336    // Setup wire to read information from rename queue.
337    fromRename = renameQueue->getWire(-renameToIEWDelay);
338}
339
340template<class Impl>
341void
342DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
343{
344    iewQueue = iq_ptr;
345
346    // Setup wire to write instructions to commit.
347    toCommit = iewQueue->getWire(0);
348}
349
350template<class Impl>
351void
352DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
353{
354    activeThreads = at_ptr;
355
356    ldstQueue.setActiveThreads(at_ptr);
357    instQueue.setActiveThreads(at_ptr);
358}
359
360template<class Impl>
361void
362DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
363{
364    scoreboard = sb_ptr;
365}
366
367template <class Impl>
368bool
369DefaultIEW<Impl>::drain()
370{
371    // IEW is ready to drain at any time.
372    cpu->signalDrained();
373    return true;
374}
375
376template <class Impl>
377void
378DefaultIEW<Impl>::resume()
379{
380}
381
382template <class Impl>
383void
384DefaultIEW<Impl>::switchOut()
385{
386    // Clear any state.
387    switchedOut = true;
388    assert(insts[0].empty());
389    assert(skidBuffer[0].empty());
390
391    instQueue.switchOut();
392    ldstQueue.switchOut();
393    fuPool->switchOut();
394
395    for (ThreadID tid = 0; tid < numThreads; tid++) {
396        while (!insts[tid].empty())
397            insts[tid].pop();
398        while (!skidBuffer[tid].empty())
399            skidBuffer[tid].pop();
400    }
401}
402
403template <class Impl>
404void
405DefaultIEW<Impl>::takeOverFrom()
406{
407    // Reset all state.
408    _status = Active;
409    exeStatus = Running;
410    wbStatus = Idle;
411    switchedOut = false;
412
413    instQueue.takeOverFrom();
414    ldstQueue.takeOverFrom();
415    fuPool->takeOver();
416
417    initStage();
418    cpu->activityThisCycle();
419
420    for (ThreadID tid = 0; tid < numThreads; tid++) {
421        dispatchStatus[tid] = Running;
422        stalls[tid].commit = false;
423        fetchRedirect[tid] = false;
424    }
425
426    updateLSQNextCycle = false;
427
428    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
429        issueToExecQueue.advance();
430    }
431}
432
433template<class Impl>
434void
435DefaultIEW<Impl>::squash(ThreadID tid)
436{
437    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
438
439    // Tell the IQ to start squashing.
440    instQueue.squash(tid);
441
442    // Tell the LDSTQ to start squashing.
443    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
444    updatedQueues = true;
445
446    // Clear the skid buffer in case it has any data in it.
447    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
448            tid, fromCommit->commitInfo[tid].doneSeqNum);
449
450    while (!skidBuffer[tid].empty()) {
451        if (skidBuffer[tid].front()->isLoad() ||
452            skidBuffer[tid].front()->isStore() ) {
453            toRename->iewInfo[tid].dispatchedToLSQ++;
454        }
455
456        toRename->iewInfo[tid].dispatched++;
457
458        skidBuffer[tid].pop();
459    }
460
461    emptyRenameInsts(tid);
462}
463
464template<class Impl>
465void
466DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
467{
468    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
469            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
470
471    if (toCommit->squash[tid] == false ||
472            inst->seqNum < toCommit->squashedSeqNum[tid]) {
473        toCommit->squash[tid] = true;
474        toCommit->squashedSeqNum[tid] = inst->seqNum;
475        toCommit->branchTaken[tid] = inst->pcState().branching();
476
477        TheISA::PCState pc = inst->pcState();
478        TheISA::advancePC(pc, inst->staticInst);
479
480        toCommit->pc[tid] = pc;
481        toCommit->mispredictInst[tid] = inst;
482        toCommit->includeSquashInst[tid] = false;
483
484        wroteToTimeBuffer = true;
485    }
486
487}
488
489template<class Impl>
490void
491DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
492{
493    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
494            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
495    // Need to include inst->seqNum in the following comparison to cover the
496    // corner case when a branch misprediction and a memory violation for the
497    // same instruction (e.g. load PC) are detected in the same cycle.  In this
498    // case the memory violator should take precedence over the branch
499    // misprediction because it requires the violator itself to be included in
500    // the squash.
501    if (toCommit->squash[tid] == false ||
502            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
503        toCommit->squash[tid] = true;
504
505        toCommit->squashedSeqNum[tid] = inst->seqNum;
506        toCommit->pc[tid] = inst->pcState();
507        toCommit->mispredictInst[tid] = NULL;
508
509        // Must include the memory violator in the squash.
510        toCommit->includeSquashInst[tid] = true;
511
512        wroteToTimeBuffer = true;
513    }
514}
515
516template<class Impl>
517void
518DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
519{
520    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
521            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
522    if (toCommit->squash[tid] == false ||
523            inst->seqNum < toCommit->squashedSeqNum[tid]) {
524        toCommit->squash[tid] = true;
525
526        toCommit->squashedSeqNum[tid] = inst->seqNum;
527        toCommit->pc[tid] = inst->pcState();
528        toCommit->mispredictInst[tid] = NULL;
529
530        // Must include the broadcasted SN in the squash.
531        toCommit->includeSquashInst[tid] = true;
532
533        ldstQueue.setLoadBlockedHandled(tid);
534
535        wroteToTimeBuffer = true;
536    }
537}
538
539template<class Impl>
540void
541DefaultIEW<Impl>::block(ThreadID tid)
542{
543    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
544
545    if (dispatchStatus[tid] != Blocked &&
546        dispatchStatus[tid] != Unblocking) {
547        toRename->iewBlock[tid] = true;
548        wroteToTimeBuffer = true;
549    }
550
551    // Add the current inputs to the skid buffer so they can be
552    // reprocessed when this stage unblocks.
553    skidInsert(tid);
554
555    dispatchStatus[tid] = Blocked;
556}
557
558template<class Impl>
559void
560DefaultIEW<Impl>::unblock(ThreadID tid)
561{
562    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
563            "buffer %u.\n",tid, tid);
564
565    // If the skid bufffer is empty, signal back to previous stages to unblock.
566    // Also switch status to running.
567    if (skidBuffer[tid].empty()) {
568        toRename->iewUnblock[tid] = true;
569        wroteToTimeBuffer = true;
570        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
571        dispatchStatus[tid] = Running;
572    }
573}
574
575template<class Impl>
576void
577DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
578{
579    instQueue.wakeDependents(inst);
580}
581
582template<class Impl>
583void
584DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
585{
586    instQueue.rescheduleMemInst(inst);
587}
588
589template<class Impl>
590void
591DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
592{
593    instQueue.replayMemInst(inst);
594}
595
596template<class Impl>
597void
598DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
599{
600    // This function should not be called after writebackInsts in a
601    // single cycle.  That will cause problems with an instruction
602    // being added to the queue to commit without being processed by
603    // writebackInsts prior to being sent to commit.
604
605    // First check the time slot that this instruction will write
606    // to.  If there are free write ports at the time, then go ahead
607    // and write the instruction to that time.  If there are not,
608    // keep looking back to see where's the first time there's a
609    // free slot.
610    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
611        ++wbNumInst;
612        if (wbNumInst == wbWidth) {
613            ++wbCycle;
614            wbNumInst = 0;
615        }
616
617        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
618    }
619
620    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
621            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
622    // Add finished instruction to queue to commit.
623    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
624    (*iewQueue)[wbCycle].size++;
625}
626
627template <class Impl>
628unsigned
629DefaultIEW<Impl>::validInstsFromRename()
630{
631    unsigned inst_count = 0;
632
633    for (int i=0; i<fromRename->size; i++) {
634        if (!fromRename->insts[i]->isSquashed())
635            inst_count++;
636    }
637
638    return inst_count;
639}
640
641template<class Impl>
642void
643DefaultIEW<Impl>::skidInsert(ThreadID tid)
644{
645    DynInstPtr inst = NULL;
646
647    while (!insts[tid].empty()) {
648        inst = insts[tid].front();
649
650        insts[tid].pop();
651
652        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
653                "dispatch skidBuffer %i\n",tid, inst->seqNum,
654                inst->pcState(),tid);
655
656        skidBuffer[tid].push(inst);
657    }
658
659    assert(skidBuffer[tid].size() <= skidBufferMax &&
660           "Skidbuffer Exceeded Max Size");
661}
662
663template<class Impl>
664int
665DefaultIEW<Impl>::skidCount()
666{
667    int max=0;
668
669    list<ThreadID>::iterator threads = activeThreads->begin();
670    list<ThreadID>::iterator end = activeThreads->end();
671
672    while (threads != end) {
673        ThreadID tid = *threads++;
674        unsigned thread_count = skidBuffer[tid].size();
675        if (max < thread_count)
676            max = thread_count;
677    }
678
679    return max;
680}
681
682template<class Impl>
683bool
684DefaultIEW<Impl>::skidsEmpty()
685{
686    list<ThreadID>::iterator threads = activeThreads->begin();
687    list<ThreadID>::iterator end = activeThreads->end();
688
689    while (threads != end) {
690        ThreadID tid = *threads++;
691
692        if (!skidBuffer[tid].empty())
693            return false;
694    }
695
696    return true;
697}
698
699template <class Impl>
700void
701DefaultIEW<Impl>::updateStatus()
702{
703    bool any_unblocking = false;
704
705    list<ThreadID>::iterator threads = activeThreads->begin();
706    list<ThreadID>::iterator end = activeThreads->end();
707
708    while (threads != end) {
709        ThreadID tid = *threads++;
710
711        if (dispatchStatus[tid] == Unblocking) {
712            any_unblocking = true;
713            break;
714        }
715    }
716
717    // If there are no ready instructions waiting to be scheduled by the IQ,
718    // and there's no stores waiting to write back, and dispatch is not
719    // unblocking, then there is no internal activity for the IEW stage.
720    instQueue.intInstQueueReads++;
721    if (_status == Active && !instQueue.hasReadyInsts() &&
722        !ldstQueue.willWB() && !any_unblocking) {
723        DPRINTF(IEW, "IEW switching to idle\n");
724
725        deactivateStage();
726
727        _status = Inactive;
728    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
729                                       ldstQueue.willWB() ||
730                                       any_unblocking)) {
731        // Otherwise there is internal activity.  Set to active.
732        DPRINTF(IEW, "IEW switching to active\n");
733
734        activateStage();
735
736        _status = Active;
737    }
738}
739
740template <class Impl>
741void
742DefaultIEW<Impl>::resetEntries()
743{
744    instQueue.resetEntries();
745    ldstQueue.resetEntries();
746}
747
748template <class Impl>
749void
750DefaultIEW<Impl>::readStallSignals(ThreadID tid)
751{
752    if (fromCommit->commitBlock[tid]) {
753        stalls[tid].commit = true;
754    }
755
756    if (fromCommit->commitUnblock[tid]) {
757        assert(stalls[tid].commit);
758        stalls[tid].commit = false;
759    }
760}
761
762template <class Impl>
763bool
764DefaultIEW<Impl>::checkStall(ThreadID tid)
765{
766    bool ret_val(false);
767
768    if (stalls[tid].commit) {
769        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
770        ret_val = true;
771    } else if (instQueue.isFull(tid)) {
772        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
773        ret_val = true;
774    } else if (ldstQueue.isFull(tid)) {
775        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
776
777        if (ldstQueue.numLoads(tid) > 0 ) {
778
779            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
780                    tid,ldstQueue.getLoadHeadSeqNum(tid));
781        }
782
783        if (ldstQueue.numStores(tid) > 0) {
784
785            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
786                    tid,ldstQueue.getStoreHeadSeqNum(tid));
787        }
788
789        ret_val = true;
790    } else if (ldstQueue.isStalled(tid)) {
791        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
792        ret_val = true;
793    }
794
795    return ret_val;
796}
797
798template <class Impl>
799void
800DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
801{
802    // Check if there's a squash signal, squash if there is
803    // Check stall signals, block if there is.
804    // If status was Blocked
805    //     if so then go to unblocking
806    // If status was Squashing
807    //     check if squashing is not high.  Switch to running this cycle.
808
809    readStallSignals(tid);
810
811    if (fromCommit->commitInfo[tid].squash) {
812        squash(tid);
813
814        if (dispatchStatus[tid] == Blocked ||
815            dispatchStatus[tid] == Unblocking) {
816            toRename->iewUnblock[tid] = true;
817            wroteToTimeBuffer = true;
818        }
819
820        dispatchStatus[tid] = Squashing;
821        fetchRedirect[tid] = false;
822        return;
823    }
824
825    if (fromCommit->commitInfo[tid].robSquashing) {
826        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
827
828        dispatchStatus[tid] = Squashing;
829        emptyRenameInsts(tid);
830        wroteToTimeBuffer = true;
831        return;
832    }
833
834    if (checkStall(tid)) {
835        block(tid);
836        dispatchStatus[tid] = Blocked;
837        return;
838    }
839
840    if (dispatchStatus[tid] == Blocked) {
841        // Status from previous cycle was blocked, but there are no more stall
842        // conditions.  Switch over to unblocking.
843        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
844                tid);
845
846        dispatchStatus[tid] = Unblocking;
847
848        unblock(tid);
849
850        return;
851    }
852
853    if (dispatchStatus[tid] == Squashing) {
854        // Switch status to running if rename isn't being told to block or
855        // squash this cycle.
856        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
857                tid);
858
859        dispatchStatus[tid] = Running;
860
861        return;
862    }
863}
864
865template <class Impl>
866void
867DefaultIEW<Impl>::sortInsts()
868{
869    int insts_from_rename = fromRename->size;
870#ifdef DEBUG
871    for (ThreadID tid = 0; tid < numThreads; tid++)
872        assert(insts[tid].empty());
873#endif
874    for (int i = 0; i < insts_from_rename; ++i) {
875        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
876    }
877}
878
879template <class Impl>
880void
881DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
882{
883    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
884
885    while (!insts[tid].empty()) {
886
887        if (insts[tid].front()->isLoad() ||
888            insts[tid].front()->isStore() ) {
889            toRename->iewInfo[tid].dispatchedToLSQ++;
890        }
891
892        toRename->iewInfo[tid].dispatched++;
893
894        insts[tid].pop();
895    }
896}
897
898template <class Impl>
899void
900DefaultIEW<Impl>::wakeCPU()
901{
902    cpu->wakeCPU();
903}
904
905template <class Impl>
906void
907DefaultIEW<Impl>::activityThisCycle()
908{
909    DPRINTF(Activity, "Activity this cycle.\n");
910    cpu->activityThisCycle();
911}
912
913template <class Impl>
914inline void
915DefaultIEW<Impl>::activateStage()
916{
917    DPRINTF(Activity, "Activating stage.\n");
918    cpu->activateStage(O3CPU::IEWIdx);
919}
920
921template <class Impl>
922inline void
923DefaultIEW<Impl>::deactivateStage()
924{
925    DPRINTF(Activity, "Deactivating stage.\n");
926    cpu->deactivateStage(O3CPU::IEWIdx);
927}
928
929template<class Impl>
930void
931DefaultIEW<Impl>::dispatch(ThreadID tid)
932{
933    // If status is Running or idle,
934    //     call dispatchInsts()
935    // If status is Unblocking,
936    //     buffer any instructions coming from rename
937    //     continue trying to empty skid buffer
938    //     check if stall conditions have passed
939
940    if (dispatchStatus[tid] == Blocked) {
941        ++iewBlockCycles;
942
943    } else if (dispatchStatus[tid] == Squashing) {
944        ++iewSquashCycles;
945    }
946
947    // Dispatch should try to dispatch as many instructions as its bandwidth
948    // will allow, as long as it is not currently blocked.
949    if (dispatchStatus[tid] == Running ||
950        dispatchStatus[tid] == Idle) {
951        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
952                "dispatch.\n", tid);
953
954        dispatchInsts(tid);
955    } else if (dispatchStatus[tid] == Unblocking) {
956        // Make sure that the skid buffer has something in it if the
957        // status is unblocking.
958        assert(!skidsEmpty());
959
960        // If the status was unblocking, then instructions from the skid
961        // buffer were used.  Remove those instructions and handle
962        // the rest of unblocking.
963        dispatchInsts(tid);
964
965        ++iewUnblockCycles;
966
967        if (validInstsFromRename()) {
968            // Add the current inputs to the skid buffer so they can be
969            // reprocessed when this stage unblocks.
970            skidInsert(tid);
971        }
972
973        unblock(tid);
974    }
975}
976
977template <class Impl>
978void
979DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
980{
981    // Obtain instructions from skid buffer if unblocking, or queue from rename
982    // otherwise.
983    std::queue<DynInstPtr> &insts_to_dispatch =
984        dispatchStatus[tid] == Unblocking ?
985        skidBuffer[tid] : insts[tid];
986
987    int insts_to_add = insts_to_dispatch.size();
988
989    DynInstPtr inst;
990    bool add_to_iq = false;
991    int dis_num_inst = 0;
992
993    // Loop through the instructions, putting them in the instruction
994    // queue.
995    for ( ; dis_num_inst < insts_to_add &&
996              dis_num_inst < dispatchWidth;
997          ++dis_num_inst)
998    {
999        inst = insts_to_dispatch.front();
1000
1001        if (dispatchStatus[tid] == Unblocking) {
1002            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1003                    "buffer\n", tid);
1004        }
1005
1006        // Make sure there's a valid instruction there.
1007        assert(inst);
1008
1009        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
1010                "IQ.\n",
1011                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1012
1013        // Be sure to mark these instructions as ready so that the
1014        // commit stage can go ahead and execute them, and mark
1015        // them as issued so the IQ doesn't reprocess them.
1016
1017        // Check for squashed instructions.
1018        if (inst->isSquashed()) {
1019            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1020                    "not adding to IQ.\n", tid);
1021
1022            ++iewDispSquashedInsts;
1023
1024            insts_to_dispatch.pop();
1025
1026            //Tell Rename That An Instruction has been processed
1027            if (inst->isLoad() || inst->isStore()) {
1028                toRename->iewInfo[tid].dispatchedToLSQ++;
1029            }
1030            toRename->iewInfo[tid].dispatched++;
1031
1032            continue;
1033        }
1034
1035        // Check for full conditions.
1036        if (instQueue.isFull(tid)) {
1037            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1038
1039            // Call function to start blocking.
1040            block(tid);
1041
1042            // Set unblock to false. Special case where we are using
1043            // skidbuffer (unblocking) instructions but then we still
1044            // get full in the IQ.
1045            toRename->iewUnblock[tid] = false;
1046
1047            ++iewIQFullEvents;
1048            break;
1049        } else if (ldstQueue.isFull(tid)) {
1050            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1051
1052            // Call function to start blocking.
1053            block(tid);
1054
1055            // Set unblock to false. Special case where we are using
1056            // skidbuffer (unblocking) instructions but then we still
1057            // get full in the IQ.
1058            toRename->iewUnblock[tid] = false;
1059
1060            ++iewLSQFullEvents;
1061            break;
1062        }
1063
1064        // Otherwise issue the instruction just fine.
1065        if (inst->isLoad()) {
1066            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1067                    "encountered, adding to LSQ.\n", tid);
1068
1069            // Reserve a spot in the load store queue for this
1070            // memory access.
1071            ldstQueue.insertLoad(inst);
1072
1073            ++iewDispLoadInsts;
1074
1075            add_to_iq = true;
1076
1077            toRename->iewInfo[tid].dispatchedToLSQ++;
1078        } else if (inst->isStore()) {
1079            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1080                    "encountered, adding to LSQ.\n", tid);
1081
1082            ldstQueue.insertStore(inst);
1083
1084            ++iewDispStoreInsts;
1085
1086            if (inst->isStoreConditional()) {
1087                // Store conditionals need to be set as "canCommit()"
1088                // so that commit can process them when they reach the
1089                // head of commit.
1090                // @todo: This is somewhat specific to Alpha.
1091                inst->setCanCommit();
1092                instQueue.insertNonSpec(inst);
1093                add_to_iq = false;
1094
1095                ++iewDispNonSpecInsts;
1096            } else {
1097                add_to_iq = true;
1098            }
1099
1100            toRename->iewInfo[tid].dispatchedToLSQ++;
1101        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1102            // Same as non-speculative stores.
1103            inst->setCanCommit();
1104            instQueue.insertBarrier(inst);
1105            add_to_iq = false;
1106        } else if (inst->isNop()) {
1107            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1108                    "skipping.\n", tid);
1109
1110            inst->setIssued();
1111            inst->setExecuted();
1112            inst->setCanCommit();
1113
1114            instQueue.recordProducer(inst);
1115
1116            iewExecutedNop[tid]++;
1117
1118            add_to_iq = false;
1119        } else if (inst->isExecuted()) {
1120            assert(0 && "Instruction shouldn't be executed.\n");
1121            DPRINTF(IEW, "Issue: Executed branch encountered, "
1122                    "skipping.\n");
1123
1124            inst->setIssued();
1125            inst->setCanCommit();
1126
1127            instQueue.recordProducer(inst);
1128
1129            add_to_iq = false;
1130        } else {
1131            add_to_iq = true;
1132        }
1133        if (inst->isNonSpeculative()) {
1134            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1135                    "encountered, skipping.\n", tid);
1136
1137            // Same as non-speculative stores.
1138            inst->setCanCommit();
1139
1140            // Specifically insert it as nonspeculative.
1141            instQueue.insertNonSpec(inst);
1142
1143            ++iewDispNonSpecInsts;
1144
1145            add_to_iq = false;
1146        }
1147
1148        // If the instruction queue is not full, then add the
1149        // instruction.
1150        if (add_to_iq) {
1151            instQueue.insert(inst);
1152        }
1153
1154        insts_to_dispatch.pop();
1155
1156        toRename->iewInfo[tid].dispatched++;
1157
1158        ++iewDispatchedInsts;
1159
1160#if TRACING_ON
1161        inst->dispatchTick = curTick();
1162#endif
1163    }
1164
1165    if (!insts_to_dispatch.empty()) {
1166        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1167        block(tid);
1168        toRename->iewUnblock[tid] = false;
1169    }
1170
1171    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1172        dispatchStatus[tid] = Running;
1173
1174        updatedQueues = true;
1175    }
1176
1177    dis_num_inst = 0;
1178}
1179
1180template <class Impl>
1181void
1182DefaultIEW<Impl>::printAvailableInsts()
1183{
1184    int inst = 0;
1185
1186    std::cout << "Available Instructions: ";
1187
1188    while (fromIssue->insts[inst]) {
1189
1190        if (inst%3==0) std::cout << "\n\t";
1191
1192        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1193             << " TN: " << fromIssue->insts[inst]->threadNumber
1194             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1195
1196        inst++;
1197
1198    }
1199
1200    std::cout << "\n";
1201}
1202
1203template <class Impl>
1204void
1205DefaultIEW<Impl>::executeInsts()
1206{
1207    wbNumInst = 0;
1208    wbCycle = 0;
1209
1210    list<ThreadID>::iterator threads = activeThreads->begin();
1211    list<ThreadID>::iterator end = activeThreads->end();
1212
1213    while (threads != end) {
1214        ThreadID tid = *threads++;
1215        fetchRedirect[tid] = false;
1216    }
1217
1218    // Uncomment this if you want to see all available instructions.
1219    // @todo This doesn't actually work anymore, we should fix it.
1220//    printAvailableInsts();
1221
1222    // Execute/writeback any instructions that are available.
1223    int insts_to_execute = fromIssue->size;
1224    int inst_num = 0;
1225    for (; inst_num < insts_to_execute;
1226          ++inst_num) {
1227
1228        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1229
1230        DynInstPtr inst = instQueue.getInstToExecute();
1231
1232        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1233                inst->pcState(), inst->threadNumber,inst->seqNum);
1234
1235        // Check if the instruction is squashed; if so then skip it
1236        if (inst->isSquashed()) {
1237            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1238                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1239                         inst->seqNum);
1240
1241            // Consider this instruction executed so that commit can go
1242            // ahead and retire the instruction.
1243            inst->setExecuted();
1244
1245            // Not sure if I should set this here or just let commit try to
1246            // commit any squashed instructions.  I like the latter a bit more.
1247            inst->setCanCommit();
1248
1249            ++iewExecSquashedInsts;
1250
1251            decrWb(inst->seqNum);
1252            continue;
1253        }
1254
1255        Fault fault = NoFault;
1256
1257        // Execute instruction.
1258        // Note that if the instruction faults, it will be handled
1259        // at the commit stage.
1260        if (inst->isMemRef()) {
1261            DPRINTF(IEW, "Execute: Calculating address for memory "
1262                    "reference.\n");
1263
1264            // Tell the LDSTQ to execute this instruction (if it is a load).
1265            if (inst->isLoad()) {
1266                // Loads will mark themselves as executed, and their writeback
1267                // event adds the instruction to the queue to commit
1268                fault = ldstQueue.executeLoad(inst);
1269
1270                if (inst->isTranslationDelayed() &&
1271                    fault == NoFault) {
1272                    // A hw page table walk is currently going on; the
1273                    // instruction must be deferred.
1274                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1275                            "load.\n");
1276                    instQueue.deferMemInst(inst);
1277                    continue;
1278                }
1279
1280                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1281                    inst->fault = NoFault;
1282                }
1283            } else if (inst->isStore()) {
1284                fault = ldstQueue.executeStore(inst);
1285
1286                if (inst->isTranslationDelayed() &&
1287                    fault == NoFault) {
1288                    // A hw page table walk is currently going on; the
1289                    // instruction must be deferred.
1290                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1291                            "store.\n");
1292                    instQueue.deferMemInst(inst);
1293                    continue;
1294                }
1295
1296                // If the store had a fault then it may not have a mem req
1297                if (fault != NoFault || inst->readPredicate() == false ||
1298                        !inst->isStoreConditional()) {
1299                    // If the instruction faulted, then we need to send it along
1300                    // to commit without the instruction completing.
1301                    // Send this instruction to commit, also make sure iew stage
1302                    // realizes there is activity.
1303                    inst->setExecuted();
1304                    instToCommit(inst);
1305                    activityThisCycle();
1306                }
1307
1308                // Store conditionals will mark themselves as
1309                // executed, and their writeback event will add the
1310                // instruction to the queue to commit.
1311            } else {
1312                panic("Unexpected memory type!\n");
1313            }
1314
1315        } else {
1316            // If the instruction has already faulted, then skip executing it.
1317            // Such case can happen when it faulted during ITLB translation.
1318            // If we execute the instruction (even if it's a nop) the fault
1319            // will be replaced and we will lose it.
1320            if (inst->getFault() == NoFault) {
1321                inst->execute();
1322                if (inst->readPredicate() == false)
1323                    inst->forwardOldRegs();
1324            }
1325
1326            inst->setExecuted();
1327
1328            instToCommit(inst);
1329        }
1330
1331        updateExeInstStats(inst);
1332
1333        // Check if branch prediction was correct, if not then we need
1334        // to tell commit to squash in flight instructions.  Only
1335        // handle this if there hasn't already been something that
1336        // redirects fetch in this group of instructions.
1337
1338        // This probably needs to prioritize the redirects if a different
1339        // scheduler is used.  Currently the scheduler schedules the oldest
1340        // instruction first, so the branch resolution order will be correct.
1341        ThreadID tid = inst->threadNumber;
1342
1343        if (!fetchRedirect[tid] ||
1344            !toCommit->squash[tid] ||
1345            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1346
1347            // Prevent testing for misprediction on load instructions,
1348            // that have not been executed.
1349            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1350
1351            if (inst->mispredicted() && !loadNotExecuted) {
1352                fetchRedirect[tid] = true;
1353
1354                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1355                DPRINTF(IEW, "Predicted target was PC: %s.\n",
1356                        inst->readPredTarg());
1357                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1358                        inst->pcState());
1359                // If incorrect, then signal the ROB that it must be squashed.
1360                squashDueToBranch(inst, tid);
1361
1362                if (inst->readPredTaken()) {
1363                    predictedTakenIncorrect++;
1364                } else {
1365                    predictedNotTakenIncorrect++;
1366                }
1367            } else if (ldstQueue.violation(tid)) {
1368                assert(inst->isMemRef());
1369                // If there was an ordering violation, then get the
1370                // DynInst that caused the violation.  Note that this
1371                // clears the violation signal.
1372                DynInstPtr violator;
1373                violator = ldstQueue.getMemDepViolator(tid);
1374
1375                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1376                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1377                        violator->pcState(), violator->seqNum,
1378                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1379
1380                fetchRedirect[tid] = true;
1381
1382                // Tell the instruction queue that a violation has occured.
1383                instQueue.violation(inst, violator);
1384
1385                // Squash.
1386                squashDueToMemOrder(violator, tid);
1387
1388                ++memOrderViolationEvents;
1389            } else if (ldstQueue.loadBlocked(tid) &&
1390                       !ldstQueue.isLoadBlockedHandled(tid)) {
1391                fetchRedirect[tid] = true;
1392
1393                DPRINTF(IEW, "Load operation couldn't execute because the "
1394                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1395                        inst->pcState(), inst->seqNum);
1396
1397                squashDueToMemBlocked(inst, tid);
1398            }
1399        } else {
1400            // Reset any state associated with redirects that will not
1401            // be used.
1402            if (ldstQueue.violation(tid)) {
1403                assert(inst->isMemRef());
1404
1405                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1406
1407                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1408                        "%s, inst PC: %s.  Addr is: %#x.\n",
1409                        violator->pcState(), inst->pcState(),
1410                        inst->physEffAddr);
1411                DPRINTF(IEW, "Violation will not be handled because "
1412                        "already squashing\n");
1413
1414                ++memOrderViolationEvents;
1415            }
1416            if (ldstQueue.loadBlocked(tid) &&
1417                !ldstQueue.isLoadBlockedHandled(tid)) {
1418                DPRINTF(IEW, "Load operation couldn't execute because the "
1419                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1420                        inst->pcState(), inst->seqNum);
1421                DPRINTF(IEW, "Blocked load will not be handled because "
1422                        "already squashing\n");
1423
1424                ldstQueue.setLoadBlockedHandled(tid);
1425            }
1426
1427        }
1428    }
1429
1430    // Update and record activity if we processed any instructions.
1431    if (inst_num) {
1432        if (exeStatus == Idle) {
1433            exeStatus = Running;
1434        }
1435
1436        updatedQueues = true;
1437
1438        cpu->activityThisCycle();
1439    }
1440
1441    // Need to reset this in case a writeback event needs to write into the
1442    // iew queue.  That way the writeback event will write into the correct
1443    // spot in the queue.
1444    wbNumInst = 0;
1445
1446}
1447
1448template <class Impl>
1449void
1450DefaultIEW<Impl>::writebackInsts()
1451{
1452    // Loop through the head of the time buffer and wake any
1453    // dependents.  These instructions are about to write back.  Also
1454    // mark scoreboard that this instruction is finally complete.
1455    // Either have IEW have direct access to scoreboard, or have this
1456    // as part of backwards communication.
1457    for (int inst_num = 0; inst_num < wbWidth &&
1458             toCommit->insts[inst_num]; inst_num++) {
1459        DynInstPtr inst = toCommit->insts[inst_num];
1460        ThreadID tid = inst->threadNumber;
1461
1462        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1463                inst->seqNum, inst->pcState());
1464
1465        iewInstsToCommit[tid]++;
1466
1467        // Some instructions will be sent to commit without having
1468        // executed because they need commit to handle them.
1469        // E.g. Uncached loads have not actually executed when they
1470        // are first sent to commit.  Instead commit must tell the LSQ
1471        // when it's ready to execute the uncached load.
1472        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1473            int dependents = instQueue.wakeDependents(inst);
1474
1475            for (int i = 0; i < inst->numDestRegs(); i++) {
1476                //mark as Ready
1477                DPRINTF(IEW,"Setting Destination Register %i\n",
1478                        inst->renamedDestRegIdx(i));
1479                scoreboard->setReg(inst->renamedDestRegIdx(i));
1480            }
1481
1482            if (dependents) {
1483                producerInst[tid]++;
1484                consumerInst[tid]+= dependents;
1485            }
1486            writebackCount[tid]++;
1487        }
1488
1489        decrWb(inst->seqNum);
1490    }
1491}
1492
1493template<class Impl>
1494void
1495DefaultIEW<Impl>::tick()
1496{
1497    wbNumInst = 0;
1498    wbCycle = 0;
1499
1500    wroteToTimeBuffer = false;
1501    updatedQueues = false;
1502
1503    sortInsts();
1504
1505    // Free function units marked as being freed this cycle.
1506    fuPool->processFreeUnits();
1507
1508    list<ThreadID>::iterator threads = activeThreads->begin();
1509    list<ThreadID>::iterator end = activeThreads->end();
1510
1511    // Check stall and squash signals, dispatch any instructions.
1512    while (threads != end) {
1513        ThreadID tid = *threads++;
1514
1515        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1516
1517        checkSignalsAndUpdate(tid);
1518        dispatch(tid);
1519    }
1520
1521    if (exeStatus != Squashing) {
1522        executeInsts();
1523
1524        writebackInsts();
1525
1526        // Have the instruction queue try to schedule any ready instructions.
1527        // (In actuality, this scheduling is for instructions that will
1528        // be executed next cycle.)
1529        instQueue.scheduleReadyInsts();
1530
1531        // Also should advance its own time buffers if the stage ran.
1532        // Not the best place for it, but this works (hopefully).
1533        issueToExecQueue.advance();
1534    }
1535
1536    bool broadcast_free_entries = false;
1537
1538    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1539        exeStatus = Idle;
1540        updateLSQNextCycle = false;
1541
1542        broadcast_free_entries = true;
1543    }
1544
1545    // Writeback any stores using any leftover bandwidth.
1546    ldstQueue.writebackStores();
1547
1548    // Check the committed load/store signals to see if there's a load
1549    // or store to commit.  Also check if it's being told to execute a
1550    // nonspeculative instruction.
1551    // This is pretty inefficient...
1552
1553    threads = activeThreads->begin();
1554    while (threads != end) {
1555        ThreadID tid = (*threads++);
1556
1557        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1558
1559        // Update structures based on instructions committed.
1560        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1561            !fromCommit->commitInfo[tid].squash &&
1562            !fromCommit->commitInfo[tid].robSquashing) {
1563
1564            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1565
1566            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1567
1568            updateLSQNextCycle = true;
1569            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1570        }
1571
1572        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1573
1574            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1575            if (fromCommit->commitInfo[tid].uncached) {
1576                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1577                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1578            } else {
1579                instQueue.scheduleNonSpec(
1580                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1581            }
1582        }
1583
1584        if (broadcast_free_entries) {
1585            toFetch->iewInfo[tid].iqCount =
1586                instQueue.getCount(tid);
1587            toFetch->iewInfo[tid].ldstqCount =
1588                ldstQueue.getCount(tid);
1589
1590            toRename->iewInfo[tid].usedIQ = true;
1591            toRename->iewInfo[tid].freeIQEntries =
1592                instQueue.numFreeEntries();
1593            toRename->iewInfo[tid].usedLSQ = true;
1594            toRename->iewInfo[tid].freeLSQEntries =
1595                ldstQueue.numFreeEntries(tid);
1596
1597            wroteToTimeBuffer = true;
1598        }
1599
1600        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1601                tid, toRename->iewInfo[tid].dispatched);
1602    }
1603
1604    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1605            "LSQ has %i free entries.\n",
1606            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1607            ldstQueue.numFreeEntries());
1608
1609    updateStatus();
1610
1611    if (wroteToTimeBuffer) {
1612        DPRINTF(Activity, "Activity this cycle.\n");
1613        cpu->activityThisCycle();
1614    }
1615}
1616
1617template <class Impl>
1618void
1619DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1620{
1621    ThreadID tid = inst->threadNumber;
1622
1623    //
1624    //  Pick off the software prefetches
1625    //
1626#ifdef TARGET_ALPHA
1627    if (inst->isDataPrefetch())
1628        iewExecutedSwp[tid]++;
1629    else
1630        iewIewExecutedcutedInsts++;
1631#else
1632    iewExecutedInsts++;
1633#endif
1634
1635#if TRACING_ON
1636    inst->completeTick = curTick();
1637#endif
1638
1639    //
1640    //  Control operations
1641    //
1642    if (inst->isControl())
1643        iewExecutedBranches[tid]++;
1644
1645    //
1646    //  Memory operations
1647    //
1648    if (inst->isMemRef()) {
1649        iewExecutedRefs[tid]++;
1650
1651        if (inst->isLoad()) {
1652            iewExecLoadInsts[tid]++;
1653        }
1654    }
1655}
1656
1657template <class Impl>
1658void
1659DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1660{
1661    ThreadID tid = inst->threadNumber;
1662
1663    if (!fetchRedirect[tid] ||
1664        !toCommit->squash[tid] ||
1665        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1666
1667        if (inst->mispredicted()) {
1668            fetchRedirect[tid] = true;
1669
1670            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1671            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1672                    inst->predInstAddr(), inst->predNextInstAddr());
1673            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1674                    " NPC: %#x.\n", inst->nextInstAddr(),
1675                    inst->nextInstAddr());
1676            // If incorrect, then signal the ROB that it must be squashed.
1677            squashDueToBranch(inst, tid);
1678
1679            if (inst->readPredTaken()) {
1680                predictedTakenIncorrect++;
1681            } else {
1682                predictedNotTakenIncorrect++;
1683            }
1684        }
1685    }
1686}
1687