iew_impl.hh revision 7852 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "cpu/timebuf.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template<class Impl>
58DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
59    : issueToExecQueue(params->backComSize, params->forwardComSize),
60      cpu(_cpu),
61      instQueue(_cpu, this, params),
62      ldstQueue(_cpu, this, params),
63      fuPool(params->fuPool),
64      commitToIEWDelay(params->commitToIEWDelay),
65      renameToIEWDelay(params->renameToIEWDelay),
66      issueToExecuteDelay(params->issueToExecuteDelay),
67      dispatchWidth(params->dispatchWidth),
68      issueWidth(params->issueWidth),
69      wbOutstanding(0),
70      wbWidth(params->wbWidth),
71      numThreads(params->numThreads),
72      switchedOut(false)
73{
74    _status = Active;
75    exeStatus = Running;
76    wbStatus = Idle;
77
78    // Setup wire to read instructions coming from issue.
79    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
80
81    // Instruction queue needs the queue between issue and execute.
82    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
83
84    for (ThreadID tid = 0; tid < numThreads; tid++) {
85        dispatchStatus[tid] = Running;
86        stalls[tid].commit = false;
87        fetchRedirect[tid] = false;
88    }
89
90    wbMax = wbWidth * params->wbDepth;
91
92    updateLSQNextCycle = false;
93
94    ableToIssue = true;
95
96    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
97}
98
99template <class Impl>
100std::string
101DefaultIEW<Impl>::name() const
102{
103    return cpu->name() + ".iew";
104}
105
106template <class Impl>
107void
108DefaultIEW<Impl>::regStats()
109{
110    using namespace Stats;
111
112    instQueue.regStats();
113    ldstQueue.regStats();
114
115    iewIdleCycles
116        .name(name() + ".iewIdleCycles")
117        .desc("Number of cycles IEW is idle");
118
119    iewSquashCycles
120        .name(name() + ".iewSquashCycles")
121        .desc("Number of cycles IEW is squashing");
122
123    iewBlockCycles
124        .name(name() + ".iewBlockCycles")
125        .desc("Number of cycles IEW is blocking");
126
127    iewUnblockCycles
128        .name(name() + ".iewUnblockCycles")
129        .desc("Number of cycles IEW is unblocking");
130
131    iewDispatchedInsts
132        .name(name() + ".iewDispatchedInsts")
133        .desc("Number of instructions dispatched to IQ");
134
135    iewDispSquashedInsts
136        .name(name() + ".iewDispSquashedInsts")
137        .desc("Number of squashed instructions skipped by dispatch");
138
139    iewDispLoadInsts
140        .name(name() + ".iewDispLoadInsts")
141        .desc("Number of dispatched load instructions");
142
143    iewDispStoreInsts
144        .name(name() + ".iewDispStoreInsts")
145        .desc("Number of dispatched store instructions");
146
147    iewDispNonSpecInsts
148        .name(name() + ".iewDispNonSpecInsts")
149        .desc("Number of dispatched non-speculative instructions");
150
151    iewIQFullEvents
152        .name(name() + ".iewIQFullEvents")
153        .desc("Number of times the IQ has become full, causing a stall");
154
155    iewLSQFullEvents
156        .name(name() + ".iewLSQFullEvents")
157        .desc("Number of times the LSQ has become full, causing a stall");
158
159    memOrderViolationEvents
160        .name(name() + ".memOrderViolationEvents")
161        .desc("Number of memory order violations");
162
163    predictedTakenIncorrect
164        .name(name() + ".predictedTakenIncorrect")
165        .desc("Number of branches that were predicted taken incorrectly");
166
167    predictedNotTakenIncorrect
168        .name(name() + ".predictedNotTakenIncorrect")
169        .desc("Number of branches that were predicted not taken incorrectly");
170
171    branchMispredicts
172        .name(name() + ".branchMispredicts")
173        .desc("Number of branch mispredicts detected at execute");
174
175    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
176
177    iewExecutedInsts
178        .name(name() + ".iewExecutedInsts")
179        .desc("Number of executed instructions");
180
181    iewExecLoadInsts
182        .init(cpu->numThreads)
183        .name(name() + ".iewExecLoadInsts")
184        .desc("Number of load instructions executed")
185        .flags(total);
186
187    iewExecSquashedInsts
188        .name(name() + ".iewExecSquashedInsts")
189        .desc("Number of squashed instructions skipped in execute");
190
191    iewExecutedSwp
192        .init(cpu->numThreads)
193        .name(name() + ".EXEC:swp")
194        .desc("number of swp insts executed")
195        .flags(total);
196
197    iewExecutedNop
198        .init(cpu->numThreads)
199        .name(name() + ".EXEC:nop")
200        .desc("number of nop insts executed")
201        .flags(total);
202
203    iewExecutedRefs
204        .init(cpu->numThreads)
205        .name(name() + ".EXEC:refs")
206        .desc("number of memory reference insts executed")
207        .flags(total);
208
209    iewExecutedBranches
210        .init(cpu->numThreads)
211        .name(name() + ".EXEC:branches")
212        .desc("Number of branches executed")
213        .flags(total);
214
215    iewExecStoreInsts
216        .name(name() + ".EXEC:stores")
217        .desc("Number of stores executed")
218        .flags(total);
219    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
220
221    iewExecRate
222        .name(name() + ".EXEC:rate")
223        .desc("Inst execution rate")
224        .flags(total);
225
226    iewExecRate = iewExecutedInsts / cpu->numCycles;
227
228    iewInstsToCommit
229        .init(cpu->numThreads)
230        .name(name() + ".WB:sent")
231        .desc("cumulative count of insts sent to commit")
232        .flags(total);
233
234    writebackCount
235        .init(cpu->numThreads)
236        .name(name() + ".WB:count")
237        .desc("cumulative count of insts written-back")
238        .flags(total);
239
240    producerInst
241        .init(cpu->numThreads)
242        .name(name() + ".WB:producers")
243        .desc("num instructions producing a value")
244        .flags(total);
245
246    consumerInst
247        .init(cpu->numThreads)
248        .name(name() + ".WB:consumers")
249        .desc("num instructions consuming a value")
250        .flags(total);
251
252    wbPenalized
253        .init(cpu->numThreads)
254        .name(name() + ".WB:penalized")
255        .desc("number of instrctions required to write to 'other' IQ")
256        .flags(total);
257
258    wbPenalizedRate
259        .name(name() + ".WB:penalized_rate")
260        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
261        .flags(total);
262
263    wbPenalizedRate = wbPenalized / writebackCount;
264
265    wbFanout
266        .name(name() + ".WB:fanout")
267        .desc("average fanout of values written-back")
268        .flags(total);
269
270    wbFanout = producerInst / consumerInst;
271
272    wbRate
273        .name(name() + ".WB:rate")
274        .desc("insts written-back per cycle")
275        .flags(total);
276    wbRate = writebackCount / cpu->numCycles;
277}
278
279template<class Impl>
280void
281DefaultIEW<Impl>::initStage()
282{
283    for (ThreadID tid = 0; tid < numThreads; tid++) {
284        toRename->iewInfo[tid].usedIQ = true;
285        toRename->iewInfo[tid].freeIQEntries =
286            instQueue.numFreeEntries(tid);
287
288        toRename->iewInfo[tid].usedLSQ = true;
289        toRename->iewInfo[tid].freeLSQEntries =
290            ldstQueue.numFreeEntries(tid);
291    }
292
293    cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300    timeBuffer = tb_ptr;
301
302    // Setup wire to read information from time buffer, from commit.
303    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
304
305    // Setup wire to write information back to previous stages.
306    toRename = timeBuffer->getWire(0);
307
308    toFetch = timeBuffer->getWire(0);
309
310    // Instruction queue also needs main time buffer.
311    instQueue.setTimeBuffer(tb_ptr);
312}
313
314template<class Impl>
315void
316DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317{
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    iewQueue = iq_ptr;
329
330    // Setup wire to write instructions to commit.
331    toCommit = iewQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
337{
338    activeThreads = at_ptr;
339
340    ldstQueue.setActiveThreads(at_ptr);
341    instQueue.setActiveThreads(at_ptr);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
347{
348    scoreboard = sb_ptr;
349}
350
351template <class Impl>
352bool
353DefaultIEW<Impl>::drain()
354{
355    // IEW is ready to drain at any time.
356    cpu->signalDrained();
357    return true;
358}
359
360template <class Impl>
361void
362DefaultIEW<Impl>::resume()
363{
364}
365
366template <class Impl>
367void
368DefaultIEW<Impl>::switchOut()
369{
370    // Clear any state.
371    switchedOut = true;
372    assert(insts[0].empty());
373    assert(skidBuffer[0].empty());
374
375    instQueue.switchOut();
376    ldstQueue.switchOut();
377    fuPool->switchOut();
378
379    for (ThreadID tid = 0; tid < numThreads; tid++) {
380        while (!insts[tid].empty())
381            insts[tid].pop();
382        while (!skidBuffer[tid].empty())
383            skidBuffer[tid].pop();
384    }
385}
386
387template <class Impl>
388void
389DefaultIEW<Impl>::takeOverFrom()
390{
391    // Reset all state.
392    _status = Active;
393    exeStatus = Running;
394    wbStatus = Idle;
395    switchedOut = false;
396
397    instQueue.takeOverFrom();
398    ldstQueue.takeOverFrom();
399    fuPool->takeOverFrom();
400
401    initStage();
402    cpu->activityThisCycle();
403
404    for (ThreadID tid = 0; tid < numThreads; tid++) {
405        dispatchStatus[tid] = Running;
406        stalls[tid].commit = false;
407        fetchRedirect[tid] = false;
408    }
409
410    updateLSQNextCycle = false;
411
412    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
413        issueToExecQueue.advance();
414    }
415}
416
417template<class Impl>
418void
419DefaultIEW<Impl>::squash(ThreadID tid)
420{
421    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
422
423    // Tell the IQ to start squashing.
424    instQueue.squash(tid);
425
426    // Tell the LDSTQ to start squashing.
427    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428    updatedQueues = true;
429
430    // Clear the skid buffer in case it has any data in it.
431    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
432            tid, fromCommit->commitInfo[tid].doneSeqNum);
433
434    while (!skidBuffer[tid].empty()) {
435        if (skidBuffer[tid].front()->isLoad() ||
436            skidBuffer[tid].front()->isStore() ) {
437            toRename->iewInfo[tid].dispatchedToLSQ++;
438        }
439
440        toRename->iewInfo[tid].dispatched++;
441
442        skidBuffer[tid].pop();
443    }
444
445    emptyRenameInsts(tid);
446}
447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455    if (toCommit->squash[tid] == false ||
456            inst->seqNum < toCommit->squashedSeqNum[tid]) {
457        toCommit->squash[tid] = true;
458        toCommit->squashedSeqNum[tid] = inst->seqNum;
459        toCommit->mispredPC[tid] = inst->instAddr();
460        toCommit->branchMispredict[tid] = true;
461        toCommit->branchTaken[tid] = inst->pcState().branching();
462
463        TheISA::PCState pc = inst->pcState();
464        TheISA::advancePC(pc, inst->staticInst);
465
466        toCommit->pc[tid] = pc;
467        toCommit->mispredictInst[tid] = inst;
468        toCommit->includeSquashInst[tid] = false;
469
470        wroteToTimeBuffer = true;
471    }
472
473}
474
475template<class Impl>
476void
477DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
478{
479    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
480            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
481
482    if (toCommit->squash[tid] == false ||
483            inst->seqNum < toCommit->squashedSeqNum[tid]) {
484        toCommit->squash[tid] = true;
485        toCommit->squashedSeqNum[tid] = inst->seqNum;
486        TheISA::PCState pc = inst->pcState();
487        TheISA::advancePC(pc, inst->staticInst);
488        toCommit->pc[tid] = pc;
489        toCommit->branchMispredict[tid] = false;
490
491        toCommit->includeSquashInst[tid] = false;
492
493        wroteToTimeBuffer = true;
494    }
495}
496
497template<class Impl>
498void
499DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
500{
501    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
502            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
503    if (toCommit->squash[tid] == false ||
504            inst->seqNum < toCommit->squashedSeqNum[tid]) {
505        toCommit->squash[tid] = true;
506
507        toCommit->squashedSeqNum[tid] = inst->seqNum;
508        toCommit->pc[tid] = inst->pcState();
509        toCommit->branchMispredict[tid] = false;
510
511        // Must include the broadcasted SN in the squash.
512        toCommit->includeSquashInst[tid] = true;
513
514        ldstQueue.setLoadBlockedHandled(tid);
515
516        wroteToTimeBuffer = true;
517    }
518}
519
520template<class Impl>
521void
522DefaultIEW<Impl>::block(ThreadID tid)
523{
524    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
525
526    if (dispatchStatus[tid] != Blocked &&
527        dispatchStatus[tid] != Unblocking) {
528        toRename->iewBlock[tid] = true;
529        wroteToTimeBuffer = true;
530    }
531
532    // Add the current inputs to the skid buffer so they can be
533    // reprocessed when this stage unblocks.
534    skidInsert(tid);
535
536    dispatchStatus[tid] = Blocked;
537}
538
539template<class Impl>
540void
541DefaultIEW<Impl>::unblock(ThreadID tid)
542{
543    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
544            "buffer %u.\n",tid, tid);
545
546    // If the skid bufffer is empty, signal back to previous stages to unblock.
547    // Also switch status to running.
548    if (skidBuffer[tid].empty()) {
549        toRename->iewUnblock[tid] = true;
550        wroteToTimeBuffer = true;
551        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
552        dispatchStatus[tid] = Running;
553    }
554}
555
556template<class Impl>
557void
558DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
559{
560    instQueue.wakeDependents(inst);
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
566{
567    instQueue.rescheduleMemInst(inst);
568}
569
570template<class Impl>
571void
572DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
573{
574    instQueue.replayMemInst(inst);
575}
576
577template<class Impl>
578void
579DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
580{
581    // This function should not be called after writebackInsts in a
582    // single cycle.  That will cause problems with an instruction
583    // being added to the queue to commit without being processed by
584    // writebackInsts prior to being sent to commit.
585
586    // First check the time slot that this instruction will write
587    // to.  If there are free write ports at the time, then go ahead
588    // and write the instruction to that time.  If there are not,
589    // keep looking back to see where's the first time there's a
590    // free slot.
591    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
592        ++wbNumInst;
593        if (wbNumInst == wbWidth) {
594            ++wbCycle;
595            wbNumInst = 0;
596        }
597
598        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
599    }
600
601    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
602            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
603    // Add finished instruction to queue to commit.
604    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
605    (*iewQueue)[wbCycle].size++;
606}
607
608template <class Impl>
609unsigned
610DefaultIEW<Impl>::validInstsFromRename()
611{
612    unsigned inst_count = 0;
613
614    for (int i=0; i<fromRename->size; i++) {
615        if (!fromRename->insts[i]->isSquashed())
616            inst_count++;
617    }
618
619    return inst_count;
620}
621
622template<class Impl>
623void
624DefaultIEW<Impl>::skidInsert(ThreadID tid)
625{
626    DynInstPtr inst = NULL;
627
628    while (!insts[tid].empty()) {
629        inst = insts[tid].front();
630
631        insts[tid].pop();
632
633        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
634                "dispatch skidBuffer %i\n",tid, inst->seqNum,
635                inst->pcState(),tid);
636
637        skidBuffer[tid].push(inst);
638    }
639
640    assert(skidBuffer[tid].size() <= skidBufferMax &&
641           "Skidbuffer Exceeded Max Size");
642}
643
644template<class Impl>
645int
646DefaultIEW<Impl>::skidCount()
647{
648    int max=0;
649
650    list<ThreadID>::iterator threads = activeThreads->begin();
651    list<ThreadID>::iterator end = activeThreads->end();
652
653    while (threads != end) {
654        ThreadID tid = *threads++;
655        unsigned thread_count = skidBuffer[tid].size();
656        if (max < thread_count)
657            max = thread_count;
658    }
659
660    return max;
661}
662
663template<class Impl>
664bool
665DefaultIEW<Impl>::skidsEmpty()
666{
667    list<ThreadID>::iterator threads = activeThreads->begin();
668    list<ThreadID>::iterator end = activeThreads->end();
669
670    while (threads != end) {
671        ThreadID tid = *threads++;
672
673        if (!skidBuffer[tid].empty())
674            return false;
675    }
676
677    return true;
678}
679
680template <class Impl>
681void
682DefaultIEW<Impl>::updateStatus()
683{
684    bool any_unblocking = false;
685
686    list<ThreadID>::iterator threads = activeThreads->begin();
687    list<ThreadID>::iterator end = activeThreads->end();
688
689    while (threads != end) {
690        ThreadID tid = *threads++;
691
692        if (dispatchStatus[tid] == Unblocking) {
693            any_unblocking = true;
694            break;
695        }
696    }
697
698    // If there are no ready instructions waiting to be scheduled by the IQ,
699    // and there's no stores waiting to write back, and dispatch is not
700    // unblocking, then there is no internal activity for the IEW stage.
701    if (_status == Active && !instQueue.hasReadyInsts() &&
702        !ldstQueue.willWB() && !any_unblocking) {
703        DPRINTF(IEW, "IEW switching to idle\n");
704
705        deactivateStage();
706
707        _status = Inactive;
708    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
709                                       ldstQueue.willWB() ||
710                                       any_unblocking)) {
711        // Otherwise there is internal activity.  Set to active.
712        DPRINTF(IEW, "IEW switching to active\n");
713
714        activateStage();
715
716        _status = Active;
717    }
718}
719
720template <class Impl>
721void
722DefaultIEW<Impl>::resetEntries()
723{
724    instQueue.resetEntries();
725    ldstQueue.resetEntries();
726}
727
728template <class Impl>
729void
730DefaultIEW<Impl>::readStallSignals(ThreadID tid)
731{
732    if (fromCommit->commitBlock[tid]) {
733        stalls[tid].commit = true;
734    }
735
736    if (fromCommit->commitUnblock[tid]) {
737        assert(stalls[tid].commit);
738        stalls[tid].commit = false;
739    }
740}
741
742template <class Impl>
743bool
744DefaultIEW<Impl>::checkStall(ThreadID tid)
745{
746    bool ret_val(false);
747
748    if (stalls[tid].commit) {
749        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
750        ret_val = true;
751    } else if (instQueue.isFull(tid)) {
752        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
753        ret_val = true;
754    } else if (ldstQueue.isFull(tid)) {
755        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
756
757        if (ldstQueue.numLoads(tid) > 0 ) {
758
759            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
760                    tid,ldstQueue.getLoadHeadSeqNum(tid));
761        }
762
763        if (ldstQueue.numStores(tid) > 0) {
764
765            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
766                    tid,ldstQueue.getStoreHeadSeqNum(tid));
767        }
768
769        ret_val = true;
770    } else if (ldstQueue.isStalled(tid)) {
771        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
772        ret_val = true;
773    }
774
775    return ret_val;
776}
777
778template <class Impl>
779void
780DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
781{
782    // Check if there's a squash signal, squash if there is
783    // Check stall signals, block if there is.
784    // If status was Blocked
785    //     if so then go to unblocking
786    // If status was Squashing
787    //     check if squashing is not high.  Switch to running this cycle.
788
789    readStallSignals(tid);
790
791    if (fromCommit->commitInfo[tid].squash) {
792        squash(tid);
793
794        if (dispatchStatus[tid] == Blocked ||
795            dispatchStatus[tid] == Unblocking) {
796            toRename->iewUnblock[tid] = true;
797            wroteToTimeBuffer = true;
798        }
799
800        dispatchStatus[tid] = Squashing;
801        fetchRedirect[tid] = false;
802        return;
803    }
804
805    if (fromCommit->commitInfo[tid].robSquashing) {
806        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
807
808        dispatchStatus[tid] = Squashing;
809        emptyRenameInsts(tid);
810        wroteToTimeBuffer = true;
811        return;
812    }
813
814    if (checkStall(tid)) {
815        block(tid);
816        dispatchStatus[tid] = Blocked;
817        return;
818    }
819
820    if (dispatchStatus[tid] == Blocked) {
821        // Status from previous cycle was blocked, but there are no more stall
822        // conditions.  Switch over to unblocking.
823        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
824                tid);
825
826        dispatchStatus[tid] = Unblocking;
827
828        unblock(tid);
829
830        return;
831    }
832
833    if (dispatchStatus[tid] == Squashing) {
834        // Switch status to running if rename isn't being told to block or
835        // squash this cycle.
836        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
837                tid);
838
839        dispatchStatus[tid] = Running;
840
841        return;
842    }
843}
844
845template <class Impl>
846void
847DefaultIEW<Impl>::sortInsts()
848{
849    int insts_from_rename = fromRename->size;
850#ifdef DEBUG
851    for (ThreadID tid = 0; tid < numThreads; tid++)
852        assert(insts[tid].empty());
853#endif
854    for (int i = 0; i < insts_from_rename; ++i) {
855        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
856    }
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
862{
863    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
864
865    while (!insts[tid].empty()) {
866
867        if (insts[tid].front()->isLoad() ||
868            insts[tid].front()->isStore() ) {
869            toRename->iewInfo[tid].dispatchedToLSQ++;
870        }
871
872        toRename->iewInfo[tid].dispatched++;
873
874        insts[tid].pop();
875    }
876}
877
878template <class Impl>
879void
880DefaultIEW<Impl>::wakeCPU()
881{
882    cpu->wakeCPU();
883}
884
885template <class Impl>
886void
887DefaultIEW<Impl>::activityThisCycle()
888{
889    DPRINTF(Activity, "Activity this cycle.\n");
890    cpu->activityThisCycle();
891}
892
893template <class Impl>
894inline void
895DefaultIEW<Impl>::activateStage()
896{
897    DPRINTF(Activity, "Activating stage.\n");
898    cpu->activateStage(O3CPU::IEWIdx);
899}
900
901template <class Impl>
902inline void
903DefaultIEW<Impl>::deactivateStage()
904{
905    DPRINTF(Activity, "Deactivating stage.\n");
906    cpu->deactivateStage(O3CPU::IEWIdx);
907}
908
909template<class Impl>
910void
911DefaultIEW<Impl>::dispatch(ThreadID tid)
912{
913    // If status is Running or idle,
914    //     call dispatchInsts()
915    // If status is Unblocking,
916    //     buffer any instructions coming from rename
917    //     continue trying to empty skid buffer
918    //     check if stall conditions have passed
919
920    if (dispatchStatus[tid] == Blocked) {
921        ++iewBlockCycles;
922
923    } else if (dispatchStatus[tid] == Squashing) {
924        ++iewSquashCycles;
925    }
926
927    // Dispatch should try to dispatch as many instructions as its bandwidth
928    // will allow, as long as it is not currently blocked.
929    if (dispatchStatus[tid] == Running ||
930        dispatchStatus[tid] == Idle) {
931        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
932                "dispatch.\n", tid);
933
934        dispatchInsts(tid);
935    } else if (dispatchStatus[tid] == Unblocking) {
936        // Make sure that the skid buffer has something in it if the
937        // status is unblocking.
938        assert(!skidsEmpty());
939
940        // If the status was unblocking, then instructions from the skid
941        // buffer were used.  Remove those instructions and handle
942        // the rest of unblocking.
943        dispatchInsts(tid);
944
945        ++iewUnblockCycles;
946
947        if (validInstsFromRename()) {
948            // Add the current inputs to the skid buffer so they can be
949            // reprocessed when this stage unblocks.
950            skidInsert(tid);
951        }
952
953        unblock(tid);
954    }
955}
956
957template <class Impl>
958void
959DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
960{
961    // Obtain instructions from skid buffer if unblocking, or queue from rename
962    // otherwise.
963    std::queue<DynInstPtr> &insts_to_dispatch =
964        dispatchStatus[tid] == Unblocking ?
965        skidBuffer[tid] : insts[tid];
966
967    int insts_to_add = insts_to_dispatch.size();
968
969    DynInstPtr inst;
970    bool add_to_iq = false;
971    int dis_num_inst = 0;
972
973    // Loop through the instructions, putting them in the instruction
974    // queue.
975    for ( ; dis_num_inst < insts_to_add &&
976              dis_num_inst < dispatchWidth;
977          ++dis_num_inst)
978    {
979        inst = insts_to_dispatch.front();
980
981        if (dispatchStatus[tid] == Unblocking) {
982            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
983                    "buffer\n", tid);
984        }
985
986        // Make sure there's a valid instruction there.
987        assert(inst);
988
989        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
990                "IQ.\n",
991                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
992
993        // Be sure to mark these instructions as ready so that the
994        // commit stage can go ahead and execute them, and mark
995        // them as issued so the IQ doesn't reprocess them.
996
997        // Check for squashed instructions.
998        if (inst->isSquashed()) {
999            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1000                    "not adding to IQ.\n", tid);
1001
1002            ++iewDispSquashedInsts;
1003
1004            insts_to_dispatch.pop();
1005
1006            //Tell Rename That An Instruction has been processed
1007            if (inst->isLoad() || inst->isStore()) {
1008                toRename->iewInfo[tid].dispatchedToLSQ++;
1009            }
1010            toRename->iewInfo[tid].dispatched++;
1011
1012            continue;
1013        }
1014
1015        // Check for full conditions.
1016        if (instQueue.isFull(tid)) {
1017            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1018
1019            // Call function to start blocking.
1020            block(tid);
1021
1022            // Set unblock to false. Special case where we are using
1023            // skidbuffer (unblocking) instructions but then we still
1024            // get full in the IQ.
1025            toRename->iewUnblock[tid] = false;
1026
1027            ++iewIQFullEvents;
1028            break;
1029        } else if (ldstQueue.isFull(tid)) {
1030            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1031
1032            // Call function to start blocking.
1033            block(tid);
1034
1035            // Set unblock to false. Special case where we are using
1036            // skidbuffer (unblocking) instructions but then we still
1037            // get full in the IQ.
1038            toRename->iewUnblock[tid] = false;
1039
1040            ++iewLSQFullEvents;
1041            break;
1042        }
1043
1044        // Otherwise issue the instruction just fine.
1045        if (inst->isLoad()) {
1046            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1047                    "encountered, adding to LSQ.\n", tid);
1048
1049            // Reserve a spot in the load store queue for this
1050            // memory access.
1051            ldstQueue.insertLoad(inst);
1052
1053            ++iewDispLoadInsts;
1054
1055            add_to_iq = true;
1056
1057            toRename->iewInfo[tid].dispatchedToLSQ++;
1058        } else if (inst->isStore()) {
1059            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1060                    "encountered, adding to LSQ.\n", tid);
1061
1062            ldstQueue.insertStore(inst);
1063
1064            ++iewDispStoreInsts;
1065
1066            if (inst->isStoreConditional()) {
1067                // Store conditionals need to be set as "canCommit()"
1068                // so that commit can process them when they reach the
1069                // head of commit.
1070                // @todo: This is somewhat specific to Alpha.
1071                inst->setCanCommit();
1072                instQueue.insertNonSpec(inst);
1073                add_to_iq = false;
1074
1075                ++iewDispNonSpecInsts;
1076            } else {
1077                add_to_iq = true;
1078            }
1079
1080            toRename->iewInfo[tid].dispatchedToLSQ++;
1081        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1082            // Same as non-speculative stores.
1083            inst->setCanCommit();
1084            instQueue.insertBarrier(inst);
1085            add_to_iq = false;
1086        } else if (inst->isNop()) {
1087            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1088                    "skipping.\n", tid);
1089
1090            inst->setIssued();
1091            inst->setExecuted();
1092            inst->setCanCommit();
1093
1094            instQueue.recordProducer(inst);
1095
1096            iewExecutedNop[tid]++;
1097
1098            add_to_iq = false;
1099        } else if (inst->isExecuted()) {
1100            assert(0 && "Instruction shouldn't be executed.\n");
1101            DPRINTF(IEW, "Issue: Executed branch encountered, "
1102                    "skipping.\n");
1103
1104            inst->setIssued();
1105            inst->setCanCommit();
1106
1107            instQueue.recordProducer(inst);
1108
1109            add_to_iq = false;
1110        } else {
1111            add_to_iq = true;
1112        }
1113        if (inst->isNonSpeculative()) {
1114            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1115                    "encountered, skipping.\n", tid);
1116
1117            // Same as non-speculative stores.
1118            inst->setCanCommit();
1119
1120            // Specifically insert it as nonspeculative.
1121            instQueue.insertNonSpec(inst);
1122
1123            ++iewDispNonSpecInsts;
1124
1125            add_to_iq = false;
1126        }
1127
1128        // If the instruction queue is not full, then add the
1129        // instruction.
1130        if (add_to_iq) {
1131            instQueue.insert(inst);
1132        }
1133
1134        insts_to_dispatch.pop();
1135
1136        toRename->iewInfo[tid].dispatched++;
1137
1138        ++iewDispatchedInsts;
1139    }
1140
1141    if (!insts_to_dispatch.empty()) {
1142        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1143        block(tid);
1144        toRename->iewUnblock[tid] = false;
1145    }
1146
1147    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1148        dispatchStatus[tid] = Running;
1149
1150        updatedQueues = true;
1151    }
1152
1153    dis_num_inst = 0;
1154}
1155
1156template <class Impl>
1157void
1158DefaultIEW<Impl>::printAvailableInsts()
1159{
1160    int inst = 0;
1161
1162    std::cout << "Available Instructions: ";
1163
1164    while (fromIssue->insts[inst]) {
1165
1166        if (inst%3==0) std::cout << "\n\t";
1167
1168        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1169             << " TN: " << fromIssue->insts[inst]->threadNumber
1170             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1171
1172        inst++;
1173
1174    }
1175
1176    std::cout << "\n";
1177}
1178
1179template <class Impl>
1180void
1181DefaultIEW<Impl>::executeInsts()
1182{
1183    wbNumInst = 0;
1184    wbCycle = 0;
1185
1186    list<ThreadID>::iterator threads = activeThreads->begin();
1187    list<ThreadID>::iterator end = activeThreads->end();
1188
1189    while (threads != end) {
1190        ThreadID tid = *threads++;
1191        fetchRedirect[tid] = false;
1192    }
1193
1194    // Uncomment this if you want to see all available instructions.
1195    // @todo This doesn't actually work anymore, we should fix it.
1196//    printAvailableInsts();
1197
1198    // Execute/writeback any instructions that are available.
1199    int insts_to_execute = fromIssue->size;
1200    int inst_num = 0;
1201    for (; inst_num < insts_to_execute;
1202          ++inst_num) {
1203
1204        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1205
1206        DynInstPtr inst = instQueue.getInstToExecute();
1207
1208        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1209                inst->pcState(), inst->threadNumber,inst->seqNum);
1210
1211        // Check if the instruction is squashed; if so then skip it
1212        if (inst->isSquashed()) {
1213            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1214
1215            // Consider this instruction executed so that commit can go
1216            // ahead and retire the instruction.
1217            inst->setExecuted();
1218
1219            // Not sure if I should set this here or just let commit try to
1220            // commit any squashed instructions.  I like the latter a bit more.
1221            inst->setCanCommit();
1222
1223            ++iewExecSquashedInsts;
1224
1225            decrWb(inst->seqNum);
1226            continue;
1227        }
1228
1229        Fault fault = NoFault;
1230
1231        // Execute instruction.
1232        // Note that if the instruction faults, it will be handled
1233        // at the commit stage.
1234        if (inst->isMemRef()) {
1235            DPRINTF(IEW, "Execute: Calculating address for memory "
1236                    "reference.\n");
1237
1238            // Tell the LDSTQ to execute this instruction (if it is a load).
1239            if (inst->isLoad()) {
1240                // Loads will mark themselves as executed, and their writeback
1241                // event adds the instruction to the queue to commit
1242                fault = ldstQueue.executeLoad(inst);
1243                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1244                    fault = NoFault;
1245                }
1246            } else if (inst->isStore()) {
1247                fault = ldstQueue.executeStore(inst);
1248
1249                // If the store had a fault then it may not have a mem req
1250                if (fault != NoFault || inst->readPredicate() == false ||
1251                        !inst->isStoreConditional()) {
1252                    // If the instruction faulted, then we need to send it along
1253                    // to commit without the instruction completing.
1254                    // Send this instruction to commit, also make sure iew stage
1255                    // realizes there is activity.
1256                    inst->setExecuted();
1257                    instToCommit(inst);
1258                    activityThisCycle();
1259                }
1260
1261                // Store conditionals will mark themselves as
1262                // executed, and their writeback event will add the
1263                // instruction to the queue to commit.
1264            } else {
1265                panic("Unexpected memory type!\n");
1266            }
1267
1268        } else {
1269            // If the instruction has already faulted, then skip executing it.
1270            // Such case can happen when it faulted during ITLB translation.
1271            // If we execute the instruction (even if it's a nop) the fault
1272            // will be replaced and we will lose it.
1273            if (inst->getFault() == NoFault) {
1274                inst->execute();
1275                if (inst->readPredicate() == false)
1276                    inst->forwardOldRegs();
1277            }
1278
1279            inst->setExecuted();
1280
1281            instToCommit(inst);
1282        }
1283
1284        updateExeInstStats(inst);
1285
1286        // Check if branch prediction was correct, if not then we need
1287        // to tell commit to squash in flight instructions.  Only
1288        // handle this if there hasn't already been something that
1289        // redirects fetch in this group of instructions.
1290
1291        // This probably needs to prioritize the redirects if a different
1292        // scheduler is used.  Currently the scheduler schedules the oldest
1293        // instruction first, so the branch resolution order will be correct.
1294        ThreadID tid = inst->threadNumber;
1295
1296        if (!fetchRedirect[tid] ||
1297            !toCommit->squash[tid] ||
1298            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1299
1300            if (inst->mispredicted()) {
1301                fetchRedirect[tid] = true;
1302
1303                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1304                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1305                        inst->predInstAddr(), inst->predNextInstAddr());
1306                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1307                        inst->pcState(), inst->nextInstAddr());
1308                // If incorrect, then signal the ROB that it must be squashed.
1309                squashDueToBranch(inst, tid);
1310
1311                if (inst->readPredTaken()) {
1312                    predictedTakenIncorrect++;
1313                } else {
1314                    predictedNotTakenIncorrect++;
1315                }
1316            } else if (ldstQueue.violation(tid)) {
1317                assert(inst->isMemRef());
1318                // If there was an ordering violation, then get the
1319                // DynInst that caused the violation.  Note that this
1320                // clears the violation signal.
1321                DynInstPtr violator;
1322                violator = ldstQueue.getMemDepViolator(tid);
1323
1324                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1325                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1326                        violator->pcState(), violator->seqNum,
1327                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1328
1329                fetchRedirect[tid] = true;
1330
1331                // Tell the instruction queue that a violation has occured.
1332                instQueue.violation(inst, violator);
1333
1334                // Squash.
1335                squashDueToMemOrder(inst,tid);
1336
1337                ++memOrderViolationEvents;
1338            } else if (ldstQueue.loadBlocked(tid) &&
1339                       !ldstQueue.isLoadBlockedHandled(tid)) {
1340                fetchRedirect[tid] = true;
1341
1342                DPRINTF(IEW, "Load operation couldn't execute because the "
1343                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1344                        inst->pcState(), inst->seqNum);
1345
1346                squashDueToMemBlocked(inst, tid);
1347            }
1348        } else {
1349            // Reset any state associated with redirects that will not
1350            // be used.
1351            if (ldstQueue.violation(tid)) {
1352                assert(inst->isMemRef());
1353
1354                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1355
1356                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1357                        "%s, inst PC: %s.  Addr is: %#x.\n",
1358                        violator->pcState(), inst->pcState(),
1359                        inst->physEffAddr);
1360                DPRINTF(IEW, "Violation will not be handled because "
1361                        "already squashing\n");
1362
1363                ++memOrderViolationEvents;
1364            }
1365            if (ldstQueue.loadBlocked(tid) &&
1366                !ldstQueue.isLoadBlockedHandled(tid)) {
1367                DPRINTF(IEW, "Load operation couldn't execute because the "
1368                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1369                        inst->pcState(), inst->seqNum);
1370                DPRINTF(IEW, "Blocked load will not be handled because "
1371                        "already squashing\n");
1372
1373                ldstQueue.setLoadBlockedHandled(tid);
1374            }
1375
1376        }
1377    }
1378
1379    // Update and record activity if we processed any instructions.
1380    if (inst_num) {
1381        if (exeStatus == Idle) {
1382            exeStatus = Running;
1383        }
1384
1385        updatedQueues = true;
1386
1387        cpu->activityThisCycle();
1388    }
1389
1390    // Need to reset this in case a writeback event needs to write into the
1391    // iew queue.  That way the writeback event will write into the correct
1392    // spot in the queue.
1393    wbNumInst = 0;
1394
1395}
1396
1397template <class Impl>
1398void
1399DefaultIEW<Impl>::writebackInsts()
1400{
1401    // Loop through the head of the time buffer and wake any
1402    // dependents.  These instructions are about to write back.  Also
1403    // mark scoreboard that this instruction is finally complete.
1404    // Either have IEW have direct access to scoreboard, or have this
1405    // as part of backwards communication.
1406    for (int inst_num = 0; inst_num < wbWidth &&
1407             toCommit->insts[inst_num]; inst_num++) {
1408        DynInstPtr inst = toCommit->insts[inst_num];
1409        ThreadID tid = inst->threadNumber;
1410
1411        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1412                inst->seqNum, inst->pcState());
1413
1414        iewInstsToCommit[tid]++;
1415
1416        // Some instructions will be sent to commit without having
1417        // executed because they need commit to handle them.
1418        // E.g. Uncached loads have not actually executed when they
1419        // are first sent to commit.  Instead commit must tell the LSQ
1420        // when it's ready to execute the uncached load.
1421        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1422            int dependents = instQueue.wakeDependents(inst);
1423
1424            for (int i = 0; i < inst->numDestRegs(); i++) {
1425                //mark as Ready
1426                DPRINTF(IEW,"Setting Destination Register %i\n",
1427                        inst->renamedDestRegIdx(i));
1428                scoreboard->setReg(inst->renamedDestRegIdx(i));
1429            }
1430
1431            if (dependents) {
1432                producerInst[tid]++;
1433                consumerInst[tid]+= dependents;
1434            }
1435            writebackCount[tid]++;
1436        }
1437
1438        decrWb(inst->seqNum);
1439    }
1440}
1441
1442template<class Impl>
1443void
1444DefaultIEW<Impl>::tick()
1445{
1446    wbNumInst = 0;
1447    wbCycle = 0;
1448
1449    wroteToTimeBuffer = false;
1450    updatedQueues = false;
1451
1452    sortInsts();
1453
1454    // Free function units marked as being freed this cycle.
1455    fuPool->processFreeUnits();
1456
1457    list<ThreadID>::iterator threads = activeThreads->begin();
1458    list<ThreadID>::iterator end = activeThreads->end();
1459
1460    // Check stall and squash signals, dispatch any instructions.
1461    while (threads != end) {
1462        ThreadID tid = *threads++;
1463
1464        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1465
1466        checkSignalsAndUpdate(tid);
1467        dispatch(tid);
1468    }
1469
1470    if (exeStatus != Squashing) {
1471        executeInsts();
1472
1473        writebackInsts();
1474
1475        // Have the instruction queue try to schedule any ready instructions.
1476        // (In actuality, this scheduling is for instructions that will
1477        // be executed next cycle.)
1478        instQueue.scheduleReadyInsts();
1479
1480        // Also should advance its own time buffers if the stage ran.
1481        // Not the best place for it, but this works (hopefully).
1482        issueToExecQueue.advance();
1483    }
1484
1485    bool broadcast_free_entries = false;
1486
1487    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1488        exeStatus = Idle;
1489        updateLSQNextCycle = false;
1490
1491        broadcast_free_entries = true;
1492    }
1493
1494    // Writeback any stores using any leftover bandwidth.
1495    ldstQueue.writebackStores();
1496
1497    // Check the committed load/store signals to see if there's a load
1498    // or store to commit.  Also check if it's being told to execute a
1499    // nonspeculative instruction.
1500    // This is pretty inefficient...
1501
1502    threads = activeThreads->begin();
1503    while (threads != end) {
1504        ThreadID tid = (*threads++);
1505
1506        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1507
1508        // Update structures based on instructions committed.
1509        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1510            !fromCommit->commitInfo[tid].squash &&
1511            !fromCommit->commitInfo[tid].robSquashing) {
1512
1513            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1514
1515            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1516
1517            updateLSQNextCycle = true;
1518            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1519        }
1520
1521        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1522
1523            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1524            if (fromCommit->commitInfo[tid].uncached) {
1525                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1526                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1527            } else {
1528                instQueue.scheduleNonSpec(
1529                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1530            }
1531        }
1532
1533        if (broadcast_free_entries) {
1534            toFetch->iewInfo[tid].iqCount =
1535                instQueue.getCount(tid);
1536            toFetch->iewInfo[tid].ldstqCount =
1537                ldstQueue.getCount(tid);
1538
1539            toRename->iewInfo[tid].usedIQ = true;
1540            toRename->iewInfo[tid].freeIQEntries =
1541                instQueue.numFreeEntries();
1542            toRename->iewInfo[tid].usedLSQ = true;
1543            toRename->iewInfo[tid].freeLSQEntries =
1544                ldstQueue.numFreeEntries(tid);
1545
1546            wroteToTimeBuffer = true;
1547        }
1548
1549        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1550                tid, toRename->iewInfo[tid].dispatched);
1551    }
1552
1553    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1554            "LSQ has %i free entries.\n",
1555            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1556            ldstQueue.numFreeEntries());
1557
1558    updateStatus();
1559
1560    if (wroteToTimeBuffer) {
1561        DPRINTF(Activity, "Activity this cycle.\n");
1562        cpu->activityThisCycle();
1563    }
1564}
1565
1566template <class Impl>
1567void
1568DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1569{
1570    ThreadID tid = inst->threadNumber;
1571
1572    //
1573    //  Pick off the software prefetches
1574    //
1575#ifdef TARGET_ALPHA
1576    if (inst->isDataPrefetch())
1577        iewExecutedSwp[tid]++;
1578    else
1579        iewIewExecutedcutedInsts++;
1580#else
1581    iewExecutedInsts++;
1582#endif
1583
1584    //
1585    //  Control operations
1586    //
1587    if (inst->isControl())
1588        iewExecutedBranches[tid]++;
1589
1590    //
1591    //  Memory operations
1592    //
1593    if (inst->isMemRef()) {
1594        iewExecutedRefs[tid]++;
1595
1596        if (inst->isLoad()) {
1597            iewExecLoadInsts[tid]++;
1598        }
1599    }
1600}
1601
1602template <class Impl>
1603void
1604DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1605{
1606    ThreadID tid = inst->threadNumber;
1607
1608    if (!fetchRedirect[tid] ||
1609        !toCommit->squash[tid] ||
1610        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1611
1612        if (inst->mispredicted()) {
1613            fetchRedirect[tid] = true;
1614
1615            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1616            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1617                    inst->predInstAddr(), inst->predNextInstAddr());
1618            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1619                    " NPC: %#x.\n", inst->nextInstAddr(),
1620                    inst->nextInstAddr());
1621            // If incorrect, then signal the ROB that it must be squashed.
1622            squashDueToBranch(inst, tid);
1623
1624            if (inst->readPredTaken()) {
1625                predictedTakenIncorrect++;
1626            } else {
1627                predictedNotTakenIncorrect++;
1628            }
1629        }
1630    }
1631}
1632