iew_impl.hh revision 7598:c0ae58952ed0
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43// @todo: Fix the instantaneous communication among all the stages within 44// iew. There's a clear delay between issue and execute, yet backwards 45// communication happens simultaneously. 46 47#include <queue> 48 49#include "base/timebuf.hh" 50#include "config/the_isa.hh" 51#include "cpu/o3/fu_pool.hh" 52#include "cpu/o3/iew.hh" 53#include "params/DerivO3CPU.hh" 54 55using namespace std; 56 57template<class Impl> 58DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 59 : issueToExecQueue(params->backComSize, params->forwardComSize), 60 cpu(_cpu), 61 instQueue(_cpu, this, params), 62 ldstQueue(_cpu, this, params), 63 fuPool(params->fuPool), 64 commitToIEWDelay(params->commitToIEWDelay), 65 renameToIEWDelay(params->renameToIEWDelay), 66 issueToExecuteDelay(params->issueToExecuteDelay), 67 dispatchWidth(params->dispatchWidth), 68 issueWidth(params->issueWidth), 69 wbOutstanding(0), 70 wbWidth(params->wbWidth), 71 numThreads(params->numThreads), 72 switchedOut(false) 73{ 74 _status = Active; 75 exeStatus = Running; 76 wbStatus = Idle; 77 78 // Setup wire to read instructions coming from issue. 79 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 80 81 // Instruction queue needs the queue between issue and execute. 82 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 83 84 for (ThreadID tid = 0; tid < numThreads; tid++) { 85 dispatchStatus[tid] = Running; 86 stalls[tid].commit = false; 87 fetchRedirect[tid] = false; 88 } 89 90 wbMax = wbWidth * params->wbDepth; 91 92 updateLSQNextCycle = false; 93 94 ableToIssue = true; 95 96 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 97} 98 99template <class Impl> 100std::string 101DefaultIEW<Impl>::name() const 102{ 103 return cpu->name() + ".iew"; 104} 105 106template <class Impl> 107void 108DefaultIEW<Impl>::regStats() 109{ 110 using namespace Stats; 111 112 instQueue.regStats(); 113 ldstQueue.regStats(); 114 115 iewIdleCycles 116 .name(name() + ".iewIdleCycles") 117 .desc("Number of cycles IEW is idle"); 118 119 iewSquashCycles 120 .name(name() + ".iewSquashCycles") 121 .desc("Number of cycles IEW is squashing"); 122 123 iewBlockCycles 124 .name(name() + ".iewBlockCycles") 125 .desc("Number of cycles IEW is blocking"); 126 127 iewUnblockCycles 128 .name(name() + ".iewUnblockCycles") 129 .desc("Number of cycles IEW is unblocking"); 130 131 iewDispatchedInsts 132 .name(name() + ".iewDispatchedInsts") 133 .desc("Number of instructions dispatched to IQ"); 134 135 iewDispSquashedInsts 136 .name(name() + ".iewDispSquashedInsts") 137 .desc("Number of squashed instructions skipped by dispatch"); 138 139 iewDispLoadInsts 140 .name(name() + ".iewDispLoadInsts") 141 .desc("Number of dispatched load instructions"); 142 143 iewDispStoreInsts 144 .name(name() + ".iewDispStoreInsts") 145 .desc("Number of dispatched store instructions"); 146 147 iewDispNonSpecInsts 148 .name(name() + ".iewDispNonSpecInsts") 149 .desc("Number of dispatched non-speculative instructions"); 150 151 iewIQFullEvents 152 .name(name() + ".iewIQFullEvents") 153 .desc("Number of times the IQ has become full, causing a stall"); 154 155 iewLSQFullEvents 156 .name(name() + ".iewLSQFullEvents") 157 .desc("Number of times the LSQ has become full, causing a stall"); 158 159 memOrderViolationEvents 160 .name(name() + ".memOrderViolationEvents") 161 .desc("Number of memory order violations"); 162 163 predictedTakenIncorrect 164 .name(name() + ".predictedTakenIncorrect") 165 .desc("Number of branches that were predicted taken incorrectly"); 166 167 predictedNotTakenIncorrect 168 .name(name() + ".predictedNotTakenIncorrect") 169 .desc("Number of branches that were predicted not taken incorrectly"); 170 171 branchMispredicts 172 .name(name() + ".branchMispredicts") 173 .desc("Number of branch mispredicts detected at execute"); 174 175 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 176 177 iewExecutedInsts 178 .name(name() + ".iewExecutedInsts") 179 .desc("Number of executed instructions"); 180 181 iewExecLoadInsts 182 .init(cpu->numThreads) 183 .name(name() + ".iewExecLoadInsts") 184 .desc("Number of load instructions executed") 185 .flags(total); 186 187 iewExecSquashedInsts 188 .name(name() + ".iewExecSquashedInsts") 189 .desc("Number of squashed instructions skipped in execute"); 190 191 iewExecutedSwp 192 .init(cpu->numThreads) 193 .name(name() + ".EXEC:swp") 194 .desc("number of swp insts executed") 195 .flags(total); 196 197 iewExecutedNop 198 .init(cpu->numThreads) 199 .name(name() + ".EXEC:nop") 200 .desc("number of nop insts executed") 201 .flags(total); 202 203 iewExecutedRefs 204 .init(cpu->numThreads) 205 .name(name() + ".EXEC:refs") 206 .desc("number of memory reference insts executed") 207 .flags(total); 208 209 iewExecutedBranches 210 .init(cpu->numThreads) 211 .name(name() + ".EXEC:branches") 212 .desc("Number of branches executed") 213 .flags(total); 214 215 iewExecStoreInsts 216 .name(name() + ".EXEC:stores") 217 .desc("Number of stores executed") 218 .flags(total); 219 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 220 221 iewExecRate 222 .name(name() + ".EXEC:rate") 223 .desc("Inst execution rate") 224 .flags(total); 225 226 iewExecRate = iewExecutedInsts / cpu->numCycles; 227 228 iewInstsToCommit 229 .init(cpu->numThreads) 230 .name(name() + ".WB:sent") 231 .desc("cumulative count of insts sent to commit") 232 .flags(total); 233 234 writebackCount 235 .init(cpu->numThreads) 236 .name(name() + ".WB:count") 237 .desc("cumulative count of insts written-back") 238 .flags(total); 239 240 producerInst 241 .init(cpu->numThreads) 242 .name(name() + ".WB:producers") 243 .desc("num instructions producing a value") 244 .flags(total); 245 246 consumerInst 247 .init(cpu->numThreads) 248 .name(name() + ".WB:consumers") 249 .desc("num instructions consuming a value") 250 .flags(total); 251 252 wbPenalized 253 .init(cpu->numThreads) 254 .name(name() + ".WB:penalized") 255 .desc("number of instrctions required to write to 'other' IQ") 256 .flags(total); 257 258 wbPenalizedRate 259 .name(name() + ".WB:penalized_rate") 260 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 261 .flags(total); 262 263 wbPenalizedRate = wbPenalized / writebackCount; 264 265 wbFanout 266 .name(name() + ".WB:fanout") 267 .desc("average fanout of values written-back") 268 .flags(total); 269 270 wbFanout = producerInst / consumerInst; 271 272 wbRate 273 .name(name() + ".WB:rate") 274 .desc("insts written-back per cycle") 275 .flags(total); 276 wbRate = writebackCount / cpu->numCycles; 277} 278 279template<class Impl> 280void 281DefaultIEW<Impl>::initStage() 282{ 283 for (ThreadID tid = 0; tid < numThreads; tid++) { 284 toRename->iewInfo[tid].usedIQ = true; 285 toRename->iewInfo[tid].freeIQEntries = 286 instQueue.numFreeEntries(tid); 287 288 toRename->iewInfo[tid].usedLSQ = true; 289 toRename->iewInfo[tid].freeLSQEntries = 290 ldstQueue.numFreeEntries(tid); 291 } 292 293 cpu->activateStage(O3CPU::IEWIdx); 294} 295 296template<class Impl> 297void 298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 299{ 300 timeBuffer = tb_ptr; 301 302 // Setup wire to read information from time buffer, from commit. 303 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 304 305 // Setup wire to write information back to previous stages. 306 toRename = timeBuffer->getWire(0); 307 308 toFetch = timeBuffer->getWire(0); 309 310 // Instruction queue also needs main time buffer. 311 instQueue.setTimeBuffer(tb_ptr); 312} 313 314template<class Impl> 315void 316DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 317{ 318 renameQueue = rq_ptr; 319 320 // Setup wire to read information from rename queue. 321 fromRename = renameQueue->getWire(-renameToIEWDelay); 322} 323 324template<class Impl> 325void 326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 327{ 328 iewQueue = iq_ptr; 329 330 // Setup wire to write instructions to commit. 331 toCommit = iewQueue->getWire(0); 332} 333 334template<class Impl> 335void 336DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 337{ 338 activeThreads = at_ptr; 339 340 ldstQueue.setActiveThreads(at_ptr); 341 instQueue.setActiveThreads(at_ptr); 342} 343 344template<class Impl> 345void 346DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 347{ 348 scoreboard = sb_ptr; 349} 350 351template <class Impl> 352bool 353DefaultIEW<Impl>::drain() 354{ 355 // IEW is ready to drain at any time. 356 cpu->signalDrained(); 357 return true; 358} 359 360template <class Impl> 361void 362DefaultIEW<Impl>::resume() 363{ 364} 365 366template <class Impl> 367void 368DefaultIEW<Impl>::switchOut() 369{ 370 // Clear any state. 371 switchedOut = true; 372 assert(insts[0].empty()); 373 assert(skidBuffer[0].empty()); 374 375 instQueue.switchOut(); 376 ldstQueue.switchOut(); 377 fuPool->switchOut(); 378 379 for (ThreadID tid = 0; tid < numThreads; tid++) { 380 while (!insts[tid].empty()) 381 insts[tid].pop(); 382 while (!skidBuffer[tid].empty()) 383 skidBuffer[tid].pop(); 384 } 385} 386 387template <class Impl> 388void 389DefaultIEW<Impl>::takeOverFrom() 390{ 391 // Reset all state. 392 _status = Active; 393 exeStatus = Running; 394 wbStatus = Idle; 395 switchedOut = false; 396 397 instQueue.takeOverFrom(); 398 ldstQueue.takeOverFrom(); 399 fuPool->takeOverFrom(); 400 401 initStage(); 402 cpu->activityThisCycle(); 403 404 for (ThreadID tid = 0; tid < numThreads; tid++) { 405 dispatchStatus[tid] = Running; 406 stalls[tid].commit = false; 407 fetchRedirect[tid] = false; 408 } 409 410 updateLSQNextCycle = false; 411 412 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 413 issueToExecQueue.advance(); 414 } 415} 416 417template<class Impl> 418void 419DefaultIEW<Impl>::squash(ThreadID tid) 420{ 421 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 422 423 // Tell the IQ to start squashing. 424 instQueue.squash(tid); 425 426 // Tell the LDSTQ to start squashing. 427 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 428 updatedQueues = true; 429 430 // Clear the skid buffer in case it has any data in it. 431 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 432 tid, fromCommit->commitInfo[tid].doneSeqNum); 433 434 while (!skidBuffer[tid].empty()) { 435 if (skidBuffer[tid].front()->isLoad() || 436 skidBuffer[tid].front()->isStore() ) { 437 toRename->iewInfo[tid].dispatchedToLSQ++; 438 } 439 440 toRename->iewInfo[tid].dispatched++; 441 442 skidBuffer[tid].pop(); 443 } 444 445 emptyRenameInsts(tid); 446} 447 448template<class Impl> 449void 450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 451{ 452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 453 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 454 455 toCommit->squash[tid] = true; 456 toCommit->squashedSeqNum[tid] = inst->seqNum; 457 toCommit->mispredPC[tid] = inst->readPC(); 458 toCommit->branchMispredict[tid] = true; 459 460#if ISA_HAS_DELAY_SLOT 461 int instSize = sizeof(TheISA::MachInst); 462 toCommit->branchTaken[tid] = 463 !(inst->readNextPC() + instSize == inst->readNextNPC() && 464 (inst->readNextPC() == inst->readPC() + instSize || 465 inst->readNextPC() == inst->readPC() + 2 * instSize)); 466#else 467 toCommit->branchTaken[tid] = inst->readNextPC() != 468 (inst->readPC() + sizeof(TheISA::MachInst)); 469#endif 470 toCommit->nextPC[tid] = inst->readNextPC(); 471 toCommit->nextNPC[tid] = inst->readNextNPC(); 472 toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 473 474 toCommit->includeSquashInst[tid] = false; 475 476 wroteToTimeBuffer = true; 477} 478 479template<class Impl> 480void 481DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 482{ 483 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 484 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 485 486 toCommit->squash[tid] = true; 487 toCommit->squashedSeqNum[tid] = inst->seqNum; 488 toCommit->nextPC[tid] = inst->readNextPC(); 489 toCommit->nextNPC[tid] = inst->readNextNPC(); 490 toCommit->branchMispredict[tid] = false; 491 492 toCommit->includeSquashInst[tid] = false; 493 494 wroteToTimeBuffer = true; 495} 496 497template<class Impl> 498void 499DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 500{ 501 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 502 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 503 504 toCommit->squash[tid] = true; 505 toCommit->squashedSeqNum[tid] = inst->seqNum; 506 toCommit->nextPC[tid] = inst->readPC(); 507 toCommit->nextNPC[tid] = inst->readNextPC(); 508 toCommit->branchMispredict[tid] = false; 509 510 // Must include the broadcasted SN in the squash. 511 toCommit->includeSquashInst[tid] = true; 512 513 ldstQueue.setLoadBlockedHandled(tid); 514 515 wroteToTimeBuffer = true; 516} 517 518template<class Impl> 519void 520DefaultIEW<Impl>::block(ThreadID tid) 521{ 522 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 523 524 if (dispatchStatus[tid] != Blocked && 525 dispatchStatus[tid] != Unblocking) { 526 toRename->iewBlock[tid] = true; 527 wroteToTimeBuffer = true; 528 } 529 530 // Add the current inputs to the skid buffer so they can be 531 // reprocessed when this stage unblocks. 532 skidInsert(tid); 533 534 dispatchStatus[tid] = Blocked; 535} 536 537template<class Impl> 538void 539DefaultIEW<Impl>::unblock(ThreadID tid) 540{ 541 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 542 "buffer %u.\n",tid, tid); 543 544 // If the skid bufffer is empty, signal back to previous stages to unblock. 545 // Also switch status to running. 546 if (skidBuffer[tid].empty()) { 547 toRename->iewUnblock[tid] = true; 548 wroteToTimeBuffer = true; 549 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 550 dispatchStatus[tid] = Running; 551 } 552} 553 554template<class Impl> 555void 556DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 557{ 558 instQueue.wakeDependents(inst); 559} 560 561template<class Impl> 562void 563DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 564{ 565 instQueue.rescheduleMemInst(inst); 566} 567 568template<class Impl> 569void 570DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 571{ 572 instQueue.replayMemInst(inst); 573} 574 575template<class Impl> 576void 577DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 578{ 579 // This function should not be called after writebackInsts in a 580 // single cycle. That will cause problems with an instruction 581 // being added to the queue to commit without being processed by 582 // writebackInsts prior to being sent to commit. 583 584 // First check the time slot that this instruction will write 585 // to. If there are free write ports at the time, then go ahead 586 // and write the instruction to that time. If there are not, 587 // keep looking back to see where's the first time there's a 588 // free slot. 589 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 590 ++wbNumInst; 591 if (wbNumInst == wbWidth) { 592 ++wbCycle; 593 wbNumInst = 0; 594 } 595 596 assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 597 } 598 599 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 600 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 601 // Add finished instruction to queue to commit. 602 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 603 (*iewQueue)[wbCycle].size++; 604} 605 606template <class Impl> 607unsigned 608DefaultIEW<Impl>::validInstsFromRename() 609{ 610 unsigned inst_count = 0; 611 612 for (int i=0; i<fromRename->size; i++) { 613 if (!fromRename->insts[i]->isSquashed()) 614 inst_count++; 615 } 616 617 return inst_count; 618} 619 620template<class Impl> 621void 622DefaultIEW<Impl>::skidInsert(ThreadID tid) 623{ 624 DynInstPtr inst = NULL; 625 626 while (!insts[tid].empty()) { 627 inst = insts[tid].front(); 628 629 insts[tid].pop(); 630 631 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 632 "dispatch skidBuffer %i\n",tid, inst->seqNum, 633 inst->readPC(),tid); 634 635 skidBuffer[tid].push(inst); 636 } 637 638 assert(skidBuffer[tid].size() <= skidBufferMax && 639 "Skidbuffer Exceeded Max Size"); 640} 641 642template<class Impl> 643int 644DefaultIEW<Impl>::skidCount() 645{ 646 int max=0; 647 648 list<ThreadID>::iterator threads = activeThreads->begin(); 649 list<ThreadID>::iterator end = activeThreads->end(); 650 651 while (threads != end) { 652 ThreadID tid = *threads++; 653 unsigned thread_count = skidBuffer[tid].size(); 654 if (max < thread_count) 655 max = thread_count; 656 } 657 658 return max; 659} 660 661template<class Impl> 662bool 663DefaultIEW<Impl>::skidsEmpty() 664{ 665 list<ThreadID>::iterator threads = activeThreads->begin(); 666 list<ThreadID>::iterator end = activeThreads->end(); 667 668 while (threads != end) { 669 ThreadID tid = *threads++; 670 671 if (!skidBuffer[tid].empty()) 672 return false; 673 } 674 675 return true; 676} 677 678template <class Impl> 679void 680DefaultIEW<Impl>::updateStatus() 681{ 682 bool any_unblocking = false; 683 684 list<ThreadID>::iterator threads = activeThreads->begin(); 685 list<ThreadID>::iterator end = activeThreads->end(); 686 687 while (threads != end) { 688 ThreadID tid = *threads++; 689 690 if (dispatchStatus[tid] == Unblocking) { 691 any_unblocking = true; 692 break; 693 } 694 } 695 696 // If there are no ready instructions waiting to be scheduled by the IQ, 697 // and there's no stores waiting to write back, and dispatch is not 698 // unblocking, then there is no internal activity for the IEW stage. 699 if (_status == Active && !instQueue.hasReadyInsts() && 700 !ldstQueue.willWB() && !any_unblocking) { 701 DPRINTF(IEW, "IEW switching to idle\n"); 702 703 deactivateStage(); 704 705 _status = Inactive; 706 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 707 ldstQueue.willWB() || 708 any_unblocking)) { 709 // Otherwise there is internal activity. Set to active. 710 DPRINTF(IEW, "IEW switching to active\n"); 711 712 activateStage(); 713 714 _status = Active; 715 } 716} 717 718template <class Impl> 719void 720DefaultIEW<Impl>::resetEntries() 721{ 722 instQueue.resetEntries(); 723 ldstQueue.resetEntries(); 724} 725 726template <class Impl> 727void 728DefaultIEW<Impl>::readStallSignals(ThreadID tid) 729{ 730 if (fromCommit->commitBlock[tid]) { 731 stalls[tid].commit = true; 732 } 733 734 if (fromCommit->commitUnblock[tid]) { 735 assert(stalls[tid].commit); 736 stalls[tid].commit = false; 737 } 738} 739 740template <class Impl> 741bool 742DefaultIEW<Impl>::checkStall(ThreadID tid) 743{ 744 bool ret_val(false); 745 746 if (stalls[tid].commit) { 747 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 748 ret_val = true; 749 } else if (instQueue.isFull(tid)) { 750 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 751 ret_val = true; 752 } else if (ldstQueue.isFull(tid)) { 753 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 754 755 if (ldstQueue.numLoads(tid) > 0 ) { 756 757 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 758 tid,ldstQueue.getLoadHeadSeqNum(tid)); 759 } 760 761 if (ldstQueue.numStores(tid) > 0) { 762 763 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 764 tid,ldstQueue.getStoreHeadSeqNum(tid)); 765 } 766 767 ret_val = true; 768 } else if (ldstQueue.isStalled(tid)) { 769 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 770 ret_val = true; 771 } 772 773 return ret_val; 774} 775 776template <class Impl> 777void 778DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 779{ 780 // Check if there's a squash signal, squash if there is 781 // Check stall signals, block if there is. 782 // If status was Blocked 783 // if so then go to unblocking 784 // If status was Squashing 785 // check if squashing is not high. Switch to running this cycle. 786 787 readStallSignals(tid); 788 789 if (fromCommit->commitInfo[tid].squash) { 790 squash(tid); 791 792 if (dispatchStatus[tid] == Blocked || 793 dispatchStatus[tid] == Unblocking) { 794 toRename->iewUnblock[tid] = true; 795 wroteToTimeBuffer = true; 796 } 797 798 dispatchStatus[tid] = Squashing; 799 800 fetchRedirect[tid] = false; 801 return; 802 } 803 804 if (fromCommit->commitInfo[tid].robSquashing) { 805 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 806 807 dispatchStatus[tid] = Squashing; 808 809 emptyRenameInsts(tid); 810 wroteToTimeBuffer = true; 811 return; 812 } 813 814 if (checkStall(tid)) { 815 block(tid); 816 dispatchStatus[tid] = Blocked; 817 return; 818 } 819 820 if (dispatchStatus[tid] == Blocked) { 821 // Status from previous cycle was blocked, but there are no more stall 822 // conditions. Switch over to unblocking. 823 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 824 tid); 825 826 dispatchStatus[tid] = Unblocking; 827 828 unblock(tid); 829 830 return; 831 } 832 833 if (dispatchStatus[tid] == Squashing) { 834 // Switch status to running if rename isn't being told to block or 835 // squash this cycle. 836 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 837 tid); 838 839 dispatchStatus[tid] = Running; 840 841 return; 842 } 843} 844 845template <class Impl> 846void 847DefaultIEW<Impl>::sortInsts() 848{ 849 int insts_from_rename = fromRename->size; 850#ifdef DEBUG 851 for (ThreadID tid = 0; tid < numThreads; tid++) 852 assert(insts[tid].empty()); 853#endif 854 for (int i = 0; i < insts_from_rename; ++i) { 855 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 856 } 857} 858 859template <class Impl> 860void 861DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 862{ 863 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 864 865 while (!insts[tid].empty()) { 866 867 if (insts[tid].front()->isLoad() || 868 insts[tid].front()->isStore() ) { 869 toRename->iewInfo[tid].dispatchedToLSQ++; 870 } 871 872 toRename->iewInfo[tid].dispatched++; 873 874 insts[tid].pop(); 875 } 876} 877 878template <class Impl> 879void 880DefaultIEW<Impl>::wakeCPU() 881{ 882 cpu->wakeCPU(); 883} 884 885template <class Impl> 886void 887DefaultIEW<Impl>::activityThisCycle() 888{ 889 DPRINTF(Activity, "Activity this cycle.\n"); 890 cpu->activityThisCycle(); 891} 892 893template <class Impl> 894inline void 895DefaultIEW<Impl>::activateStage() 896{ 897 DPRINTF(Activity, "Activating stage.\n"); 898 cpu->activateStage(O3CPU::IEWIdx); 899} 900 901template <class Impl> 902inline void 903DefaultIEW<Impl>::deactivateStage() 904{ 905 DPRINTF(Activity, "Deactivating stage.\n"); 906 cpu->deactivateStage(O3CPU::IEWIdx); 907} 908 909template<class Impl> 910void 911DefaultIEW<Impl>::dispatch(ThreadID tid) 912{ 913 // If status is Running or idle, 914 // call dispatchInsts() 915 // If status is Unblocking, 916 // buffer any instructions coming from rename 917 // continue trying to empty skid buffer 918 // check if stall conditions have passed 919 920 if (dispatchStatus[tid] == Blocked) { 921 ++iewBlockCycles; 922 923 } else if (dispatchStatus[tid] == Squashing) { 924 ++iewSquashCycles; 925 } 926 927 // Dispatch should try to dispatch as many instructions as its bandwidth 928 // will allow, as long as it is not currently blocked. 929 if (dispatchStatus[tid] == Running || 930 dispatchStatus[tid] == Idle) { 931 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 932 "dispatch.\n", tid); 933 934 dispatchInsts(tid); 935 } else if (dispatchStatus[tid] == Unblocking) { 936 // Make sure that the skid buffer has something in it if the 937 // status is unblocking. 938 assert(!skidsEmpty()); 939 940 // If the status was unblocking, then instructions from the skid 941 // buffer were used. Remove those instructions and handle 942 // the rest of unblocking. 943 dispatchInsts(tid); 944 945 ++iewUnblockCycles; 946 947 if (validInstsFromRename()) { 948 // Add the current inputs to the skid buffer so they can be 949 // reprocessed when this stage unblocks. 950 skidInsert(tid); 951 } 952 953 unblock(tid); 954 } 955} 956 957template <class Impl> 958void 959DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 960{ 961 // Obtain instructions from skid buffer if unblocking, or queue from rename 962 // otherwise. 963 std::queue<DynInstPtr> &insts_to_dispatch = 964 dispatchStatus[tid] == Unblocking ? 965 skidBuffer[tid] : insts[tid]; 966 967 int insts_to_add = insts_to_dispatch.size(); 968 969 DynInstPtr inst; 970 bool add_to_iq = false; 971 int dis_num_inst = 0; 972 973 // Loop through the instructions, putting them in the instruction 974 // queue. 975 for ( ; dis_num_inst < insts_to_add && 976 dis_num_inst < dispatchWidth; 977 ++dis_num_inst) 978 { 979 inst = insts_to_dispatch.front(); 980 981 if (dispatchStatus[tid] == Unblocking) { 982 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 983 "buffer\n", tid); 984 } 985 986 // Make sure there's a valid instruction there. 987 assert(inst); 988 989 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 990 "IQ.\n", 991 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 992 993 // Be sure to mark these instructions as ready so that the 994 // commit stage can go ahead and execute them, and mark 995 // them as issued so the IQ doesn't reprocess them. 996 997 // Check for squashed instructions. 998 if (inst->isSquashed()) { 999 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1000 "not adding to IQ.\n", tid); 1001 1002 ++iewDispSquashedInsts; 1003 1004 insts_to_dispatch.pop(); 1005 1006 //Tell Rename That An Instruction has been processed 1007 if (inst->isLoad() || inst->isStore()) { 1008 toRename->iewInfo[tid].dispatchedToLSQ++; 1009 } 1010 toRename->iewInfo[tid].dispatched++; 1011 1012 continue; 1013 } 1014 1015 // Check for full conditions. 1016 if (instQueue.isFull(tid)) { 1017 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1018 1019 // Call function to start blocking. 1020 block(tid); 1021 1022 // Set unblock to false. Special case where we are using 1023 // skidbuffer (unblocking) instructions but then we still 1024 // get full in the IQ. 1025 toRename->iewUnblock[tid] = false; 1026 1027 ++iewIQFullEvents; 1028 break; 1029 } else if (ldstQueue.isFull(tid)) { 1030 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1031 1032 // Call function to start blocking. 1033 block(tid); 1034 1035 // Set unblock to false. Special case where we are using 1036 // skidbuffer (unblocking) instructions but then we still 1037 // get full in the IQ. 1038 toRename->iewUnblock[tid] = false; 1039 1040 ++iewLSQFullEvents; 1041 break; 1042 } 1043 1044 // Otherwise issue the instruction just fine. 1045 if (inst->isLoad()) { 1046 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1047 "encountered, adding to LSQ.\n", tid); 1048 1049 // Reserve a spot in the load store queue for this 1050 // memory access. 1051 ldstQueue.insertLoad(inst); 1052 1053 ++iewDispLoadInsts; 1054 1055 add_to_iq = true; 1056 1057 toRename->iewInfo[tid].dispatchedToLSQ++; 1058 } else if (inst->isStore()) { 1059 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1060 "encountered, adding to LSQ.\n", tid); 1061 1062 ldstQueue.insertStore(inst); 1063 1064 ++iewDispStoreInsts; 1065 1066 if (inst->isStoreConditional()) { 1067 // Store conditionals need to be set as "canCommit()" 1068 // so that commit can process them when they reach the 1069 // head of commit. 1070 // @todo: This is somewhat specific to Alpha. 1071 inst->setCanCommit(); 1072 instQueue.insertNonSpec(inst); 1073 add_to_iq = false; 1074 1075 ++iewDispNonSpecInsts; 1076 } else { 1077 add_to_iq = true; 1078 } 1079 1080 toRename->iewInfo[tid].dispatchedToLSQ++; 1081 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1082 // Same as non-speculative stores. 1083 inst->setCanCommit(); 1084 instQueue.insertBarrier(inst); 1085 add_to_iq = false; 1086 } else if (inst->isNop()) { 1087 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1088 "skipping.\n", tid); 1089 1090 inst->setIssued(); 1091 inst->setExecuted(); 1092 inst->setCanCommit(); 1093 1094 instQueue.recordProducer(inst); 1095 1096 iewExecutedNop[tid]++; 1097 1098 add_to_iq = false; 1099 } else if (inst->isExecuted()) { 1100 assert(0 && "Instruction shouldn't be executed.\n"); 1101 DPRINTF(IEW, "Issue: Executed branch encountered, " 1102 "skipping.\n"); 1103 1104 inst->setIssued(); 1105 inst->setCanCommit(); 1106 1107 instQueue.recordProducer(inst); 1108 1109 add_to_iq = false; 1110 } else { 1111 add_to_iq = true; 1112 } 1113 if (inst->isNonSpeculative()) { 1114 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1115 "encountered, skipping.\n", tid); 1116 1117 // Same as non-speculative stores. 1118 inst->setCanCommit(); 1119 1120 // Specifically insert it as nonspeculative. 1121 instQueue.insertNonSpec(inst); 1122 1123 ++iewDispNonSpecInsts; 1124 1125 add_to_iq = false; 1126 } 1127 1128 // If the instruction queue is not full, then add the 1129 // instruction. 1130 if (add_to_iq) { 1131 instQueue.insert(inst); 1132 } 1133 1134 insts_to_dispatch.pop(); 1135 1136 toRename->iewInfo[tid].dispatched++; 1137 1138 ++iewDispatchedInsts; 1139 } 1140 1141 if (!insts_to_dispatch.empty()) { 1142 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1143 block(tid); 1144 toRename->iewUnblock[tid] = false; 1145 } 1146 1147 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1148 dispatchStatus[tid] = Running; 1149 1150 updatedQueues = true; 1151 } 1152 1153 dis_num_inst = 0; 1154} 1155 1156template <class Impl> 1157void 1158DefaultIEW<Impl>::printAvailableInsts() 1159{ 1160 int inst = 0; 1161 1162 std::cout << "Available Instructions: "; 1163 1164 while (fromIssue->insts[inst]) { 1165 1166 if (inst%3==0) std::cout << "\n\t"; 1167 1168 std::cout << "PC: " << fromIssue->insts[inst]->readPC() 1169 << " TN: " << fromIssue->insts[inst]->threadNumber 1170 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1171 1172 inst++; 1173 1174 } 1175 1176 std::cout << "\n"; 1177} 1178 1179template <class Impl> 1180void 1181DefaultIEW<Impl>::executeInsts() 1182{ 1183 wbNumInst = 0; 1184 wbCycle = 0; 1185 1186 list<ThreadID>::iterator threads = activeThreads->begin(); 1187 list<ThreadID>::iterator end = activeThreads->end(); 1188 1189 while (threads != end) { 1190 ThreadID tid = *threads++; 1191 fetchRedirect[tid] = false; 1192 } 1193 1194 // Uncomment this if you want to see all available instructions. 1195// printAvailableInsts(); 1196 1197 // Execute/writeback any instructions that are available. 1198 int insts_to_execute = fromIssue->size; 1199 int inst_num = 0; 1200 for (; inst_num < insts_to_execute; 1201 ++inst_num) { 1202 1203 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1204 1205 DynInstPtr inst = instQueue.getInstToExecute(); 1206 1207 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1208 inst->readPC(), inst->threadNumber,inst->seqNum); 1209 1210 // Check if the instruction is squashed; if so then skip it 1211 if (inst->isSquashed()) { 1212 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1213 1214 // Consider this instruction executed so that commit can go 1215 // ahead and retire the instruction. 1216 inst->setExecuted(); 1217 1218 // Not sure if I should set this here or just let commit try to 1219 // commit any squashed instructions. I like the latter a bit more. 1220 inst->setCanCommit(); 1221 1222 ++iewExecSquashedInsts; 1223 1224 decrWb(inst->seqNum); 1225 continue; 1226 } 1227 1228 Fault fault = NoFault; 1229 1230 // Execute instruction. 1231 // Note that if the instruction faults, it will be handled 1232 // at the commit stage. 1233 if (inst->isMemRef() && 1234 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1235 DPRINTF(IEW, "Execute: Calculating address for memory " 1236 "reference.\n"); 1237 1238 // Tell the LDSTQ to execute this instruction (if it is a load). 1239 if (inst->isLoad()) { 1240 // Loads will mark themselves as executed, and their writeback 1241 // event adds the instruction to the queue to commit 1242 fault = ldstQueue.executeLoad(inst); 1243 } else if (inst->isStore()) { 1244 fault = ldstQueue.executeStore(inst); 1245 1246 // If the store had a fault then it may not have a mem req 1247 if (!inst->isStoreConditional() && fault == NoFault) { 1248 inst->setExecuted(); 1249 1250 instToCommit(inst); 1251 } else if (fault != NoFault) { 1252 // If the instruction faulted, then we need to send it along to commit 1253 // without the instruction completing. 1254 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 1255 fault->name(), inst->seqNum); 1256 1257 // Send this instruction to commit, also make sure iew stage 1258 // realizes there is activity. 1259 inst->setExecuted(); 1260 1261 instToCommit(inst); 1262 activityThisCycle(); 1263 } 1264 1265 // Store conditionals will mark themselves as 1266 // executed, and their writeback event will add the 1267 // instruction to the queue to commit. 1268 } else { 1269 panic("Unexpected memory type!\n"); 1270 } 1271 1272 } else { 1273 inst->execute(); 1274 1275 inst->setExecuted(); 1276 1277 instToCommit(inst); 1278 } 1279 1280 updateExeInstStats(inst); 1281 1282 // Check if branch prediction was correct, if not then we need 1283 // to tell commit to squash in flight instructions. Only 1284 // handle this if there hasn't already been something that 1285 // redirects fetch in this group of instructions. 1286 1287 // This probably needs to prioritize the redirects if a different 1288 // scheduler is used. Currently the scheduler schedules the oldest 1289 // instruction first, so the branch resolution order will be correct. 1290 ThreadID tid = inst->threadNumber; 1291 1292 if (!fetchRedirect[tid] || 1293 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1294 1295 if (inst->mispredicted()) { 1296 fetchRedirect[tid] = true; 1297 1298 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1299 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1300 inst->readPredPC(), inst->readPredNPC()); 1301 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1302 " NPC: %#x.\n", inst->readNextPC(), 1303 inst->readNextNPC()); 1304 // If incorrect, then signal the ROB that it must be squashed. 1305 squashDueToBranch(inst, tid); 1306 1307 if (inst->readPredTaken()) { 1308 predictedTakenIncorrect++; 1309 } else { 1310 predictedNotTakenIncorrect++; 1311 } 1312 } else if (ldstQueue.violation(tid)) { 1313 assert(inst->isMemRef()); 1314 // If there was an ordering violation, then get the 1315 // DynInst that caused the violation. Note that this 1316 // clears the violation signal. 1317 DynInstPtr violator; 1318 violator = ldstQueue.getMemDepViolator(tid); 1319 1320 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1321 "%#x, inst PC: %#x. Addr is: %#x.\n", 1322 violator->readPC(), inst->readPC(), inst->physEffAddr); 1323 1324 // Ensure the violating instruction is older than 1325 // current squash 1326/* if (fetchRedirect[tid] && 1327 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 1328 continue; 1329*/ 1330 fetchRedirect[tid] = true; 1331 1332 // Tell the instruction queue that a violation has occured. 1333 instQueue.violation(inst, violator); 1334 1335 // Squash. 1336 squashDueToMemOrder(inst,tid); 1337 1338 ++memOrderViolationEvents; 1339 } else if (ldstQueue.loadBlocked(tid) && 1340 !ldstQueue.isLoadBlockedHandled(tid)) { 1341 fetchRedirect[tid] = true; 1342 1343 DPRINTF(IEW, "Load operation couldn't execute because the " 1344 "memory system is blocked. PC: %#x [sn:%lli]\n", 1345 inst->readPC(), inst->seqNum); 1346 1347 squashDueToMemBlocked(inst, tid); 1348 } 1349 } else { 1350 // Reset any state associated with redirects that will not 1351 // be used. 1352 if (ldstQueue.violation(tid)) { 1353 assert(inst->isMemRef()); 1354 1355 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1356 1357 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1358 "%#x, inst PC: %#x. Addr is: %#x.\n", 1359 violator->readPC(), inst->readPC(), inst->physEffAddr); 1360 DPRINTF(IEW, "Violation will not be handled because " 1361 "already squashing\n"); 1362 1363 ++memOrderViolationEvents; 1364 } 1365 if (ldstQueue.loadBlocked(tid) && 1366 !ldstQueue.isLoadBlockedHandled(tid)) { 1367 DPRINTF(IEW, "Load operation couldn't execute because the " 1368 "memory system is blocked. PC: %#x [sn:%lli]\n", 1369 inst->readPC(), inst->seqNum); 1370 DPRINTF(IEW, "Blocked load will not be handled because " 1371 "already squashing\n"); 1372 1373 ldstQueue.setLoadBlockedHandled(tid); 1374 } 1375 1376 } 1377 } 1378 1379 // Update and record activity if we processed any instructions. 1380 if (inst_num) { 1381 if (exeStatus == Idle) { 1382 exeStatus = Running; 1383 } 1384 1385 updatedQueues = true; 1386 1387 cpu->activityThisCycle(); 1388 } 1389 1390 // Need to reset this in case a writeback event needs to write into the 1391 // iew queue. That way the writeback event will write into the correct 1392 // spot in the queue. 1393 wbNumInst = 0; 1394} 1395 1396template <class Impl> 1397void 1398DefaultIEW<Impl>::writebackInsts() 1399{ 1400 // Loop through the head of the time buffer and wake any 1401 // dependents. These instructions are about to write back. Also 1402 // mark scoreboard that this instruction is finally complete. 1403 // Either have IEW have direct access to scoreboard, or have this 1404 // as part of backwards communication. 1405 for (int inst_num = 0; inst_num < wbWidth && 1406 toCommit->insts[inst_num]; inst_num++) { 1407 DynInstPtr inst = toCommit->insts[inst_num]; 1408 ThreadID tid = inst->threadNumber; 1409 1410 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1411 inst->seqNum, inst->readPC()); 1412 1413 iewInstsToCommit[tid]++; 1414 1415 // Some instructions will be sent to commit without having 1416 // executed because they need commit to handle them. 1417 // E.g. Uncached loads have not actually executed when they 1418 // are first sent to commit. Instead commit must tell the LSQ 1419 // when it's ready to execute the uncached load. 1420 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1421 int dependents = instQueue.wakeDependents(inst); 1422 1423 for (int i = 0; i < inst->numDestRegs(); i++) { 1424 //mark as Ready 1425 DPRINTF(IEW,"Setting Destination Register %i\n", 1426 inst->renamedDestRegIdx(i)); 1427 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1428 } 1429 1430 if (dependents) { 1431 producerInst[tid]++; 1432 consumerInst[tid]+= dependents; 1433 } 1434 writebackCount[tid]++; 1435 } 1436 1437 decrWb(inst->seqNum); 1438 } 1439} 1440 1441template<class Impl> 1442void 1443DefaultIEW<Impl>::tick() 1444{ 1445 wbNumInst = 0; 1446 wbCycle = 0; 1447 1448 wroteToTimeBuffer = false; 1449 updatedQueues = false; 1450 1451 sortInsts(); 1452 1453 // Free function units marked as being freed this cycle. 1454 fuPool->processFreeUnits(); 1455 1456 list<ThreadID>::iterator threads = activeThreads->begin(); 1457 list<ThreadID>::iterator end = activeThreads->end(); 1458 1459 // Check stall and squash signals, dispatch any instructions. 1460 while (threads != end) { 1461 ThreadID tid = *threads++; 1462 1463 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1464 1465 checkSignalsAndUpdate(tid); 1466 dispatch(tid); 1467 } 1468 1469 if (exeStatus != Squashing) { 1470 executeInsts(); 1471 1472 writebackInsts(); 1473 1474 // Have the instruction queue try to schedule any ready instructions. 1475 // (In actuality, this scheduling is for instructions that will 1476 // be executed next cycle.) 1477 instQueue.scheduleReadyInsts(); 1478 1479 // Also should advance its own time buffers if the stage ran. 1480 // Not the best place for it, but this works (hopefully). 1481 issueToExecQueue.advance(); 1482 } 1483 1484 bool broadcast_free_entries = false; 1485 1486 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1487 exeStatus = Idle; 1488 updateLSQNextCycle = false; 1489 1490 broadcast_free_entries = true; 1491 } 1492 1493 // Writeback any stores using any leftover bandwidth. 1494 ldstQueue.writebackStores(); 1495 1496 // Check the committed load/store signals to see if there's a load 1497 // or store to commit. Also check if it's being told to execute a 1498 // nonspeculative instruction. 1499 // This is pretty inefficient... 1500 1501 threads = activeThreads->begin(); 1502 while (threads != end) { 1503 ThreadID tid = (*threads++); 1504 1505 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1506 1507 // Update structures based on instructions committed. 1508 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1509 !fromCommit->commitInfo[tid].squash && 1510 !fromCommit->commitInfo[tid].robSquashing) { 1511 1512 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1513 1514 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1515 1516 updateLSQNextCycle = true; 1517 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1518 } 1519 1520 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1521 1522 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1523 if (fromCommit->commitInfo[tid].uncached) { 1524 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1525 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1526 } else { 1527 instQueue.scheduleNonSpec( 1528 fromCommit->commitInfo[tid].nonSpecSeqNum); 1529 } 1530 } 1531 1532 if (broadcast_free_entries) { 1533 toFetch->iewInfo[tid].iqCount = 1534 instQueue.getCount(tid); 1535 toFetch->iewInfo[tid].ldstqCount = 1536 ldstQueue.getCount(tid); 1537 1538 toRename->iewInfo[tid].usedIQ = true; 1539 toRename->iewInfo[tid].freeIQEntries = 1540 instQueue.numFreeEntries(); 1541 toRename->iewInfo[tid].usedLSQ = true; 1542 toRename->iewInfo[tid].freeLSQEntries = 1543 ldstQueue.numFreeEntries(tid); 1544 1545 wroteToTimeBuffer = true; 1546 } 1547 1548 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1549 tid, toRename->iewInfo[tid].dispatched); 1550 } 1551 1552 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1553 "LSQ has %i free entries.\n", 1554 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1555 ldstQueue.numFreeEntries()); 1556 1557 updateStatus(); 1558 1559 if (wroteToTimeBuffer) { 1560 DPRINTF(Activity, "Activity this cycle.\n"); 1561 cpu->activityThisCycle(); 1562 } 1563} 1564 1565template <class Impl> 1566void 1567DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1568{ 1569 ThreadID tid = inst->threadNumber; 1570 1571 // 1572 // Pick off the software prefetches 1573 // 1574#ifdef TARGET_ALPHA 1575 if (inst->isDataPrefetch()) 1576 iewExecutedSwp[tid]++; 1577 else 1578 iewIewExecutedcutedInsts++; 1579#else 1580 iewExecutedInsts++; 1581#endif 1582 1583 // 1584 // Control operations 1585 // 1586 if (inst->isControl()) 1587 iewExecutedBranches[tid]++; 1588 1589 // 1590 // Memory operations 1591 // 1592 if (inst->isMemRef()) { 1593 iewExecutedRefs[tid]++; 1594 1595 if (inst->isLoad()) { 1596 iewExecLoadInsts[tid]++; 1597 } 1598 } 1599} 1600 1601template <class Impl> 1602void 1603DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1604{ 1605 ThreadID tid = inst->threadNumber; 1606 1607 if (!fetchRedirect[tid] || 1608 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1609 1610 if (inst->mispredicted()) { 1611 fetchRedirect[tid] = true; 1612 1613 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1614 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1615 inst->readPredPC(), inst->readPredNPC()); 1616 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1617 " NPC: %#x.\n", inst->readNextPC(), 1618 inst->readNextNPC()); 1619 // If incorrect, then signal the ROB that it must be squashed. 1620 squashDueToBranch(inst, tid); 1621 1622 if (inst->readPredTaken()) { 1623 predictedTakenIncorrect++; 1624 } else { 1625 predictedNotTakenIncorrect++; 1626 } 1627 } 1628 } 1629} 1630