iew_impl.hh revision 3221 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43    : issueToExecQueue(params->backComSize, params->forwardComSize),
44      instQueue(params),
45      ldstQueue(params),
46      fuPool(params->fuPool),
47      commitToIEWDelay(params->commitToIEWDelay),
48      renameToIEWDelay(params->renameToIEWDelay),
49      issueToExecuteDelay(params->issueToExecuteDelay),
50      dispatchWidth(params->dispatchWidth),
51      issueWidth(params->issueWidth),
52      wbOutstanding(0),
53      wbWidth(params->wbWidth),
54      numThreads(params->numberOfThreads),
55      switchedOut(false)
56{
57    _status = Active;
58    exeStatus = Running;
59    wbStatus = Idle;
60
61    // Setup wire to read instructions coming from issue.
62    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64    // Instruction queue needs the queue between issue and execute.
65    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67    instQueue.setIEW(this);
68    ldstQueue.setIEW(this);
69
70    for (int i=0; i < numThreads; i++) {
71        dispatchStatus[i] = Running;
72        stalls[i].commit = false;
73        fetchRedirect[i] = false;
74        bdelayDoneSeqNum[i] = 0;
75    }
76
77    wbMax = wbWidth * params->wbDepth;
78
79    updateLSQNextCycle = false;
80
81    ableToIssue = true;
82
83    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90    return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97    using namespace Stats;
98
99    instQueue.regStats();
100    ldstQueue.regStats();
101
102    iewIdleCycles
103        .name(name() + ".iewIdleCycles")
104        .desc("Number of cycles IEW is idle");
105
106    iewSquashCycles
107        .name(name() + ".iewSquashCycles")
108        .desc("Number of cycles IEW is squashing");
109
110    iewBlockCycles
111        .name(name() + ".iewBlockCycles")
112        .desc("Number of cycles IEW is blocking");
113
114    iewUnblockCycles
115        .name(name() + ".iewUnblockCycles")
116        .desc("Number of cycles IEW is unblocking");
117
118    iewDispatchedInsts
119        .name(name() + ".iewDispatchedInsts")
120        .desc("Number of instructions dispatched to IQ");
121
122    iewDispSquashedInsts
123        .name(name() + ".iewDispSquashedInsts")
124        .desc("Number of squashed instructions skipped by dispatch");
125
126    iewDispLoadInsts
127        .name(name() + ".iewDispLoadInsts")
128        .desc("Number of dispatched load instructions");
129
130    iewDispStoreInsts
131        .name(name() + ".iewDispStoreInsts")
132        .desc("Number of dispatched store instructions");
133
134    iewDispNonSpecInsts
135        .name(name() + ".iewDispNonSpecInsts")
136        .desc("Number of dispatched non-speculative instructions");
137
138    iewIQFullEvents
139        .name(name() + ".iewIQFullEvents")
140        .desc("Number of times the IQ has become full, causing a stall");
141
142    iewLSQFullEvents
143        .name(name() + ".iewLSQFullEvents")
144        .desc("Number of times the LSQ has become full, causing a stall");
145
146    memOrderViolationEvents
147        .name(name() + ".memOrderViolationEvents")
148        .desc("Number of memory order violations");
149
150    predictedTakenIncorrect
151        .name(name() + ".predictedTakenIncorrect")
152        .desc("Number of branches that were predicted taken incorrectly");
153
154    predictedNotTakenIncorrect
155        .name(name() + ".predictedNotTakenIncorrect")
156        .desc("Number of branches that were predicted not taken incorrectly");
157
158    branchMispredicts
159        .name(name() + ".branchMispredicts")
160        .desc("Number of branch mispredicts detected at execute");
161
162    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164    iewExecutedInsts
165        .name(name() + ".iewExecutedInsts")
166        .desc("Number of executed instructions");
167
168    iewExecLoadInsts
169        .init(cpu->number_of_threads)
170        .name(name() + ".iewExecLoadInsts")
171        .desc("Number of load instructions executed")
172        .flags(total);
173
174    iewExecSquashedInsts
175        .name(name() + ".iewExecSquashedInsts")
176        .desc("Number of squashed instructions skipped in execute");
177
178    iewExecutedSwp
179        .init(cpu->number_of_threads)
180        .name(name() + ".EXEC:swp")
181        .desc("number of swp insts executed")
182        .flags(total);
183
184    iewExecutedNop
185        .init(cpu->number_of_threads)
186        .name(name() + ".EXEC:nop")
187        .desc("number of nop insts executed")
188        .flags(total);
189
190    iewExecutedRefs
191        .init(cpu->number_of_threads)
192        .name(name() + ".EXEC:refs")
193        .desc("number of memory reference insts executed")
194        .flags(total);
195
196    iewExecutedBranches
197        .init(cpu->number_of_threads)
198        .name(name() + ".EXEC:branches")
199        .desc("Number of branches executed")
200        .flags(total);
201
202    iewExecStoreInsts
203        .name(name() + ".EXEC:stores")
204        .desc("Number of stores executed")
205        .flags(total);
206    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208    iewExecRate
209        .name(name() + ".EXEC:rate")
210        .desc("Inst execution rate")
211        .flags(total);
212
213    iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215    iewInstsToCommit
216        .init(cpu->number_of_threads)
217        .name(name() + ".WB:sent")
218        .desc("cumulative count of insts sent to commit")
219        .flags(total);
220
221    writebackCount
222        .init(cpu->number_of_threads)
223        .name(name() + ".WB:count")
224        .desc("cumulative count of insts written-back")
225        .flags(total);
226
227    producerInst
228        .init(cpu->number_of_threads)
229        .name(name() + ".WB:producers")
230        .desc("num instructions producing a value")
231        .flags(total);
232
233    consumerInst
234        .init(cpu->number_of_threads)
235        .name(name() + ".WB:consumers")
236        .desc("num instructions consuming a value")
237        .flags(total);
238
239    wbPenalized
240        .init(cpu->number_of_threads)
241        .name(name() + ".WB:penalized")
242        .desc("number of instrctions required to write to 'other' IQ")
243        .flags(total);
244
245    wbPenalizedRate
246        .name(name() + ".WB:penalized_rate")
247        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248        .flags(total);
249
250    wbPenalizedRate = wbPenalized / writebackCount;
251
252    wbFanout
253        .name(name() + ".WB:fanout")
254        .desc("average fanout of values written-back")
255        .flags(total);
256
257    wbFanout = producerInst / consumerInst;
258
259    wbRate
260        .name(name() + ".WB:rate")
261        .desc("insts written-back per cycle")
262        .flags(total);
263    wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270    for (int tid=0; tid < numThreads; tid++) {
271        toRename->iewInfo[tid].usedIQ = true;
272        toRename->iewInfo[tid].freeIQEntries =
273            instQueue.numFreeEntries(tid);
274
275        toRename->iewInfo[tid].usedLSQ = true;
276        toRename->iewInfo[tid].freeLSQEntries =
277            ldstQueue.numFreeEntries(tid);
278    }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285    DPRINTF(IEW, "Setting CPU pointer.\n");
286    cpu = cpu_ptr;
287
288    instQueue.setCPU(cpu_ptr);
289    ldstQueue.setCPU(cpu_ptr);
290
291    cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298    DPRINTF(IEW, "Setting time buffer pointer.\n");
299    timeBuffer = tb_ptr;
300
301    // Setup wire to read information from time buffer, from commit.
302    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304    // Setup wire to write information back to previous stages.
305    toRename = timeBuffer->getWire(0);
306
307    toFetch = timeBuffer->getWire(0);
308
309    // Instruction queue also needs main time buffer.
310    instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317    DPRINTF(IEW, "Setting rename queue pointer.\n");
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    DPRINTF(IEW, "Setting IEW queue pointer.\n");
329    iewQueue = iq_ptr;
330
331    // Setup wire to write instructions to commit.
332    toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339    DPRINTF(IEW, "Setting active threads list pointer.\n");
340    activeThreads = at_ptr;
341
342    ldstQueue.setActiveThreads(at_ptr);
343    instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350    DPRINTF(IEW, "Setting scoreboard pointer.\n");
351    scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358    // IEW is ready to drain at any time.
359    cpu->signalDrained();
360    return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373    // Clear any state.
374    switchedOut = true;
375    assert(insts[0].empty());
376    assert(skidBuffer[0].empty());
377
378    instQueue.switchOut();
379    ldstQueue.switchOut();
380    fuPool->switchOut();
381
382    for (int i = 0; i < numThreads; i++) {
383        while (!insts[i].empty())
384            insts[i].pop();
385        while (!skidBuffer[i].empty())
386            skidBuffer[i].pop();
387    }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394    // Reset all state.
395    _status = Active;
396    exeStatus = Running;
397    wbStatus = Idle;
398    switchedOut = false;
399
400    instQueue.takeOverFrom();
401    ldstQueue.takeOverFrom();
402    fuPool->takeOverFrom();
403
404    initStage();
405    cpu->activityThisCycle();
406
407    for (int i=0; i < numThreads; i++) {
408        dispatchStatus[i] = Running;
409        stalls[i].commit = false;
410        fetchRedirect[i] = false;
411    }
412
413    updateLSQNextCycle = false;
414
415    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416        issueToExecQueue.advance();
417    }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425            tid);
426
427    // Tell the IQ to start squashing.
428    instQueue.squash(tid);
429
430    // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436    updatedQueues = true;
437
438    // Clear the skid buffer in case it has any data in it.
439    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442    while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444        if (skidBuffer[tid].front()->seqNum <=
445            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447                    "that occur before delay slot [sn:%i].\n",
448                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449                    tid);
450            break;
451        } else {
452            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454        }
455#endif
456        if (skidBuffer[tid].front()->isLoad() ||
457            skidBuffer[tid].front()->isStore() ) {
458            toRename->iewInfo[tid].dispatchedToLSQ++;
459        }
460
461        toRename->iewInfo[tid].dispatched++;
462
463        skidBuffer[tid].pop();
464    }
465
466    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468    emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478    toCommit->squash[tid] = true;
479    toCommit->squashedSeqNum[tid] = inst->seqNum;
480    toCommit->mispredPC[tid] = inst->readPC();
481    toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484    bool branch_taken = inst->readNextNPC() !=
485        (inst->readNextPC() + sizeof(TheISA::MachInst));
486
487    toCommit->branchTaken[tid] = branch_taken;
488
489    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491    if (inst->isCondDelaySlot() && branch_taken) {
492        toCommit->nextPC[tid] = inst->readNextPC();
493    } else {
494        toCommit->nextPC[tid] = inst->readNextNPC();
495    }
496#else
497    toCommit->branchTaken[tid] = inst->readNextPC() !=
498        (inst->readPC() + sizeof(TheISA::MachInst));
499    toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502    toCommit->includeSquashInst[tid] = false;
503
504    wroteToTimeBuffer = true;
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514    toCommit->squash[tid] = true;
515    toCommit->squashedSeqNum[tid] = inst->seqNum;
516    toCommit->nextPC[tid] = inst->readNextPC();
517
518    toCommit->includeSquashInst[tid] = false;
519
520    wroteToTimeBuffer = true;
521}
522
523template<class Impl>
524void
525DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
526{
527    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
528            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
529
530    toCommit->squash[tid] = true;
531    toCommit->squashedSeqNum[tid] = inst->seqNum;
532    toCommit->nextPC[tid] = inst->readPC();
533
534    // Must include the broadcasted SN in the squash.
535    toCommit->includeSquashInst[tid] = true;
536
537    ldstQueue.setLoadBlockedHandled(tid);
538
539    wroteToTimeBuffer = true;
540}
541
542template<class Impl>
543void
544DefaultIEW<Impl>::block(unsigned tid)
545{
546    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
547
548    if (dispatchStatus[tid] != Blocked &&
549        dispatchStatus[tid] != Unblocking) {
550        toRename->iewBlock[tid] = true;
551        wroteToTimeBuffer = true;
552    }
553
554    // Add the current inputs to the skid buffer so they can be
555    // reprocessed when this stage unblocks.
556    skidInsert(tid);
557
558    dispatchStatus[tid] = Blocked;
559}
560
561template<class Impl>
562void
563DefaultIEW<Impl>::unblock(unsigned tid)
564{
565    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
566            "buffer %u.\n",tid, tid);
567
568    // If the skid bufffer is empty, signal back to previous stages to unblock.
569    // Also switch status to running.
570    if (skidBuffer[tid].empty()) {
571        toRename->iewUnblock[tid] = true;
572        wroteToTimeBuffer = true;
573        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
574        dispatchStatus[tid] = Running;
575    }
576}
577
578template<class Impl>
579void
580DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
581{
582    instQueue.wakeDependents(inst);
583}
584
585template<class Impl>
586void
587DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
588{
589    instQueue.rescheduleMemInst(inst);
590}
591
592template<class Impl>
593void
594DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
595{
596    instQueue.replayMemInst(inst);
597}
598
599template<class Impl>
600void
601DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
602{
603    // This function should not be called after writebackInsts in a
604    // single cycle.  That will cause problems with an instruction
605    // being added to the queue to commit without being processed by
606    // writebackInsts prior to being sent to commit.
607
608    // First check the time slot that this instruction will write
609    // to.  If there are free write ports at the time, then go ahead
610    // and write the instruction to that time.  If there are not,
611    // keep looking back to see where's the first time there's a
612    // free slot.
613    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
614        ++wbNumInst;
615        if (wbNumInst == wbWidth) {
616            ++wbCycle;
617            wbNumInst = 0;
618        }
619
620        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
621    }
622
623    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
624            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
625    // Add finished instruction to queue to commit.
626    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
627    (*iewQueue)[wbCycle].size++;
628}
629
630template <class Impl>
631unsigned
632DefaultIEW<Impl>::validInstsFromRename()
633{
634    unsigned inst_count = 0;
635
636    for (int i=0; i<fromRename->size; i++) {
637        if (!fromRename->insts[i]->isSquashed())
638            inst_count++;
639    }
640
641    return inst_count;
642}
643
644template<class Impl>
645void
646DefaultIEW<Impl>::skidInsert(unsigned tid)
647{
648    DynInstPtr inst = NULL;
649
650    while (!insts[tid].empty()) {
651        inst = insts[tid].front();
652
653        insts[tid].pop();
654
655        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
656                "dispatch skidBuffer %i\n",tid, inst->seqNum,
657                inst->readPC(),tid);
658
659        skidBuffer[tid].push(inst);
660    }
661
662    assert(skidBuffer[tid].size() <= skidBufferMax &&
663           "Skidbuffer Exceeded Max Size");
664}
665
666template<class Impl>
667int
668DefaultIEW<Impl>::skidCount()
669{
670    int max=0;
671
672    std::list<unsigned>::iterator threads = (*activeThreads).begin();
673
674    while (threads != (*activeThreads).end()) {
675        unsigned thread_count = skidBuffer[*threads++].size();
676        if (max < thread_count)
677            max = thread_count;
678    }
679
680    return max;
681}
682
683template<class Impl>
684bool
685DefaultIEW<Impl>::skidsEmpty()
686{
687    std::list<unsigned>::iterator threads = (*activeThreads).begin();
688
689    while (threads != (*activeThreads).end()) {
690        if (!skidBuffer[*threads++].empty())
691            return false;
692    }
693
694    return true;
695}
696
697template <class Impl>
698void
699DefaultIEW<Impl>::updateStatus()
700{
701    bool any_unblocking = false;
702
703    std::list<unsigned>::iterator threads = (*activeThreads).begin();
704
705    threads = (*activeThreads).begin();
706
707    while (threads != (*activeThreads).end()) {
708        unsigned tid = *threads++;
709
710        if (dispatchStatus[tid] == Unblocking) {
711            any_unblocking = true;
712            break;
713        }
714    }
715
716    // If there are no ready instructions waiting to be scheduled by the IQ,
717    // and there's no stores waiting to write back, and dispatch is not
718    // unblocking, then there is no internal activity for the IEW stage.
719    if (_status == Active && !instQueue.hasReadyInsts() &&
720        !ldstQueue.willWB() && !any_unblocking) {
721        DPRINTF(IEW, "IEW switching to idle\n");
722
723        deactivateStage();
724
725        _status = Inactive;
726    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
727                                       ldstQueue.willWB() ||
728                                       any_unblocking)) {
729        // Otherwise there is internal activity.  Set to active.
730        DPRINTF(IEW, "IEW switching to active\n");
731
732        activateStage();
733
734        _status = Active;
735    }
736}
737
738template <class Impl>
739void
740DefaultIEW<Impl>::resetEntries()
741{
742    instQueue.resetEntries();
743    ldstQueue.resetEntries();
744}
745
746template <class Impl>
747void
748DefaultIEW<Impl>::readStallSignals(unsigned tid)
749{
750    if (fromCommit->commitBlock[tid]) {
751        stalls[tid].commit = true;
752    }
753
754    if (fromCommit->commitUnblock[tid]) {
755        assert(stalls[tid].commit);
756        stalls[tid].commit = false;
757    }
758}
759
760template <class Impl>
761bool
762DefaultIEW<Impl>::checkStall(unsigned tid)
763{
764    bool ret_val(false);
765
766    if (stalls[tid].commit) {
767        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
768        ret_val = true;
769    } else if (instQueue.isFull(tid)) {
770        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
771        ret_val = true;
772    } else if (ldstQueue.isFull(tid)) {
773        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
774
775        if (ldstQueue.numLoads(tid) > 0 ) {
776
777            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
778                    tid,ldstQueue.getLoadHeadSeqNum(tid));
779        }
780
781        if (ldstQueue.numStores(tid) > 0) {
782
783            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
784                    tid,ldstQueue.getStoreHeadSeqNum(tid));
785        }
786
787        ret_val = true;
788    } else if (ldstQueue.isStalled(tid)) {
789        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
790        ret_val = true;
791    }
792
793    return ret_val;
794}
795
796template <class Impl>
797void
798DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
799{
800    // Check if there's a squash signal, squash if there is
801    // Check stall signals, block if there is.
802    // If status was Blocked
803    //     if so then go to unblocking
804    // If status was Squashing
805    //     check if squashing is not high.  Switch to running this cycle.
806
807    readStallSignals(tid);
808
809    if (fromCommit->commitInfo[tid].squash) {
810        squash(tid);
811
812        if (dispatchStatus[tid] == Blocked ||
813            dispatchStatus[tid] == Unblocking) {
814            toRename->iewUnblock[tid] = true;
815            wroteToTimeBuffer = true;
816        }
817
818        dispatchStatus[tid] = Squashing;
819
820        fetchRedirect[tid] = false;
821        return;
822    }
823
824    if (fromCommit->commitInfo[tid].robSquashing) {
825        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
826
827        dispatchStatus[tid] = Squashing;
828
829        emptyRenameInsts(tid);
830        wroteToTimeBuffer = true;
831        return;
832    }
833
834    if (checkStall(tid)) {
835        block(tid);
836        dispatchStatus[tid] = Blocked;
837        return;
838    }
839
840    if (dispatchStatus[tid] == Blocked) {
841        // Status from previous cycle was blocked, but there are no more stall
842        // conditions.  Switch over to unblocking.
843        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
844                tid);
845
846        dispatchStatus[tid] = Unblocking;
847
848        unblock(tid);
849
850        return;
851    }
852
853    if (dispatchStatus[tid] == Squashing) {
854        // Switch status to running if rename isn't being told to block or
855        // squash this cycle.
856        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
857                tid);
858
859        dispatchStatus[tid] = Running;
860
861        return;
862    }
863}
864
865template <class Impl>
866void
867DefaultIEW<Impl>::sortInsts()
868{
869    int insts_from_rename = fromRename->size;
870#ifdef DEBUG
871#if !ISA_HAS_DELAY_SLOT
872    for (int i = 0; i < numThreads; i++)
873        assert(insts[i].empty());
874#endif
875#endif
876    for (int i = 0; i < insts_from_rename; ++i) {
877        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
878    }
879}
880
881template <class Impl>
882void
883DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
884{
885    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
886            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
887
888    while (!insts[tid].empty()) {
889#if ISA_HAS_DELAY_SLOT
890        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
891            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
892                    " that occurs at or before delay slot [sn:%i].\n",
893                    tid, bdelayDoneSeqNum[tid]);
894            break;
895        } else {
896            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
897                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
898        }
899#endif
900
901        if (insts[tid].front()->isLoad() ||
902            insts[tid].front()->isStore() ) {
903            toRename->iewInfo[tid].dispatchedToLSQ++;
904        }
905
906        toRename->iewInfo[tid].dispatched++;
907
908        insts[tid].pop();
909    }
910}
911
912template <class Impl>
913void
914DefaultIEW<Impl>::wakeCPU()
915{
916    cpu->wakeCPU();
917}
918
919template <class Impl>
920void
921DefaultIEW<Impl>::activityThisCycle()
922{
923    DPRINTF(Activity, "Activity this cycle.\n");
924    cpu->activityThisCycle();
925}
926
927template <class Impl>
928inline void
929DefaultIEW<Impl>::activateStage()
930{
931    DPRINTF(Activity, "Activating stage.\n");
932    cpu->activateStage(O3CPU::IEWIdx);
933}
934
935template <class Impl>
936inline void
937DefaultIEW<Impl>::deactivateStage()
938{
939    DPRINTF(Activity, "Deactivating stage.\n");
940    cpu->deactivateStage(O3CPU::IEWIdx);
941}
942
943template<class Impl>
944void
945DefaultIEW<Impl>::dispatch(unsigned tid)
946{
947    // If status is Running or idle,
948    //     call dispatchInsts()
949    // If status is Unblocking,
950    //     buffer any instructions coming from rename
951    //     continue trying to empty skid buffer
952    //     check if stall conditions have passed
953
954    if (dispatchStatus[tid] == Blocked) {
955        ++iewBlockCycles;
956
957    } else if (dispatchStatus[tid] == Squashing) {
958        ++iewSquashCycles;
959    }
960
961    // Dispatch should try to dispatch as many instructions as its bandwidth
962    // will allow, as long as it is not currently blocked.
963    if (dispatchStatus[tid] == Running ||
964        dispatchStatus[tid] == Idle) {
965        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
966                "dispatch.\n", tid);
967
968        dispatchInsts(tid);
969    } else if (dispatchStatus[tid] == Unblocking) {
970        // Make sure that the skid buffer has something in it if the
971        // status is unblocking.
972        assert(!skidsEmpty());
973
974        // If the status was unblocking, then instructions from the skid
975        // buffer were used.  Remove those instructions and handle
976        // the rest of unblocking.
977        dispatchInsts(tid);
978
979        ++iewUnblockCycles;
980
981        if (validInstsFromRename() && dispatchedAllInsts) {
982            // Add the current inputs to the skid buffer so they can be
983            // reprocessed when this stage unblocks.
984            skidInsert(tid);
985        }
986
987        unblock(tid);
988    }
989}
990
991template <class Impl>
992void
993DefaultIEW<Impl>::dispatchInsts(unsigned tid)
994{
995    dispatchedAllInsts = true;
996
997    // Obtain instructions from skid buffer if unblocking, or queue from rename
998    // otherwise.
999    std::queue<DynInstPtr> &insts_to_dispatch =
1000        dispatchStatus[tid] == Unblocking ?
1001        skidBuffer[tid] : insts[tid];
1002
1003    int insts_to_add = insts_to_dispatch.size();
1004
1005    DynInstPtr inst;
1006    bool add_to_iq = false;
1007    int dis_num_inst = 0;
1008
1009    // Loop through the instructions, putting them in the instruction
1010    // queue.
1011    for ( ; dis_num_inst < insts_to_add &&
1012              dis_num_inst < dispatchWidth;
1013          ++dis_num_inst)
1014    {
1015        inst = insts_to_dispatch.front();
1016
1017        if (dispatchStatus[tid] == Unblocking) {
1018            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1019                    "buffer\n", tid);
1020        }
1021
1022        // Make sure there's a valid instruction there.
1023        assert(inst);
1024
1025        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1026                "IQ.\n",
1027                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1028
1029        // Be sure to mark these instructions as ready so that the
1030        // commit stage can go ahead and execute them, and mark
1031        // them as issued so the IQ doesn't reprocess them.
1032
1033        // Check for squashed instructions.
1034        if (inst->isSquashed()) {
1035            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1036                    "not adding to IQ.\n", tid);
1037
1038            ++iewDispSquashedInsts;
1039
1040            insts_to_dispatch.pop();
1041
1042            //Tell Rename That An Instruction has been processed
1043            if (inst->isLoad() || inst->isStore()) {
1044                toRename->iewInfo[tid].dispatchedToLSQ++;
1045            }
1046            toRename->iewInfo[tid].dispatched++;
1047
1048            continue;
1049        }
1050
1051        // Check for full conditions.
1052        if (instQueue.isFull(tid)) {
1053            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1054
1055            // Call function to start blocking.
1056            block(tid);
1057
1058            // Set unblock to false. Special case where we are using
1059            // skidbuffer (unblocking) instructions but then we still
1060            // get full in the IQ.
1061            toRename->iewUnblock[tid] = false;
1062
1063            dispatchedAllInsts = false;
1064
1065            ++iewIQFullEvents;
1066            break;
1067        } else if (ldstQueue.isFull(tid)) {
1068            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1069
1070            // Call function to start blocking.
1071            block(tid);
1072
1073            // Set unblock to false. Special case where we are using
1074            // skidbuffer (unblocking) instructions but then we still
1075            // get full in the IQ.
1076            toRename->iewUnblock[tid] = false;
1077
1078            dispatchedAllInsts = false;
1079
1080            ++iewLSQFullEvents;
1081            break;
1082        }
1083
1084        // Otherwise issue the instruction just fine.
1085        if (inst->isLoad()) {
1086            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1087                    "encountered, adding to LSQ.\n", tid);
1088
1089            // Reserve a spot in the load store queue for this
1090            // memory access.
1091            ldstQueue.insertLoad(inst);
1092
1093            ++iewDispLoadInsts;
1094
1095            add_to_iq = true;
1096
1097            toRename->iewInfo[tid].dispatchedToLSQ++;
1098        } else if (inst->isStore()) {
1099            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1100                    "encountered, adding to LSQ.\n", tid);
1101
1102            ldstQueue.insertStore(inst);
1103
1104            ++iewDispStoreInsts;
1105
1106            if (inst->isStoreConditional()) {
1107                // Store conditionals need to be set as "canCommit()"
1108                // so that commit can process them when they reach the
1109                // head of commit.
1110                // @todo: This is somewhat specific to Alpha.
1111                inst->setCanCommit();
1112                instQueue.insertNonSpec(inst);
1113                add_to_iq = false;
1114
1115                ++iewDispNonSpecInsts;
1116            } else {
1117                add_to_iq = true;
1118            }
1119
1120            toRename->iewInfo[tid].dispatchedToLSQ++;
1121#if FULL_SYSTEM
1122        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1123            // Same as non-speculative stores.
1124            inst->setCanCommit();
1125            instQueue.insertBarrier(inst);
1126            add_to_iq = false;
1127#endif
1128        } else if (inst->isNonSpeculative()) {
1129            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1130                    "encountered, skipping.\n", tid);
1131
1132            // Same as non-speculative stores.
1133            inst->setCanCommit();
1134
1135            // Specifically insert it as nonspeculative.
1136            instQueue.insertNonSpec(inst);
1137
1138            ++iewDispNonSpecInsts;
1139
1140            add_to_iq = false;
1141        } else if (inst->isNop()) {
1142            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1143                    "skipping.\n", tid);
1144
1145            inst->setIssued();
1146            inst->setExecuted();
1147            inst->setCanCommit();
1148
1149            instQueue.recordProducer(inst);
1150
1151            iewExecutedNop[tid]++;
1152
1153            add_to_iq = false;
1154        } else if (inst->isExecuted()) {
1155            assert(0 && "Instruction shouldn't be executed.\n");
1156            DPRINTF(IEW, "Issue: Executed branch encountered, "
1157                    "skipping.\n");
1158
1159            inst->setIssued();
1160            inst->setCanCommit();
1161
1162            instQueue.recordProducer(inst);
1163
1164            add_to_iq = false;
1165        } else {
1166            add_to_iq = true;
1167        }
1168
1169        // If the instruction queue is not full, then add the
1170        // instruction.
1171        if (add_to_iq) {
1172            instQueue.insert(inst);
1173        }
1174
1175        insts_to_dispatch.pop();
1176
1177        toRename->iewInfo[tid].dispatched++;
1178
1179        ++iewDispatchedInsts;
1180    }
1181
1182    if (!insts_to_dispatch.empty()) {
1183        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1184        block(tid);
1185        toRename->iewUnblock[tid] = false;
1186    }
1187
1188    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1189        dispatchStatus[tid] = Running;
1190
1191        updatedQueues = true;
1192    }
1193
1194    dis_num_inst = 0;
1195}
1196
1197template <class Impl>
1198void
1199DefaultIEW<Impl>::printAvailableInsts()
1200{
1201    int inst = 0;
1202
1203    std::cout << "Available Instructions: ";
1204
1205    while (fromIssue->insts[inst]) {
1206
1207        if (inst%3==0) std::cout << "\n\t";
1208
1209        std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1210             << " TN: " << fromIssue->insts[inst]->threadNumber
1211             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1212
1213        inst++;
1214
1215    }
1216
1217    std::cout << "\n";
1218}
1219
1220template <class Impl>
1221void
1222DefaultIEW<Impl>::executeInsts()
1223{
1224    wbNumInst = 0;
1225    wbCycle = 0;
1226
1227    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1228
1229    while (threads != (*activeThreads).end()) {
1230        unsigned tid = *threads++;
1231        fetchRedirect[tid] = false;
1232    }
1233
1234    // Uncomment this if you want to see all available instructions.
1235//    printAvailableInsts();
1236
1237    // Execute/writeback any instructions that are available.
1238    int insts_to_execute = fromIssue->size;
1239    int inst_num = 0;
1240    for (; inst_num < insts_to_execute;
1241          ++inst_num) {
1242
1243        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1244
1245        DynInstPtr inst = instQueue.getInstToExecute();
1246
1247        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1248                inst->readPC(), inst->threadNumber,inst->seqNum);
1249
1250        // Check if the instruction is squashed; if so then skip it
1251        if (inst->isSquashed()) {
1252            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1253
1254            // Consider this instruction executed so that commit can go
1255            // ahead and retire the instruction.
1256            inst->setExecuted();
1257
1258            // Not sure if I should set this here or just let commit try to
1259            // commit any squashed instructions.  I like the latter a bit more.
1260            inst->setCanCommit();
1261
1262            ++iewExecSquashedInsts;
1263
1264            decrWb(inst->seqNum);
1265            continue;
1266        }
1267
1268        Fault fault = NoFault;
1269
1270        // Execute instruction.
1271        // Note that if the instruction faults, it will be handled
1272        // at the commit stage.
1273        if (inst->isMemRef() &&
1274            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1275            DPRINTF(IEW, "Execute: Calculating address for memory "
1276                    "reference.\n");
1277
1278            // Tell the LDSTQ to execute this instruction (if it is a load).
1279            if (inst->isLoad()) {
1280                // Loads will mark themselves as executed, and their writeback
1281                // event adds the instruction to the queue to commit
1282                fault = ldstQueue.executeLoad(inst);
1283            } else if (inst->isStore()) {
1284                fault = ldstQueue.executeStore(inst);
1285
1286                // If the store had a fault then it may not have a mem req
1287                if (!inst->isStoreConditional() && fault == NoFault) {
1288                    inst->setExecuted();
1289
1290                    instToCommit(inst);
1291                } else if (fault != NoFault) {
1292                    // If the instruction faulted, then we need to send it along to commit
1293                    // without the instruction completing.
1294                    DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
1295
1296                    // Send this instruction to commit, also make sure iew stage
1297                    // realizes there is activity.
1298                    inst->setExecuted();
1299
1300                    instToCommit(inst);
1301                    activityThisCycle();
1302                }
1303
1304                // Store conditionals will mark themselves as
1305                // executed, and their writeback event will add the
1306                // instruction to the queue to commit.
1307            } else {
1308                panic("Unexpected memory type!\n");
1309            }
1310
1311        } else {
1312            inst->execute();
1313
1314            inst->setExecuted();
1315
1316            instToCommit(inst);
1317        }
1318
1319        updateExeInstStats(inst);
1320
1321        // Check if branch prediction was correct, if not then we need
1322        // to tell commit to squash in flight instructions.  Only
1323        // handle this if there hasn't already been something that
1324        // redirects fetch in this group of instructions.
1325
1326        // This probably needs to prioritize the redirects if a different
1327        // scheduler is used.  Currently the scheduler schedules the oldest
1328        // instruction first, so the branch resolution order will be correct.
1329        unsigned tid = inst->threadNumber;
1330
1331        if (!fetchRedirect[tid]) {
1332
1333            if (inst->mispredicted()) {
1334                fetchRedirect[tid] = true;
1335
1336                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1337#if ISA_HAS_DELAY_SLOT
1338                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1339                        inst->nextNPC);
1340#else
1341                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1342                        inst->nextPC);
1343#endif
1344                // If incorrect, then signal the ROB that it must be squashed.
1345                squashDueToBranch(inst, tid);
1346
1347                if (inst->predTaken()) {
1348                    predictedTakenIncorrect++;
1349                } else {
1350                    predictedNotTakenIncorrect++;
1351                }
1352            } else if (ldstQueue.violation(tid)) {
1353                fetchRedirect[tid] = true;
1354
1355                // If there was an ordering violation, then get the
1356                // DynInst that caused the violation.  Note that this
1357                // clears the violation signal.
1358                DynInstPtr violator;
1359                violator = ldstQueue.getMemDepViolator(tid);
1360
1361                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1362                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1363                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1364
1365                // Tell the instruction queue that a violation has occured.
1366                instQueue.violation(inst, violator);
1367
1368                // Squash.
1369                squashDueToMemOrder(inst,tid);
1370
1371                ++memOrderViolationEvents;
1372            } else if (ldstQueue.loadBlocked(tid) &&
1373                       !ldstQueue.isLoadBlockedHandled(tid)) {
1374                fetchRedirect[tid] = true;
1375
1376                DPRINTF(IEW, "Load operation couldn't execute because the "
1377                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1378                        inst->readPC(), inst->seqNum);
1379
1380                squashDueToMemBlocked(inst, tid);
1381            }
1382        }
1383    }
1384
1385    // Update and record activity if we processed any instructions.
1386    if (inst_num) {
1387        if (exeStatus == Idle) {
1388            exeStatus = Running;
1389        }
1390
1391        updatedQueues = true;
1392
1393        cpu->activityThisCycle();
1394    }
1395
1396    // Need to reset this in case a writeback event needs to write into the
1397    // iew queue.  That way the writeback event will write into the correct
1398    // spot in the queue.
1399    wbNumInst = 0;
1400}
1401
1402template <class Impl>
1403void
1404DefaultIEW<Impl>::writebackInsts()
1405{
1406    // Loop through the head of the time buffer and wake any
1407    // dependents.  These instructions are about to write back.  Also
1408    // mark scoreboard that this instruction is finally complete.
1409    // Either have IEW have direct access to scoreboard, or have this
1410    // as part of backwards communication.
1411    for (int inst_num = 0; inst_num < issueWidth &&
1412             toCommit->insts[inst_num]; inst_num++) {
1413        DynInstPtr inst = toCommit->insts[inst_num];
1414        int tid = inst->threadNumber;
1415
1416        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1417                inst->seqNum, inst->readPC());
1418
1419        iewInstsToCommit[tid]++;
1420
1421        // Some instructions will be sent to commit without having
1422        // executed because they need commit to handle them.
1423        // E.g. Uncached loads have not actually executed when they
1424        // are first sent to commit.  Instead commit must tell the LSQ
1425        // when it's ready to execute the uncached load.
1426        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1427            int dependents = instQueue.wakeDependents(inst);
1428
1429            for (int i = 0; i < inst->numDestRegs(); i++) {
1430                //mark as Ready
1431                DPRINTF(IEW,"Setting Destination Register %i\n",
1432                        inst->renamedDestRegIdx(i));
1433                scoreboard->setReg(inst->renamedDestRegIdx(i));
1434            }
1435
1436            if (dependents) {
1437                producerInst[tid]++;
1438                consumerInst[tid]+= dependents;
1439            }
1440            writebackCount[tid]++;
1441        }
1442
1443        decrWb(inst->seqNum);
1444    }
1445}
1446
1447template<class Impl>
1448void
1449DefaultIEW<Impl>::tick()
1450{
1451    wbNumInst = 0;
1452    wbCycle = 0;
1453
1454    wroteToTimeBuffer = false;
1455    updatedQueues = false;
1456
1457    sortInsts();
1458
1459    // Free function units marked as being freed this cycle.
1460    fuPool->processFreeUnits();
1461
1462    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1463
1464    // Check stall and squash signals, dispatch any instructions.
1465    while (threads != (*activeThreads).end()) {
1466           unsigned tid = *threads++;
1467
1468        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1469
1470        checkSignalsAndUpdate(tid);
1471        dispatch(tid);
1472    }
1473
1474    if (exeStatus != Squashing) {
1475        executeInsts();
1476
1477        writebackInsts();
1478
1479        // Have the instruction queue try to schedule any ready instructions.
1480        // (In actuality, this scheduling is for instructions that will
1481        // be executed next cycle.)
1482        instQueue.scheduleReadyInsts();
1483
1484        // Also should advance its own time buffers if the stage ran.
1485        // Not the best place for it, but this works (hopefully).
1486        issueToExecQueue.advance();
1487    }
1488
1489    bool broadcast_free_entries = false;
1490
1491    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1492        exeStatus = Idle;
1493        updateLSQNextCycle = false;
1494
1495        broadcast_free_entries = true;
1496    }
1497
1498    // Writeback any stores using any leftover bandwidth.
1499    ldstQueue.writebackStores();
1500
1501    // Check the committed load/store signals to see if there's a load
1502    // or store to commit.  Also check if it's being told to execute a
1503    // nonspeculative instruction.
1504    // This is pretty inefficient...
1505
1506    threads = (*activeThreads).begin();
1507    while (threads != (*activeThreads).end()) {
1508        unsigned tid = (*threads++);
1509
1510        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1511
1512        // Update structures based on instructions committed.
1513        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1514            !fromCommit->commitInfo[tid].squash &&
1515            !fromCommit->commitInfo[tid].robSquashing) {
1516
1517            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1518
1519            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1520
1521            updateLSQNextCycle = true;
1522            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1523        }
1524
1525        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1526
1527            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1528            if (fromCommit->commitInfo[tid].uncached) {
1529                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1530            } else {
1531                instQueue.scheduleNonSpec(
1532                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1533            }
1534        }
1535
1536        if (broadcast_free_entries) {
1537            toFetch->iewInfo[tid].iqCount =
1538                instQueue.getCount(tid);
1539            toFetch->iewInfo[tid].ldstqCount =
1540                ldstQueue.getCount(tid);
1541
1542            toRename->iewInfo[tid].usedIQ = true;
1543            toRename->iewInfo[tid].freeIQEntries =
1544                instQueue.numFreeEntries();
1545            toRename->iewInfo[tid].usedLSQ = true;
1546            toRename->iewInfo[tid].freeLSQEntries =
1547                ldstQueue.numFreeEntries(tid);
1548
1549            wroteToTimeBuffer = true;
1550        }
1551
1552        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1553                tid, toRename->iewInfo[tid].dispatched);
1554    }
1555
1556    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1557            "LSQ has %i free entries.\n",
1558            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1559            ldstQueue.numFreeEntries());
1560
1561    updateStatus();
1562
1563    if (wroteToTimeBuffer) {
1564        DPRINTF(Activity, "Activity this cycle.\n");
1565        cpu->activityThisCycle();
1566    }
1567}
1568
1569template <class Impl>
1570void
1571DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1572{
1573    int thread_number = inst->threadNumber;
1574
1575    //
1576    //  Pick off the software prefetches
1577    //
1578#ifdef TARGET_ALPHA
1579    if (inst->isDataPrefetch())
1580        iewExecutedSwp[thread_number]++;
1581    else
1582        iewIewExecutedcutedInsts++;
1583#else
1584    iewExecutedInsts++;
1585#endif
1586
1587    //
1588    //  Control operations
1589    //
1590    if (inst->isControl())
1591        iewExecutedBranches[thread_number]++;
1592
1593    //
1594    //  Memory operations
1595    //
1596    if (inst->isMemRef()) {
1597        iewExecutedRefs[thread_number]++;
1598
1599        if (inst->isLoad()) {
1600            iewExecLoadInsts[thread_number]++;
1601        }
1602    }
1603}
1604