iew_impl.hh revision 2333
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 311986Sandreas.sandberg@arm.com * All rights reserved. 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411986Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511986Sandreas.sandberg@arm.com * 1611986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911986Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111986Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311986Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411986Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511986Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611986Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711986Sandreas.sandberg@arm.com */ 2811986Sandreas.sandberg@arm.com 2911986Sandreas.sandberg@arm.com// @todo: Fix the instantaneous communication among all the stages within 3011986Sandreas.sandberg@arm.com// iew. There's a clear delay between issue and execute, yet backwards 3111986Sandreas.sandberg@arm.com// communication happens simultaneously. 3211986Sandreas.sandberg@arm.com 3311986Sandreas.sandberg@arm.com#include <queue> 3411986Sandreas.sandberg@arm.com 3511986Sandreas.sandberg@arm.com#include "base/timebuf.hh" 3611986Sandreas.sandberg@arm.com#include "cpu/o3/fu_pool.hh" 3711986Sandreas.sandberg@arm.com#include "cpu/o3/iew.hh" 3811986Sandreas.sandberg@arm.com 3911986Sandreas.sandberg@arm.comusing namespace std; 4011986Sandreas.sandberg@arm.com 4111986Sandreas.sandberg@arm.comtemplate<class Impl> 4211986Sandreas.sandberg@arm.comDefaultIEW<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst, 4311986Sandreas.sandberg@arm.com DefaultIEW<Impl> *_iew) 4411986Sandreas.sandberg@arm.com : Event(&mainEventQueue), inst(_inst), iewStage(_iew) 4511986Sandreas.sandberg@arm.com{ 4611986Sandreas.sandberg@arm.com this->setFlags(Event::AutoDelete); 4711986Sandreas.sandberg@arm.com} 4811986Sandreas.sandberg@arm.com 4911986Sandreas.sandberg@arm.comtemplate<class Impl> 5011986Sandreas.sandberg@arm.comvoid 5111986Sandreas.sandberg@arm.comDefaultIEW<Impl>::LdWritebackEvent::process() 5211986Sandreas.sandberg@arm.com{ 5311986Sandreas.sandberg@arm.com DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum); 5411986Sandreas.sandberg@arm.com DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 5511986Sandreas.sandberg@arm.com 5611986Sandreas.sandberg@arm.com //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 5711986Sandreas.sandberg@arm.com 5811986Sandreas.sandberg@arm.com if (iewStage->isSwitchedOut()) { 5911986Sandreas.sandberg@arm.com inst = NULL; 6011986Sandreas.sandberg@arm.com return; 6111986Sandreas.sandberg@arm.com } else if (inst->isSquashed()) { 6211986Sandreas.sandberg@arm.com iewStage->wakeCPU(); 6311986Sandreas.sandberg@arm.com inst = NULL; 6411986Sandreas.sandberg@arm.com return; 6511986Sandreas.sandberg@arm.com } 6611986Sandreas.sandberg@arm.com 6711986Sandreas.sandberg@arm.com iewStage->wakeCPU(); 6811986Sandreas.sandberg@arm.com 6911986Sandreas.sandberg@arm.com if (!inst->isExecuted()) { 7011986Sandreas.sandberg@arm.com inst->setExecuted(); 7111986Sandreas.sandberg@arm.com 7211986Sandreas.sandberg@arm.com // Complete access to copy data to proper place. 7311986Sandreas.sandberg@arm.com if (inst->isStore()) { 7411986Sandreas.sandberg@arm.com inst->completeAcc(); 7511986Sandreas.sandberg@arm.com } 7611986Sandreas.sandberg@arm.com } 7711986Sandreas.sandberg@arm.com 7811986Sandreas.sandberg@arm.com // Need to insert instruction into queue to commit 7911986Sandreas.sandberg@arm.com iewStage->instToCommit(inst); 8011986Sandreas.sandberg@arm.com 8111986Sandreas.sandberg@arm.com iewStage->activityThisCycle(); 8211986Sandreas.sandberg@arm.com 8311986Sandreas.sandberg@arm.com inst = NULL; 8411986Sandreas.sandberg@arm.com} 8511986Sandreas.sandberg@arm.com 8611986Sandreas.sandberg@arm.comtemplate<class Impl> 8711986Sandreas.sandberg@arm.comconst char * 8811986Sandreas.sandberg@arm.comDefaultIEW<Impl>::LdWritebackEvent::description() 8911986Sandreas.sandberg@arm.com{ 9011986Sandreas.sandberg@arm.com return "Load writeback event"; 9111986Sandreas.sandberg@arm.com} 9211986Sandreas.sandberg@arm.com 9311986Sandreas.sandberg@arm.comtemplate<class Impl> 9411986Sandreas.sandberg@arm.comDefaultIEW<Impl>::DefaultIEW(Params *params) 9511986Sandreas.sandberg@arm.com : // @todo: Make this into a parameter. 9611986Sandreas.sandberg@arm.com issueToExecQueue(5, 5), 9711986Sandreas.sandberg@arm.com instQueue(params), 9811986Sandreas.sandberg@arm.com ldstQueue(params), 9911986Sandreas.sandberg@arm.com fuPool(params->fuPool), 10011986Sandreas.sandberg@arm.com commitToIEWDelay(params->commitToIEWDelay), 10111986Sandreas.sandberg@arm.com renameToIEWDelay(params->renameToIEWDelay), 10211986Sandreas.sandberg@arm.com issueToExecuteDelay(params->issueToExecuteDelay), 10311986Sandreas.sandberg@arm.com issueReadWidth(params->issueWidth), 10411986Sandreas.sandberg@arm.com issueWidth(params->issueWidth), 10511986Sandreas.sandberg@arm.com executeWidth(params->executeWidth), 10611986Sandreas.sandberg@arm.com numThreads(params->numberOfThreads), 10711986Sandreas.sandberg@arm.com switchedOut(false) 10811986Sandreas.sandberg@arm.com{ 10911986Sandreas.sandberg@arm.com _status = Active; 11011986Sandreas.sandberg@arm.com exeStatus = Running; 11111986Sandreas.sandberg@arm.com wbStatus = Idle; 11211986Sandreas.sandberg@arm.com 11311986Sandreas.sandberg@arm.com // Setup wire to read instructions coming from issue. 11411986Sandreas.sandberg@arm.com fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 11511986Sandreas.sandberg@arm.com 11611986Sandreas.sandberg@arm.com // Instruction queue needs the queue between issue and execute. 11711986Sandreas.sandberg@arm.com instQueue.setIssueToExecuteQueue(&issueToExecQueue); 118 119 instQueue.setIEW(this); 120 ldstQueue.setIEW(this); 121 122 for (int i=0; i < numThreads; i++) { 123 dispatchStatus[i] = Running; 124 stalls[i].commit = false; 125 fetchRedirect[i] = false; 126 } 127 128 updateLSQNextCycle = false; 129 130 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 131} 132 133template <class Impl> 134std::string 135DefaultIEW<Impl>::name() const 136{ 137 return cpu->name() + ".iew"; 138} 139 140template <class Impl> 141void 142DefaultIEW<Impl>::regStats() 143{ 144 using namespace Stats; 145 146 instQueue.regStats(); 147 148 iewIdleCycles 149 .name(name() + ".iewIdleCycles") 150 .desc("Number of cycles IEW is idle"); 151 152 iewSquashCycles 153 .name(name() + ".iewSquashCycles") 154 .desc("Number of cycles IEW is squashing"); 155 156 iewBlockCycles 157 .name(name() + ".iewBlockCycles") 158 .desc("Number of cycles IEW is blocking"); 159 160 iewUnblockCycles 161 .name(name() + ".iewUnblockCycles") 162 .desc("Number of cycles IEW is unblocking"); 163 164 iewDispatchedInsts 165 .name(name() + ".iewDispatchedInsts") 166 .desc("Number of instructions dispatched to IQ"); 167 168 iewDispSquashedInsts 169 .name(name() + ".iewDispSquashedInsts") 170 .desc("Number of squashed instructions skipped by dispatch"); 171 172 iewDispLoadInsts 173 .name(name() + ".iewDispLoadInsts") 174 .desc("Number of dispatched load instructions"); 175 176 iewDispStoreInsts 177 .name(name() + ".iewDispStoreInsts") 178 .desc("Number of dispatched store instructions"); 179 180 iewDispNonSpecInsts 181 .name(name() + ".iewDispNonSpecInsts") 182 .desc("Number of dispatched non-speculative instructions"); 183 184 iewIQFullEvents 185 .name(name() + ".iewIQFullEvents") 186 .desc("Number of times the IQ has become full, causing a stall"); 187 188 iewLSQFullEvents 189 .name(name() + ".iewLSQFullEvents") 190 .desc("Number of times the LSQ has become full, causing a stall"); 191 192 iewExecutedInsts 193 .name(name() + ".iewExecutedInsts") 194 .desc("Number of executed instructions"); 195 196 iewExecLoadInsts 197 .init(cpu->number_of_threads) 198 .name(name() + ".iewExecLoadInsts") 199 .desc("Number of load instructions executed") 200 .flags(total); 201 202 iewExecSquashedInsts 203 .name(name() + ".iewExecSquashedInsts") 204 .desc("Number of squashed instructions skipped in execute"); 205 206 memOrderViolationEvents 207 .name(name() + ".memOrderViolationEvents") 208 .desc("Number of memory order violations"); 209 210 predictedTakenIncorrect 211 .name(name() + ".predictedTakenIncorrect") 212 .desc("Number of branches that were predicted taken incorrectly"); 213 214 predictedNotTakenIncorrect 215 .name(name() + ".predictedNotTakenIncorrect") 216 .desc("Number of branches that were predicted not taken incorrectly"); 217 218 branchMispredicts 219 .name(name() + ".branchMispredicts") 220 .desc("Number of branch mispredicts detected at execute"); 221 222 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 223 224 exeSwp 225 .init(cpu->number_of_threads) 226 .name(name() + ".EXEC:swp") 227 .desc("number of swp insts executed") 228 .flags(total) 229 ; 230 231 exeNop 232 .init(cpu->number_of_threads) 233 .name(name() + ".EXEC:nop") 234 .desc("number of nop insts executed") 235 .flags(total) 236 ; 237 238 exeRefs 239 .init(cpu->number_of_threads) 240 .name(name() + ".EXEC:refs") 241 .desc("number of memory reference insts executed") 242 .flags(total) 243 ; 244 245 exeBranches 246 .init(cpu->number_of_threads) 247 .name(name() + ".EXEC:branches") 248 .desc("Number of branches executed") 249 .flags(total) 250 ; 251 252 issueRate 253 .name(name() + ".EXEC:rate") 254 .desc("Inst execution rate") 255 .flags(total) 256 ; 257 issueRate = iewExecutedInsts / cpu->numCycles; 258 259 iewExecStoreInsts 260 .name(name() + ".EXEC:stores") 261 .desc("Number of stores executed") 262 .flags(total) 263 ; 264 iewExecStoreInsts = exeRefs - iewExecLoadInsts; 265/* 266 for (int i=0; i<Num_OpClasses; ++i) { 267 stringstream subname; 268 subname << opClassStrings[i] << "_delay"; 269 issue_delay_dist.subname(i, subname.str()); 270 } 271*/ 272 // 273 // Other stats 274 // 275 276 iewInstsToCommit 277 .init(cpu->number_of_threads) 278 .name(name() + ".WB:sent") 279 .desc("cumulative count of insts sent to commit") 280 .flags(total) 281 ; 282 283 writebackCount 284 .init(cpu->number_of_threads) 285 .name(name() + ".WB:count") 286 .desc("cumulative count of insts written-back") 287 .flags(total) 288 ; 289 290 producerInst 291 .init(cpu->number_of_threads) 292 .name(name() + ".WB:producers") 293 .desc("num instructions producing a value") 294 .flags(total) 295 ; 296 297 consumerInst 298 .init(cpu->number_of_threads) 299 .name(name() + ".WB:consumers") 300 .desc("num instructions consuming a value") 301 .flags(total) 302 ; 303 304 wbPenalized 305 .init(cpu->number_of_threads) 306 .name(name() + ".WB:penalized") 307 .desc("number of instrctions required to write to 'other' IQ") 308 .flags(total) 309 ; 310 311 wbPenalizedRate 312 .name(name() + ".WB:penalized_rate") 313 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 314 .flags(total) 315 ; 316 317 wbPenalizedRate = wbPenalized / writebackCount; 318 319 wbFanout 320 .name(name() + ".WB:fanout") 321 .desc("average fanout of values written-back") 322 .flags(total) 323 ; 324 325 wbFanout = producerInst / consumerInst; 326 327 wbRate 328 .name(name() + ".WB:rate") 329 .desc("insts written-back per cycle") 330 .flags(total) 331 ; 332 wbRate = writebackCount / cpu->numCycles; 333} 334 335template<class Impl> 336void 337DefaultIEW<Impl>::initStage() 338{ 339 for (int tid=0; tid < numThreads; tid++) { 340 toRename->iewInfo[tid].usedIQ = true; 341 toRename->iewInfo[tid].freeIQEntries = 342 instQueue.numFreeEntries(tid); 343 344 toRename->iewInfo[tid].usedLSQ = true; 345 toRename->iewInfo[tid].freeLSQEntries = 346 ldstQueue.numFreeEntries(tid); 347 } 348} 349 350template<class Impl> 351void 352DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) 353{ 354 DPRINTF(IEW, "Setting CPU pointer.\n"); 355 cpu = cpu_ptr; 356 357 instQueue.setCPU(cpu_ptr); 358 ldstQueue.setCPU(cpu_ptr); 359 360 cpu->activateStage(FullCPU::IEWIdx); 361} 362 363template<class Impl> 364void 365DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 366{ 367 DPRINTF(IEW, "Setting time buffer pointer.\n"); 368 timeBuffer = tb_ptr; 369 370 // Setup wire to read information from time buffer, from commit. 371 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 372 373 // Setup wire to write information back to previous stages. 374 toRename = timeBuffer->getWire(0); 375 376 toFetch = timeBuffer->getWire(0); 377 378 // Instruction queue also needs main time buffer. 379 instQueue.setTimeBuffer(tb_ptr); 380} 381 382template<class Impl> 383void 384DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 385{ 386 DPRINTF(IEW, "Setting rename queue pointer.\n"); 387 renameQueue = rq_ptr; 388 389 // Setup wire to read information from rename queue. 390 fromRename = renameQueue->getWire(-renameToIEWDelay); 391} 392 393template<class Impl> 394void 395DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 396{ 397 DPRINTF(IEW, "Setting IEW queue pointer.\n"); 398 iewQueue = iq_ptr; 399 400 // Setup wire to write instructions to commit. 401 toCommit = iewQueue->getWire(0); 402} 403 404template<class Impl> 405void 406DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 407{ 408 DPRINTF(IEW, "Setting active threads list pointer.\n"); 409 activeThreads = at_ptr; 410 411 ldstQueue.setActiveThreads(at_ptr); 412 instQueue.setActiveThreads(at_ptr); 413} 414 415template<class Impl> 416void 417DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 418{ 419 DPRINTF(IEW, "Setting scoreboard pointer.\n"); 420 scoreboard = sb_ptr; 421} 422 423#if 0 424template<class Impl> 425void 426DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr) 427{ 428 ldstQueue.setPageTable(pt_ptr); 429} 430#endif 431 432template <class Impl> 433void 434DefaultIEW<Impl>::switchOut() 435{ 436 cpu->signalSwitched(); 437} 438 439template <class Impl> 440void 441DefaultIEW<Impl>::doSwitchOut() 442{ 443 switchedOut = true; 444 445 instQueue.switchOut(); 446 ldstQueue.switchOut(); 447 fuPool->switchOut(); 448 449 for (int i = 0; i < numThreads; i++) { 450 while (!insts[i].empty()) 451 insts[i].pop(); 452 while (!skidBuffer[i].empty()) 453 skidBuffer[i].pop(); 454 } 455} 456 457template <class Impl> 458void 459DefaultIEW<Impl>::takeOverFrom() 460{ 461 _status = Active; 462 exeStatus = Running; 463 wbStatus = Idle; 464 switchedOut = false; 465 466 instQueue.takeOverFrom(); 467 ldstQueue.takeOverFrom(); 468 fuPool->takeOverFrom(); 469 470 initStage(); 471 cpu->activityThisCycle(); 472 473 for (int i=0; i < numThreads; i++) { 474 dispatchStatus[i] = Running; 475 stalls[i].commit = false; 476 fetchRedirect[i] = false; 477 } 478 479 updateLSQNextCycle = false; 480 481 // @todo: Fix hardcoded number 482 for (int i = 0; i < 6; ++i) { 483 issueToExecQueue.advance(); 484 } 485} 486 487template<class Impl> 488void 489DefaultIEW<Impl>::squash(unsigned tid) 490{ 491 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 492 tid); 493 494 // Tell the IQ to start squashing. 495 instQueue.squash(tid); 496 497 // Tell the LDSTQ to start squashing. 498 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 499 500 updatedQueues = true; 501 502 // Clear the skid buffer in case it has any data in it. 503 while (!skidBuffer[tid].empty()) { 504 505 if (skidBuffer[tid].front()->isLoad() || 506 skidBuffer[tid].front()->isStore() ) { 507 toRename->iewInfo[tid].dispatchedToLSQ++; 508 } 509 510 toRename->iewInfo[tid].dispatched++; 511 512 skidBuffer[tid].pop(); 513 } 514 515 while (!insts[tid].empty()) { 516 if (insts[tid].front()->isLoad() || 517 insts[tid].front()->isStore() ) { 518 toRename->iewInfo[tid].dispatchedToLSQ++; 519 } 520 521 toRename->iewInfo[tid].dispatched++; 522 523 insts[tid].pop(); 524 } 525} 526 527template<class Impl> 528void 529DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 530{ 531 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 532 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 533 534 toCommit->squash[tid] = true; 535 toCommit->squashedSeqNum[tid] = inst->seqNum; 536 toCommit->mispredPC[tid] = inst->readPC(); 537 toCommit->nextPC[tid] = inst->readNextPC(); 538 toCommit->branchMispredict[tid] = true; 539 toCommit->branchTaken[tid] = inst->readNextPC() != 540 (inst->readPC() + sizeof(TheISA::MachInst)); 541 542 toCommit->includeSquashInst[tid] = false; 543 544 wroteToTimeBuffer = true; 545} 546 547template<class Impl> 548void 549DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 550{ 551 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 552 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 553 554 toCommit->squash[tid] = true; 555 toCommit->squashedSeqNum[tid] = inst->seqNum; 556 toCommit->nextPC[tid] = inst->readNextPC(); 557 558 toCommit->includeSquashInst[tid] = false; 559 560 wroteToTimeBuffer = true; 561} 562 563template<class Impl> 564void 565DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 566{ 567 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 568 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 569 570 toCommit->squash[tid] = true; 571 toCommit->squashedSeqNum[tid] = inst->seqNum; 572 toCommit->nextPC[tid] = inst->readPC(); 573 574 toCommit->includeSquashInst[tid] = true; 575 576 ldstQueue.setLoadBlockedHandled(tid); 577 578 wroteToTimeBuffer = true; 579} 580 581template<class Impl> 582void 583DefaultIEW<Impl>::block(unsigned tid) 584{ 585 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 586 587 if (dispatchStatus[tid] != Blocked && 588 dispatchStatus[tid] != Unblocking) { 589 toRename->iewBlock[tid] = true; 590 wroteToTimeBuffer = true; 591 } 592 593 // Add the current inputs to the skid buffer so they can be 594 // reprocessed when this stage unblocks. 595 skidInsert(tid); 596 597 dispatchStatus[tid] = Blocked; 598} 599 600template<class Impl> 601void 602DefaultIEW<Impl>::unblock(unsigned tid) 603{ 604 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 605 "buffer %u.\n",tid, tid); 606 607 // If the skid bufffer is empty, signal back to previous stages to unblock. 608 // Also switch status to running. 609 if (skidBuffer[tid].empty()) { 610 toRename->iewUnblock[tid] = true; 611 wroteToTimeBuffer = true; 612 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 613 dispatchStatus[tid] = Running; 614 } 615} 616 617template<class Impl> 618void 619DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 620{ 621 instQueue.wakeDependents(inst); 622} 623 624template<class Impl> 625void 626DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 627{ 628 instQueue.rescheduleMemInst(inst); 629} 630 631template<class Impl> 632void 633DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 634{ 635 instQueue.replayMemInst(inst); 636} 637 638template<class Impl> 639void 640DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 641{ 642 // First check the time slot that this instruction will write 643 // to. If there are free write ports at the time, then go ahead 644 // and write the instruction to that time. If there are not, 645 // keep looking back to see where's the first time there's a 646 // free slot. 647 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 648 ++wbNumInst; 649 if (wbNumInst == issueWidth) { 650 ++wbCycle; 651 wbNumInst = 0; 652 } 653 654 assert(wbCycle < 5); 655 } 656 657 // Add finished instruction to queue to commit. 658 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 659 (*iewQueue)[wbCycle].size++; 660} 661 662template <class Impl> 663unsigned 664DefaultIEW<Impl>::validInstsFromRename() 665{ 666 unsigned inst_count = 0; 667 668 for (int i=0; i<fromRename->size; i++) { 669 if (!fromRename->insts[i]->squashed) 670 inst_count++; 671 } 672 673 return inst_count; 674} 675 676template<class Impl> 677void 678DefaultIEW<Impl>::skidInsert(unsigned tid) 679{ 680 DynInstPtr inst = NULL; 681 682 while (!insts[tid].empty()) { 683 inst = insts[tid].front(); 684 685 insts[tid].pop(); 686 687 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 688 "dispatch skidBuffer %i\n",tid, inst->seqNum, 689 inst->readPC(),tid); 690 691 skidBuffer[tid].push(inst); 692 } 693 694 assert(skidBuffer[tid].size() <= skidBufferMax && 695 "Skidbuffer Exceeded Max Size"); 696} 697 698template<class Impl> 699int 700DefaultIEW<Impl>::skidCount() 701{ 702 int max=0; 703 704 list<unsigned>::iterator threads = (*activeThreads).begin(); 705 706 while (threads != (*activeThreads).end()) { 707 unsigned thread_count = skidBuffer[*threads++].size(); 708 if (max < thread_count) 709 max = thread_count; 710 } 711 712 return max; 713} 714 715template<class Impl> 716bool 717DefaultIEW<Impl>::skidsEmpty() 718{ 719 list<unsigned>::iterator threads = (*activeThreads).begin(); 720 721 while (threads != (*activeThreads).end()) { 722 if (!skidBuffer[*threads++].empty()) 723 return false; 724 } 725 726 return true; 727} 728 729template <class Impl> 730void 731DefaultIEW<Impl>::updateStatus() 732{ 733 bool any_unblocking = false; 734 735 list<unsigned>::iterator threads = (*activeThreads).begin(); 736 737 threads = (*activeThreads).begin(); 738 739 while (threads != (*activeThreads).end()) { 740 unsigned tid = *threads++; 741 742 if (dispatchStatus[tid] == Unblocking) { 743 any_unblocking = true; 744 break; 745 } 746 } 747 748 // If there are no ready instructions waiting to be scheduled by the IQ, 749 // and there's no stores waiting to write back, and dispatch is not 750 // unblocking, then there is no internal activity for the IEW stage. 751 if (_status == Active && !instQueue.hasReadyInsts() && 752 !ldstQueue.willWB() && !any_unblocking) { 753 DPRINTF(IEW, "IEW switching to idle\n"); 754 755 deactivateStage(); 756 757 _status = Inactive; 758 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 759 ldstQueue.willWB() || 760 any_unblocking)) { 761 // Otherwise there is internal activity. Set to active. 762 DPRINTF(IEW, "IEW switching to active\n"); 763 764 activateStage(); 765 766 _status = Active; 767 } 768} 769 770template <class Impl> 771void 772DefaultIEW<Impl>::resetEntries() 773{ 774 instQueue.resetEntries(); 775 ldstQueue.resetEntries(); 776} 777 778template <class Impl> 779void 780DefaultIEW<Impl>::readStallSignals(unsigned tid) 781{ 782 if (fromCommit->commitBlock[tid]) { 783 stalls[tid].commit = true; 784 } 785 786 if (fromCommit->commitUnblock[tid]) { 787 assert(stalls[tid].commit); 788 stalls[tid].commit = false; 789 } 790} 791 792template <class Impl> 793bool 794DefaultIEW<Impl>::checkStall(unsigned tid) 795{ 796 bool ret_val(false); 797 798 if (stalls[tid].commit) { 799 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 800 ret_val = true; 801 } else if (instQueue.isFull(tid)) { 802 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 803 ret_val = true; 804 } else if (ldstQueue.isFull(tid)) { 805 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 806 807 if (ldstQueue.numLoads(tid) > 0 ) { 808 809 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 810 tid,ldstQueue.getLoadHeadSeqNum(tid)); 811 } 812 813 if (ldstQueue.numStores(tid) > 0) { 814 815 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 816 tid,ldstQueue.getStoreHeadSeqNum(tid)); 817 } 818 819 ret_val = true; 820 } else if (ldstQueue.isStalled(tid)) { 821 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 822 ret_val = true; 823 } 824 825 return ret_val; 826} 827 828template <class Impl> 829void 830DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 831{ 832 // Check if there's a squash signal, squash if there is 833 // Check stall signals, block if there is. 834 // If status was Blocked 835 // if so then go to unblocking 836 // If status was Squashing 837 // check if squashing is not high. Switch to running this cycle. 838 839 readStallSignals(tid); 840 841 if (fromCommit->commitInfo[tid].squash) { 842 squash(tid); 843 844 if (dispatchStatus[tid] == Blocked || 845 dispatchStatus[tid] == Unblocking) { 846 toRename->iewUnblock[tid] = true; 847 wroteToTimeBuffer = true; 848 } 849 850 dispatchStatus[tid] = Squashing; 851 852 fetchRedirect[tid] = false; 853 return; 854 } 855 856 if (fromCommit->commitInfo[tid].robSquashing) { 857 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n"); 858 859 dispatchStatus[tid] = Squashing; 860 861 return; 862 } 863 864 if (checkStall(tid)) { 865 block(tid); 866 dispatchStatus[tid] = Blocked; 867 return; 868 } 869 870 if (dispatchStatus[tid] == Blocked) { 871 // Status from previous cycle was blocked, but there are no more stall 872 // conditions. Switch over to unblocking. 873 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 874 tid); 875 876 dispatchStatus[tid] = Unblocking; 877 878 unblock(tid); 879 880 return; 881 } 882 883 if (dispatchStatus[tid] == Squashing) { 884 // Switch status to running if rename isn't being told to block or 885 // squash this cycle. 886 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 887 tid); 888 889 dispatchStatus[tid] = Running; 890 891 return; 892 } 893} 894 895template <class Impl> 896void 897DefaultIEW<Impl>::sortInsts() 898{ 899 int insts_from_rename = fromRename->size; 900#ifdef DEBUG 901 for (int i = 0; i < numThreads; i++) 902 assert(insts[i].empty()); 903#endif 904 for (int i = 0; i < insts_from_rename; ++i) { 905 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 906 } 907} 908 909template <class Impl> 910void 911DefaultIEW<Impl>::wakeCPU() 912{ 913 cpu->wakeCPU(); 914} 915 916template <class Impl> 917void 918DefaultIEW<Impl>::activityThisCycle() 919{ 920 DPRINTF(Activity, "Activity this cycle.\n"); 921 cpu->activityThisCycle(); 922} 923 924template <class Impl> 925inline void 926DefaultIEW<Impl>::activateStage() 927{ 928 DPRINTF(Activity, "Activating stage.\n"); 929 cpu->activateStage(FullCPU::IEWIdx); 930} 931 932template <class Impl> 933inline void 934DefaultIEW<Impl>::deactivateStage() 935{ 936 DPRINTF(Activity, "Deactivating stage.\n"); 937 cpu->deactivateStage(FullCPU::IEWIdx); 938} 939 940template<class Impl> 941void 942DefaultIEW<Impl>::dispatch(unsigned tid) 943{ 944 // If status is Running or idle, 945 // call dispatchInsts() 946 // If status is Unblocking, 947 // buffer any instructions coming from rename 948 // continue trying to empty skid buffer 949 // check if stall conditions have passed 950 951 if (dispatchStatus[tid] == Blocked) { 952 ++iewBlockCycles; 953 954 } else if (dispatchStatus[tid] == Squashing) { 955 ++iewSquashCycles; 956 } 957 958 // Dispatch should try to dispatch as many instructions as its bandwidth 959 // will allow, as long as it is not currently blocked. 960 if (dispatchStatus[tid] == Running || 961 dispatchStatus[tid] == Idle) { 962 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 963 "dispatch.\n", tid); 964 965 dispatchInsts(tid); 966 } else if (dispatchStatus[tid] == Unblocking) { 967 // Make sure that the skid buffer has something in it if the 968 // status is unblocking. 969 assert(!skidsEmpty()); 970 971 // If the status was unblocking, then instructions from the skid 972 // buffer were used. Remove those instructions and handle 973 // the rest of unblocking. 974 dispatchInsts(tid); 975 976 ++iewUnblockCycles; 977 978 if (validInstsFromRename() && dispatchedAllInsts) { 979 // Add the current inputs to the skid buffer so they can be 980 // reprocessed when this stage unblocks. 981 skidInsert(tid); 982 } 983 984 unblock(tid); 985 } 986} 987 988template <class Impl> 989void 990DefaultIEW<Impl>::dispatchInsts(unsigned tid) 991{ 992 dispatchedAllInsts = true; 993 994 // Obtain instructions from skid buffer if unblocking, or queue from rename 995 // otherwise. 996 std::queue<DynInstPtr> &insts_to_dispatch = 997 dispatchStatus[tid] == Unblocking ? 998 skidBuffer[tid] : insts[tid]; 999 1000 int insts_to_add = insts_to_dispatch.size(); 1001 1002 DynInstPtr inst; 1003 bool add_to_iq = false; 1004 int dis_num_inst = 0; 1005 1006 // Loop through the instructions, putting them in the instruction 1007 // queue. 1008 for ( ; dis_num_inst < insts_to_add && 1009 dis_num_inst < issueReadWidth; 1010 ++dis_num_inst) 1011 { 1012 inst = insts_to_dispatch.front(); 1013 1014 if (dispatchStatus[tid] == Unblocking) { 1015 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 1016 "buffer\n", tid); 1017 } 1018 1019 // Make sure there's a valid instruction there. 1020 assert(inst); 1021 1022 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 1023 "IQ.\n", 1024 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 1025 1026 // Be sure to mark these instructions as ready so that the 1027 // commit stage can go ahead and execute them, and mark 1028 // them as issued so the IQ doesn't reprocess them. 1029 1030 // Check for squashed instructions. 1031 if (inst->isSquashed()) { 1032 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1033 "not adding to IQ.\n", tid); 1034 1035 ++iewDispSquashedInsts; 1036 1037 insts_to_dispatch.pop(); 1038 1039 //Tell Rename That An Instruction has been processed 1040 if (inst->isLoad() || inst->isStore()) { 1041 toRename->iewInfo[tid].dispatchedToLSQ++; 1042 } 1043 toRename->iewInfo[tid].dispatched++; 1044 1045 continue; 1046 } 1047 1048 // Check for full conditions. 1049 if (instQueue.isFull(tid)) { 1050 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1051 1052 // Call function to start blocking. 1053 block(tid); 1054 1055 // Set unblock to false. Special case where we are using 1056 // skidbuffer (unblocking) instructions but then we still 1057 // get full in the IQ. 1058 toRename->iewUnblock[tid] = false; 1059 1060 dispatchedAllInsts = false; 1061 1062 ++iewIQFullEvents; 1063 break; 1064 } else if (ldstQueue.isFull(tid)) { 1065 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1066 1067 // Call function to start blocking. 1068 block(tid); 1069 1070 // Set unblock to false. Special case where we are using 1071 // skidbuffer (unblocking) instructions but then we still 1072 // get full in the IQ. 1073 toRename->iewUnblock[tid] = false; 1074 1075 dispatchedAllInsts = false; 1076 1077 ++iewLSQFullEvents; 1078 break; 1079 } 1080 1081 // Otherwise issue the instruction just fine. 1082 if (inst->isLoad()) { 1083 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1084 "encountered, adding to LSQ.\n", tid); 1085 1086 // Reserve a spot in the load store queue for this 1087 // memory access. 1088 ldstQueue.insertLoad(inst); 1089 1090 ++iewDispLoadInsts; 1091 1092 add_to_iq = true; 1093 1094 toRename->iewInfo[tid].dispatchedToLSQ++; 1095 } else if (inst->isStore()) { 1096 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1097 "encountered, adding to LSQ.\n", tid); 1098 1099 ldstQueue.insertStore(inst); 1100 1101 ++iewDispStoreInsts; 1102 1103 if (inst->isNonSpeculative()) { 1104 // Non-speculative stores (namely store conditionals) 1105 // need to be set as "canCommit()" so that commit can 1106 // process them when they reach the head of commit. 1107 inst->setCanCommit(); 1108 instQueue.insertNonSpec(inst); 1109 add_to_iq = false; 1110 1111 ++iewDispNonSpecInsts; 1112 } else { 1113 add_to_iq = true; 1114 } 1115 1116 toRename->iewInfo[tid].dispatchedToLSQ++; 1117#if FULL_SYSTEM 1118 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1119 // Same as non-speculative stores. 1120 inst->setCanCommit(); 1121 instQueue.insertBarrier(inst); 1122 add_to_iq = false; 1123#endif 1124 } else if (inst->isNonSpeculative()) { 1125 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1126 "encountered, skipping.\n", tid); 1127 1128 // Same as non-speculative stores. 1129 inst->setCanCommit(); 1130 1131 // Specifically insert it as nonspeculative. 1132 instQueue.insertNonSpec(inst); 1133 1134 ++iewDispNonSpecInsts; 1135 1136 add_to_iq = false; 1137 } else if (inst->isNop()) { 1138 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1139 "skipping.\n", tid); 1140 1141 inst->setIssued(); 1142 inst->setExecuted(); 1143 inst->setCanCommit(); 1144 1145 instQueue.recordProducer(inst); 1146 1147 exeNop[tid]++; 1148 1149 add_to_iq = false; 1150 } else if (inst->isExecuted()) { 1151 assert(0 && "Instruction shouldn't be executed.\n"); 1152 DPRINTF(IEW, "Issue: Executed branch encountered, " 1153 "skipping.\n"); 1154 1155 inst->setIssued(); 1156 inst->setCanCommit(); 1157 1158 instQueue.recordProducer(inst); 1159 1160 add_to_iq = false; 1161 } else { 1162 add_to_iq = true; 1163 } 1164 1165 // If the instruction queue is not full, then add the 1166 // instruction. 1167 if (add_to_iq) { 1168 instQueue.insert(inst); 1169 } 1170 1171 insts_to_dispatch.pop(); 1172 1173 toRename->iewInfo[tid].dispatched++; 1174 1175 ++iewDispatchedInsts; 1176 } 1177 1178 if (!insts_to_dispatch.empty()) { 1179 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 1180 block(tid); 1181 toRename->iewUnblock[tid] = false; 1182 } 1183 1184 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1185 dispatchStatus[tid] = Running; 1186 1187 updatedQueues = true; 1188 } 1189 1190 dis_num_inst = 0; 1191} 1192 1193template <class Impl> 1194void 1195DefaultIEW<Impl>::printAvailableInsts() 1196{ 1197 int inst = 0; 1198 1199 cout << "Available Instructions: "; 1200 1201 while (fromIssue->insts[inst]) { 1202 1203 if (inst%3==0) cout << "\n\t"; 1204 1205 cout << "PC: " << fromIssue->insts[inst]->readPC() 1206 << " TN: " << fromIssue->insts[inst]->threadNumber 1207 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1208 1209 inst++; 1210 1211 } 1212 1213 cout << "\n"; 1214} 1215 1216template <class Impl> 1217void 1218DefaultIEW<Impl>::executeInsts() 1219{ 1220 wbNumInst = 0; 1221 wbCycle = 0; 1222 1223 list<unsigned>::iterator threads = (*activeThreads).begin(); 1224 1225 while (threads != (*activeThreads).end()) { 1226 unsigned tid = *threads++; 1227 fetchRedirect[tid] = false; 1228 } 1229 1230#if 0 1231 printAvailableInsts(); 1232#endif 1233 1234 // Execute/writeback any instructions that are available. 1235 int insts_to_execute = fromIssue->size; 1236 int inst_num = 0; 1237 for (; inst_num < insts_to_execute; 1238 ++inst_num) { 1239 1240 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1241 1242 DynInstPtr inst = instQueue.getInstToExecute(); 1243 1244 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1245 inst->readPC(), inst->threadNumber,inst->seqNum); 1246 1247 // Check if the instruction is squashed; if so then skip it 1248 if (inst->isSquashed()) { 1249 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1250 1251 // Consider this instruction executed so that commit can go 1252 // ahead and retire the instruction. 1253 inst->setExecuted(); 1254 1255 // Not sure if I should set this here or just let commit try to 1256 // commit any squashed instructions. I like the latter a bit more. 1257 inst->setCanCommit(); 1258 1259 ++iewExecSquashedInsts; 1260 1261 continue; 1262 } 1263 1264 Fault fault = NoFault; 1265 1266 // Execute instruction. 1267 // Note that if the instruction faults, it will be handled 1268 // at the commit stage. 1269 if (inst->isMemRef() && 1270 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1271 DPRINTF(IEW, "Execute: Calculating address for memory " 1272 "reference.\n"); 1273 1274 // Tell the LDSTQ to execute this instruction (if it is a load). 1275 if (inst->isLoad()) { 1276 // Loads will mark themselves as executed, and their writeback 1277 // event adds the instruction to the queue to commit 1278 fault = ldstQueue.executeLoad(inst); 1279 } else if (inst->isStore()) { 1280 ldstQueue.executeStore(inst); 1281 1282 // If the store had a fault then it may not have a mem req 1283 if (inst->req && !(inst->req->flags & LOCKED)) { 1284 inst->setExecuted(); 1285 1286 instToCommit(inst); 1287 } 1288 1289 // Store conditionals will mark themselves as 1290 // executed, and their writeback event will add the 1291 // instruction to the queue to commit. 1292 } else { 1293 panic("Unexpected memory type!\n"); 1294 } 1295 1296 } else { 1297 inst->execute(); 1298 1299 inst->setExecuted(); 1300 1301 instToCommit(inst); 1302 } 1303 1304 updateExeInstStats(inst); 1305 1306 // Check if branch prediction was correct, if not then we need 1307 // to tell commit to squash in flight instructions. Only 1308 // handle this if there hasn't already been something that 1309 // redirects fetch in this group of instructions. 1310 1311 // This probably needs to prioritize the redirects if a different 1312 // scheduler is used. Currently the scheduler schedules the oldest 1313 // instruction first, so the branch resolution order will be correct. 1314 unsigned tid = inst->threadNumber; 1315 1316 if (!fetchRedirect[tid]) { 1317 1318 if (inst->mispredicted()) { 1319 fetchRedirect[tid] = true; 1320 1321 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1322 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1323 inst->nextPC); 1324 1325 // If incorrect, then signal the ROB that it must be squashed. 1326 squashDueToBranch(inst, tid); 1327 1328 if (inst->predTaken()) { 1329 predictedTakenIncorrect++; 1330 } else { 1331 predictedNotTakenIncorrect++; 1332 } 1333 } else if (ldstQueue.violation(tid)) { 1334 fetchRedirect[tid] = true; 1335 1336 // If there was an ordering violation, then get the 1337 // DynInst that caused the violation. Note that this 1338 // clears the violation signal. 1339 DynInstPtr violator; 1340 violator = ldstQueue.getMemDepViolator(tid); 1341 1342 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1343 "%#x, inst PC: %#x. Addr is: %#x.\n", 1344 violator->readPC(), inst->readPC(), inst->physEffAddr); 1345 1346 // Tell the instruction queue that a violation has occured. 1347 instQueue.violation(inst, violator); 1348 1349 // Squash. 1350 squashDueToMemOrder(inst,tid); 1351 1352 ++memOrderViolationEvents; 1353 } else if (ldstQueue.loadBlocked(tid) && 1354 !ldstQueue.isLoadBlockedHandled(tid)) { 1355 fetchRedirect[tid] = true; 1356 1357 DPRINTF(IEW, "Load operation couldn't execute because the " 1358 "memory system is blocked. PC: %#x [sn:%lli]\n", 1359 inst->readPC(), inst->seqNum); 1360 1361 squashDueToMemBlocked(inst, tid); 1362 } 1363 } 1364 } 1365 1366 if (inst_num) { 1367 if (exeStatus == Idle) { 1368 exeStatus = Running; 1369 } 1370 1371 updatedQueues = true; 1372 1373 cpu->activityThisCycle(); 1374 } 1375 1376 // Need to reset this in case a writeback event needs to write into the 1377 // iew queue. That way the writeback event will write into the correct 1378 // spot in the queue. 1379 wbNumInst = 0; 1380} 1381 1382template <class Impl> 1383void 1384DefaultIEW<Impl>::writebackInsts() 1385{ 1386 // Loop through the head of the time buffer and wake any 1387 // dependents. These instructions are about to write back. Also 1388 // mark scoreboard that this instruction is finally complete. 1389 // Either have IEW have direct access to scoreboard, or have this 1390 // as part of backwards communication. 1391 for (int inst_num = 0; inst_num < issueWidth && 1392 toCommit->insts[inst_num]; inst_num++) { 1393 DynInstPtr inst = toCommit->insts[inst_num]; 1394 int tid = inst->threadNumber; 1395 1396 DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n", 1397 inst->readPC()); 1398 1399 iewInstsToCommit[tid]++; 1400 1401 // Some instructions will be sent to commit without having 1402 // executed because they need commit to handle them. 1403 // E.g. Uncached loads have not actually executed when they 1404 // are first sent to commit. Instead commit must tell the LSQ 1405 // when it's ready to execute the uncached load. 1406 if (!inst->isSquashed() && inst->isExecuted()) { 1407 int dependents = instQueue.wakeDependents(inst); 1408 1409 for (int i = 0; i < inst->numDestRegs(); i++) { 1410 //mark as Ready 1411 DPRINTF(IEW,"Setting Destination Register %i\n", 1412 inst->renamedDestRegIdx(i)); 1413 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1414 } 1415 1416 producerInst[tid]++; 1417 consumerInst[tid]+= dependents; 1418 writebackCount[tid]++; 1419 } 1420 } 1421} 1422 1423template<class Impl> 1424void 1425DefaultIEW<Impl>::tick() 1426{ 1427 wbNumInst = 0; 1428 wbCycle = 0; 1429 1430 wroteToTimeBuffer = false; 1431 updatedQueues = false; 1432 1433 sortInsts(); 1434 1435 // Free function units marked as being freed this cycle. 1436 fuPool->processFreeUnits(); 1437 1438 list<unsigned>::iterator threads = (*activeThreads).begin(); 1439 1440 // Check stall and squash signals, dispatch any instructions. 1441 while (threads != (*activeThreads).end()) { 1442 unsigned tid = *threads++; 1443 1444 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1445 1446 checkSignalsAndUpdate(tid); 1447 dispatch(tid); 1448 } 1449 1450 if (exeStatus != Squashing) { 1451 executeInsts(); 1452 1453 writebackInsts(); 1454 1455 // Have the instruction queue try to schedule any ready instructions. 1456 // (In actuality, this scheduling is for instructions that will 1457 // be executed next cycle.) 1458 instQueue.scheduleReadyInsts(); 1459 1460 // Also should advance its own time buffers if the stage ran. 1461 // Not the best place for it, but this works (hopefully). 1462 issueToExecQueue.advance(); 1463 } 1464 1465 bool broadcast_free_entries = false; 1466 1467 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1468 exeStatus = Idle; 1469 updateLSQNextCycle = false; 1470 1471 broadcast_free_entries = true; 1472 } 1473 1474 // Writeback any stores using any leftover bandwidth. 1475 ldstQueue.writebackStores(); 1476 1477 // Check the committed load/store signals to see if there's a load 1478 // or store to commit. Also check if it's being told to execute a 1479 // nonspeculative instruction. 1480 // This is pretty inefficient... 1481 1482 threads = (*activeThreads).begin(); 1483 while (threads != (*activeThreads).end()) { 1484 unsigned tid = (*threads++); 1485 1486 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1487 1488 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1489 !fromCommit->commitInfo[tid].squash && 1490 !fromCommit->commitInfo[tid].robSquashing) { 1491 1492 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1493 1494 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1495 1496 updateLSQNextCycle = true; 1497 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1498 } 1499 1500 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1501 1502 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1503 if (fromCommit->commitInfo[tid].uncached) { 1504 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1505 } else { 1506 instQueue.scheduleNonSpec( 1507 fromCommit->commitInfo[tid].nonSpecSeqNum); 1508 } 1509 } 1510 1511 if (broadcast_free_entries) { 1512 toFetch->iewInfo[tid].iqCount = 1513 instQueue.getCount(tid); 1514 toFetch->iewInfo[tid].ldstqCount = 1515 ldstQueue.getCount(tid); 1516 1517 toRename->iewInfo[tid].usedIQ = true; 1518 toRename->iewInfo[tid].freeIQEntries = 1519 instQueue.numFreeEntries(); 1520 toRename->iewInfo[tid].usedLSQ = true; 1521 toRename->iewInfo[tid].freeLSQEntries = 1522 ldstQueue.numFreeEntries(tid); 1523 1524 wroteToTimeBuffer = true; 1525 } 1526 1527 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1528 tid, toRename->iewInfo[tid].dispatched); 1529 } 1530 1531 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1532 "LSQ has %i free entries.\n", 1533 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1534 ldstQueue.numFreeEntries()); 1535 1536 updateStatus(); 1537 1538 if (wroteToTimeBuffer) { 1539 DPRINTF(Activity, "Activity this cycle.\n"); 1540 cpu->activityThisCycle(); 1541 } 1542} 1543 1544template <class Impl> 1545void 1546DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1547{ 1548 int thread_number = inst->threadNumber; 1549 1550 // 1551 // Pick off the software prefetches 1552 // 1553#ifdef TARGET_ALPHA 1554 if (inst->isDataPrefetch()) 1555 exeSwp[thread_number]++; 1556 else 1557 iewExecutedInsts++; 1558#else 1559 iewExecutedInsts[thread_number]++; 1560#endif 1561 1562 // 1563 // Control operations 1564 // 1565 if (inst->isControl()) 1566 exeBranches[thread_number]++; 1567 1568 // 1569 // Memory operations 1570 // 1571 if (inst->isMemRef()) { 1572 exeRefs[thread_number]++; 1573 1574 if (inst->isLoad()) { 1575 iewExecLoadInsts[thread_number]++; 1576 } 1577 } 1578} 1579