iew_impl.hh revision 13453:4a7a060ea26e 
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
45#define __CPU_O3_IEW_IMPL_IMPL_HH__
46
47// @todo: Fix the instantaneous communication among all the stages within
48// iew.  There's a clear delay between issue and execute, yet backwards
49// communication happens simultaneously.
50
51#include <queue>
52
53#include "arch/utility.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/fu_pool.hh"
57#include "cpu/o3/iew.hh"
58#include "cpu/timebuf.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/IEW.hh"
62#include "debug/O3PipeView.hh"
63#include "params/DerivO3CPU.hh"
64
65using namespace std;
66
67template<class Impl>
68DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
69    : issueToExecQueue(params->backComSize, params->forwardComSize),
70      cpu(_cpu),
71      instQueue(_cpu, this, params),
72      ldstQueue(_cpu, this, params),
73      fuPool(params->fuPool),
74      commitToIEWDelay(params->commitToIEWDelay),
75      renameToIEWDelay(params->renameToIEWDelay),
76      issueToExecuteDelay(params->issueToExecuteDelay),
77      dispatchWidth(params->dispatchWidth),
78      issueWidth(params->issueWidth),
79      wbNumInst(0),
80      wbCycle(0),
81      wbWidth(params->wbWidth),
82      numThreads(params->numThreads)
83{
84    if (dispatchWidth > Impl::MaxWidth)
85        fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
86             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
87             dispatchWidth, static_cast<int>(Impl::MaxWidth));
88    if (issueWidth > Impl::MaxWidth)
89        fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
90             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
91             issueWidth, static_cast<int>(Impl::MaxWidth));
92    if (wbWidth > Impl::MaxWidth)
93        fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
94             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
95             wbWidth, static_cast<int>(Impl::MaxWidth));
96
97    _status = Active;
98    exeStatus = Running;
99    wbStatus = Idle;
100
101    // Setup wire to read instructions coming from issue.
102    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
103
104    // Instruction queue needs the queue between issue and execute.
105    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
106
107    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
108        dispatchStatus[tid] = Running;
109        fetchRedirect[tid] = false;
110    }
111
112    updateLSQNextCycle = false;
113
114    skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
115}
116
117template <class Impl>
118std::string
119DefaultIEW<Impl>::name() const
120{
121    return cpu->name() + ".iew";
122}
123
124template <class Impl>
125void
126DefaultIEW<Impl>::regProbePoints()
127{
128    ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
129    ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
130    /**
131     * Probe point with dynamic instruction as the argument used to probe when
132     * an instruction starts to execute.
133     */
134    ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
135                                              "Execute");
136    /**
137     * Probe point with dynamic instruction as the argument used to probe when
138     * an instruction execution completes and it is marked ready to commit.
139     */
140    ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
141                                               "ToCommit");
142}
143
144template <class Impl>
145void
146DefaultIEW<Impl>::regStats()
147{
148    using namespace Stats;
149
150    instQueue.regStats();
151    ldstQueue.regStats();
152
153    iewIdleCycles
154        .name(name() + ".iewIdleCycles")
155        .desc("Number of cycles IEW is idle");
156
157    iewSquashCycles
158        .name(name() + ".iewSquashCycles")
159        .desc("Number of cycles IEW is squashing");
160
161    iewBlockCycles
162        .name(name() + ".iewBlockCycles")
163        .desc("Number of cycles IEW is blocking");
164
165    iewUnblockCycles
166        .name(name() + ".iewUnblockCycles")
167        .desc("Number of cycles IEW is unblocking");
168
169    iewDispatchedInsts
170        .name(name() + ".iewDispatchedInsts")
171        .desc("Number of instructions dispatched to IQ");
172
173    iewDispSquashedInsts
174        .name(name() + ".iewDispSquashedInsts")
175        .desc("Number of squashed instructions skipped by dispatch");
176
177    iewDispLoadInsts
178        .name(name() + ".iewDispLoadInsts")
179        .desc("Number of dispatched load instructions");
180
181    iewDispStoreInsts
182        .name(name() + ".iewDispStoreInsts")
183        .desc("Number of dispatched store instructions");
184
185    iewDispNonSpecInsts
186        .name(name() + ".iewDispNonSpecInsts")
187        .desc("Number of dispatched non-speculative instructions");
188
189    iewIQFullEvents
190        .name(name() + ".iewIQFullEvents")
191        .desc("Number of times the IQ has become full, causing a stall");
192
193    iewLSQFullEvents
194        .name(name() + ".iewLSQFullEvents")
195        .desc("Number of times the LSQ has become full, causing a stall");
196
197    memOrderViolationEvents
198        .name(name() + ".memOrderViolationEvents")
199        .desc("Number of memory order violations");
200
201    predictedTakenIncorrect
202        .name(name() + ".predictedTakenIncorrect")
203        .desc("Number of branches that were predicted taken incorrectly");
204
205    predictedNotTakenIncorrect
206        .name(name() + ".predictedNotTakenIncorrect")
207        .desc("Number of branches that were predicted not taken incorrectly");
208
209    branchMispredicts
210        .name(name() + ".branchMispredicts")
211        .desc("Number of branch mispredicts detected at execute");
212
213    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
214
215    iewExecutedInsts
216        .name(name() + ".iewExecutedInsts")
217        .desc("Number of executed instructions");
218
219    iewExecLoadInsts
220        .init(cpu->numThreads)
221        .name(name() + ".iewExecLoadInsts")
222        .desc("Number of load instructions executed")
223        .flags(total);
224
225    iewExecSquashedInsts
226        .name(name() + ".iewExecSquashedInsts")
227        .desc("Number of squashed instructions skipped in execute");
228
229    iewExecutedSwp
230        .init(cpu->numThreads)
231        .name(name() + ".exec_swp")
232        .desc("number of swp insts executed")
233        .flags(total);
234
235    iewExecutedNop
236        .init(cpu->numThreads)
237        .name(name() + ".exec_nop")
238        .desc("number of nop insts executed")
239        .flags(total);
240
241    iewExecutedRefs
242        .init(cpu->numThreads)
243        .name(name() + ".exec_refs")
244        .desc("number of memory reference insts executed")
245        .flags(total);
246
247    iewExecutedBranches
248        .init(cpu->numThreads)
249        .name(name() + ".exec_branches")
250        .desc("Number of branches executed")
251        .flags(total);
252
253    iewExecStoreInsts
254        .name(name() + ".exec_stores")
255        .desc("Number of stores executed")
256        .flags(total);
257    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
258
259    iewExecRate
260        .name(name() + ".exec_rate")
261        .desc("Inst execution rate")
262        .flags(total);
263
264    iewExecRate = iewExecutedInsts / cpu->numCycles;
265
266    iewInstsToCommit
267        .init(cpu->numThreads)
268        .name(name() + ".wb_sent")
269        .desc("cumulative count of insts sent to commit")
270        .flags(total);
271
272    writebackCount
273        .init(cpu->numThreads)
274        .name(name() + ".wb_count")
275        .desc("cumulative count of insts written-back")
276        .flags(total);
277
278    producerInst
279        .init(cpu->numThreads)
280        .name(name() + ".wb_producers")
281        .desc("num instructions producing a value")
282        .flags(total);
283
284    consumerInst
285        .init(cpu->numThreads)
286        .name(name() + ".wb_consumers")
287        .desc("num instructions consuming a value")
288        .flags(total);
289
290    wbFanout
291        .name(name() + ".wb_fanout")
292        .desc("average fanout of values written-back")
293        .flags(total);
294
295    wbFanout = producerInst / consumerInst;
296
297    wbRate
298        .name(name() + ".wb_rate")
299        .desc("insts written-back per cycle")
300        .flags(total);
301    wbRate = writebackCount / cpu->numCycles;
302}
303
304template<class Impl>
305void
306DefaultIEW<Impl>::startupStage()
307{
308    for (ThreadID tid = 0; tid < numThreads; tid++) {
309        toRename->iewInfo[tid].usedIQ = true;
310        toRename->iewInfo[tid].freeIQEntries =
311            instQueue.numFreeEntries(tid);
312
313        toRename->iewInfo[tid].usedLSQ = true;
314        toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
315        toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
316    }
317
318    // Initialize the checker's dcache port here
319    if (cpu->checker) {
320        cpu->checker->setDcachePort(&cpu->getDataPort());
321    }
322
323    cpu->activateStage(O3CPU::IEWIdx);
324}
325
326template<class Impl>
327void
328DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
329{
330    timeBuffer = tb_ptr;
331
332    // Setup wire to read information from time buffer, from commit.
333    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
334
335    // Setup wire to write information back to previous stages.
336    toRename = timeBuffer->getWire(0);
337
338    toFetch = timeBuffer->getWire(0);
339
340    // Instruction queue also needs main time buffer.
341    instQueue.setTimeBuffer(tb_ptr);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
347{
348    renameQueue = rq_ptr;
349
350    // Setup wire to read information from rename queue.
351    fromRename = renameQueue->getWire(-renameToIEWDelay);
352}
353
354template<class Impl>
355void
356DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
357{
358    iewQueue = iq_ptr;
359
360    // Setup wire to write instructions to commit.
361    toCommit = iewQueue->getWire(0);
362}
363
364template<class Impl>
365void
366DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
367{
368    activeThreads = at_ptr;
369
370    ldstQueue.setActiveThreads(at_ptr);
371    instQueue.setActiveThreads(at_ptr);
372}
373
374template<class Impl>
375void
376DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
377{
378    scoreboard = sb_ptr;
379}
380
381template <class Impl>
382bool
383DefaultIEW<Impl>::isDrained() const
384{
385    bool drained = ldstQueue.isDrained() && instQueue.isDrained();
386
387    for (ThreadID tid = 0; tid < numThreads; tid++) {
388        if (!insts[tid].empty()) {
389            DPRINTF(Drain, "%i: Insts not empty.\n", tid);
390            drained = false;
391        }
392        if (!skidBuffer[tid].empty()) {
393            DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
394            drained = false;
395        }
396        drained = drained && dispatchStatus[tid] == Running;
397    }
398
399    // Also check the FU pool as instructions are "stored" in FU
400    // completion events until they are done and not accounted for
401    // above
402    if (drained && !fuPool->isDrained()) {
403        DPRINTF(Drain, "FU pool still busy.\n");
404        drained = false;
405    }
406
407    return drained;
408}
409
410template <class Impl>
411void
412DefaultIEW<Impl>::drainSanityCheck() const
413{
414    assert(isDrained());
415
416    instQueue.drainSanityCheck();
417    ldstQueue.drainSanityCheck();
418}
419
420template <class Impl>
421void
422DefaultIEW<Impl>::takeOverFrom()
423{
424    // Reset all state.
425    _status = Active;
426    exeStatus = Running;
427    wbStatus = Idle;
428
429    instQueue.takeOverFrom();
430    ldstQueue.takeOverFrom();
431    fuPool->takeOverFrom();
432
433    startupStage();
434    cpu->activityThisCycle();
435
436    for (ThreadID tid = 0; tid < numThreads; tid++) {
437        dispatchStatus[tid] = Running;
438        fetchRedirect[tid] = false;
439    }
440
441    updateLSQNextCycle = false;
442
443    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
444        issueToExecQueue.advance();
445    }
446}
447
448template<class Impl>
449void
450DefaultIEW<Impl>::squash(ThreadID tid)
451{
452    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
453
454    // Tell the IQ to start squashing.
455    instQueue.squash(tid);
456
457    // Tell the LDSTQ to start squashing.
458    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
459    updatedQueues = true;
460
461    // Clear the skid buffer in case it has any data in it.
462    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
463            tid, fromCommit->commitInfo[tid].doneSeqNum);
464
465    while (!skidBuffer[tid].empty()) {
466        if (skidBuffer[tid].front()->isLoad()) {
467            toRename->iewInfo[tid].dispatchedToLQ++;
468        }
469        if (skidBuffer[tid].front()->isStore()) {
470            toRename->iewInfo[tid].dispatchedToSQ++;
471        }
472
473        toRename->iewInfo[tid].dispatched++;
474
475        skidBuffer[tid].pop();
476    }
477
478    emptyRenameInsts(tid);
479}
480
481template<class Impl>
482void
483DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
484{
485    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
486            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
487
488    if (!toCommit->squash[tid] ||
489            inst->seqNum < toCommit->squashedSeqNum[tid]) {
490        toCommit->squash[tid] = true;
491        toCommit->squashedSeqNum[tid] = inst->seqNum;
492        toCommit->branchTaken[tid] = inst->pcState().branching();
493
494        TheISA::PCState pc = inst->pcState();
495        TheISA::advancePC(pc, inst->staticInst);
496
497        toCommit->pc[tid] = pc;
498        toCommit->mispredictInst[tid] = inst;
499        toCommit->includeSquashInst[tid] = false;
500
501        wroteToTimeBuffer = true;
502    }
503
504}
505
506template<class Impl>
507void
508DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
509{
510    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
511            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
512    // Need to include inst->seqNum in the following comparison to cover the
513    // corner case when a branch misprediction and a memory violation for the
514    // same instruction (e.g. load PC) are detected in the same cycle.  In this
515    // case the memory violator should take precedence over the branch
516    // misprediction because it requires the violator itself to be included in
517    // the squash.
518    if (!toCommit->squash[tid] ||
519            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
520        toCommit->squash[tid] = true;
521
522        toCommit->squashedSeqNum[tid] = inst->seqNum;
523        toCommit->pc[tid] = inst->pcState();
524        toCommit->mispredictInst[tid] = NULL;
525
526        // Must include the memory violator in the squash.
527        toCommit->includeSquashInst[tid] = true;
528
529        wroteToTimeBuffer = true;
530    }
531}
532
533template<class Impl>
534void
535DefaultIEW<Impl>::block(ThreadID tid)
536{
537    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
538
539    if (dispatchStatus[tid] != Blocked &&
540        dispatchStatus[tid] != Unblocking) {
541        toRename->iewBlock[tid] = true;
542        wroteToTimeBuffer = true;
543    }
544
545    // Add the current inputs to the skid buffer so they can be
546    // reprocessed when this stage unblocks.
547    skidInsert(tid);
548
549    dispatchStatus[tid] = Blocked;
550}
551
552template<class Impl>
553void
554DefaultIEW<Impl>::unblock(ThreadID tid)
555{
556    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
557            "buffer %u.\n",tid, tid);
558
559    // If the skid bufffer is empty, signal back to previous stages to unblock.
560    // Also switch status to running.
561    if (skidBuffer[tid].empty()) {
562        toRename->iewUnblock[tid] = true;
563        wroteToTimeBuffer = true;
564        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
565        dispatchStatus[tid] = Running;
566    }
567}
568
569template<class Impl>
570void
571DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst)
572{
573    instQueue.wakeDependents(inst);
574}
575
576template<class Impl>
577void
578DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst)
579{
580    instQueue.rescheduleMemInst(inst);
581}
582
583template<class Impl>
584void
585DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst)
586{
587    instQueue.replayMemInst(inst);
588}
589
590template<class Impl>
591void
592DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst)
593{
594    instQueue.blockMemInst(inst);
595}
596
597template<class Impl>
598void
599DefaultIEW<Impl>::cacheUnblocked()
600{
601    instQueue.cacheUnblocked();
602}
603
604template<class Impl>
605void
606DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst)
607{
608    // This function should not be called after writebackInsts in a
609    // single cycle.  That will cause problems with an instruction
610    // being added to the queue to commit without being processed by
611    // writebackInsts prior to being sent to commit.
612
613    // First check the time slot that this instruction will write
614    // to.  If there are free write ports at the time, then go ahead
615    // and write the instruction to that time.  If there are not,
616    // keep looking back to see where's the first time there's a
617    // free slot.
618    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
619        ++wbNumInst;
620        if (wbNumInst == wbWidth) {
621            ++wbCycle;
622            wbNumInst = 0;
623        }
624    }
625
626    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
627            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
628    // Add finished instruction to queue to commit.
629    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
630    (*iewQueue)[wbCycle].size++;
631}
632
633template <class Impl>
634unsigned
635DefaultIEW<Impl>::validInstsFromRename()
636{
637    unsigned inst_count = 0;
638
639    for (int i=0; i<fromRename->size; i++) {
640        if (!fromRename->insts[i]->isSquashed())
641            inst_count++;
642    }
643
644    return inst_count;
645}
646
647template<class Impl>
648void
649DefaultIEW<Impl>::skidInsert(ThreadID tid)
650{
651    DynInstPtr inst = NULL;
652
653    while (!insts[tid].empty()) {
654        inst = insts[tid].front();
655
656        insts[tid].pop();
657
658        DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
659                "dispatch skidBuffer %i\n",tid, inst->seqNum,
660                inst->pcState(),tid);
661
662        skidBuffer[tid].push(inst);
663    }
664
665    assert(skidBuffer[tid].size() <= skidBufferMax &&
666           "Skidbuffer Exceeded Max Size");
667}
668
669template<class Impl>
670int
671DefaultIEW<Impl>::skidCount()
672{
673    int max=0;
674
675    list<ThreadID>::iterator threads = activeThreads->begin();
676    list<ThreadID>::iterator end = activeThreads->end();
677
678    while (threads != end) {
679        ThreadID tid = *threads++;
680        unsigned thread_count = skidBuffer[tid].size();
681        if (max < thread_count)
682            max = thread_count;
683    }
684
685    return max;
686}
687
688template<class Impl>
689bool
690DefaultIEW<Impl>::skidsEmpty()
691{
692    list<ThreadID>::iterator threads = activeThreads->begin();
693    list<ThreadID>::iterator end = activeThreads->end();
694
695    while (threads != end) {
696        ThreadID tid = *threads++;
697
698        if (!skidBuffer[tid].empty())
699            return false;
700    }
701
702    return true;
703}
704
705template <class Impl>
706void
707DefaultIEW<Impl>::updateStatus()
708{
709    bool any_unblocking = false;
710
711    list<ThreadID>::iterator threads = activeThreads->begin();
712    list<ThreadID>::iterator end = activeThreads->end();
713
714    while (threads != end) {
715        ThreadID tid = *threads++;
716
717        if (dispatchStatus[tid] == Unblocking) {
718            any_unblocking = true;
719            break;
720        }
721    }
722
723    // If there are no ready instructions waiting to be scheduled by the IQ,
724    // and there's no stores waiting to write back, and dispatch is not
725    // unblocking, then there is no internal activity for the IEW stage.
726    instQueue.intInstQueueReads++;
727    if (_status == Active && !instQueue.hasReadyInsts() &&
728        !ldstQueue.willWB() && !any_unblocking) {
729        DPRINTF(IEW, "IEW switching to idle\n");
730
731        deactivateStage();
732
733        _status = Inactive;
734    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
735                                       ldstQueue.willWB() ||
736                                       any_unblocking)) {
737        // Otherwise there is internal activity.  Set to active.
738        DPRINTF(IEW, "IEW switching to active\n");
739
740        activateStage();
741
742        _status = Active;
743    }
744}
745
746template <class Impl>
747void
748DefaultIEW<Impl>::resetEntries()
749{
750    instQueue.resetEntries();
751    ldstQueue.resetEntries();
752}
753
754template <class Impl>
755bool
756DefaultIEW<Impl>::checkStall(ThreadID tid)
757{
758    bool ret_val(false);
759
760    if (fromCommit->commitInfo[tid].robSquashing) {
761        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
762        ret_val = true;
763    } else if (instQueue.isFull(tid)) {
764        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
765        ret_val = true;
766    }
767
768    return ret_val;
769}
770
771template <class Impl>
772void
773DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
774{
775    // Check if there's a squash signal, squash if there is
776    // Check stall signals, block if there is.
777    // If status was Blocked
778    //     if so then go to unblocking
779    // If status was Squashing
780    //     check if squashing is not high.  Switch to running this cycle.
781
782    if (fromCommit->commitInfo[tid].squash) {
783        squash(tid);
784
785        if (dispatchStatus[tid] == Blocked ||
786            dispatchStatus[tid] == Unblocking) {
787            toRename->iewUnblock[tid] = true;
788            wroteToTimeBuffer = true;
789        }
790
791        dispatchStatus[tid] = Squashing;
792        fetchRedirect[tid] = false;
793        return;
794    }
795
796    if (fromCommit->commitInfo[tid].robSquashing) {
797        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
798
799        dispatchStatus[tid] = Squashing;
800        emptyRenameInsts(tid);
801        wroteToTimeBuffer = true;
802    }
803
804    if (checkStall(tid)) {
805        block(tid);
806        dispatchStatus[tid] = Blocked;
807        return;
808    }
809
810    if (dispatchStatus[tid] == Blocked) {
811        // Status from previous cycle was blocked, but there are no more stall
812        // conditions.  Switch over to unblocking.
813        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
814                tid);
815
816        dispatchStatus[tid] = Unblocking;
817
818        unblock(tid);
819
820        return;
821    }
822
823    if (dispatchStatus[tid] == Squashing) {
824        // Switch status to running if rename isn't being told to block or
825        // squash this cycle.
826        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
827                tid);
828
829        dispatchStatus[tid] = Running;
830
831        return;
832    }
833}
834
835template <class Impl>
836void
837DefaultIEW<Impl>::sortInsts()
838{
839    int insts_from_rename = fromRename->size;
840#ifdef DEBUG
841    for (ThreadID tid = 0; tid < numThreads; tid++)
842        assert(insts[tid].empty());
843#endif
844    for (int i = 0; i < insts_from_rename; ++i) {
845        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
846    }
847}
848
849template <class Impl>
850void
851DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
852{
853    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
854
855    while (!insts[tid].empty()) {
856
857        if (insts[tid].front()->isLoad()) {
858            toRename->iewInfo[tid].dispatchedToLQ++;
859        }
860        if (insts[tid].front()->isStore()) {
861            toRename->iewInfo[tid].dispatchedToSQ++;
862        }
863
864        toRename->iewInfo[tid].dispatched++;
865
866        insts[tid].pop();
867    }
868}
869
870template <class Impl>
871void
872DefaultIEW<Impl>::wakeCPU()
873{
874    cpu->wakeCPU();
875}
876
877template <class Impl>
878void
879DefaultIEW<Impl>::activityThisCycle()
880{
881    DPRINTF(Activity, "Activity this cycle.\n");
882    cpu->activityThisCycle();
883}
884
885template <class Impl>
886inline void
887DefaultIEW<Impl>::activateStage()
888{
889    DPRINTF(Activity, "Activating stage.\n");
890    cpu->activateStage(O3CPU::IEWIdx);
891}
892
893template <class Impl>
894inline void
895DefaultIEW<Impl>::deactivateStage()
896{
897    DPRINTF(Activity, "Deactivating stage.\n");
898    cpu->deactivateStage(O3CPU::IEWIdx);
899}
900
901template<class Impl>
902void
903DefaultIEW<Impl>::dispatch(ThreadID tid)
904{
905    // If status is Running or idle,
906    //     call dispatchInsts()
907    // If status is Unblocking,
908    //     buffer any instructions coming from rename
909    //     continue trying to empty skid buffer
910    //     check if stall conditions have passed
911
912    if (dispatchStatus[tid] == Blocked) {
913        ++iewBlockCycles;
914
915    } else if (dispatchStatus[tid] == Squashing) {
916        ++iewSquashCycles;
917    }
918
919    // Dispatch should try to dispatch as many instructions as its bandwidth
920    // will allow, as long as it is not currently blocked.
921    if (dispatchStatus[tid] == Running ||
922        dispatchStatus[tid] == Idle) {
923        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
924                "dispatch.\n", tid);
925
926        dispatchInsts(tid);
927    } else if (dispatchStatus[tid] == Unblocking) {
928        // Make sure that the skid buffer has something in it if the
929        // status is unblocking.
930        assert(!skidsEmpty());
931
932        // If the status was unblocking, then instructions from the skid
933        // buffer were used.  Remove those instructions and handle
934        // the rest of unblocking.
935        dispatchInsts(tid);
936
937        ++iewUnblockCycles;
938
939        if (validInstsFromRename()) {
940            // Add the current inputs to the skid buffer so they can be
941            // reprocessed when this stage unblocks.
942            skidInsert(tid);
943        }
944
945        unblock(tid);
946    }
947}
948
949template <class Impl>
950void
951DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
952{
953    // Obtain instructions from skid buffer if unblocking, or queue from rename
954    // otherwise.
955    std::queue<DynInstPtr> &insts_to_dispatch =
956        dispatchStatus[tid] == Unblocking ?
957        skidBuffer[tid] : insts[tid];
958
959    int insts_to_add = insts_to_dispatch.size();
960
961    DynInstPtr inst;
962    bool add_to_iq = false;
963    int dis_num_inst = 0;
964
965    // Loop through the instructions, putting them in the instruction
966    // queue.
967    for ( ; dis_num_inst < insts_to_add &&
968              dis_num_inst < dispatchWidth;
969          ++dis_num_inst)
970    {
971        inst = insts_to_dispatch.front();
972
973        if (dispatchStatus[tid] == Unblocking) {
974            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
975                    "buffer\n", tid);
976        }
977
978        // Make sure there's a valid instruction there.
979        assert(inst);
980
981        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
982                "IQ.\n",
983                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
984
985        // Be sure to mark these instructions as ready so that the
986        // commit stage can go ahead and execute them, and mark
987        // them as issued so the IQ doesn't reprocess them.
988
989        // Check for squashed instructions.
990        if (inst->isSquashed()) {
991            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
992                    "not adding to IQ.\n", tid);
993
994            ++iewDispSquashedInsts;
995
996            insts_to_dispatch.pop();
997
998            //Tell Rename That An Instruction has been processed
999            if (inst->isLoad()) {
1000                toRename->iewInfo[tid].dispatchedToLQ++;
1001            }
1002            if (inst->isStore()) {
1003                toRename->iewInfo[tid].dispatchedToSQ++;
1004            }
1005
1006            toRename->iewInfo[tid].dispatched++;
1007
1008            continue;
1009        }
1010
1011        // Check for full conditions.
1012        if (instQueue.isFull(tid)) {
1013            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1014
1015            // Call function to start blocking.
1016            block(tid);
1017
1018            // Set unblock to false. Special case where we are using
1019            // skidbuffer (unblocking) instructions but then we still
1020            // get full in the IQ.
1021            toRename->iewUnblock[tid] = false;
1022
1023            ++iewIQFullEvents;
1024            break;
1025        }
1026
1027        // Check LSQ if inst is LD/ST
1028        if ((inst->isLoad() && ldstQueue.lqFull(tid)) ||
1029            (inst->isStore() && ldstQueue.sqFull(tid))) {
1030            DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1031                    inst->isLoad() ? "LQ" : "SQ");
1032
1033            // Call function to start blocking.
1034            block(tid);
1035
1036            // Set unblock to false. Special case where we are using
1037            // skidbuffer (unblocking) instructions but then we still
1038            // get full in the IQ.
1039            toRename->iewUnblock[tid] = false;
1040
1041            ++iewLSQFullEvents;
1042            break;
1043        }
1044
1045        // Otherwise issue the instruction just fine.
1046        if (inst->isLoad()) {
1047            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1048                    "encountered, adding to LSQ.\n", tid);
1049
1050            // Reserve a spot in the load store queue for this
1051            // memory access.
1052            ldstQueue.insertLoad(inst);
1053
1054            ++iewDispLoadInsts;
1055
1056            add_to_iq = true;
1057
1058            toRename->iewInfo[tid].dispatchedToLQ++;
1059        } else if (inst->isStore()) {
1060            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1061                    "encountered, adding to LSQ.\n", tid);
1062
1063            ldstQueue.insertStore(inst);
1064
1065            ++iewDispStoreInsts;
1066
1067            if (inst->isStoreConditional()) {
1068                // Store conditionals need to be set as "canCommit()"
1069                // so that commit can process them when they reach the
1070                // head of commit.
1071                // @todo: This is somewhat specific to Alpha.
1072                inst->setCanCommit();
1073                instQueue.insertNonSpec(inst);
1074                add_to_iq = false;
1075
1076                ++iewDispNonSpecInsts;
1077            } else {
1078                add_to_iq = true;
1079            }
1080
1081            toRename->iewInfo[tid].dispatchedToSQ++;
1082        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1083            // Same as non-speculative stores.
1084            inst->setCanCommit();
1085            instQueue.insertBarrier(inst);
1086            add_to_iq = false;
1087        } else if (inst->isNop()) {
1088            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1089                    "skipping.\n", tid);
1090
1091            inst->setIssued();
1092            inst->setExecuted();
1093            inst->setCanCommit();
1094
1095            instQueue.recordProducer(inst);
1096
1097            iewExecutedNop[tid]++;
1098
1099            add_to_iq = false;
1100        } else {
1101            assert(!inst->isExecuted());
1102            add_to_iq = true;
1103        }
1104
1105        if (add_to_iq && inst->isNonSpeculative()) {
1106            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1107                    "encountered, skipping.\n", tid);
1108
1109            // Same as non-speculative stores.
1110            inst->setCanCommit();
1111
1112            // Specifically insert it as nonspeculative.
1113            instQueue.insertNonSpec(inst);
1114
1115            ++iewDispNonSpecInsts;
1116
1117            add_to_iq = false;
1118        }
1119
1120        // If the instruction queue is not full, then add the
1121        // instruction.
1122        if (add_to_iq) {
1123            instQueue.insert(inst);
1124        }
1125
1126        insts_to_dispatch.pop();
1127
1128        toRename->iewInfo[tid].dispatched++;
1129
1130        ++iewDispatchedInsts;
1131
1132#if TRACING_ON
1133        inst->dispatchTick = curTick() - inst->fetchTick;
1134#endif
1135        ppDispatch->notify(inst);
1136    }
1137
1138    if (!insts_to_dispatch.empty()) {
1139        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1140        block(tid);
1141        toRename->iewUnblock[tid] = false;
1142    }
1143
1144    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1145        dispatchStatus[tid] = Running;
1146
1147        updatedQueues = true;
1148    }
1149
1150    dis_num_inst = 0;
1151}
1152
1153template <class Impl>
1154void
1155DefaultIEW<Impl>::printAvailableInsts()
1156{
1157    int inst = 0;
1158
1159    std::cout << "Available Instructions: ";
1160
1161    while (fromIssue->insts[inst]) {
1162
1163        if (inst%3==0) std::cout << "\n\t";
1164
1165        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1166             << " TN: " << fromIssue->insts[inst]->threadNumber
1167             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1168
1169        inst++;
1170
1171    }
1172
1173    std::cout << "\n";
1174}
1175
1176template <class Impl>
1177void
1178DefaultIEW<Impl>::executeInsts()
1179{
1180    wbNumInst = 0;
1181    wbCycle = 0;
1182
1183    list<ThreadID>::iterator threads = activeThreads->begin();
1184    list<ThreadID>::iterator end = activeThreads->end();
1185
1186    while (threads != end) {
1187        ThreadID tid = *threads++;
1188        fetchRedirect[tid] = false;
1189    }
1190
1191    // Uncomment this if you want to see all available instructions.
1192    // @todo This doesn't actually work anymore, we should fix it.
1193//    printAvailableInsts();
1194
1195    // Execute/writeback any instructions that are available.
1196    int insts_to_execute = fromIssue->size;
1197    int inst_num = 0;
1198    for (; inst_num < insts_to_execute;
1199          ++inst_num) {
1200
1201        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1202
1203        DynInstPtr inst = instQueue.getInstToExecute();
1204
1205        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1206                inst->pcState(), inst->threadNumber,inst->seqNum);
1207
1208        // Notify potential listeners that this instruction has started
1209        // executing
1210        ppExecute->notify(inst);
1211
1212        // Check if the instruction is squashed; if so then skip it
1213        if (inst->isSquashed()) {
1214            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1215                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1216                         inst->seqNum);
1217
1218            // Consider this instruction executed so that commit can go
1219            // ahead and retire the instruction.
1220            inst->setExecuted();
1221
1222            // Not sure if I should set this here or just let commit try to
1223            // commit any squashed instructions.  I like the latter a bit more.
1224            inst->setCanCommit();
1225
1226            ++iewExecSquashedInsts;
1227
1228            continue;
1229        }
1230
1231        Fault fault = NoFault;
1232
1233        // Execute instruction.
1234        // Note that if the instruction faults, it will be handled
1235        // at the commit stage.
1236        if (inst->isMemRef()) {
1237            DPRINTF(IEW, "Execute: Calculating address for memory "
1238                    "reference.\n");
1239
1240            // Tell the LDSTQ to execute this instruction (if it is a load).
1241            if (inst->isLoad()) {
1242                // Loads will mark themselves as executed, and their writeback
1243                // event adds the instruction to the queue to commit
1244                fault = ldstQueue.executeLoad(inst);
1245
1246                if (inst->isTranslationDelayed() &&
1247                    fault == NoFault) {
1248                    // A hw page table walk is currently going on; the
1249                    // instruction must be deferred.
1250                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1251                            "load.\n");
1252                    instQueue.deferMemInst(inst);
1253                    continue;
1254                }
1255
1256                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1257                    inst->fault = NoFault;
1258                }
1259            } else if (inst->isStore()) {
1260                fault = ldstQueue.executeStore(inst);
1261
1262                if (inst->isTranslationDelayed() &&
1263                    fault == NoFault) {
1264                    // A hw page table walk is currently going on; the
1265                    // instruction must be deferred.
1266                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1267                            "store.\n");
1268                    instQueue.deferMemInst(inst);
1269                    continue;
1270                }
1271
1272                // If the store had a fault then it may not have a mem req
1273                if (fault != NoFault || !inst->readPredicate() ||
1274                        !inst->isStoreConditional()) {
1275                    // If the instruction faulted, then we need to send it along
1276                    // to commit without the instruction completing.
1277                    // Send this instruction to commit, also make sure iew stage
1278                    // realizes there is activity.
1279                    inst->setExecuted();
1280                    instToCommit(inst);
1281                    activityThisCycle();
1282                }
1283
1284                // Store conditionals will mark themselves as
1285                // executed, and their writeback event will add the
1286                // instruction to the queue to commit.
1287            } else {
1288                panic("Unexpected memory type!\n");
1289            }
1290
1291        } else {
1292            // If the instruction has already faulted, then skip executing it.
1293            // Such case can happen when it faulted during ITLB translation.
1294            // If we execute the instruction (even if it's a nop) the fault
1295            // will be replaced and we will lose it.
1296            if (inst->getFault() == NoFault) {
1297                inst->execute();
1298                if (!inst->readPredicate())
1299                    inst->forwardOldRegs();
1300            }
1301
1302            inst->setExecuted();
1303
1304            instToCommit(inst);
1305        }
1306
1307        updateExeInstStats(inst);
1308
1309        // Check if branch prediction was correct, if not then we need
1310        // to tell commit to squash in flight instructions.  Only
1311        // handle this if there hasn't already been something that
1312        // redirects fetch in this group of instructions.
1313
1314        // This probably needs to prioritize the redirects if a different
1315        // scheduler is used.  Currently the scheduler schedules the oldest
1316        // instruction first, so the branch resolution order will be correct.
1317        ThreadID tid = inst->threadNumber;
1318
1319        if (!fetchRedirect[tid] ||
1320            !toCommit->squash[tid] ||
1321            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1322
1323            // Prevent testing for misprediction on load instructions,
1324            // that have not been executed.
1325            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1326
1327            if (inst->mispredicted() && !loadNotExecuted) {
1328                fetchRedirect[tid] = true;
1329
1330                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1331                DPRINTF(IEW, "Predicted target was PC: %s.\n",
1332                        inst->readPredTarg());
1333                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1334                        inst->pcState());
1335                // If incorrect, then signal the ROB that it must be squashed.
1336                squashDueToBranch(inst, tid);
1337
1338                ppMispredict->notify(inst);
1339
1340                if (inst->readPredTaken()) {
1341                    predictedTakenIncorrect++;
1342                } else {
1343                    predictedNotTakenIncorrect++;
1344                }
1345            } else if (ldstQueue.violation(tid)) {
1346                assert(inst->isMemRef());
1347                // If there was an ordering violation, then get the
1348                // DynInst that caused the violation.  Note that this
1349                // clears the violation signal.
1350                DynInstPtr violator;
1351                violator = ldstQueue.getMemDepViolator(tid);
1352
1353                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1354                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1355                        violator->pcState(), violator->seqNum,
1356                        inst->pcState(), inst->seqNum, inst->physEffAddrLow);
1357
1358                fetchRedirect[tid] = true;
1359
1360                // Tell the instruction queue that a violation has occured.
1361                instQueue.violation(inst, violator);
1362
1363                // Squash.
1364                squashDueToMemOrder(violator, tid);
1365
1366                ++memOrderViolationEvents;
1367            }
1368        } else {
1369            // Reset any state associated with redirects that will not
1370            // be used.
1371            if (ldstQueue.violation(tid)) {
1372                assert(inst->isMemRef());
1373
1374                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1375
1376                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1377                        "%s, inst PC: %s.  Addr is: %#x.\n",
1378                        violator->pcState(), inst->pcState(),
1379                        inst->physEffAddrLow);
1380                DPRINTF(IEW, "Violation will not be handled because "
1381                        "already squashing\n");
1382
1383                ++memOrderViolationEvents;
1384            }
1385        }
1386    }
1387
1388    // Update and record activity if we processed any instructions.
1389    if (inst_num) {
1390        if (exeStatus == Idle) {
1391            exeStatus = Running;
1392        }
1393
1394        updatedQueues = true;
1395
1396        cpu->activityThisCycle();
1397    }
1398
1399    // Need to reset this in case a writeback event needs to write into the
1400    // iew queue.  That way the writeback event will write into the correct
1401    // spot in the queue.
1402    wbNumInst = 0;
1403
1404}
1405
1406template <class Impl>
1407void
1408DefaultIEW<Impl>::writebackInsts()
1409{
1410    // Loop through the head of the time buffer and wake any
1411    // dependents.  These instructions are about to write back.  Also
1412    // mark scoreboard that this instruction is finally complete.
1413    // Either have IEW have direct access to scoreboard, or have this
1414    // as part of backwards communication.
1415    for (int inst_num = 0; inst_num < wbWidth &&
1416             toCommit->insts[inst_num]; inst_num++) {
1417        DynInstPtr inst = toCommit->insts[inst_num];
1418        ThreadID tid = inst->threadNumber;
1419
1420        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1421                inst->seqNum, inst->pcState());
1422
1423        iewInstsToCommit[tid]++;
1424        // Notify potential listeners that execution is complete for this
1425        // instruction.
1426        ppToCommit->notify(inst);
1427
1428        // Some instructions will be sent to commit without having
1429        // executed because they need commit to handle them.
1430        // E.g. Strictly ordered loads have not actually executed when they
1431        // are first sent to commit.  Instead commit must tell the LSQ
1432        // when it's ready to execute the strictly ordered load.
1433        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1434            int dependents = instQueue.wakeDependents(inst);
1435
1436            for (int i = 0; i < inst->numDestRegs(); i++) {
1437                //mark as Ready
1438                DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1439                        inst->renamedDestRegIdx(i)->index(),
1440                        inst->renamedDestRegIdx(i)->className());
1441                scoreboard->setReg(inst->renamedDestRegIdx(i));
1442            }
1443
1444            if (dependents) {
1445                producerInst[tid]++;
1446                consumerInst[tid]+= dependents;
1447            }
1448            writebackCount[tid]++;
1449        }
1450    }
1451}
1452
1453template<class Impl>
1454void
1455DefaultIEW<Impl>::tick()
1456{
1457    wbNumInst = 0;
1458    wbCycle = 0;
1459
1460    wroteToTimeBuffer = false;
1461    updatedQueues = false;
1462
1463    sortInsts();
1464
1465    // Free function units marked as being freed this cycle.
1466    fuPool->processFreeUnits();
1467
1468    list<ThreadID>::iterator threads = activeThreads->begin();
1469    list<ThreadID>::iterator end = activeThreads->end();
1470
1471    // Check stall and squash signals, dispatch any instructions.
1472    while (threads != end) {
1473        ThreadID tid = *threads++;
1474
1475        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1476
1477        checkSignalsAndUpdate(tid);
1478        dispatch(tid);
1479    }
1480
1481    if (exeStatus != Squashing) {
1482        executeInsts();
1483
1484        writebackInsts();
1485
1486        // Have the instruction queue try to schedule any ready instructions.
1487        // (In actuality, this scheduling is for instructions that will
1488        // be executed next cycle.)
1489        instQueue.scheduleReadyInsts();
1490
1491        // Also should advance its own time buffers if the stage ran.
1492        // Not the best place for it, but this works (hopefully).
1493        issueToExecQueue.advance();
1494    }
1495
1496    bool broadcast_free_entries = false;
1497
1498    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1499        exeStatus = Idle;
1500        updateLSQNextCycle = false;
1501
1502        broadcast_free_entries = true;
1503    }
1504
1505    // Writeback any stores using any leftover bandwidth.
1506    ldstQueue.writebackStores();
1507
1508    // Check the committed load/store signals to see if there's a load
1509    // or store to commit.  Also check if it's being told to execute a
1510    // nonspeculative instruction.
1511    // This is pretty inefficient...
1512
1513    threads = activeThreads->begin();
1514    while (threads != end) {
1515        ThreadID tid = (*threads++);
1516
1517        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1518
1519        // Update structures based on instructions committed.
1520        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1521            !fromCommit->commitInfo[tid].squash &&
1522            !fromCommit->commitInfo[tid].robSquashing) {
1523
1524            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1525
1526            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1527
1528            updateLSQNextCycle = true;
1529            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1530        }
1531
1532        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1533
1534            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1535            if (fromCommit->commitInfo[tid].strictlyOrdered) {
1536                instQueue.replayMemInst(
1537                    fromCommit->commitInfo[tid].strictlyOrderedLoad);
1538                fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1539            } else {
1540                instQueue.scheduleNonSpec(
1541                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1542            }
1543        }
1544
1545        if (broadcast_free_entries) {
1546            toFetch->iewInfo[tid].iqCount =
1547                instQueue.getCount(tid);
1548            toFetch->iewInfo[tid].ldstqCount =
1549                ldstQueue.getCount(tid);
1550
1551            toRename->iewInfo[tid].usedIQ = true;
1552            toRename->iewInfo[tid].freeIQEntries =
1553                instQueue.numFreeEntries(tid);
1554            toRename->iewInfo[tid].usedLSQ = true;
1555
1556            toRename->iewInfo[tid].freeLQEntries =
1557                ldstQueue.numFreeLoadEntries(tid);
1558            toRename->iewInfo[tid].freeSQEntries =
1559                ldstQueue.numFreeStoreEntries(tid);
1560
1561            wroteToTimeBuffer = true;
1562        }
1563
1564        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1565                tid, toRename->iewInfo[tid].dispatched);
1566    }
1567
1568    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1569            "LQ has %i free entries. SQ has %i free entries.\n",
1570            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1571            ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries());
1572
1573    updateStatus();
1574
1575    if (wroteToTimeBuffer) {
1576        DPRINTF(Activity, "Activity this cycle.\n");
1577        cpu->activityThisCycle();
1578    }
1579}
1580
1581template <class Impl>
1582void
1583DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
1584{
1585    ThreadID tid = inst->threadNumber;
1586
1587    iewExecutedInsts++;
1588
1589#if TRACING_ON
1590    if (DTRACE(O3PipeView)) {
1591        inst->completeTick = curTick() - inst->fetchTick;
1592    }
1593#endif
1594
1595    //
1596    //  Control operations
1597    //
1598    if (inst->isControl())
1599        iewExecutedBranches[tid]++;
1600
1601    //
1602    //  Memory operations
1603    //
1604    if (inst->isMemRef()) {
1605        iewExecutedRefs[tid]++;
1606
1607        if (inst->isLoad()) {
1608            iewExecLoadInsts[tid]++;
1609        }
1610    }
1611}
1612
1613template <class Impl>
1614void
1615DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
1616{
1617    ThreadID tid = inst->threadNumber;
1618
1619    if (!fetchRedirect[tid] ||
1620        !toCommit->squash[tid] ||
1621        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1622
1623        if (inst->mispredicted()) {
1624            fetchRedirect[tid] = true;
1625
1626            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1627            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1628                    inst->predInstAddr(), inst->predNextInstAddr());
1629            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1630                    " NPC: %#x.\n", inst->nextInstAddr(),
1631                    inst->nextInstAddr());
1632            // If incorrect, then signal the ROB that it must be squashed.
1633            squashDueToBranch(inst, tid);
1634
1635            if (inst->readPredTaken()) {
1636                predictedTakenIncorrect++;
1637            } else {
1638                predictedNotTakenIncorrect++;
1639            }
1640        }
1641    }
1642}
1643
1644#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
1645