iew_impl.hh revision 9527
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 431060SN/A// @todo: Fix the instantaneous communication among all the stages within 441060SN/A// iew. There's a clear delay between issue and execute, yet backwards 451689SN/A// communication happens simultaneously. 461060SN/A 471060SN/A#include <queue> 481060SN/A 498230Snate@binkert.org#include "arch/utility.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 518887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 531717SN/A#include "cpu/o3/iew.hh" 548229Snate@binkert.org#include "cpu/timebuf.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Decode.hh" 579444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 588232Snate@binkert.org#include "debug/IEW.hh" 599527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 605529Snate@binkert.org#include "params/DerivO3CPU.hh" 611060SN/A 626221Snate@binkert.orgusing namespace std; 636221Snate@binkert.org 641681SN/Atemplate<class Impl> 655529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 662873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 674329Sktlim@umich.edu cpu(_cpu), 684329Sktlim@umich.edu instQueue(_cpu, this, params), 694329Sktlim@umich.edu ldstQueue(_cpu, this, params), 702292SN/A fuPool(params->fuPool), 712292SN/A commitToIEWDelay(params->commitToIEWDelay), 722292SN/A renameToIEWDelay(params->renameToIEWDelay), 732292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 742820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 752292SN/A issueWidth(params->issueWidth), 762820Sktlim@umich.edu wbOutstanding(0), 772820Sktlim@umich.edu wbWidth(params->wbWidth), 789444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 791060SN/A{ 802292SN/A _status = Active; 812292SN/A exeStatus = Running; 822292SN/A wbStatus = Idle; 831060SN/A 841060SN/A // Setup wire to read instructions coming from issue. 851060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 861060SN/A 871060SN/A // Instruction queue needs the queue between issue and execute. 881060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 891681SN/A 906221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 916221Snate@binkert.org dispatchStatus[tid] = Running; 926221Snate@binkert.org stalls[tid].commit = false; 936221Snate@binkert.org fetchRedirect[tid] = false; 942292SN/A } 952292SN/A 962820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 972820Sktlim@umich.edu 982292SN/A updateLSQNextCycle = false; 992292SN/A 1002820Sktlim@umich.edu ableToIssue = true; 1012820Sktlim@umich.edu 1022292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1032292SN/A} 1042292SN/A 1052292SN/Atemplate <class Impl> 1062292SN/Astd::string 1072292SN/ADefaultIEW<Impl>::name() const 1082292SN/A{ 1092292SN/A return cpu->name() + ".iew"; 1101060SN/A} 1111060SN/A 1121681SN/Atemplate <class Impl> 1131062SN/Avoid 1142292SN/ADefaultIEW<Impl>::regStats() 1151062SN/A{ 1162301SN/A using namespace Stats; 1172301SN/A 1181062SN/A instQueue.regStats(); 1192727Sktlim@umich.edu ldstQueue.regStats(); 1201062SN/A 1211062SN/A iewIdleCycles 1221062SN/A .name(name() + ".iewIdleCycles") 1231062SN/A .desc("Number of cycles IEW is idle"); 1241062SN/A 1251062SN/A iewSquashCycles 1261062SN/A .name(name() + ".iewSquashCycles") 1271062SN/A .desc("Number of cycles IEW is squashing"); 1281062SN/A 1291062SN/A iewBlockCycles 1301062SN/A .name(name() + ".iewBlockCycles") 1311062SN/A .desc("Number of cycles IEW is blocking"); 1321062SN/A 1331062SN/A iewUnblockCycles 1341062SN/A .name(name() + ".iewUnblockCycles") 1351062SN/A .desc("Number of cycles IEW is unblocking"); 1361062SN/A 1371062SN/A iewDispatchedInsts 1381062SN/A .name(name() + ".iewDispatchedInsts") 1391062SN/A .desc("Number of instructions dispatched to IQ"); 1401062SN/A 1411062SN/A iewDispSquashedInsts 1421062SN/A .name(name() + ".iewDispSquashedInsts") 1431062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1441062SN/A 1451062SN/A iewDispLoadInsts 1461062SN/A .name(name() + ".iewDispLoadInsts") 1471062SN/A .desc("Number of dispatched load instructions"); 1481062SN/A 1491062SN/A iewDispStoreInsts 1501062SN/A .name(name() + ".iewDispStoreInsts") 1511062SN/A .desc("Number of dispatched store instructions"); 1521062SN/A 1531062SN/A iewDispNonSpecInsts 1541062SN/A .name(name() + ".iewDispNonSpecInsts") 1551062SN/A .desc("Number of dispatched non-speculative instructions"); 1561062SN/A 1571062SN/A iewIQFullEvents 1581062SN/A .name(name() + ".iewIQFullEvents") 1591062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1601062SN/A 1612292SN/A iewLSQFullEvents 1622292SN/A .name(name() + ".iewLSQFullEvents") 1632292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1642292SN/A 1651062SN/A memOrderViolationEvents 1661062SN/A .name(name() + ".memOrderViolationEvents") 1671062SN/A .desc("Number of memory order violations"); 1681062SN/A 1691062SN/A predictedTakenIncorrect 1701062SN/A .name(name() + ".predictedTakenIncorrect") 1711062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1722292SN/A 1732292SN/A predictedNotTakenIncorrect 1742292SN/A .name(name() + ".predictedNotTakenIncorrect") 1752292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1762292SN/A 1772292SN/A branchMispredicts 1782292SN/A .name(name() + ".branchMispredicts") 1792292SN/A .desc("Number of branch mispredicts detected at execute"); 1802292SN/A 1812292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1822301SN/A 1832727Sktlim@umich.edu iewExecutedInsts 1842353SN/A .name(name() + ".iewExecutedInsts") 1852727Sktlim@umich.edu .desc("Number of executed instructions"); 1862727Sktlim@umich.edu 1872727Sktlim@umich.edu iewExecLoadInsts 1886221Snate@binkert.org .init(cpu->numThreads) 1892353SN/A .name(name() + ".iewExecLoadInsts") 1902727Sktlim@umich.edu .desc("Number of load instructions executed") 1912727Sktlim@umich.edu .flags(total); 1922727Sktlim@umich.edu 1932727Sktlim@umich.edu iewExecSquashedInsts 1942353SN/A .name(name() + ".iewExecSquashedInsts") 1952727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1962727Sktlim@umich.edu 1972727Sktlim@umich.edu iewExecutedSwp 1986221Snate@binkert.org .init(cpu->numThreads) 1998240Snate@binkert.org .name(name() + ".exec_swp") 2002301SN/A .desc("number of swp insts executed") 2012727Sktlim@umich.edu .flags(total); 2022301SN/A 2032727Sktlim@umich.edu iewExecutedNop 2046221Snate@binkert.org .init(cpu->numThreads) 2058240Snate@binkert.org .name(name() + ".exec_nop") 2062301SN/A .desc("number of nop insts executed") 2072727Sktlim@umich.edu .flags(total); 2082301SN/A 2092727Sktlim@umich.edu iewExecutedRefs 2106221Snate@binkert.org .init(cpu->numThreads) 2118240Snate@binkert.org .name(name() + ".exec_refs") 2122301SN/A .desc("number of memory reference insts executed") 2132727Sktlim@umich.edu .flags(total); 2142301SN/A 2152727Sktlim@umich.edu iewExecutedBranches 2166221Snate@binkert.org .init(cpu->numThreads) 2178240Snate@binkert.org .name(name() + ".exec_branches") 2182301SN/A .desc("Number of branches executed") 2192727Sktlim@umich.edu .flags(total); 2202301SN/A 2212301SN/A iewExecStoreInsts 2228240Snate@binkert.org .name(name() + ".exec_stores") 2232301SN/A .desc("Number of stores executed") 2242727Sktlim@umich.edu .flags(total); 2252727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu iewExecRate 2288240Snate@binkert.org .name(name() + ".exec_rate") 2292727Sktlim@umich.edu .desc("Inst execution rate") 2302727Sktlim@umich.edu .flags(total); 2312727Sktlim@umich.edu 2322727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2332301SN/A 2342301SN/A iewInstsToCommit 2356221Snate@binkert.org .init(cpu->numThreads) 2368240Snate@binkert.org .name(name() + ".wb_sent") 2372301SN/A .desc("cumulative count of insts sent to commit") 2382727Sktlim@umich.edu .flags(total); 2392301SN/A 2402326SN/A writebackCount 2416221Snate@binkert.org .init(cpu->numThreads) 2428240Snate@binkert.org .name(name() + ".wb_count") 2432301SN/A .desc("cumulative count of insts written-back") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A producerInst 2476221Snate@binkert.org .init(cpu->numThreads) 2488240Snate@binkert.org .name(name() + ".wb_producers") 2492301SN/A .desc("num instructions producing a value") 2502727Sktlim@umich.edu .flags(total); 2512301SN/A 2522326SN/A consumerInst 2536221Snate@binkert.org .init(cpu->numThreads) 2548240Snate@binkert.org .name(name() + ".wb_consumers") 2552301SN/A .desc("num instructions consuming a value") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A wbPenalized 2596221Snate@binkert.org .init(cpu->numThreads) 2608240Snate@binkert.org .name(name() + ".wb_penalized") 2612301SN/A .desc("number of instrctions required to write to 'other' IQ") 2622727Sktlim@umich.edu .flags(total); 2632301SN/A 2642326SN/A wbPenalizedRate 2658240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2662301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2672727Sktlim@umich.edu .flags(total); 2682301SN/A 2692326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2702301SN/A 2712326SN/A wbFanout 2728240Snate@binkert.org .name(name() + ".wb_fanout") 2732301SN/A .desc("average fanout of values written-back") 2742727Sktlim@umich.edu .flags(total); 2752301SN/A 2762326SN/A wbFanout = producerInst / consumerInst; 2772301SN/A 2782326SN/A wbRate 2798240Snate@binkert.org .name(name() + ".wb_rate") 2802301SN/A .desc("insts written-back per cycle") 2812727Sktlim@umich.edu .flags(total); 2822326SN/A wbRate = writebackCount / cpu->numCycles; 2831062SN/A} 2841062SN/A 2851681SN/Atemplate<class Impl> 2861060SN/Avoid 2879427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 2881060SN/A{ 2896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2902292SN/A toRename->iewInfo[tid].usedIQ = true; 2912292SN/A toRename->iewInfo[tid].freeIQEntries = 2922292SN/A instQueue.numFreeEntries(tid); 2932292SN/A 2942292SN/A toRename->iewInfo[tid].usedLSQ = true; 2952292SN/A toRename->iewInfo[tid].freeLSQEntries = 2962292SN/A ldstQueue.numFreeEntries(tid); 2972292SN/A } 2982292SN/A 2998887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3008733Sgeoffrey.blake@arm.com if (cpu->checker) { 3018850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3028887Sgeoffrey.blake@arm.com } 3038733Sgeoffrey.blake@arm.com 3042733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3051060SN/A} 3061060SN/A 3071681SN/Atemplate<class Impl> 3081060SN/Avoid 3092292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3101060SN/A{ 3111060SN/A timeBuffer = tb_ptr; 3121060SN/A 3131060SN/A // Setup wire to read information from time buffer, from commit. 3141060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3151060SN/A 3161060SN/A // Setup wire to write information back to previous stages. 3171060SN/A toRename = timeBuffer->getWire(0); 3181060SN/A 3192292SN/A toFetch = timeBuffer->getWire(0); 3202292SN/A 3211060SN/A // Instruction queue also needs main time buffer. 3221060SN/A instQueue.setTimeBuffer(tb_ptr); 3231060SN/A} 3241060SN/A 3251681SN/Atemplate<class Impl> 3261060SN/Avoid 3272292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3281060SN/A{ 3291060SN/A renameQueue = rq_ptr; 3301060SN/A 3311060SN/A // Setup wire to read information from rename queue. 3321060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3331060SN/A} 3341060SN/A 3351681SN/Atemplate<class Impl> 3361060SN/Avoid 3372292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3381060SN/A{ 3391060SN/A iewQueue = iq_ptr; 3401060SN/A 3411060SN/A // Setup wire to write instructions to commit. 3421060SN/A toCommit = iewQueue->getWire(0); 3431060SN/A} 3441060SN/A 3451681SN/Atemplate<class Impl> 3461060SN/Avoid 3476221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3481060SN/A{ 3492292SN/A activeThreads = at_ptr; 3502292SN/A 3512292SN/A ldstQueue.setActiveThreads(at_ptr); 3522292SN/A instQueue.setActiveThreads(at_ptr); 3531060SN/A} 3541060SN/A 3551681SN/Atemplate<class Impl> 3561060SN/Avoid 3572292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3581060SN/A{ 3592292SN/A scoreboard = sb_ptr; 3601060SN/A} 3611060SN/A 3622307SN/Atemplate <class Impl> 3632863Sktlim@umich.edubool 3649444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3652307SN/A{ 3669444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3679444SAndreas.Sandberg@ARM.com 3689444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3699444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3709444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3719444SAndreas.Sandberg@ARM.com drained = false; 3729444SAndreas.Sandberg@ARM.com } 3739444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3749444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3759444SAndreas.Sandberg@ARM.com drained = false; 3769444SAndreas.Sandberg@ARM.com } 3779444SAndreas.Sandberg@ARM.com } 3789444SAndreas.Sandberg@ARM.com 3799444SAndreas.Sandberg@ARM.com return drained; 3801681SN/A} 3811681SN/A 3822316SN/Atemplate <class Impl> 3831681SN/Avoid 3849444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 3852843Sktlim@umich.edu{ 3869444SAndreas.Sandberg@ARM.com assert(isDrained()); 3872843Sktlim@umich.edu 3889444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 3899444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 3909444SAndreas.Sandberg@ARM.com fuPool->drainSanityCheck(); 3911681SN/A} 3921681SN/A 3932307SN/Atemplate <class Impl> 3941681SN/Avoid 3952307SN/ADefaultIEW<Impl>::takeOverFrom() 3961060SN/A{ 3972348SN/A // Reset all state. 3982307SN/A _status = Active; 3992307SN/A exeStatus = Running; 4002307SN/A wbStatus = Idle; 4011060SN/A 4022307SN/A instQueue.takeOverFrom(); 4032307SN/A ldstQueue.takeOverFrom(); 4049444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4051060SN/A 4069427SAndreas.Sandberg@ARM.com startupStage(); 4072307SN/A cpu->activityThisCycle(); 4081060SN/A 4096221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4106221Snate@binkert.org dispatchStatus[tid] = Running; 4116221Snate@binkert.org stalls[tid].commit = false; 4126221Snate@binkert.org fetchRedirect[tid] = false; 4132307SN/A } 4141060SN/A 4152307SN/A updateLSQNextCycle = false; 4162307SN/A 4172873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4182307SN/A issueToExecQueue.advance(); 4191060SN/A } 4201060SN/A} 4211060SN/A 4221681SN/Atemplate<class Impl> 4231060SN/Avoid 4246221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4252107SN/A{ 4266221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4272107SN/A 4282292SN/A // Tell the IQ to start squashing. 4292292SN/A instQueue.squash(tid); 4302107SN/A 4312292SN/A // Tell the LDSTQ to start squashing. 4322326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4332292SN/A updatedQueues = true; 4342107SN/A 4352292SN/A // Clear the skid buffer in case it has any data in it. 4362935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4374632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4382935Sksewell@umich.edu 4392292SN/A while (!skidBuffer[tid].empty()) { 4402292SN/A if (skidBuffer[tid].front()->isLoad() || 4412292SN/A skidBuffer[tid].front()->isStore() ) { 4422292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4432292SN/A } 4442107SN/A 4452292SN/A toRename->iewInfo[tid].dispatched++; 4462107SN/A 4472292SN/A skidBuffer[tid].pop(); 4482292SN/A } 4492107SN/A 4502702Sktlim@umich.edu emptyRenameInsts(tid); 4512107SN/A} 4522107SN/A 4532107SN/Atemplate<class Impl> 4542107SN/Avoid 4556221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4562292SN/A{ 4577720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4587720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4592292SN/A 4607852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4617852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4627852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4637852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4647852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4652935Sksewell@umich.edu 4667852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4677852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4682292SN/A 4697852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4707852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4717852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4722292SN/A 4737852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4747852SMatt.Horsnell@arm.com } 4757852SMatt.Horsnell@arm.com 4762292SN/A} 4772292SN/A 4782292SN/Atemplate<class Impl> 4792292SN/Avoid 4806221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4812292SN/A{ 4828513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 4838513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4848513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 4858513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 4868513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 4878513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 4888513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 4898513SGiacomo.Gabrielli@arm.com // the squash. 4908513SGiacomo.Gabrielli@arm.com if (toCommit->squash[tid] == false || 4918513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 4928513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 4932292SN/A 4947852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4958513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 4968137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 4972292SN/A 4988513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 4998513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5002292SN/A 5017852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5027852SMatt.Horsnell@arm.com } 5032292SN/A} 5042292SN/A 5052292SN/Atemplate<class Impl> 5062292SN/Avoid 5076221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5082292SN/A{ 5092292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5107720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5117852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5127852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5137852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5142292SN/A 5157852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5167852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5178137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5182292SN/A 5197852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5207852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5212292SN/A 5227852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5232292SN/A 5247852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5257852SMatt.Horsnell@arm.com } 5262292SN/A} 5272292SN/A 5282292SN/Atemplate<class Impl> 5292292SN/Avoid 5306221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5312292SN/A{ 5322292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5332292SN/A 5342292SN/A if (dispatchStatus[tid] != Blocked && 5352292SN/A dispatchStatus[tid] != Unblocking) { 5362292SN/A toRename->iewBlock[tid] = true; 5372292SN/A wroteToTimeBuffer = true; 5382292SN/A } 5392292SN/A 5402292SN/A // Add the current inputs to the skid buffer so they can be 5412292SN/A // reprocessed when this stage unblocks. 5422292SN/A skidInsert(tid); 5432292SN/A 5442292SN/A dispatchStatus[tid] = Blocked; 5452292SN/A} 5462292SN/A 5472292SN/Atemplate<class Impl> 5482292SN/Avoid 5496221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5502292SN/A{ 5512292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5522292SN/A "buffer %u.\n",tid, tid); 5532292SN/A 5542292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5552292SN/A // Also switch status to running. 5562292SN/A if (skidBuffer[tid].empty()) { 5572292SN/A toRename->iewUnblock[tid] = true; 5582292SN/A wroteToTimeBuffer = true; 5592292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5602292SN/A dispatchStatus[tid] = Running; 5612292SN/A } 5622292SN/A} 5632292SN/A 5642292SN/Atemplate<class Impl> 5652292SN/Avoid 5662292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5671060SN/A{ 5681681SN/A instQueue.wakeDependents(inst); 5691060SN/A} 5701060SN/A 5712292SN/Atemplate<class Impl> 5722292SN/Avoid 5732292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5742292SN/A{ 5752292SN/A instQueue.rescheduleMemInst(inst); 5762292SN/A} 5771681SN/A 5781681SN/Atemplate<class Impl> 5791060SN/Avoid 5802292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5811060SN/A{ 5822292SN/A instQueue.replayMemInst(inst); 5832292SN/A} 5841060SN/A 5852292SN/Atemplate<class Impl> 5862292SN/Avoid 5872292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5882292SN/A{ 5893221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5903221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5913221Sktlim@umich.edu // being added to the queue to commit without being processed by 5923221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5933221Sktlim@umich.edu 5942292SN/A // First check the time slot that this instruction will write 5952292SN/A // to. If there are free write ports at the time, then go ahead 5962292SN/A // and write the instruction to that time. If there are not, 5972292SN/A // keep looking back to see where's the first time there's a 5982326SN/A // free slot. 5992292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6002292SN/A ++wbNumInst; 6012820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6022292SN/A ++wbCycle; 6032292SN/A wbNumInst = 0; 6042292SN/A } 6052292SN/A 6062353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6072292SN/A } 6082292SN/A 6092353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6102353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6112292SN/A // Add finished instruction to queue to commit. 6122292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6132292SN/A (*iewQueue)[wbCycle].size++; 6142292SN/A} 6152292SN/A 6162292SN/Atemplate <class Impl> 6172292SN/Aunsigned 6182292SN/ADefaultIEW<Impl>::validInstsFromRename() 6192292SN/A{ 6202292SN/A unsigned inst_count = 0; 6212292SN/A 6222292SN/A for (int i=0; i<fromRename->size; i++) { 6232731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6242292SN/A inst_count++; 6252292SN/A } 6262292SN/A 6272292SN/A return inst_count; 6282292SN/A} 6292292SN/A 6302292SN/Atemplate<class Impl> 6312292SN/Avoid 6326221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6332292SN/A{ 6342292SN/A DynInstPtr inst = NULL; 6352292SN/A 6362292SN/A while (!insts[tid].empty()) { 6372292SN/A inst = insts[tid].front(); 6382292SN/A 6392292SN/A insts[tid].pop(); 6402292SN/A 6417720Sgblack@eecs.umich.edu DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6422292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6437720Sgblack@eecs.umich.edu inst->pcState(),tid); 6442292SN/A 6452292SN/A skidBuffer[tid].push(inst); 6462292SN/A } 6472292SN/A 6482292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6492292SN/A "Skidbuffer Exceeded Max Size"); 6502292SN/A} 6512292SN/A 6522292SN/Atemplate<class Impl> 6532292SN/Aint 6542292SN/ADefaultIEW<Impl>::skidCount() 6552292SN/A{ 6562292SN/A int max=0; 6572292SN/A 6586221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6596221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6602292SN/A 6613867Sbinkertn@umich.edu while (threads != end) { 6626221Snate@binkert.org ThreadID tid = *threads++; 6633867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6642292SN/A if (max < thread_count) 6652292SN/A max = thread_count; 6662292SN/A } 6672292SN/A 6682292SN/A return max; 6692292SN/A} 6702292SN/A 6712292SN/Atemplate<class Impl> 6722292SN/Abool 6732292SN/ADefaultIEW<Impl>::skidsEmpty() 6742292SN/A{ 6756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6772292SN/A 6783867Sbinkertn@umich.edu while (threads != end) { 6796221Snate@binkert.org ThreadID tid = *threads++; 6803867Sbinkertn@umich.edu 6813867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6822292SN/A return false; 6832292SN/A } 6842292SN/A 6852292SN/A return true; 6861062SN/A} 6871062SN/A 6881681SN/Atemplate <class Impl> 6891062SN/Avoid 6902292SN/ADefaultIEW<Impl>::updateStatus() 6911062SN/A{ 6922292SN/A bool any_unblocking = false; 6931062SN/A 6946221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6956221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6961062SN/A 6973867Sbinkertn@umich.edu while (threads != end) { 6986221Snate@binkert.org ThreadID tid = *threads++; 6991062SN/A 7002292SN/A if (dispatchStatus[tid] == Unblocking) { 7012292SN/A any_unblocking = true; 7022292SN/A break; 7032292SN/A } 7042292SN/A } 7051062SN/A 7062292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7072292SN/A // and there's no stores waiting to write back, and dispatch is not 7082292SN/A // unblocking, then there is no internal activity for the IEW stage. 7097897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7102292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7112292SN/A !ldstQueue.willWB() && !any_unblocking) { 7122292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7131062SN/A 7142292SN/A deactivateStage(); 7151062SN/A 7162292SN/A _status = Inactive; 7172292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7182292SN/A ldstQueue.willWB() || 7192292SN/A any_unblocking)) { 7202292SN/A // Otherwise there is internal activity. Set to active. 7212292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7221062SN/A 7232292SN/A activateStage(); 7241062SN/A 7252292SN/A _status = Active; 7261062SN/A } 7271062SN/A} 7281062SN/A 7291681SN/Atemplate <class Impl> 7301062SN/Avoid 7312292SN/ADefaultIEW<Impl>::resetEntries() 7321062SN/A{ 7332292SN/A instQueue.resetEntries(); 7342292SN/A ldstQueue.resetEntries(); 7352292SN/A} 7361062SN/A 7372292SN/Atemplate <class Impl> 7382292SN/Avoid 7396221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7402292SN/A{ 7412292SN/A if (fromCommit->commitBlock[tid]) { 7422292SN/A stalls[tid].commit = true; 7432292SN/A } 7441062SN/A 7452292SN/A if (fromCommit->commitUnblock[tid]) { 7462292SN/A assert(stalls[tid].commit); 7472292SN/A stalls[tid].commit = false; 7482292SN/A } 7492292SN/A} 7502292SN/A 7512292SN/Atemplate <class Impl> 7522292SN/Abool 7536221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7542292SN/A{ 7552292SN/A bool ret_val(false); 7562292SN/A 7572292SN/A if (stalls[tid].commit) { 7582292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7592292SN/A ret_val = true; 7602292SN/A } else if (instQueue.isFull(tid)) { 7612292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7622292SN/A ret_val = true; 7632292SN/A } else if (ldstQueue.isFull(tid)) { 7642292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7652292SN/A 7662292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7672292SN/A 7682292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7692292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7702292SN/A } 7712292SN/A 7722292SN/A if (ldstQueue.numStores(tid) > 0) { 7732292SN/A 7742292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7752292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7762292SN/A } 7772292SN/A 7782292SN/A ret_val = true; 7792292SN/A } else if (ldstQueue.isStalled(tid)) { 7802292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7812292SN/A ret_val = true; 7822292SN/A } 7832292SN/A 7842292SN/A return ret_val; 7852292SN/A} 7862292SN/A 7872292SN/Atemplate <class Impl> 7882292SN/Avoid 7896221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7902292SN/A{ 7912292SN/A // Check if there's a squash signal, squash if there is 7922292SN/A // Check stall signals, block if there is. 7932292SN/A // If status was Blocked 7942292SN/A // if so then go to unblocking 7952292SN/A // If status was Squashing 7962292SN/A // check if squashing is not high. Switch to running this cycle. 7972292SN/A 7982292SN/A readStallSignals(tid); 7992292SN/A 8002292SN/A if (fromCommit->commitInfo[tid].squash) { 8012292SN/A squash(tid); 8022292SN/A 8032292SN/A if (dispatchStatus[tid] == Blocked || 8042292SN/A dispatchStatus[tid] == Unblocking) { 8052292SN/A toRename->iewUnblock[tid] = true; 8062292SN/A wroteToTimeBuffer = true; 8072292SN/A } 8082292SN/A 8092292SN/A dispatchStatus[tid] = Squashing; 8102292SN/A fetchRedirect[tid] = false; 8112292SN/A return; 8122292SN/A } 8132292SN/A 8142292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8152702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8162292SN/A 8172292SN/A dispatchStatus[tid] = Squashing; 8182702Sktlim@umich.edu emptyRenameInsts(tid); 8192702Sktlim@umich.edu wroteToTimeBuffer = true; 8202292SN/A return; 8212292SN/A } 8222292SN/A 8232292SN/A if (checkStall(tid)) { 8242292SN/A block(tid); 8252292SN/A dispatchStatus[tid] = Blocked; 8262292SN/A return; 8272292SN/A } 8282292SN/A 8292292SN/A if (dispatchStatus[tid] == Blocked) { 8302292SN/A // Status from previous cycle was blocked, but there are no more stall 8312292SN/A // conditions. Switch over to unblocking. 8322292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8332292SN/A tid); 8342292SN/A 8352292SN/A dispatchStatus[tid] = Unblocking; 8362292SN/A 8372292SN/A unblock(tid); 8382292SN/A 8392292SN/A return; 8402292SN/A } 8412292SN/A 8422292SN/A if (dispatchStatus[tid] == Squashing) { 8432292SN/A // Switch status to running if rename isn't being told to block or 8442292SN/A // squash this cycle. 8452292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8462292SN/A tid); 8472292SN/A 8482292SN/A dispatchStatus[tid] = Running; 8492292SN/A 8502292SN/A return; 8512292SN/A } 8522292SN/A} 8532292SN/A 8542292SN/Atemplate <class Impl> 8552292SN/Avoid 8562292SN/ADefaultIEW<Impl>::sortInsts() 8572292SN/A{ 8582292SN/A int insts_from_rename = fromRename->size; 8592326SN/A#ifdef DEBUG 8606221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8616221Snate@binkert.org assert(insts[tid].empty()); 8622326SN/A#endif 8632292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8642292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8652292SN/A } 8662292SN/A} 8672292SN/A 8682292SN/Atemplate <class Impl> 8692292SN/Avoid 8706221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8712702Sktlim@umich.edu{ 8724632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8732935Sksewell@umich.edu 8742702Sktlim@umich.edu while (!insts[tid].empty()) { 8752935Sksewell@umich.edu 8762702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8772702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8782702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8792702Sktlim@umich.edu } 8802702Sktlim@umich.edu 8812702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8822702Sktlim@umich.edu 8832702Sktlim@umich.edu insts[tid].pop(); 8842702Sktlim@umich.edu } 8852702Sktlim@umich.edu} 8862702Sktlim@umich.edu 8872702Sktlim@umich.edutemplate <class Impl> 8882702Sktlim@umich.eduvoid 8892292SN/ADefaultIEW<Impl>::wakeCPU() 8902292SN/A{ 8912292SN/A cpu->wakeCPU(); 8922292SN/A} 8932292SN/A 8942292SN/Atemplate <class Impl> 8952292SN/Avoid 8962292SN/ADefaultIEW<Impl>::activityThisCycle() 8972292SN/A{ 8982292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8992292SN/A cpu->activityThisCycle(); 9002292SN/A} 9012292SN/A 9022292SN/Atemplate <class Impl> 9032292SN/Ainline void 9042292SN/ADefaultIEW<Impl>::activateStage() 9052292SN/A{ 9062292SN/A DPRINTF(Activity, "Activating stage.\n"); 9072733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9082292SN/A} 9092292SN/A 9102292SN/Atemplate <class Impl> 9112292SN/Ainline void 9122292SN/ADefaultIEW<Impl>::deactivateStage() 9132292SN/A{ 9142292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9152733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9162292SN/A} 9172292SN/A 9182292SN/Atemplate<class Impl> 9192292SN/Avoid 9206221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9212292SN/A{ 9222292SN/A // If status is Running or idle, 9232292SN/A // call dispatchInsts() 9242292SN/A // If status is Unblocking, 9252292SN/A // buffer any instructions coming from rename 9262292SN/A // continue trying to empty skid buffer 9272292SN/A // check if stall conditions have passed 9282292SN/A 9292292SN/A if (dispatchStatus[tid] == Blocked) { 9302292SN/A ++iewBlockCycles; 9312292SN/A 9322292SN/A } else if (dispatchStatus[tid] == Squashing) { 9332292SN/A ++iewSquashCycles; 9342292SN/A } 9352292SN/A 9362292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9372292SN/A // will allow, as long as it is not currently blocked. 9382292SN/A if (dispatchStatus[tid] == Running || 9392292SN/A dispatchStatus[tid] == Idle) { 9402292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9412292SN/A "dispatch.\n", tid); 9422292SN/A 9432292SN/A dispatchInsts(tid); 9442292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9452292SN/A // Make sure that the skid buffer has something in it if the 9462292SN/A // status is unblocking. 9472292SN/A assert(!skidsEmpty()); 9482292SN/A 9492292SN/A // If the status was unblocking, then instructions from the skid 9502292SN/A // buffer were used. Remove those instructions and handle 9512292SN/A // the rest of unblocking. 9522292SN/A dispatchInsts(tid); 9532292SN/A 9542292SN/A ++iewUnblockCycles; 9552292SN/A 9565215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9572292SN/A // Add the current inputs to the skid buffer so they can be 9582292SN/A // reprocessed when this stage unblocks. 9592292SN/A skidInsert(tid); 9602292SN/A } 9612292SN/A 9622292SN/A unblock(tid); 9632292SN/A } 9642292SN/A} 9652292SN/A 9662292SN/Atemplate <class Impl> 9672292SN/Avoid 9686221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9692292SN/A{ 9702292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9712292SN/A // otherwise. 9722292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9732292SN/A dispatchStatus[tid] == Unblocking ? 9742292SN/A skidBuffer[tid] : insts[tid]; 9752292SN/A 9762292SN/A int insts_to_add = insts_to_dispatch.size(); 9772292SN/A 9782292SN/A DynInstPtr inst; 9792292SN/A bool add_to_iq = false; 9802292SN/A int dis_num_inst = 0; 9812292SN/A 9822292SN/A // Loop through the instructions, putting them in the instruction 9832292SN/A // queue. 9842292SN/A for ( ; dis_num_inst < insts_to_add && 9852820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9862292SN/A ++dis_num_inst) 9872292SN/A { 9882292SN/A inst = insts_to_dispatch.front(); 9892292SN/A 9902292SN/A if (dispatchStatus[tid] == Unblocking) { 9912292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9922292SN/A "buffer\n", tid); 9932292SN/A } 9942292SN/A 9952292SN/A // Make sure there's a valid instruction there. 9962292SN/A assert(inst); 9972292SN/A 9987720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9992292SN/A "IQ.\n", 10007720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10012292SN/A 10022292SN/A // Be sure to mark these instructions as ready so that the 10032292SN/A // commit stage can go ahead and execute them, and mark 10042292SN/A // them as issued so the IQ doesn't reprocess them. 10052292SN/A 10062292SN/A // Check for squashed instructions. 10072292SN/A if (inst->isSquashed()) { 10082292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10092292SN/A "not adding to IQ.\n", tid); 10102292SN/A 10112292SN/A ++iewDispSquashedInsts; 10122292SN/A 10132292SN/A insts_to_dispatch.pop(); 10142292SN/A 10152292SN/A //Tell Rename That An Instruction has been processed 10162292SN/A if (inst->isLoad() || inst->isStore()) { 10172292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10182292SN/A } 10192292SN/A toRename->iewInfo[tid].dispatched++; 10202292SN/A 10212292SN/A continue; 10222292SN/A } 10232292SN/A 10242292SN/A // Check for full conditions. 10252292SN/A if (instQueue.isFull(tid)) { 10262292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10272292SN/A 10282292SN/A // Call function to start blocking. 10292292SN/A block(tid); 10302292SN/A 10312292SN/A // Set unblock to false. Special case where we are using 10322292SN/A // skidbuffer (unblocking) instructions but then we still 10332292SN/A // get full in the IQ. 10342292SN/A toRename->iewUnblock[tid] = false; 10352292SN/A 10362292SN/A ++iewIQFullEvents; 10372292SN/A break; 10382292SN/A } else if (ldstQueue.isFull(tid)) { 10392292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10402292SN/A 10412292SN/A // Call function to start blocking. 10422292SN/A block(tid); 10432292SN/A 10442292SN/A // Set unblock to false. Special case where we are using 10452292SN/A // skidbuffer (unblocking) instructions but then we still 10462292SN/A // get full in the IQ. 10472292SN/A toRename->iewUnblock[tid] = false; 10482292SN/A 10492292SN/A ++iewLSQFullEvents; 10502292SN/A break; 10512292SN/A } 10522292SN/A 10532292SN/A // Otherwise issue the instruction just fine. 10542292SN/A if (inst->isLoad()) { 10552292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10562292SN/A "encountered, adding to LSQ.\n", tid); 10572292SN/A 10582292SN/A // Reserve a spot in the load store queue for this 10592292SN/A // memory access. 10602292SN/A ldstQueue.insertLoad(inst); 10612292SN/A 10622292SN/A ++iewDispLoadInsts; 10632292SN/A 10642292SN/A add_to_iq = true; 10652292SN/A 10662292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10672292SN/A } else if (inst->isStore()) { 10682292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10692292SN/A "encountered, adding to LSQ.\n", tid); 10702292SN/A 10712292SN/A ldstQueue.insertStore(inst); 10722292SN/A 10732292SN/A ++iewDispStoreInsts; 10742292SN/A 10752336SN/A if (inst->isStoreConditional()) { 10762336SN/A // Store conditionals need to be set as "canCommit()" 10772336SN/A // so that commit can process them when they reach the 10782336SN/A // head of commit. 10792348SN/A // @todo: This is somewhat specific to Alpha. 10802292SN/A inst->setCanCommit(); 10812292SN/A instQueue.insertNonSpec(inst); 10822292SN/A add_to_iq = false; 10832292SN/A 10842292SN/A ++iewDispNonSpecInsts; 10852292SN/A } else { 10862292SN/A add_to_iq = true; 10872292SN/A } 10882292SN/A 10892292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10902292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10912326SN/A // Same as non-speculative stores. 10922292SN/A inst->setCanCommit(); 10932292SN/A instQueue.insertBarrier(inst); 10942292SN/A add_to_iq = false; 10952292SN/A } else if (inst->isNop()) { 10962292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10972292SN/A "skipping.\n", tid); 10982292SN/A 10992292SN/A inst->setIssued(); 11002292SN/A inst->setExecuted(); 11012292SN/A inst->setCanCommit(); 11022292SN/A 11032326SN/A instQueue.recordProducer(inst); 11042292SN/A 11052727Sktlim@umich.edu iewExecutedNop[tid]++; 11062301SN/A 11072292SN/A add_to_iq = false; 11082292SN/A } else if (inst->isExecuted()) { 11092292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11102292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11112292SN/A "skipping.\n"); 11122292SN/A 11132292SN/A inst->setIssued(); 11142292SN/A inst->setCanCommit(); 11152292SN/A 11162326SN/A instQueue.recordProducer(inst); 11172292SN/A 11182292SN/A add_to_iq = false; 11192292SN/A } else { 11202292SN/A add_to_iq = true; 11212292SN/A } 11224033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11234033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11244033Sktlim@umich.edu "encountered, skipping.\n", tid); 11254033Sktlim@umich.edu 11264033Sktlim@umich.edu // Same as non-speculative stores. 11274033Sktlim@umich.edu inst->setCanCommit(); 11284033Sktlim@umich.edu 11294033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11304033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11314033Sktlim@umich.edu 11324033Sktlim@umich.edu ++iewDispNonSpecInsts; 11334033Sktlim@umich.edu 11344033Sktlim@umich.edu add_to_iq = false; 11354033Sktlim@umich.edu } 11362292SN/A 11372292SN/A // If the instruction queue is not full, then add the 11382292SN/A // instruction. 11392292SN/A if (add_to_iq) { 11402292SN/A instQueue.insert(inst); 11412292SN/A } 11422292SN/A 11432292SN/A insts_to_dispatch.pop(); 11442292SN/A 11452292SN/A toRename->iewInfo[tid].dispatched++; 11462292SN/A 11472292SN/A ++iewDispatchedInsts; 11488471SGiacomo.Gabrielli@arm.com 11498471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11509046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11518471SGiacomo.Gabrielli@arm.com#endif 11522292SN/A } 11532292SN/A 11542292SN/A if (!insts_to_dispatch.empty()) { 11552935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11562292SN/A block(tid); 11572292SN/A toRename->iewUnblock[tid] = false; 11582292SN/A } 11592292SN/A 11602292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11612292SN/A dispatchStatus[tid] = Running; 11622292SN/A 11632292SN/A updatedQueues = true; 11642292SN/A } 11652292SN/A 11662292SN/A dis_num_inst = 0; 11672292SN/A} 11682292SN/A 11692292SN/Atemplate <class Impl> 11702292SN/Avoid 11712292SN/ADefaultIEW<Impl>::printAvailableInsts() 11722292SN/A{ 11732292SN/A int inst = 0; 11742292SN/A 11752980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11762292SN/A 11772292SN/A while (fromIssue->insts[inst]) { 11782292SN/A 11792980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11802292SN/A 11817720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11822292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11832292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11842292SN/A 11852292SN/A inst++; 11862292SN/A 11872292SN/A } 11882292SN/A 11892980Sgblack@eecs.umich.edu std::cout << "\n"; 11902292SN/A} 11912292SN/A 11922292SN/Atemplate <class Impl> 11932292SN/Avoid 11942292SN/ADefaultIEW<Impl>::executeInsts() 11952292SN/A{ 11962292SN/A wbNumInst = 0; 11972292SN/A wbCycle = 0; 11982292SN/A 11996221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12006221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12012292SN/A 12023867Sbinkertn@umich.edu while (threads != end) { 12036221Snate@binkert.org ThreadID tid = *threads++; 12042292SN/A fetchRedirect[tid] = false; 12052292SN/A } 12062292SN/A 12072698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12087599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12092698Sktlim@umich.edu// printAvailableInsts(); 12101062SN/A 12111062SN/A // Execute/writeback any instructions that are available. 12122333SN/A int insts_to_execute = fromIssue->size; 12132292SN/A int inst_num = 0; 12142333SN/A for (; inst_num < insts_to_execute; 12152326SN/A ++inst_num) { 12161062SN/A 12172292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12181062SN/A 12192333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12201062SN/A 12217720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12227720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12231062SN/A 12241062SN/A // Check if the instruction is squashed; if so then skip it 12251062SN/A if (inst->isSquashed()) { 12268315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12278315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12288315Sgeoffrey.blake@arm.com inst->seqNum); 12291062SN/A 12301062SN/A // Consider this instruction executed so that commit can go 12311062SN/A // ahead and retire the instruction. 12321062SN/A inst->setExecuted(); 12331062SN/A 12342292SN/A // Not sure if I should set this here or just let commit try to 12352292SN/A // commit any squashed instructions. I like the latter a bit more. 12362292SN/A inst->setCanCommit(); 12371062SN/A 12381062SN/A ++iewExecSquashedInsts; 12391062SN/A 12402820Sktlim@umich.edu decrWb(inst->seqNum); 12411062SN/A continue; 12421062SN/A } 12431062SN/A 12442292SN/A Fault fault = NoFault; 12451062SN/A 12461062SN/A // Execute instruction. 12471062SN/A // Note that if the instruction faults, it will be handled 12481062SN/A // at the commit stage. 12497850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12502292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12511062SN/A "reference.\n"); 12521062SN/A 12531062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12541062SN/A if (inst->isLoad()) { 12552292SN/A // Loads will mark themselves as executed, and their writeback 12562292SN/A // event adds the instruction to the queue to commit 12572292SN/A fault = ldstQueue.executeLoad(inst); 12587944SGiacomo.Gabrielli@arm.com 12597944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12607944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12617944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12627944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12637944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12647944SGiacomo.Gabrielli@arm.com "load.\n"); 12657944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12667944SGiacomo.Gabrielli@arm.com continue; 12677944SGiacomo.Gabrielli@arm.com } 12687944SGiacomo.Gabrielli@arm.com 12697850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12708073SAli.Saidi@ARM.com inst->fault = NoFault; 12717850SMatt.Horsnell@arm.com } 12721062SN/A } else if (inst->isStore()) { 12732367SN/A fault = ldstQueue.executeStore(inst); 12741062SN/A 12757944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12767944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12777944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12787944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12797944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12807944SGiacomo.Gabrielli@arm.com "store.\n"); 12817944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12827944SGiacomo.Gabrielli@arm.com continue; 12837944SGiacomo.Gabrielli@arm.com } 12847944SGiacomo.Gabrielli@arm.com 12852292SN/A // If the store had a fault then it may not have a mem req 12867782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 12877782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12887782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12897782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12902367SN/A // Send this instruction to commit, also make sure iew stage 12912367SN/A // realizes there is activity. 12922367SN/A inst->setExecuted(); 12932367SN/A instToCommit(inst); 12942367SN/A activityThisCycle(); 12952292SN/A } 12962326SN/A 12972326SN/A // Store conditionals will mark themselves as 12982326SN/A // executed, and their writeback event will add the 12992326SN/A // instruction to the queue to commit. 13001062SN/A } else { 13012292SN/A panic("Unexpected memory type!\n"); 13021062SN/A } 13031062SN/A 13041062SN/A } else { 13057847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13067847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13077847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13087847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13097847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13107847Sminkyu.jeong@arm.com inst->execute(); 13117848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 13127848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13137847Sminkyu.jeong@arm.com } 13141062SN/A 13152292SN/A inst->setExecuted(); 13162292SN/A 13172292SN/A instToCommit(inst); 13181062SN/A } 13191062SN/A 13202301SN/A updateExeInstStats(inst); 13211681SN/A 13222326SN/A // Check if branch prediction was correct, if not then we need 13232326SN/A // to tell commit to squash in flight instructions. Only 13242326SN/A // handle this if there hasn't already been something that 13252107SN/A // redirects fetch in this group of instructions. 13261681SN/A 13272292SN/A // This probably needs to prioritize the redirects if a different 13282292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13292292SN/A // instruction first, so the branch resolution order will be correct. 13306221Snate@binkert.org ThreadID tid = inst->threadNumber; 13311062SN/A 13323732Sktlim@umich.edu if (!fetchRedirect[tid] || 13337852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13343732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13351062SN/A 13367856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13377856SMatt.Horsnell@arm.com // that have not been executed. 13387856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13397856SMatt.Horsnell@arm.com 13407856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13412292SN/A fetchRedirect[tid] = true; 13421062SN/A 13432292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13448674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13458674Snilay@cs.wisc.edu inst->readPredTarg()); 13467720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13478674Snilay@cs.wisc.edu inst->pcState()); 13481062SN/A // If incorrect, then signal the ROB that it must be squashed. 13492292SN/A squashDueToBranch(inst, tid); 13501062SN/A 13513795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13521062SN/A predictedTakenIncorrect++; 13532292SN/A } else { 13542292SN/A predictedNotTakenIncorrect++; 13551062SN/A } 13562292SN/A } else if (ldstQueue.violation(tid)) { 13574033Sktlim@umich.edu assert(inst->isMemRef()); 13582326SN/A // If there was an ordering violation, then get the 13592326SN/A // DynInst that caused the violation. Note that this 13602292SN/A // clears the violation signal. 13612292SN/A DynInstPtr violator; 13622292SN/A violator = ldstQueue.getMemDepViolator(tid); 13631062SN/A 13647720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13657720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13667720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13677720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13687720Sgblack@eecs.umich.edu 13693732Sktlim@umich.edu fetchRedirect[tid] = true; 13703732Sktlim@umich.edu 13711062SN/A // Tell the instruction queue that a violation has occured. 13721062SN/A instQueue.violation(inst, violator); 13731062SN/A 13741062SN/A // Squash. 13758513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13761062SN/A 13771062SN/A ++memOrderViolationEvents; 13782292SN/A } else if (ldstQueue.loadBlocked(tid) && 13792292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13802292SN/A fetchRedirect[tid] = true; 13812292SN/A 13822292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13837720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13847720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13852292SN/A 13862292SN/A squashDueToMemBlocked(inst, tid); 13871062SN/A } 13884033Sktlim@umich.edu } else { 13894033Sktlim@umich.edu // Reset any state associated with redirects that will not 13904033Sktlim@umich.edu // be used. 13914033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13924033Sktlim@umich.edu assert(inst->isMemRef()); 13934033Sktlim@umich.edu 13944033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13954033Sktlim@umich.edu 13964033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13977720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13987720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 13997720Sgblack@eecs.umich.edu inst->physEffAddr); 14004033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14014033Sktlim@umich.edu "already squashing\n"); 14024033Sktlim@umich.edu 14034033Sktlim@umich.edu ++memOrderViolationEvents; 14044033Sktlim@umich.edu } 14054033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14064033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14074033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14087720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14097720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14104033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14114033Sktlim@umich.edu "already squashing\n"); 14124033Sktlim@umich.edu 14134033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14144033Sktlim@umich.edu } 14154033Sktlim@umich.edu 14161062SN/A } 14171062SN/A } 14182292SN/A 14192348SN/A // Update and record activity if we processed any instructions. 14202292SN/A if (inst_num) { 14212292SN/A if (exeStatus == Idle) { 14222292SN/A exeStatus = Running; 14232292SN/A } 14242292SN/A 14252292SN/A updatedQueues = true; 14262292SN/A 14272292SN/A cpu->activityThisCycle(); 14282292SN/A } 14292292SN/A 14302292SN/A // Need to reset this in case a writeback event needs to write into the 14312292SN/A // iew queue. That way the writeback event will write into the correct 14322292SN/A // spot in the queue. 14332292SN/A wbNumInst = 0; 14347852SMatt.Horsnell@arm.com 14352107SN/A} 14362107SN/A 14372292SN/Atemplate <class Impl> 14382107SN/Avoid 14392292SN/ADefaultIEW<Impl>::writebackInsts() 14402107SN/A{ 14412326SN/A // Loop through the head of the time buffer and wake any 14422326SN/A // dependents. These instructions are about to write back. Also 14432326SN/A // mark scoreboard that this instruction is finally complete. 14442326SN/A // Either have IEW have direct access to scoreboard, or have this 14452326SN/A // as part of backwards communication. 14463958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14472292SN/A toCommit->insts[inst_num]; inst_num++) { 14482107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14496221Snate@binkert.org ThreadID tid = inst->threadNumber; 14502107SN/A 14517720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14527720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14532107SN/A 14542301SN/A iewInstsToCommit[tid]++; 14552301SN/A 14562292SN/A // Some instructions will be sent to commit without having 14572292SN/A // executed because they need commit to handle them. 14582292SN/A // E.g. Uncached loads have not actually executed when they 14592292SN/A // are first sent to commit. Instead commit must tell the LSQ 14602292SN/A // when it's ready to execute the uncached load. 14612367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14622301SN/A int dependents = instQueue.wakeDependents(inst); 14632107SN/A 14642292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14652292SN/A //mark as Ready 14662292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14672292SN/A inst->renamedDestRegIdx(i)); 14682292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14692107SN/A } 14702301SN/A 14712348SN/A if (dependents) { 14722348SN/A producerInst[tid]++; 14732348SN/A consumerInst[tid]+= dependents; 14742348SN/A } 14752326SN/A writebackCount[tid]++; 14762107SN/A } 14772820Sktlim@umich.edu 14782820Sktlim@umich.edu decrWb(inst->seqNum); 14792107SN/A } 14801060SN/A} 14811060SN/A 14821681SN/Atemplate<class Impl> 14831060SN/Avoid 14842292SN/ADefaultIEW<Impl>::tick() 14851060SN/A{ 14862292SN/A wbNumInst = 0; 14872292SN/A wbCycle = 0; 14881060SN/A 14892292SN/A wroteToTimeBuffer = false; 14902292SN/A updatedQueues = false; 14911060SN/A 14922292SN/A sortInsts(); 14931060SN/A 14942326SN/A // Free function units marked as being freed this cycle. 14952326SN/A fuPool->processFreeUnits(); 14961062SN/A 14976221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14986221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14991060SN/A 15002326SN/A // Check stall and squash signals, dispatch any instructions. 15013867Sbinkertn@umich.edu while (threads != end) { 15026221Snate@binkert.org ThreadID tid = *threads++; 15031060SN/A 15042292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15051060SN/A 15062292SN/A checkSignalsAndUpdate(tid); 15072292SN/A dispatch(tid); 15081060SN/A } 15091060SN/A 15102292SN/A if (exeStatus != Squashing) { 15112292SN/A executeInsts(); 15121060SN/A 15132292SN/A writebackInsts(); 15142292SN/A 15152292SN/A // Have the instruction queue try to schedule any ready instructions. 15162292SN/A // (In actuality, this scheduling is for instructions that will 15172292SN/A // be executed next cycle.) 15182292SN/A instQueue.scheduleReadyInsts(); 15192292SN/A 15202292SN/A // Also should advance its own time buffers if the stage ran. 15212292SN/A // Not the best place for it, but this works (hopefully). 15222292SN/A issueToExecQueue.advance(); 15232292SN/A } 15242292SN/A 15252292SN/A bool broadcast_free_entries = false; 15262292SN/A 15272292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15282292SN/A exeStatus = Idle; 15292292SN/A updateLSQNextCycle = false; 15302292SN/A 15312292SN/A broadcast_free_entries = true; 15322292SN/A } 15332292SN/A 15342292SN/A // Writeback any stores using any leftover bandwidth. 15351681SN/A ldstQueue.writebackStores(); 15361681SN/A 15371061SN/A // Check the committed load/store signals to see if there's a load 15381061SN/A // or store to commit. Also check if it's being told to execute a 15391061SN/A // nonspeculative instruction. 15401681SN/A // This is pretty inefficient... 15412292SN/A 15423867Sbinkertn@umich.edu threads = activeThreads->begin(); 15433867Sbinkertn@umich.edu while (threads != end) { 15446221Snate@binkert.org ThreadID tid = (*threads++); 15452292SN/A 15462292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15472292SN/A 15482348SN/A // Update structures based on instructions committed. 15492292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15502292SN/A !fromCommit->commitInfo[tid].squash && 15512292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15522292SN/A 15532292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15542292SN/A 15552292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15562292SN/A 15572292SN/A updateLSQNextCycle = true; 15582292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15592292SN/A } 15602292SN/A 15612292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15622292SN/A 15632292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15642292SN/A if (fromCommit->commitInfo[tid].uncached) { 15652292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15664033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15672292SN/A } else { 15682292SN/A instQueue.scheduleNonSpec( 15692292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15702292SN/A } 15712292SN/A } 15722292SN/A 15732292SN/A if (broadcast_free_entries) { 15742292SN/A toFetch->iewInfo[tid].iqCount = 15752292SN/A instQueue.getCount(tid); 15762292SN/A toFetch->iewInfo[tid].ldstqCount = 15772292SN/A ldstQueue.getCount(tid); 15782292SN/A 15792292SN/A toRename->iewInfo[tid].usedIQ = true; 15802292SN/A toRename->iewInfo[tid].freeIQEntries = 15812292SN/A instQueue.numFreeEntries(); 15822292SN/A toRename->iewInfo[tid].usedLSQ = true; 15832292SN/A toRename->iewInfo[tid].freeLSQEntries = 15842292SN/A ldstQueue.numFreeEntries(tid); 15852292SN/A 15862292SN/A wroteToTimeBuffer = true; 15872292SN/A } 15882292SN/A 15892292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15902292SN/A tid, toRename->iewInfo[tid].dispatched); 15911061SN/A } 15921061SN/A 15932292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15942292SN/A "LSQ has %i free entries.\n", 15952292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15962292SN/A ldstQueue.numFreeEntries()); 15972292SN/A 15982292SN/A updateStatus(); 15992292SN/A 16002292SN/A if (wroteToTimeBuffer) { 16012292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16022292SN/A cpu->activityThisCycle(); 16031061SN/A } 16041060SN/A} 16051060SN/A 16062301SN/Atemplate <class Impl> 16071060SN/Avoid 16082301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16091060SN/A{ 16106221Snate@binkert.org ThreadID tid = inst->threadNumber; 16111060SN/A 16122669Sktlim@umich.edu iewExecutedInsts++; 16131060SN/A 16148471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16159527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16169527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16179527SMatt.Horsnell@arm.com } 16188471SGiacomo.Gabrielli@arm.com#endif 16198471SGiacomo.Gabrielli@arm.com 16202301SN/A // 16212301SN/A // Control operations 16222301SN/A // 16232301SN/A if (inst->isControl()) 16246221Snate@binkert.org iewExecutedBranches[tid]++; 16251060SN/A 16262301SN/A // 16272301SN/A // Memory operations 16282301SN/A // 16292301SN/A if (inst->isMemRef()) { 16306221Snate@binkert.org iewExecutedRefs[tid]++; 16311060SN/A 16322301SN/A if (inst->isLoad()) { 16336221Snate@binkert.org iewExecLoadInsts[tid]++; 16341060SN/A } 16351060SN/A } 16361060SN/A} 16377598Sminkyu.jeong@arm.com 16387598Sminkyu.jeong@arm.comtemplate <class Impl> 16397598Sminkyu.jeong@arm.comvoid 16407598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16417598Sminkyu.jeong@arm.com{ 16427598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16437598Sminkyu.jeong@arm.com 16447598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16457852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16467598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16477598Sminkyu.jeong@arm.com 16487598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16497598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16507598Sminkyu.jeong@arm.com 16517598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16527598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16537720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16547598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16557720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16567720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16577598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16587598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16597598Sminkyu.jeong@arm.com 16607598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16617598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16627598Sminkyu.jeong@arm.com } else { 16637598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16647598Sminkyu.jeong@arm.com } 16657598Sminkyu.jeong@arm.com } 16667598Sminkyu.jeong@arm.com } 16677598Sminkyu.jeong@arm.com} 1668