iew_impl.hh revision 7856
12068SN/A/* 22068SN/A * Copyright (c) 2010 ARM Limited 32068SN/A * All rights reserved. 42068SN/A * 52068SN/A * The license below extends only to copyright in the software and shall 62068SN/A * not be construed as granting a license to any other intellectual 72068SN/A * property including but not limited to intellectual property relating 82068SN/A * to a hardware implementation of the functionality of the software 92068SN/A * licensed hereunder. You may use the software subject to the license 102068SN/A * terms below provided that you ensure that this notice is replicated 112068SN/A * unmodified and in its entirety in all distributions of the software, 122068SN/A * modified or unmodified, in source code or in binary form. 132068SN/A * 142068SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152068SN/A * All rights reserved. 162068SN/A * 172068SN/A * Redistribution and use in source and binary forms, with or without 182068SN/A * modification, are permitted provided that the following conditions are 192068SN/A * met: redistributions of source code must retain the above copyright 202068SN/A * notice, this list of conditions and the following disclaimer; 212068SN/A * redistributions in binary form must reproduce the above copyright 222068SN/A * notice, this list of conditions and the following disclaimer in the 232068SN/A * documentation and/or other materials provided with the distribution; 242068SN/A * neither the name of the copyright holders nor the names of its 252068SN/A * contributors may be used to endorse or promote products derived from 262068SN/A * this software without specific prior written permission. 272068SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312068SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322649Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332649Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342649Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352649Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362649Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372068SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382068SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392068SN/A * 402068SN/A * Authors: Kevin Lim 412068SN/A */ 422068SN/A 432068SN/A// @todo: Fix the instantaneous communication among all the stages within 442068SN/A// iew. There's a clear delay between issue and execute, yet backwards 452068SN/A// communication happens simultaneously. 465736Snate@binkert.org 472068SN/A#include <queue> 482107SN/A 492068SN/A#include "cpu/timebuf.hh" 502107SN/A#include "config/the_isa.hh" 512068SN/A#include "cpu/o3/fu_pool.hh" 522068SN/A#include "cpu/o3/iew.hh" 532227SN/A#include "params/DerivO3CPU.hh" 542107SN/A 552107SN/Ausing namespace std; 562068SN/A 575736Snate@binkert.orgtemplate<class Impl> 582068SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 592068SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 602068SN/A cpu(_cpu), 612068SN/A instQueue(_cpu, this, params), 622068SN/A ldstQueue(_cpu, this, params), 632068SN/A fuPool(params->fuPool), 642068SN/A commitToIEWDelay(params->commitToIEWDelay), 652068SN/A renameToIEWDelay(params->renameToIEWDelay), 662107SN/A issueToExecuteDelay(params->issueToExecuteDelay), 672107SN/A dispatchWidth(params->dispatchWidth), 682068SN/A issueWidth(params->issueWidth), 692068SN/A wbOutstanding(0), 702068SN/A wbWidth(params->wbWidth), 712068SN/A numThreads(params->numThreads), 722068SN/A switchedOut(false) 732068SN/A{ 742068SN/A _status = Active; 752068SN/A exeStatus = Running; 762068SN/A wbStatus = Idle; 772068SN/A 782068SN/A // Setup wire to read instructions coming from issue. 792068SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 802068SN/A 812227SN/A // Instruction queue needs the queue between issue and execute. 822107SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 832107SN/A 842068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 852068SN/A dispatchStatus[tid] = Running; 862068SN/A stalls[tid].commit = false; 872068SN/A fetchRedirect[tid] = false; 882068SN/A } 892068SN/A 902068SN/A wbMax = wbWidth * params->wbDepth; 912068SN/A 922068SN/A updateLSQNextCycle = false; 932068SN/A 942068SN/A ableToIssue = true; 952068SN/A 962068SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 972068SN/A} 982068SN/A 992068SN/Atemplate <class Impl> 1002227SN/Astd::string 1012107SN/ADefaultIEW<Impl>::name() const 1022107SN/A{ 1032068SN/A return cpu->name() + ".iew"; 1042068SN/A} 1052068SN/A 1062068SN/Atemplate <class Impl> 1072068SN/Avoid 1082068SN/ADefaultIEW<Impl>::regStats() 1092068SN/A{ 1102068SN/A using namespace Stats; 1112068SN/A 1122068SN/A instQueue.regStats(); 1132068SN/A ldstQueue.regStats(); 1142068SN/A 1152068SN/A iewIdleCycles 1162068SN/A .name(name() + ".iewIdleCycles") 1172068SN/A .desc("Number of cycles IEW is idle"); 1182068SN/A 1192068SN/A iewSquashCycles 1202068SN/A .name(name() + ".iewSquashCycles") 1212068SN/A .desc("Number of cycles IEW is squashing"); 1222068SN/A 1232068SN/A iewBlockCycles 1242068SN/A .name(name() + ".iewBlockCycles") 1252068SN/A .desc("Number of cycles IEW is blocking"); 1262068SN/A 1272068SN/A iewUnblockCycles 1282068SN/A .name(name() + ".iewUnblockCycles") 1293953Sstever@eecs.umich.edu .desc("Number of cycles IEW is unblocking"); 1302068SN/A 1312068SN/A iewDispatchedInsts 1322068SN/A .name(name() + ".iewDispatchedInsts") 1332068SN/A .desc("Number of instructions dispatched to IQ"); 1342068SN/A 1352068SN/A iewDispSquashedInsts 1362068SN/A .name(name() + ".iewDispSquashedInsts") 1372068SN/A .desc("Number of squashed instructions skipped by dispatch"); 1382068SN/A 1392068SN/A iewDispLoadInsts 1402068SN/A .name(name() + ".iewDispLoadInsts") 1412068SN/A .desc("Number of dispatched load instructions"); 1422068SN/A 1432068SN/A iewDispStoreInsts 1442068SN/A .name(name() + ".iewDispStoreInsts") 1452068SN/A .desc("Number of dispatched store instructions"); 1462068SN/A 1472068SN/A iewDispNonSpecInsts 1482068SN/A .name(name() + ".iewDispNonSpecInsts") 1492068SN/A .desc("Number of dispatched non-speculative instructions"); 1502068SN/A 1512068SN/A iewIQFullEvents 1522227SN/A .name(name() + ".iewIQFullEvents") 1532068SN/A .desc("Number of times the IQ has become full, causing a stall"); 1542068SN/A 1552068SN/A iewLSQFullEvents 1562068SN/A .name(name() + ".iewLSQFullEvents") 1572068SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1582068SN/A 1592068SN/A memOrderViolationEvents 1602068SN/A .name(name() + ".memOrderViolationEvents") 1612068SN/A .desc("Number of memory order violations"); 1622068SN/A 1632068SN/A predictedTakenIncorrect 1642227SN/A .name(name() + ".predictedTakenIncorrect") 1652068SN/A .desc("Number of branches that were predicted taken incorrectly"); 1662068SN/A 1672068SN/A predictedNotTakenIncorrect 1682068SN/A .name(name() + ".predictedNotTakenIncorrect") 1692068SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1702068SN/A 1712068SN/A branchMispredicts 1722227SN/A .name(name() + ".branchMispredicts") 1732068SN/A .desc("Number of branch mispredicts detected at execute"); 1742068SN/A 1752095SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1762095SN/A 1772095SN/A iewExecutedInsts 1782095SN/A .name(name() + ".iewExecutedInsts") 1792068SN/A .desc("Number of executed instructions"); 1802068SN/A 1812068SN/A iewExecLoadInsts 1822095SN/A .init(cpu->numThreads) 1832095SN/A .name(name() + ".iewExecLoadInsts") 1842132SN/A .desc("Number of load instructions executed") 1852095SN/A .flags(total); 1862095SN/A 1872095SN/A iewExecSquashedInsts 1882095SN/A .name(name() + ".iewExecSquashedInsts") 1893349Sbinkertn@umich.edu .desc("Number of squashed instructions skipped in execute"); 1902623SN/A 1912095SN/A iewExecutedSwp 1922095SN/A .init(cpu->numThreads) 1932095SN/A .name(name() + ".EXEC:swp") 1943953Sstever@eecs.umich.edu .desc("number of swp insts executed") 1952068SN/A .flags(total); 1962068SN/A 1972068SN/A iewExecutedNop 1982227SN/A .init(cpu->numThreads) 1992068SN/A .name(name() + ".EXEC:nop") 2002068SN/A .desc("number of nop insts executed") 2013953Sstever@eecs.umich.edu .flags(total); 2022068SN/A 2033953Sstever@eecs.umich.edu iewExecutedRefs 2042068SN/A .init(cpu->numThreads) 2053953Sstever@eecs.umich.edu .name(name() + ".EXEC:refs") 2063953Sstever@eecs.umich.edu .desc("number of memory reference insts executed") 2072227SN/A .flags(total); 2082068SN/A 2092068SN/A iewExecutedBranches 2103953Sstever@eecs.umich.edu .init(cpu->numThreads) 2112068SN/A .name(name() + ".EXEC:branches") 2123953Sstever@eecs.umich.edu .desc("Number of branches executed") 2132068SN/A .flags(total); 2143953Sstever@eecs.umich.edu 2153953Sstever@eecs.umich.edu iewExecStoreInsts 2162227SN/A .name(name() + ".EXEC:stores") 2172068SN/A .desc("Number of stores executed") 2182068SN/A .flags(total); 2192068SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2202068SN/A 2212068SN/A iewExecRate 2222068SN/A .name(name() + ".EXEC:rate") 2232068SN/A .desc("Inst execution rate") 2242068SN/A .flags(total); 2252068SN/A 2262132SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2272068SN/A 2282068SN/A iewInstsToCommit 2292068SN/A .init(cpu->numThreads) 2302068SN/A .name(name() + ".WB:sent") 2312132SN/A .desc("cumulative count of insts sent to commit") 2322068SN/A .flags(total); 2332068SN/A 2342068SN/A writebackCount 2352068SN/A .init(cpu->numThreads) 2363953Sstever@eecs.umich.edu .name(name() + ".WB:count") 2372068SN/A .desc("cumulative count of insts written-back") 2382090SN/A .flags(total); 2392068SN/A 2402068SN/A producerInst 2412068SN/A .init(cpu->numThreads) 2422068SN/A .name(name() + ".WB:producers") 2432068SN/A .desc("num instructions producing a value") 2442068SN/A .flags(total); 2452068SN/A 2462068SN/A consumerInst 2472069SN/A .init(cpu->numThreads) 2482132SN/A .name(name() + ".WB:consumers") 2492068SN/A .desc("num instructions consuming a value") 2502068SN/A .flags(total); 2512068SN/A 2522068SN/A wbPenalized 2532132SN/A .init(cpu->numThreads) 2542068SN/A .name(name() + ".WB:penalized") 2552068SN/A .desc("number of instrctions required to write to 'other' IQ") 2562068SN/A .flags(total); 2572069SN/A 2582068SN/A wbPenalizedRate 2592068SN/A .name(name() + ".WB:penalized_rate") 2602090SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2612069SN/A .flags(total); 2623953Sstever@eecs.umich.edu 2632068SN/A wbPenalizedRate = wbPenalized / writebackCount; 2642068SN/A 2652090SN/A wbFanout 2662069SN/A .name(name() + ".WB:fanout") 2672068SN/A .desc("average fanout of values written-back") 2682068SN/A .flags(total); 2692068SN/A 2702068SN/A wbFanout = producerInst / consumerInst; 2712068SN/A 2722068SN/A wbRate 2732068SN/A .name(name() + ".WB:rate") 2742069SN/A .desc("insts written-back per cycle") 2752132SN/A .flags(total); 2762068SN/A wbRate = writebackCount / cpu->numCycles; 2772068SN/A} 2782068SN/A 2792132SN/Atemplate<class Impl> 2802068SN/Avoid 2812068SN/ADefaultIEW<Impl>::initStage() 2822068SN/A{ 2832069SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2842068SN/A toRename->iewInfo[tid].usedIQ = true; 2852068SN/A toRename->iewInfo[tid].freeIQEntries = 2862090SN/A instQueue.numFreeEntries(tid); 2872069SN/A 2882068SN/A toRename->iewInfo[tid].usedLSQ = true; 2892068SN/A toRename->iewInfo[tid].freeLSQEntries = 2902068SN/A ldstQueue.numFreeEntries(tid); 2912090SN/A } 2922069SN/A 2932069SN/A cpu->activateStage(O3CPU::IEWIdx); 2942069SN/A} 2952069SN/A 2962069SN/Atemplate<class Impl> 2972069SN/Avoid 2982069SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2992069SN/A{ 3002095SN/A timeBuffer = tb_ptr; 3012132SN/A 3022095SN/A // Setup wire to read information from time buffer, from commit. 3032095SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3042095SN/A 3052132SN/A // Setup wire to write information back to previous stages. 3062095SN/A toRename = timeBuffer->getWire(0); 3072095SN/A 3082095SN/A toFetch = timeBuffer->getWire(0); 3092095SN/A 3102095SN/A // Instruction queue also needs main time buffer. 3112095SN/A instQueue.setTimeBuffer(tb_ptr); 3122098SN/A} 3132095SN/A 3142095SN/Atemplate<class Impl> 3152095SN/Avoid 3162095SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3172095SN/A{ 3182095SN/A renameQueue = rq_ptr; 3192095SN/A 3202095SN/A // Setup wire to read information from rename queue. 3212095SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3223349Sbinkertn@umich.edu} 3232095SN/A 3242095SN/Atemplate<class Impl> 3252095SN/Avoid 3262132SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3272095SN/A{ 3282095SN/A iewQueue = iq_ptr; 3292506SN/A 3302095SN/A // Setup wire to write instructions to commit. 3312623SN/A toCommit = iewQueue->getWire(0); 3322095SN/A} 3332098SN/A 3342095SN/Atemplate<class Impl> 3352095SN/Avoid 3362095SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3372098SN/A{ 3382095SN/A activeThreads = at_ptr; 3392095SN/A 3402095SN/A ldstQueue.setActiveThreads(at_ptr); 3412095SN/A instQueue.setActiveThreads(at_ptr); 3422095SN/A} 3432095SN/A 3442095SN/Atemplate<class Impl> 3452095SN/Avoid 3462069SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3472132SN/A{ 3482069SN/A scoreboard = sb_ptr; 3492069SN/A} 3502069SN/A 3512069SN/Atemplate <class Impl> 3522132SN/Abool 3534027Sstever@eecs.umich.eduDefaultIEW<Impl>::drain() 3544027Sstever@eecs.umich.edu{ 3554027Sstever@eecs.umich.edu // IEW is ready to drain at any time. 3564027Sstever@eecs.umich.edu cpu->signalDrained(); 3574027Sstever@eecs.umich.edu return true; 3584027Sstever@eecs.umich.edu} 3594027Sstever@eecs.umich.edu 3604027Sstever@eecs.umich.edutemplate <class Impl> 3614027Sstever@eecs.umich.eduvoid 3624027Sstever@eecs.umich.eduDefaultIEW<Impl>::resume() 3634027Sstever@eecs.umich.edu{ 3644027Sstever@eecs.umich.edu} 3654027Sstever@eecs.umich.edu 3664027Sstever@eecs.umich.edutemplate <class Impl> 3674027Sstever@eecs.umich.eduvoid 3684027Sstever@eecs.umich.eduDefaultIEW<Impl>::switchOut() 3694027Sstever@eecs.umich.edu{ 3704027Sstever@eecs.umich.edu // Clear any state. 3714027Sstever@eecs.umich.edu switchedOut = true; 3724027Sstever@eecs.umich.edu assert(insts[0].empty()); 3734027Sstever@eecs.umich.edu assert(skidBuffer[0].empty()); 3744027Sstever@eecs.umich.edu 3754027Sstever@eecs.umich.edu instQueue.switchOut(); 3764027Sstever@eecs.umich.edu ldstQueue.switchOut(); 3774027Sstever@eecs.umich.edu fuPool->switchOut(); 3784027Sstever@eecs.umich.edu 3794027Sstever@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3804027Sstever@eecs.umich.edu while (!insts[tid].empty()) 3814027Sstever@eecs.umich.edu insts[tid].pop(); 3824027Sstever@eecs.umich.edu while (!skidBuffer[tid].empty()) 3834027Sstever@eecs.umich.edu skidBuffer[tid].pop(); 3844027Sstever@eecs.umich.edu } 3854027Sstever@eecs.umich.edu} 3864027Sstever@eecs.umich.edu 3874027Sstever@eecs.umich.edutemplate <class Impl> 3882069SN/Avoid 3892069SN/ADefaultIEW<Impl>::takeOverFrom() 3902069SN/A{ 3912069SN/A // Reset all state. 3922069SN/A _status = Active; 3932069SN/A exeStatus = Running; 3942069SN/A wbStatus = Idle; 3952090SN/A switchedOut = false; 3963953Sstever@eecs.umich.edu 3972069SN/A instQueue.takeOverFrom(); 3982069SN/A ldstQueue.takeOverFrom(); 3992090SN/A fuPool->takeOverFrom(); 4002069SN/A 4012069SN/A initStage(); 4022069SN/A cpu->activityThisCycle(); 4032068SN/A 4042068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4052090SN/A dispatchStatus[tid] = Running; 4062068SN/A stalls[tid].commit = false; 4072068SN/A fetchRedirect[tid] = false; 4082068SN/A } 4092090SN/A 4102069SN/A updateLSQNextCycle = false; 4112068SN/A 4122068SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4132068SN/A issueToExecQueue.advance(); 4142068SN/A } 4152068SN/A} 4162068SN/A 4172068SN/Atemplate<class Impl> 4182069SN/Avoid 4192132SN/ADefaultIEW<Impl>::squash(ThreadID tid) 4202069SN/A{ 4212069SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4222069SN/A 4232132SN/A // Tell the IQ to start squashing. 4244027Sstever@eecs.umich.edu instQueue.squash(tid); 4254027Sstever@eecs.umich.edu 4264027Sstever@eecs.umich.edu // Tell the LDSTQ to start squashing. 4274027Sstever@eecs.umich.edu ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4284027Sstever@eecs.umich.edu updatedQueues = true; 4294027Sstever@eecs.umich.edu 4304027Sstever@eecs.umich.edu // Clear the skid buffer in case it has any data in it. 4314027Sstever@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4324027Sstever@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4334027Sstever@eecs.umich.edu 4344027Sstever@eecs.umich.edu while (!skidBuffer[tid].empty()) { 4354027Sstever@eecs.umich.edu if (skidBuffer[tid].front()->isLoad() || 4364027Sstever@eecs.umich.edu skidBuffer[tid].front()->isStore() ) { 4374027Sstever@eecs.umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 4384027Sstever@eecs.umich.edu } 4394027Sstever@eecs.umich.edu 4404027Sstever@eecs.umich.edu toRename->iewInfo[tid].dispatched++; 4414027Sstever@eecs.umich.edu 4424027Sstever@eecs.umich.edu skidBuffer[tid].pop(); 4434027Sstever@eecs.umich.edu } 4444027Sstever@eecs.umich.edu 4454027Sstever@eecs.umich.edu emptyRenameInsts(tid); 4464027Sstever@eecs.umich.edu} 4474027Sstever@eecs.umich.edu 4484027Sstever@eecs.umich.edutemplate<class Impl> 4494027Sstever@eecs.umich.eduvoid 4504027Sstever@eecs.umich.eduDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4514027Sstever@eecs.umich.edu{ 4524027Sstever@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4534027Sstever@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4544027Sstever@eecs.umich.edu 4554027Sstever@eecs.umich.edu if (toCommit->squash[tid] == false || 4564027Sstever@eecs.umich.edu inst->seqNum < toCommit->squashedSeqNum[tid]) { 4574027Sstever@eecs.umich.edu toCommit->squash[tid] = true; 4582069SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4592069SN/A toCommit->mispredPC[tid] = inst->instAddr(); 4602069SN/A toCommit->branchMispredict[tid] = true; 4612069SN/A toCommit->branchTaken[tid] = inst->pcState().branching(); 4622069SN/A 4632069SN/A TheISA::PCState pc = inst->pcState(); 4642069SN/A TheISA::advancePC(pc, inst->staticInst); 4652090SN/A 4662069SN/A toCommit->pc[tid] = pc; 4672069SN/A toCommit->mispredictInst[tid] = inst; 4682069SN/A toCommit->includeSquashInst[tid] = false; 4692090SN/A 4702069SN/A wroteToTimeBuffer = true; 4712069SN/A } 4722069SN/A 4732069SN/A} 4742069SN/A 4752090SN/Atemplate<class Impl> 4762069SN/Avoid 4772069SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4782069SN/A{ 4792090SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4802069SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4812069SN/A 4822069SN/A if (toCommit->squash[tid] == false || 4832069SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4842069SN/A toCommit->squash[tid] = true; 4852069SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4862069SN/A TheISA::PCState pc = inst->pcState(); 4872095SN/A TheISA::advancePC(pc, inst->staticInst); 4882132SN/A toCommit->pc[tid] = pc; 4892095SN/A toCommit->branchMispredict[tid] = false; 4902095SN/A 4912095SN/A toCommit->includeSquashInst[tid] = false; 4922132SN/A 4932095SN/A wroteToTimeBuffer = true; 4942095SN/A } 4952506SN/A} 4962095SN/A 4972095SN/Atemplate<class Impl> 4982095SN/Avoid 4992098SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5002095SN/A{ 5012095SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5022095SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5032098SN/A if (toCommit->squash[tid] == false || 5042095SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 5052623SN/A toCommit->squash[tid] = true; 5062095SN/A 5072095SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5082095SN/A toCommit->pc[tid] = inst->pcState(); 5092095SN/A toCommit->branchMispredict[tid] = false; 5102095SN/A 5112095SN/A // Must include the broadcasted SN in the squash. 5122095SN/A toCommit->includeSquashInst[tid] = true; 5132095SN/A 5142095SN/A ldstQueue.setLoadBlockedHandled(tid); 5153349Sbinkertn@umich.edu 5162095SN/A wroteToTimeBuffer = true; 5172095SN/A } 5182095SN/A} 5192132SN/A 5202095SN/Atemplate<class Impl> 5212095SN/Avoid 5222095SN/ADefaultIEW<Impl>::block(ThreadID tid) 5232095SN/A{ 5242623SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5252623SN/A 5262623SN/A if (dispatchStatus[tid] != Blocked && 5272623SN/A dispatchStatus[tid] != Unblocking) { 5282623SN/A toRename->iewBlock[tid] = true; 5292623SN/A wroteToTimeBuffer = true; 5302623SN/A } 5312623SN/A 5322623SN/A // Add the current inputs to the skid buffer so they can be 5332623SN/A // reprocessed when this stage unblocks. 5342623SN/A skidInsert(tid); 5352623SN/A 5362623SN/A dispatchStatus[tid] = Blocked; 5372623SN/A} 5383349Sbinkertn@umich.edu 5392623SN/Atemplate<class Impl> 5402623SN/Avoid 5412623SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5422623SN/A{ 5432623SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5442623SN/A "buffer %u.\n",tid, tid); 5452623SN/A 5462623SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5474040Ssaidi@eecs.umich.edu // Also switch status to running. 5482095SN/A if (skidBuffer[tid].empty()) { 5492098SN/A toRename->iewUnblock[tid] = true; 5502095SN/A wroteToTimeBuffer = true; 5512095SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5522095SN/A dispatchStatus[tid] = Running; 5532098SN/A } 5542095SN/A} 5552095SN/A 5562095SN/Atemplate<class Impl> 5572095SN/Avoid 5582095SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5592095SN/A{ 5602095SN/A instQueue.wakeDependents(inst); 5612069SN/A} 5622069SN/A 5632132SN/Atemplate<class Impl> 5642069SN/Avoid 5652069SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5662069SN/A{ 5672132SN/A instQueue.rescheduleMemInst(inst); 5682069SN/A} 5692069SN/A 5702069SN/Atemplate<class Impl> 5712069SN/Avoid 5722069SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5732069SN/A{ 5742090SN/A instQueue.replayMemInst(inst); 5753953Sstever@eecs.umich.edu} 5762069SN/A 5772069SN/Atemplate<class Impl> 5782090SN/Avoid 5792069SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5802069SN/A{ 5812069SN/A // This function should not be called after writebackInsts in a 5822069SN/A // single cycle. That will cause problems with an instruction 5832132SN/A // being added to the queue to commit without being processed by 5842068SN/A // writebackInsts prior to being sent to commit. 5852068SN/A 5862068SN/A // First check the time slot that this instruction will write 5872132SN/A // to. If there are free write ports at the time, then go ahead 5882068SN/A // and write the instruction to that time. If there are not, 5892068SN/A // keep looking back to see where's the first time there's a 5902068SN/A // free slot. 5912069SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5922068SN/A ++wbNumInst; 5932068SN/A if (wbNumInst == wbWidth) { 5942090SN/A ++wbCycle; 5952069SN/A wbNumInst = 0; 5962068SN/A } 5972068SN/A 5982090SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5992068SN/A } 6002068SN/A 6012068SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6022095SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6032132SN/A // Add finished instruction to queue to commit. 6042095SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6052095SN/A (*iewQueue)[wbCycle].size++; 6062355SN/A} 6072098SN/A 6082095SN/Atemplate <class Impl> 6092095SN/Aunsigned 6102095SN/ADefaultIEW<Impl>::validInstsFromRename() 6112095SN/A{ 6122095SN/A unsigned inst_count = 0; 6133349Sbinkertn@umich.edu 6142095SN/A for (int i=0; i<fromRename->size; i++) { 6152095SN/A if (!fromRename->insts[i]->isSquashed()) 6162095SN/A inst_count++; 6172355SN/A } 6182110SN/A 6192098SN/A return inst_count; 6202095SN/A} 6212095SN/A 6222095SN/Atemplate<class Impl> 6232068SN/Avoid 6242068SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6252068SN/A{ 6262068SN/A DynInstPtr inst = NULL; 6272068SN/A 6282068SN/A while (!insts[tid].empty()) { 6292068SN/A inst = insts[tid].front(); 6302068SN/A 6312068SN/A insts[tid].pop(); 6322068SN/A 6332068SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6342068SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6352068SN/A inst->pcState(),tid); 6362068SN/A 6372068SN/A skidBuffer[tid].push(inst); 6382068SN/A } 6392068SN/A 6402068SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6412068SN/A "Skidbuffer Exceeded Max Size"); 6422068SN/A} 6432068SN/A 6442068SN/Atemplate<class Impl> 6452068SN/Aint 6462068SN/ADefaultIEW<Impl>::skidCount() 6472068SN/A{ 6482068SN/A int max=0; 6492068SN/A 6502075SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6512075SN/A list<ThreadID>::iterator end = activeThreads->end(); 6522069SN/A 6532075SN/A while (threads != end) { 6542075SN/A ThreadID tid = *threads++; 6552075SN/A unsigned thread_count = skidBuffer[tid].size(); 6562068SN/A if (max < thread_count) 6572068SN/A max = thread_count; 6582068SN/A } 6592068SN/A 6602068SN/A return max; 6612068SN/A} 6622068SN/A 6632068SN/Atemplate<class Impl> 6642068SN/Abool 6652068SN/ADefaultIEW<Impl>::skidsEmpty() 6663953Sstever@eecs.umich.edu{ 6673953Sstever@eecs.umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 6683953Sstever@eecs.umich.edu list<ThreadID>::iterator end = activeThreads->end(); 6693953Sstever@eecs.umich.edu 6703953Sstever@eecs.umich.edu while (threads != end) { 6713953Sstever@eecs.umich.edu ThreadID tid = *threads++; 6723953Sstever@eecs.umich.edu 6733953Sstever@eecs.umich.edu if (!skidBuffer[tid].empty()) 6743953Sstever@eecs.umich.edu return false; 6753953Sstever@eecs.umich.edu } 6763953Sstever@eecs.umich.edu 6773953Sstever@eecs.umich.edu return true; 6782068SN/A} 6792068SN/A 6805736Snate@binkert.orgtemplate <class Impl> 6815736Snate@binkert.orgvoid 6822068SN/ADefaultIEW<Impl>::updateStatus() 6832068SN/A{ 6842068SN/A bool any_unblocking = false; 6852069SN/A 6862623SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6874027Sstever@eecs.umich.edu list<ThreadID>::iterator end = activeThreads->end(); 6884027Sstever@eecs.umich.edu 6892623SN/A while (threads != end) { 6902623SN/A ThreadID tid = *threads++; 6912069SN/A 6922069SN/A if (dispatchStatus[tid] == Unblocking) { 6932095SN/A any_unblocking = true; 6942095SN/A break; 6952069SN/A } 6962068SN/A } 6973953Sstever@eecs.umich.edu 6983953Sstever@eecs.umich.edu // If there are no ready instructions waiting to be scheduled by the IQ, 6993953Sstever@eecs.umich.edu // and there's no stores waiting to write back, and dispatch is not 7003953Sstever@eecs.umich.edu // unblocking, then there is no internal activity for the IEW stage. 7012068SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7022068SN/A !ldstQueue.willWB() && !any_unblocking) { 7032069SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7042095SN/A 7053953Sstever@eecs.umich.edu deactivateStage(); 7063953Sstever@eecs.umich.edu 7072068SN/A _status = Inactive; 7082068SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7092075SN/A ldstQueue.willWB() || 7102075SN/A any_unblocking)) { 7112068SN/A // Otherwise there is internal activity. Set to active. 7122075SN/A DPRINTF(IEW, "IEW switching to active\n"); 7132069SN/A 7142069SN/A activateStage(); 7152068SN/A 7162068SN/A _status = Active; 7172068SN/A } 7182068SN/A} 7192075SN/A 7202075SN/Atemplate <class Impl> 7212068SN/Avoid 7222068SN/ADefaultIEW<Impl>::resetEntries() 7232075SN/A{ 7242069SN/A instQueue.resetEntries(); 7252069SN/A ldstQueue.resetEntries(); 7262068SN/A} 7272068SN/A 7282068SN/Atemplate <class Impl> 7292075SN/Avoid 7302075SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7312075SN/A{ 7322075SN/A if (fromCommit->commitBlock[tid]) { 7332075SN/A stalls[tid].commit = true; 7342075SN/A } 7352075SN/A 7362075SN/A if (fromCommit->commitUnblock[tid]) { 7372068SN/A assert(stalls[tid].commit); 7382068SN/A stalls[tid].commit = false; 7392069SN/A } 7402069SN/A} 7412075SN/A 7422068SN/Atemplate <class Impl> 7432068SN/Abool 7442068SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7452068SN/A{ 7462068SN/A bool ret_val(false); 7472068SN/A 7482068SN/A if (stalls[tid].commit) { 7492075SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7502075SN/A ret_val = true; 7512068SN/A } else if (instQueue.isFull(tid)) { 7522075SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7532069SN/A ret_val = true; 7542068SN/A } else if (ldstQueue.isFull(tid)) { 7552068SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7562068SN/A 7572075SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7582075SN/A 7592075SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7602068SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7612075SN/A } 7622623SN/A 7632068SN/A if (ldstQueue.numStores(tid) > 0) { 7642068SN/A 7652068SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7662068SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7672075SN/A } 7682075SN/A 7692068SN/A ret_val = true; 7702075SN/A } else if (ldstQueue.isStalled(tid)) { 7712069SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7722068SN/A ret_val = true; 7732068SN/A } 7742068SN/A 775 return ret_val; 776} 777 778template <class Impl> 779void 780DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 781{ 782 // Check if there's a squash signal, squash if there is 783 // Check stall signals, block if there is. 784 // If status was Blocked 785 // if so then go to unblocking 786 // If status was Squashing 787 // check if squashing is not high. Switch to running this cycle. 788 789 readStallSignals(tid); 790 791 if (fromCommit->commitInfo[tid].squash) { 792 squash(tid); 793 794 if (dispatchStatus[tid] == Blocked || 795 dispatchStatus[tid] == Unblocking) { 796 toRename->iewUnblock[tid] = true; 797 wroteToTimeBuffer = true; 798 } 799 800 dispatchStatus[tid] = Squashing; 801 fetchRedirect[tid] = false; 802 return; 803 } 804 805 if (fromCommit->commitInfo[tid].robSquashing) { 806 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 807 808 dispatchStatus[tid] = Squashing; 809 emptyRenameInsts(tid); 810 wroteToTimeBuffer = true; 811 return; 812 } 813 814 if (checkStall(tid)) { 815 block(tid); 816 dispatchStatus[tid] = Blocked; 817 return; 818 } 819 820 if (dispatchStatus[tid] == Blocked) { 821 // Status from previous cycle was blocked, but there are no more stall 822 // conditions. Switch over to unblocking. 823 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 824 tid); 825 826 dispatchStatus[tid] = Unblocking; 827 828 unblock(tid); 829 830 return; 831 } 832 833 if (dispatchStatus[tid] == Squashing) { 834 // Switch status to running if rename isn't being told to block or 835 // squash this cycle. 836 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 837 tid); 838 839 dispatchStatus[tid] = Running; 840 841 return; 842 } 843} 844 845template <class Impl> 846void 847DefaultIEW<Impl>::sortInsts() 848{ 849 int insts_from_rename = fromRename->size; 850#ifdef DEBUG 851 for (ThreadID tid = 0; tid < numThreads; tid++) 852 assert(insts[tid].empty()); 853#endif 854 for (int i = 0; i < insts_from_rename; ++i) { 855 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 856 } 857} 858 859template <class Impl> 860void 861DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 862{ 863 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 864 865 while (!insts[tid].empty()) { 866 867 if (insts[tid].front()->isLoad() || 868 insts[tid].front()->isStore() ) { 869 toRename->iewInfo[tid].dispatchedToLSQ++; 870 } 871 872 toRename->iewInfo[tid].dispatched++; 873 874 insts[tid].pop(); 875 } 876} 877 878template <class Impl> 879void 880DefaultIEW<Impl>::wakeCPU() 881{ 882 cpu->wakeCPU(); 883} 884 885template <class Impl> 886void 887DefaultIEW<Impl>::activityThisCycle() 888{ 889 DPRINTF(Activity, "Activity this cycle.\n"); 890 cpu->activityThisCycle(); 891} 892 893template <class Impl> 894inline void 895DefaultIEW<Impl>::activateStage() 896{ 897 DPRINTF(Activity, "Activating stage.\n"); 898 cpu->activateStage(O3CPU::IEWIdx); 899} 900 901template <class Impl> 902inline void 903DefaultIEW<Impl>::deactivateStage() 904{ 905 DPRINTF(Activity, "Deactivating stage.\n"); 906 cpu->deactivateStage(O3CPU::IEWIdx); 907} 908 909template<class Impl> 910void 911DefaultIEW<Impl>::dispatch(ThreadID tid) 912{ 913 // If status is Running or idle, 914 // call dispatchInsts() 915 // If status is Unblocking, 916 // buffer any instructions coming from rename 917 // continue trying to empty skid buffer 918 // check if stall conditions have passed 919 920 if (dispatchStatus[tid] == Blocked) { 921 ++iewBlockCycles; 922 923 } else if (dispatchStatus[tid] == Squashing) { 924 ++iewSquashCycles; 925 } 926 927 // Dispatch should try to dispatch as many instructions as its bandwidth 928 // will allow, as long as it is not currently blocked. 929 if (dispatchStatus[tid] == Running || 930 dispatchStatus[tid] == Idle) { 931 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 932 "dispatch.\n", tid); 933 934 dispatchInsts(tid); 935 } else if (dispatchStatus[tid] == Unblocking) { 936 // Make sure that the skid buffer has something in it if the 937 // status is unblocking. 938 assert(!skidsEmpty()); 939 940 // If the status was unblocking, then instructions from the skid 941 // buffer were used. Remove those instructions and handle 942 // the rest of unblocking. 943 dispatchInsts(tid); 944 945 ++iewUnblockCycles; 946 947 if (validInstsFromRename()) { 948 // Add the current inputs to the skid buffer so they can be 949 // reprocessed when this stage unblocks. 950 skidInsert(tid); 951 } 952 953 unblock(tid); 954 } 955} 956 957template <class Impl> 958void 959DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 960{ 961 // Obtain instructions from skid buffer if unblocking, or queue from rename 962 // otherwise. 963 std::queue<DynInstPtr> &insts_to_dispatch = 964 dispatchStatus[tid] == Unblocking ? 965 skidBuffer[tid] : insts[tid]; 966 967 int insts_to_add = insts_to_dispatch.size(); 968 969 DynInstPtr inst; 970 bool add_to_iq = false; 971 int dis_num_inst = 0; 972 973 // Loop through the instructions, putting them in the instruction 974 // queue. 975 for ( ; dis_num_inst < insts_to_add && 976 dis_num_inst < dispatchWidth; 977 ++dis_num_inst) 978 { 979 inst = insts_to_dispatch.front(); 980 981 if (dispatchStatus[tid] == Unblocking) { 982 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 983 "buffer\n", tid); 984 } 985 986 // Make sure there's a valid instruction there. 987 assert(inst); 988 989 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 990 "IQ.\n", 991 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 992 993 // Be sure to mark these instructions as ready so that the 994 // commit stage can go ahead and execute them, and mark 995 // them as issued so the IQ doesn't reprocess them. 996 997 // Check for squashed instructions. 998 if (inst->isSquashed()) { 999 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1000 "not adding to IQ.\n", tid); 1001 1002 ++iewDispSquashedInsts; 1003 1004 insts_to_dispatch.pop(); 1005 1006 //Tell Rename That An Instruction has been processed 1007 if (inst->isLoad() || inst->isStore()) { 1008 toRename->iewInfo[tid].dispatchedToLSQ++; 1009 } 1010 toRename->iewInfo[tid].dispatched++; 1011 1012 continue; 1013 } 1014 1015 // Check for full conditions. 1016 if (instQueue.isFull(tid)) { 1017 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1018 1019 // Call function to start blocking. 1020 block(tid); 1021 1022 // Set unblock to false. Special case where we are using 1023 // skidbuffer (unblocking) instructions but then we still 1024 // get full in the IQ. 1025 toRename->iewUnblock[tid] = false; 1026 1027 ++iewIQFullEvents; 1028 break; 1029 } else if (ldstQueue.isFull(tid)) { 1030 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1031 1032 // Call function to start blocking. 1033 block(tid); 1034 1035 // Set unblock to false. Special case where we are using 1036 // skidbuffer (unblocking) instructions but then we still 1037 // get full in the IQ. 1038 toRename->iewUnblock[tid] = false; 1039 1040 ++iewLSQFullEvents; 1041 break; 1042 } 1043 1044 // Otherwise issue the instruction just fine. 1045 if (inst->isLoad()) { 1046 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1047 "encountered, adding to LSQ.\n", tid); 1048 1049 // Reserve a spot in the load store queue for this 1050 // memory access. 1051 ldstQueue.insertLoad(inst); 1052 1053 ++iewDispLoadInsts; 1054 1055 add_to_iq = true; 1056 1057 toRename->iewInfo[tid].dispatchedToLSQ++; 1058 } else if (inst->isStore()) { 1059 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1060 "encountered, adding to LSQ.\n", tid); 1061 1062 ldstQueue.insertStore(inst); 1063 1064 ++iewDispStoreInsts; 1065 1066 if (inst->isStoreConditional()) { 1067 // Store conditionals need to be set as "canCommit()" 1068 // so that commit can process them when they reach the 1069 // head of commit. 1070 // @todo: This is somewhat specific to Alpha. 1071 inst->setCanCommit(); 1072 instQueue.insertNonSpec(inst); 1073 add_to_iq = false; 1074 1075 ++iewDispNonSpecInsts; 1076 } else { 1077 add_to_iq = true; 1078 } 1079 1080 toRename->iewInfo[tid].dispatchedToLSQ++; 1081 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1082 // Same as non-speculative stores. 1083 inst->setCanCommit(); 1084 instQueue.insertBarrier(inst); 1085 add_to_iq = false; 1086 } else if (inst->isNop()) { 1087 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1088 "skipping.\n", tid); 1089 1090 inst->setIssued(); 1091 inst->setExecuted(); 1092 inst->setCanCommit(); 1093 1094 instQueue.recordProducer(inst); 1095 1096 iewExecutedNop[tid]++; 1097 1098 add_to_iq = false; 1099 } else if (inst->isExecuted()) { 1100 assert(0 && "Instruction shouldn't be executed.\n"); 1101 DPRINTF(IEW, "Issue: Executed branch encountered, " 1102 "skipping.\n"); 1103 1104 inst->setIssued(); 1105 inst->setCanCommit(); 1106 1107 instQueue.recordProducer(inst); 1108 1109 add_to_iq = false; 1110 } else { 1111 add_to_iq = true; 1112 } 1113 if (inst->isNonSpeculative()) { 1114 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1115 "encountered, skipping.\n", tid); 1116 1117 // Same as non-speculative stores. 1118 inst->setCanCommit(); 1119 1120 // Specifically insert it as nonspeculative. 1121 instQueue.insertNonSpec(inst); 1122 1123 ++iewDispNonSpecInsts; 1124 1125 add_to_iq = false; 1126 } 1127 1128 // If the instruction queue is not full, then add the 1129 // instruction. 1130 if (add_to_iq) { 1131 instQueue.insert(inst); 1132 } 1133 1134 insts_to_dispatch.pop(); 1135 1136 toRename->iewInfo[tid].dispatched++; 1137 1138 ++iewDispatchedInsts; 1139 } 1140 1141 if (!insts_to_dispatch.empty()) { 1142 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1143 block(tid); 1144 toRename->iewUnblock[tid] = false; 1145 } 1146 1147 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1148 dispatchStatus[tid] = Running; 1149 1150 updatedQueues = true; 1151 } 1152 1153 dis_num_inst = 0; 1154} 1155 1156template <class Impl> 1157void 1158DefaultIEW<Impl>::printAvailableInsts() 1159{ 1160 int inst = 0; 1161 1162 std::cout << "Available Instructions: "; 1163 1164 while (fromIssue->insts[inst]) { 1165 1166 if (inst%3==0) std::cout << "\n\t"; 1167 1168 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1169 << " TN: " << fromIssue->insts[inst]->threadNumber 1170 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1171 1172 inst++; 1173 1174 } 1175 1176 std::cout << "\n"; 1177} 1178 1179template <class Impl> 1180void 1181DefaultIEW<Impl>::executeInsts() 1182{ 1183 wbNumInst = 0; 1184 wbCycle = 0; 1185 1186 list<ThreadID>::iterator threads = activeThreads->begin(); 1187 list<ThreadID>::iterator end = activeThreads->end(); 1188 1189 while (threads != end) { 1190 ThreadID tid = *threads++; 1191 fetchRedirect[tid] = false; 1192 } 1193 1194 // Uncomment this if you want to see all available instructions. 1195 // @todo This doesn't actually work anymore, we should fix it. 1196// printAvailableInsts(); 1197 1198 // Execute/writeback any instructions that are available. 1199 int insts_to_execute = fromIssue->size; 1200 int inst_num = 0; 1201 for (; inst_num < insts_to_execute; 1202 ++inst_num) { 1203 1204 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1205 1206 DynInstPtr inst = instQueue.getInstToExecute(); 1207 1208 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1209 inst->pcState(), inst->threadNumber,inst->seqNum); 1210 1211 // Check if the instruction is squashed; if so then skip it 1212 if (inst->isSquashed()) { 1213 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1214 1215 // Consider this instruction executed so that commit can go 1216 // ahead and retire the instruction. 1217 inst->setExecuted(); 1218 1219 // Not sure if I should set this here or just let commit try to 1220 // commit any squashed instructions. I like the latter a bit more. 1221 inst->setCanCommit(); 1222 1223 ++iewExecSquashedInsts; 1224 1225 decrWb(inst->seqNum); 1226 continue; 1227 } 1228 1229 Fault fault = NoFault; 1230 1231 // Execute instruction. 1232 // Note that if the instruction faults, it will be handled 1233 // at the commit stage. 1234 if (inst->isMemRef()) { 1235 DPRINTF(IEW, "Execute: Calculating address for memory " 1236 "reference.\n"); 1237 1238 // Tell the LDSTQ to execute this instruction (if it is a load). 1239 if (inst->isLoad()) { 1240 // Loads will mark themselves as executed, and their writeback 1241 // event adds the instruction to the queue to commit 1242 fault = ldstQueue.executeLoad(inst); 1243 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1244 fault = NoFault; 1245 } 1246 } else if (inst->isStore()) { 1247 fault = ldstQueue.executeStore(inst); 1248 1249 // If the store had a fault then it may not have a mem req 1250 if (fault != NoFault || inst->readPredicate() == false || 1251 !inst->isStoreConditional()) { 1252 // If the instruction faulted, then we need to send it along 1253 // to commit without the instruction completing. 1254 // Send this instruction to commit, also make sure iew stage 1255 // realizes there is activity. 1256 inst->setExecuted(); 1257 instToCommit(inst); 1258 activityThisCycle(); 1259 } 1260 1261 // Store conditionals will mark themselves as 1262 // executed, and their writeback event will add the 1263 // instruction to the queue to commit. 1264 } else { 1265 panic("Unexpected memory type!\n"); 1266 } 1267 1268 } else { 1269 // If the instruction has already faulted, then skip executing it. 1270 // Such case can happen when it faulted during ITLB translation. 1271 // If we execute the instruction (even if it's a nop) the fault 1272 // will be replaced and we will lose it. 1273 if (inst->getFault() == NoFault) { 1274 inst->execute(); 1275 if (inst->readPredicate() == false) 1276 inst->forwardOldRegs(); 1277 } 1278 1279 inst->setExecuted(); 1280 1281 instToCommit(inst); 1282 } 1283 1284 updateExeInstStats(inst); 1285 1286 // Check if branch prediction was correct, if not then we need 1287 // to tell commit to squash in flight instructions. Only 1288 // handle this if there hasn't already been something that 1289 // redirects fetch in this group of instructions. 1290 1291 // This probably needs to prioritize the redirects if a different 1292 // scheduler is used. Currently the scheduler schedules the oldest 1293 // instruction first, so the branch resolution order will be correct. 1294 ThreadID tid = inst->threadNumber; 1295 1296 if (!fetchRedirect[tid] || 1297 !toCommit->squash[tid] || 1298 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1299 1300 // Prevent testing for misprediction on load instructions, 1301 // that have not been executed. 1302 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1303 1304 if (inst->mispredicted() && !loadNotExecuted) { 1305 fetchRedirect[tid] = true; 1306 1307 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1308 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1309 inst->predInstAddr(), inst->predNextInstAddr()); 1310 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1311 inst->pcState(), inst->nextInstAddr()); 1312 // If incorrect, then signal the ROB that it must be squashed. 1313 squashDueToBranch(inst, tid); 1314 1315 if (inst->readPredTaken()) { 1316 predictedTakenIncorrect++; 1317 } else { 1318 predictedNotTakenIncorrect++; 1319 } 1320 } else if (ldstQueue.violation(tid)) { 1321 assert(inst->isMemRef()); 1322 // If there was an ordering violation, then get the 1323 // DynInst that caused the violation. Note that this 1324 // clears the violation signal. 1325 DynInstPtr violator; 1326 violator = ldstQueue.getMemDepViolator(tid); 1327 1328 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1329 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1330 violator->pcState(), violator->seqNum, 1331 inst->pcState(), inst->seqNum, inst->physEffAddr); 1332 1333 fetchRedirect[tid] = true; 1334 1335 // Tell the instruction queue that a violation has occured. 1336 instQueue.violation(inst, violator); 1337 1338 // Squash. 1339 squashDueToMemOrder(inst,tid); 1340 1341 ++memOrderViolationEvents; 1342 } else if (ldstQueue.loadBlocked(tid) && 1343 !ldstQueue.isLoadBlockedHandled(tid)) { 1344 fetchRedirect[tid] = true; 1345 1346 DPRINTF(IEW, "Load operation couldn't execute because the " 1347 "memory system is blocked. PC: %s [sn:%lli]\n", 1348 inst->pcState(), inst->seqNum); 1349 1350 squashDueToMemBlocked(inst, tid); 1351 } 1352 } else { 1353 // Reset any state associated with redirects that will not 1354 // be used. 1355 if (ldstQueue.violation(tid)) { 1356 assert(inst->isMemRef()); 1357 1358 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1359 1360 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1361 "%s, inst PC: %s. Addr is: %#x.\n", 1362 violator->pcState(), inst->pcState(), 1363 inst->physEffAddr); 1364 DPRINTF(IEW, "Violation will not be handled because " 1365 "already squashing\n"); 1366 1367 ++memOrderViolationEvents; 1368 } 1369 if (ldstQueue.loadBlocked(tid) && 1370 !ldstQueue.isLoadBlockedHandled(tid)) { 1371 DPRINTF(IEW, "Load operation couldn't execute because the " 1372 "memory system is blocked. PC: %s [sn:%lli]\n", 1373 inst->pcState(), inst->seqNum); 1374 DPRINTF(IEW, "Blocked load will not be handled because " 1375 "already squashing\n"); 1376 1377 ldstQueue.setLoadBlockedHandled(tid); 1378 } 1379 1380 } 1381 } 1382 1383 // Update and record activity if we processed any instructions. 1384 if (inst_num) { 1385 if (exeStatus == Idle) { 1386 exeStatus = Running; 1387 } 1388 1389 updatedQueues = true; 1390 1391 cpu->activityThisCycle(); 1392 } 1393 1394 // Need to reset this in case a writeback event needs to write into the 1395 // iew queue. That way the writeback event will write into the correct 1396 // spot in the queue. 1397 wbNumInst = 0; 1398 1399} 1400 1401template <class Impl> 1402void 1403DefaultIEW<Impl>::writebackInsts() 1404{ 1405 // Loop through the head of the time buffer and wake any 1406 // dependents. These instructions are about to write back. Also 1407 // mark scoreboard that this instruction is finally complete. 1408 // Either have IEW have direct access to scoreboard, or have this 1409 // as part of backwards communication. 1410 for (int inst_num = 0; inst_num < wbWidth && 1411 toCommit->insts[inst_num]; inst_num++) { 1412 DynInstPtr inst = toCommit->insts[inst_num]; 1413 ThreadID tid = inst->threadNumber; 1414 1415 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1416 inst->seqNum, inst->pcState()); 1417 1418 iewInstsToCommit[tid]++; 1419 1420 // Some instructions will be sent to commit without having 1421 // executed because they need commit to handle them. 1422 // E.g. Uncached loads have not actually executed when they 1423 // are first sent to commit. Instead commit must tell the LSQ 1424 // when it's ready to execute the uncached load. 1425 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1426 int dependents = instQueue.wakeDependents(inst); 1427 1428 for (int i = 0; i < inst->numDestRegs(); i++) { 1429 //mark as Ready 1430 DPRINTF(IEW,"Setting Destination Register %i\n", 1431 inst->renamedDestRegIdx(i)); 1432 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1433 } 1434 1435 if (dependents) { 1436 producerInst[tid]++; 1437 consumerInst[tid]+= dependents; 1438 } 1439 writebackCount[tid]++; 1440 } 1441 1442 decrWb(inst->seqNum); 1443 } 1444} 1445 1446template<class Impl> 1447void 1448DefaultIEW<Impl>::tick() 1449{ 1450 wbNumInst = 0; 1451 wbCycle = 0; 1452 1453 wroteToTimeBuffer = false; 1454 updatedQueues = false; 1455 1456 sortInsts(); 1457 1458 // Free function units marked as being freed this cycle. 1459 fuPool->processFreeUnits(); 1460 1461 list<ThreadID>::iterator threads = activeThreads->begin(); 1462 list<ThreadID>::iterator end = activeThreads->end(); 1463 1464 // Check stall and squash signals, dispatch any instructions. 1465 while (threads != end) { 1466 ThreadID tid = *threads++; 1467 1468 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1469 1470 checkSignalsAndUpdate(tid); 1471 dispatch(tid); 1472 } 1473 1474 if (exeStatus != Squashing) { 1475 executeInsts(); 1476 1477 writebackInsts(); 1478 1479 // Have the instruction queue try to schedule any ready instructions. 1480 // (In actuality, this scheduling is for instructions that will 1481 // be executed next cycle.) 1482 instQueue.scheduleReadyInsts(); 1483 1484 // Also should advance its own time buffers if the stage ran. 1485 // Not the best place for it, but this works (hopefully). 1486 issueToExecQueue.advance(); 1487 } 1488 1489 bool broadcast_free_entries = false; 1490 1491 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1492 exeStatus = Idle; 1493 updateLSQNextCycle = false; 1494 1495 broadcast_free_entries = true; 1496 } 1497 1498 // Writeback any stores using any leftover bandwidth. 1499 ldstQueue.writebackStores(); 1500 1501 // Check the committed load/store signals to see if there's a load 1502 // or store to commit. Also check if it's being told to execute a 1503 // nonspeculative instruction. 1504 // This is pretty inefficient... 1505 1506 threads = activeThreads->begin(); 1507 while (threads != end) { 1508 ThreadID tid = (*threads++); 1509 1510 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1511 1512 // Update structures based on instructions committed. 1513 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1514 !fromCommit->commitInfo[tid].squash && 1515 !fromCommit->commitInfo[tid].robSquashing) { 1516 1517 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1518 1519 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1520 1521 updateLSQNextCycle = true; 1522 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1523 } 1524 1525 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1526 1527 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1528 if (fromCommit->commitInfo[tid].uncached) { 1529 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1530 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1531 } else { 1532 instQueue.scheduleNonSpec( 1533 fromCommit->commitInfo[tid].nonSpecSeqNum); 1534 } 1535 } 1536 1537 if (broadcast_free_entries) { 1538 toFetch->iewInfo[tid].iqCount = 1539 instQueue.getCount(tid); 1540 toFetch->iewInfo[tid].ldstqCount = 1541 ldstQueue.getCount(tid); 1542 1543 toRename->iewInfo[tid].usedIQ = true; 1544 toRename->iewInfo[tid].freeIQEntries = 1545 instQueue.numFreeEntries(); 1546 toRename->iewInfo[tid].usedLSQ = true; 1547 toRename->iewInfo[tid].freeLSQEntries = 1548 ldstQueue.numFreeEntries(tid); 1549 1550 wroteToTimeBuffer = true; 1551 } 1552 1553 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1554 tid, toRename->iewInfo[tid].dispatched); 1555 } 1556 1557 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1558 "LSQ has %i free entries.\n", 1559 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1560 ldstQueue.numFreeEntries()); 1561 1562 updateStatus(); 1563 1564 if (wroteToTimeBuffer) { 1565 DPRINTF(Activity, "Activity this cycle.\n"); 1566 cpu->activityThisCycle(); 1567 } 1568} 1569 1570template <class Impl> 1571void 1572DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1573{ 1574 ThreadID tid = inst->threadNumber; 1575 1576 // 1577 // Pick off the software prefetches 1578 // 1579#ifdef TARGET_ALPHA 1580 if (inst->isDataPrefetch()) 1581 iewExecutedSwp[tid]++; 1582 else 1583 iewIewExecutedcutedInsts++; 1584#else 1585 iewExecutedInsts++; 1586#endif 1587 1588 // 1589 // Control operations 1590 // 1591 if (inst->isControl()) 1592 iewExecutedBranches[tid]++; 1593 1594 // 1595 // Memory operations 1596 // 1597 if (inst->isMemRef()) { 1598 iewExecutedRefs[tid]++; 1599 1600 if (inst->isLoad()) { 1601 iewExecLoadInsts[tid]++; 1602 } 1603 } 1604} 1605 1606template <class Impl> 1607void 1608DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1609{ 1610 ThreadID tid = inst->threadNumber; 1611 1612 if (!fetchRedirect[tid] || 1613 !toCommit->squash[tid] || 1614 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1615 1616 if (inst->mispredicted()) { 1617 fetchRedirect[tid] = true; 1618 1619 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1620 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1621 inst->predInstAddr(), inst->predNextInstAddr()); 1622 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1623 " NPC: %#x.\n", inst->nextInstAddr(), 1624 inst->nextInstAddr()); 1625 // If incorrect, then signal the ROB that it must be squashed. 1626 squashDueToBranch(inst, tid); 1627 1628 if (inst->readPredTaken()) { 1629 predictedTakenIncorrect++; 1630 } else { 1631 predictedNotTakenIncorrect++; 1632 } 1633 } 1634 } 1635} 1636