iew_impl.hh revision 5529
12124SN/A/* 22124SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu * 285268Sksewell@umich.edu * Authors: Kevin Lim 295268Sksewell@umich.edu */ 305268Sksewell@umich.edu 312022SN/A// @todo: Fix the instantaneous communication among all the stages within 322649Ssaidi@eecs.umich.edu// iew. There's a clear delay between issue and execute, yet backwards 332649Ssaidi@eecs.umich.edu// communication happens simultaneously. 342706Sksewell@umich.edu 352649Ssaidi@eecs.umich.edu#include <queue> 362649Ssaidi@eecs.umich.edu 372022SN/A#include "base/timebuf.hh" 382124SN/A#include "cpu/o3/fu_pool.hh" 392124SN/A#include "cpu/o3/iew.hh" 402124SN/A#include "params/DerivO3CPU.hh" 412124SN/A 422124SN/Atemplate<class Impl> 432124SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 442124SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 455736Snate@binkert.org cpu(_cpu), 462239SN/A instQueue(_cpu, this, params), 472124SN/A ldstQueue(_cpu, this, params), 482124SN/A fuPool(params->fuPool), 492124SN/A commitToIEWDelay(params->commitToIEWDelay), 502124SN/A renameToIEWDelay(params->renameToIEWDelay), 516207Sksewell@umich.edu issueToExecuteDelay(params->issueToExecuteDelay), 522124SN/A dispatchWidth(params->dispatchWidth), 532742Sksewell@umich.edu issueWidth(params->issueWidth), 542022SN/A wbOutstanding(0), 552124SN/A wbWidth(params->wbWidth), 562022SN/A numThreads(params->numThreads), 572124SN/A switchedOut(false) 582124SN/A{ 592124SN/A _status = Active; 602124SN/A exeStatus = Running; 612742Sksewell@umich.edu wbStatus = Idle; 622742Sksewell@umich.edu 632742Sksewell@umich.edu // Setup wire to read instructions coming from issue. 642742Sksewell@umich.edu fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 652742Sksewell@umich.edu 662742Sksewell@umich.edu // Instruction queue needs the queue between issue and execute. 672742Sksewell@umich.edu instQueue.setIssueToExecuteQueue(&issueToExecQueue); 682742Sksewell@umich.edu 696207Sksewell@umich.edu for (int i=0; i < numThreads; i++) { 706207Sksewell@umich.edu dispatchStatus[i] = Running; 712742Sksewell@umich.edu stalls[i].commit = false; 722742Sksewell@umich.edu fetchRedirect[i] = false; 732742Sksewell@umich.edu } 742742Sksewell@umich.edu 752742Sksewell@umich.edu wbMax = wbWidth * params->wbDepth; 762742Sksewell@umich.edu 772022SN/A updateLSQNextCycle = false; 782022SN/A 792124SN/A ableToIssue = true; 802022SN/A 812124SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 822124SN/A} 832124SN/A 842742Sksewell@umich.edutemplate <class Impl> 852239SN/Astd::string 862124SN/ADefaultIEW<Impl>::name() const 872124SN/A{ 882742Sksewell@umich.edu return cpu->name() + ".iew"; 892742Sksewell@umich.edu} 902742Sksewell@umich.edu 912742Sksewell@umich.edutemplate <class Impl> 922742Sksewell@umich.eduvoid 932742Sksewell@umich.eduDefaultIEW<Impl>::regStats() 942742Sksewell@umich.edu{ 952742Sksewell@umich.edu using namespace Stats; 964661Sksewell@umich.edu 974661Sksewell@umich.edu instQueue.regStats(); 984661Sksewell@umich.edu ldstQueue.regStats(); 994661Sksewell@umich.edu 1004661Sksewell@umich.edu iewIdleCycles 1014661Sksewell@umich.edu .name(name() + ".iewIdleCycles") 1024661Sksewell@umich.edu .desc("Number of cycles IEW is idle"); 1035222Sksewell@umich.edu 1044661Sksewell@umich.edu iewSquashCycles 1054661Sksewell@umich.edu .name(name() + ".iewSquashCycles") 1065222Sksewell@umich.edu .desc("Number of cycles IEW is squashing"); 1074661Sksewell@umich.edu 1084661Sksewell@umich.edu iewBlockCycles 1095222Sksewell@umich.edu .name(name() + ".iewBlockCycles") 1104661Sksewell@umich.edu .desc("Number of cycles IEW is blocking"); 1114661Sksewell@umich.edu 1125222Sksewell@umich.edu iewUnblockCycles 1134661Sksewell@umich.edu .name(name() + ".iewUnblockCycles") 1144661Sksewell@umich.edu .desc("Number of cycles IEW is unblocking"); 1155222Sksewell@umich.edu 1164661Sksewell@umich.edu iewDispatchedInsts 1174661Sksewell@umich.edu .name(name() + ".iewDispatchedInsts") 1184661Sksewell@umich.edu .desc("Number of instructions dispatched to IQ"); 1194661Sksewell@umich.edu 1204661Sksewell@umich.edu iewDispSquashedInsts 1214661Sksewell@umich.edu .name(name() + ".iewDispSquashedInsts") 1224661Sksewell@umich.edu .desc("Number of squashed instructions skipped by dispatch"); 1234661Sksewell@umich.edu 1244661Sksewell@umich.edu iewDispLoadInsts 1254661Sksewell@umich.edu .name(name() + ".iewDispLoadInsts") 1264661Sksewell@umich.edu .desc("Number of dispatched load instructions"); 1272022SN/A 1282022SN/A iewDispStoreInsts 1292124SN/A .name(name() + ".iewDispStoreInsts") 1302124SN/A .desc("Number of dispatched store instructions"); 1312124SN/A 1322124SN/A iewDispNonSpecInsts 1332124SN/A .name(name() + ".iewDispNonSpecInsts") 1342124SN/A .desc("Number of dispatched non-speculative instructions"); 1352124SN/A 1362124SN/A iewIQFullEvents 1372124SN/A .name(name() + ".iewIQFullEvents") 1384661Sksewell@umich.edu .desc("Number of times the IQ has become full, causing a stall"); 1392124SN/A 1402124SN/A iewLSQFullEvents 1412124SN/A .name(name() + ".iewLSQFullEvents") 1426207Sksewell@umich.edu .desc("Number of times the LSQ has become full, causing a stall"); 1436207Sksewell@umich.edu 1442124SN/A memOrderViolationEvents 1452124SN/A .name(name() + ".memOrderViolationEvents") 1462124SN/A .desc("Number of memory order violations"); 1472124SN/A 1482022SN/A predictedTakenIncorrect 1492022SN/A .name(name() + ".predictedTakenIncorrect") 1506207Sksewell@umich.edu .desc("Number of branches that were predicted taken incorrectly"); 1516207Sksewell@umich.edu 1526207Sksewell@umich.edu predictedNotTakenIncorrect 1532124SN/A .name(name() + ".predictedNotTakenIncorrect") 1542124SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1552132SN/A 1562022SN/A branchMispredicts 1572124SN/A .name(name() + ".branchMispredicts") 1582124SN/A .desc("Number of branch mispredicts detected at execute"); 1592124SN/A 1604661Sksewell@umich.edu branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1612124SN/A 1622124SN/A iewExecutedInsts 1636207Sksewell@umich.edu .name(name() + ".iewExecutedInsts") 1646207Sksewell@umich.edu .desc("Number of executed instructions"); 1656207Sksewell@umich.edu 1662124SN/A iewExecLoadInsts 1673953Sstever@eecs.umich.edu .init(cpu->number_of_threads) 1682124SN/A .name(name() + ".iewExecLoadInsts") 1693953Sstever@eecs.umich.edu .desc("Number of load instructions executed") 1702124SN/A .flags(total); 1713953Sstever@eecs.umich.edu 1722124SN/A iewExecSquashedInsts 1732132SN/A .name(name() + ".iewExecSquashedInsts") 1746207Sksewell@umich.edu .desc("Number of squashed instructions skipped in execute"); 1752124SN/A 1762124SN/A iewExecutedSwp 1772124SN/A .init(cpu->number_of_threads) 1782132SN/A .name(name() + ".EXEC:swp") 1792124SN/A .desc("number of swp insts executed") 1805222Sksewell@umich.edu .flags(total); 1815222Sksewell@umich.edu 1825222Sksewell@umich.edu iewExecutedNop 1835222Sksewell@umich.edu .init(cpu->number_of_threads) 1845222Sksewell@umich.edu .name(name() + ".EXEC:nop") 1855222Sksewell@umich.edu .desc("number of nop insts executed") 1865222Sksewell@umich.edu .flags(total); 1872124SN/A 1882124SN/A iewExecutedRefs 1893953Sstever@eecs.umich.edu .init(cpu->number_of_threads) 1902124SN/A .name(name() + ".EXEC:refs") 1914661Sksewell@umich.edu .desc("number of memory reference insts executed") 1922124SN/A .flags(total); 1932124SN/A 1942124SN/A iewExecutedBranches 1952124SN/A .init(cpu->number_of_threads) 1962124SN/A .name(name() + ".EXEC:branches") 1972124SN/A .desc("Number of branches executed") 1982124SN/A .flags(total); 1992124SN/A 2002124SN/A iewExecStoreInsts 2012132SN/A .name(name() + ".EXEC:stores") 2022124SN/A .desc("Number of stores executed") 2032124SN/A .flags(total); 2042124SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2052132SN/A 2062124SN/A iewExecRate 2075222Sksewell@umich.edu .name(name() + ".EXEC:rate") 2085222Sksewell@umich.edu .desc("Inst execution rate") 2095222Sksewell@umich.edu .flags(total); 2105222Sksewell@umich.edu 2115222Sksewell@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2125222Sksewell@umich.edu 2135222Sksewell@umich.edu iewInstsToCommit 2142124SN/A .init(cpu->number_of_threads) 2152124SN/A .name(name() + ".WB:sent") 2162124SN/A .desc("cumulative count of insts sent to commit") 2172124SN/A .flags(total); 2182124SN/A 2192124SN/A writebackCount 2202124SN/A .init(cpu->number_of_threads) 2212124SN/A .name(name() + ".WB:count") 2222124SN/A .desc("cumulative count of insts written-back") 2232124SN/A .flags(total); 2242124SN/A 2252124SN/A producerInst 2262124SN/A .init(cpu->number_of_threads) 2272124SN/A .name(name() + ".WB:producers") 2282124SN/A .desc("num instructions producing a value") 2292124SN/A .flags(total); 2302124SN/A 2312124SN/A consumerInst 2322124SN/A .init(cpu->number_of_threads) 2332132SN/A .name(name() + ".WB:consumers") 2342124SN/A .desc("num instructions consuming a value") 2352124SN/A .flags(total); 2362239SN/A 2372132SN/A wbPenalized 2382239SN/A .init(cpu->number_of_threads) 2395222Sksewell@umich.edu .name(name() + ".WB:penalized") 2405222Sksewell@umich.edu .desc("number of instrctions required to write to 'other' IQ") 2415222Sksewell@umich.edu .flags(total); 2425222Sksewell@umich.edu 2435222Sksewell@umich.edu wbPenalizedRate 2445222Sksewell@umich.edu .name(name() + ".WB:penalized_rate") 2455222Sksewell@umich.edu .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2462239SN/A .flags(total); 2472239SN/A 2482239SN/A wbPenalizedRate = wbPenalized / writebackCount; 2492239SN/A 2502239SN/A wbFanout 2512239SN/A .name(name() + ".WB:fanout") 2522239SN/A .desc("average fanout of values written-back") 2532239SN/A .flags(total); 2542124SN/A 2552124SN/A wbFanout = producerInst / consumerInst; 2562124SN/A 2572124SN/A wbRate 2582124SN/A .name(name() + ".WB:rate") 2594661Sksewell@umich.edu .desc("insts written-back per cycle") 2602124SN/A .flags(total); 2612124SN/A wbRate = writebackCount / cpu->numCycles; 2622124SN/A} 2632132SN/A 2642239SN/Atemplate<class Impl> 2655222Sksewell@umich.eduvoid 2665222Sksewell@umich.eduDefaultIEW<Impl>::initStage() 2675222Sksewell@umich.edu{ 2685222Sksewell@umich.edu for (int tid=0; tid < numThreads; tid++) { 2695222Sksewell@umich.edu toRename->iewInfo[tid].usedIQ = true; 2705222Sksewell@umich.edu toRename->iewInfo[tid].freeIQEntries = 2715222Sksewell@umich.edu instQueue.numFreeEntries(tid); 2722506SN/A 2734661Sksewell@umich.edu toRename->iewInfo[tid].usedLSQ = true; 2742239SN/A toRename->iewInfo[tid].freeLSQEntries = 2752935Sksewell@umich.edu ldstQueue.numFreeEntries(tid); 2762239SN/A } 2772239SN/A 2782239SN/A cpu->activateStage(O3CPU::IEWIdx); 2792239SN/A} 2802239SN/A 2812239SN/Atemplate<class Impl> 2822239SN/Avoid 2832239SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2842239SN/A{ 2852124SN/A timeBuffer = tb_ptr; 2862124SN/A 2872124SN/A // Setup wire to read information from time buffer, from commit. 2882124SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2892124SN/A 2902132SN/A // Setup wire to write information back to previous stages. 2912124SN/A toRename = timeBuffer->getWire(0); 2922124SN/A 2932124SN/A toFetch = timeBuffer->getWire(0); 2942132SN/A 2954056Sstever@eecs.umich.edu // Instruction queue also needs main time buffer. 2964056Sstever@eecs.umich.edu instQueue.setTimeBuffer(tb_ptr); 2974056Sstever@eecs.umich.edu} 2984056Sstever@eecs.umich.edu 2994056Sstever@eecs.umich.edutemplate<class Impl> 3004056Sstever@eecs.umich.eduvoid 3014056Sstever@eecs.umich.eduDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3024056Sstever@eecs.umich.edu{ 3034056Sstever@eecs.umich.edu renameQueue = rq_ptr; 3044056Sstever@eecs.umich.edu 3054056Sstever@eecs.umich.edu // Setup wire to read information from rename queue. 3064056Sstever@eecs.umich.edu fromRename = renameQueue->getWire(-renameToIEWDelay); 3074675Sksewell@umich.edu} 3084056Sstever@eecs.umich.edu 3094056Sstever@eecs.umich.edutemplate<class Impl> 3104056Sstever@eecs.umich.eduvoid 3114056Sstever@eecs.umich.eduDefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3124056Sstever@eecs.umich.edu{ 3134056Sstever@eecs.umich.edu iewQueue = iq_ptr; 3144056Sstever@eecs.umich.edu 3154056Sstever@eecs.umich.edu // Setup wire to write instructions to commit. 3164056Sstever@eecs.umich.edu toCommit = iewQueue->getWire(0); 3174056Sstever@eecs.umich.edu} 3184056Sstever@eecs.umich.edu 3194056Sstever@eecs.umich.edutemplate<class Impl> 3204056Sstever@eecs.umich.eduvoid 3214056Sstever@eecs.umich.eduDefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3225222Sksewell@umich.edu{ 3235222Sksewell@umich.edu activeThreads = at_ptr; 3245222Sksewell@umich.edu 3255222Sksewell@umich.edu ldstQueue.setActiveThreads(at_ptr); 3265222Sksewell@umich.edu instQueue.setActiveThreads(at_ptr); 3275222Sksewell@umich.edu} 3285222Sksewell@umich.edu 3295222Sksewell@umich.edutemplate<class Impl> 3305222Sksewell@umich.eduvoid 3315222Sksewell@umich.eduDefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3325222Sksewell@umich.edu{ 3335222Sksewell@umich.edu scoreboard = sb_ptr; 3345222Sksewell@umich.edu} 3355222Sksewell@umich.edu 3365222Sksewell@umich.edutemplate <class Impl> 3375222Sksewell@umich.edubool 3385222Sksewell@umich.eduDefaultIEW<Impl>::drain() 3395222Sksewell@umich.edu{ 3405222Sksewell@umich.edu // IEW is ready to drain at any time. 3415222Sksewell@umich.edu cpu->signalDrained(); 3425222Sksewell@umich.edu return true; 3435222Sksewell@umich.edu} 3445222Sksewell@umich.edu 3455222Sksewell@umich.edutemplate <class Impl> 3465222Sksewell@umich.eduvoid 3475222Sksewell@umich.eduDefaultIEW<Impl>::resume() 3485222Sksewell@umich.edu{ 3495222Sksewell@umich.edu} 3505222Sksewell@umich.edu 3515222Sksewell@umich.edutemplate <class Impl> 3525222Sksewell@umich.eduvoid 3535222Sksewell@umich.eduDefaultIEW<Impl>::switchOut() 3545222Sksewell@umich.edu{ 3555222Sksewell@umich.edu // Clear any state. 3565222Sksewell@umich.edu switchedOut = true; 3575222Sksewell@umich.edu assert(insts[0].empty()); 3584056Sstever@eecs.umich.edu assert(skidBuffer[0].empty()); 3594056Sstever@eecs.umich.edu 3604056Sstever@eecs.umich.edu instQueue.switchOut(); 3614056Sstever@eecs.umich.edu ldstQueue.switchOut(); 3624056Sstever@eecs.umich.edu fuPool->switchOut(); 3634056Sstever@eecs.umich.edu 3642124SN/A for (int i = 0; i < numThreads; i++) { 3652124SN/A while (!insts[i].empty()) 3662124SN/A insts[i].pop(); 3672124SN/A while (!skidBuffer[i].empty()) 3682124SN/A skidBuffer[i].pop(); 3692124SN/A } 3702124SN/A} 3712124SN/A 3722124SN/Atemplate <class Impl> 3732124SN/Avoid 3742124SN/ADefaultIEW<Impl>::takeOverFrom() 3752124SN/A{ 3762124SN/A // Reset all state. 3772124SN/A _status = Active; 3782124SN/A exeStatus = Running; 3792124SN/A wbStatus = Idle; 3802124SN/A switchedOut = false; 3812124SN/A 3822124SN/A instQueue.takeOverFrom(); 3832124SN/A ldstQueue.takeOverFrom(); 3842124SN/A fuPool->takeOverFrom(); 3852124SN/A 3862124SN/A initStage(); 3872124SN/A cpu->activityThisCycle(); 3882124SN/A 3892124SN/A for (int i=0; i < numThreads; i++) { 3902124SN/A dispatchStatus[i] = Running; 3912124SN/A stalls[i].commit = false; 3922124SN/A fetchRedirect[i] = false; 3932132SN/A } 3942124SN/A 3952124SN/A updateLSQNextCycle = false; 3962239SN/A 3972132SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 3982239SN/A issueToExecQueue.advance(); 3992239SN/A } 4002506SN/A} 4012239SN/A 4022239SN/Atemplate<class Impl> 4032239SN/Avoid 4042239SN/ADefaultIEW<Impl>::squash(unsigned tid) 4052239SN/A{ 4062239SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4072239SN/A tid); 4082239SN/A 4092239SN/A // Tell the IQ to start squashing. 4102935Sksewell@umich.edu instQueue.squash(tid); 4112239SN/A 4122239SN/A // Tell the LDSTQ to start squashing. 4132124SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4142124SN/A updatedQueues = true; 4152124SN/A 4162124SN/A // Clear the skid buffer in case it has any data in it. 4172124SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4182124SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4194661Sksewell@umich.edu 4202124SN/A while (!skidBuffer[tid].empty()) { 4212124SN/A if (skidBuffer[tid].front()->isLoad() || 4222124SN/A skidBuffer[tid].front()->isStore() ) { 4237712Sgblack@eecs.umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 4242935Sksewell@umich.edu } 4252935Sksewell@umich.edu 4262935Sksewell@umich.edu toRename->iewInfo[tid].dispatched++; 4272935Sksewell@umich.edu 4284661Sksewell@umich.edu skidBuffer[tid].pop(); 4292935Sksewell@umich.edu } 4302935Sksewell@umich.edu 4312935Sksewell@umich.edu emptyRenameInsts(tid); 4322935Sksewell@umich.edu} 4332935Sksewell@umich.edu 4342935Sksewell@umich.edutemplate<class Impl> 4352935Sksewell@umich.eduvoid 4362935Sksewell@umich.eduDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4374055Ssaidi@eecs.umich.edu{ 4382239SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4392239SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4402239SN/A 4412239SN/A toCommit->squash[tid] = true; 4422239SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4432239SN/A toCommit->mispredPC[tid] = inst->readPC(); 4442239SN/A toCommit->branchMispredict[tid] = true; 4452239SN/A 4462239SN/A#if ISA_HAS_DELAY_SLOT 4472124SN/A int instSize = sizeof(TheISA::MachInst); 4482124SN/A toCommit->branchTaken[tid] = 4492124SN/A !(inst->readNextPC() + instSize == inst->readNextNPC() && 4502124SN/A (inst->readNextPC() == inst->readPC() + instSize || 4512686Sksewell@umich.edu inst->readNextPC() == inst->readPC() + 2 * instSize)); 4522686Sksewell@umich.edu#else 4532686Sksewell@umich.edu toCommit->branchTaken[tid] = inst->readNextPC() != 4542686Sksewell@umich.edu (inst->readPC() + sizeof(TheISA::MachInst)); 4557725SAli.Saidi@ARM.com#endif 4562686Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4572686Sksewell@umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4582686Sksewell@umich.edu toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 4592686Sksewell@umich.edu 4602686Sksewell@umich.edu toCommit->includeSquashInst[tid] = false; 4612686Sksewell@umich.edu 4622686Sksewell@umich.edu wroteToTimeBuffer = true; 4632686Sksewell@umich.edu} 4642686Sksewell@umich.edu 4652686Sksewell@umich.edutemplate<class Impl> 4662686Sksewell@umich.eduvoid 4672686Sksewell@umich.eduDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4682686Sksewell@umich.edu{ 4692686Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4702686Sksewell@umich.edu "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4712686Sksewell@umich.edu 4722686Sksewell@umich.edu toCommit->squash[tid] = true; 4732686Sksewell@umich.edu toCommit->squashedSeqNum[tid] = inst->seqNum; 4742686Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4752686Sksewell@umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4762686Sksewell@umich.edu toCommit->branchMispredict[tid] = false; 4772686Sksewell@umich.edu 4782686Sksewell@umich.edu toCommit->includeSquashInst[tid] = false; 4792686Sksewell@umich.edu 4802686Sksewell@umich.edu wroteToTimeBuffer = true; 4812686Sksewell@umich.edu} 4824661Sksewell@umich.edu 4832686Sksewell@umich.edutemplate<class Impl> 4842686Sksewell@umich.eduvoid 4852686Sksewell@umich.eduDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 4862686Sksewell@umich.edu{ 4872686Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4882686Sksewell@umich.edu "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4892686Sksewell@umich.edu 4902686Sksewell@umich.edu toCommit->squash[tid] = true; 4912686Sksewell@umich.edu toCommit->squashedSeqNum[tid] = inst->seqNum; 4922124SN/A toCommit->nextPC[tid] = inst->readPC(); 4932124SN/A toCommit->nextNPC[tid] = inst->readNextPC(); 4942124SN/A toCommit->branchMispredict[tid] = false; 4952124SN/A 4962750Sksewell@umich.edu // Must include the broadcasted SN in the squash. 4972124SN/A toCommit->includeSquashInst[tid] = true; 4982124SN/A 4992124SN/A ldstQueue.setLoadBlockedHandled(tid); 5005222Sksewell@umich.edu 5012124SN/A wroteToTimeBuffer = true; 5022124SN/A} 5032124SN/A 5042124SN/Atemplate<class Impl> 5052124SN/Avoid 5062124SN/ADefaultIEW<Impl>::block(unsigned tid) 5072124SN/A{ 5082686Sksewell@umich.edu DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5092573SN/A 5105222Sksewell@umich.edu if (dispatchStatus[tid] != Blocked && 5112573SN/A dispatchStatus[tid] != Unblocking) { 5122573SN/A toRename->iewBlock[tid] = true; 5132750Sksewell@umich.edu wroteToTimeBuffer = true; 5142573SN/A } 5152573SN/A 5162573SN/A // Add the current inputs to the skid buffer so they can be 5172686Sksewell@umich.edu // reprocessed when this stage unblocks. 5182573SN/A skidInsert(tid); 5195222Sksewell@umich.edu 5202573SN/A dispatchStatus[tid] = Blocked; 5212573SN/A} 5222573SN/A 5232573SN/Atemplate<class Impl> 5242573SN/Avoid 5255222Sksewell@umich.eduDefaultIEW<Impl>::unblock(unsigned tid) 5265222Sksewell@umich.edu{ 5275222Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5285222Sksewell@umich.edu "buffer %u.\n",tid, tid); 5295222Sksewell@umich.edu 5305222Sksewell@umich.edu // If the skid bufffer is empty, signal back to previous stages to unblock. 5315222Sksewell@umich.edu // Also switch status to running. 5325222Sksewell@umich.edu if (skidBuffer[tid].empty()) { 5335222Sksewell@umich.edu toRename->iewUnblock[tid] = true; 5345222Sksewell@umich.edu wroteToTimeBuffer = true; 5355222Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5365222Sksewell@umich.edu dispatchStatus[tid] = Running; 5375222Sksewell@umich.edu } 5385222Sksewell@umich.edu} 5395222Sksewell@umich.edu 5405222Sksewell@umich.edutemplate<class Impl> 5415222Sksewell@umich.eduvoid 5425222Sksewell@umich.eduDefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5432686Sksewell@umich.edu{ 5442686Sksewell@umich.edu instQueue.wakeDependents(inst); 5452686Sksewell@umich.edu} 5462686Sksewell@umich.edu 5472686Sksewell@umich.edutemplate<class Impl> 5482686Sksewell@umich.eduvoid 5492686Sksewell@umich.eduDefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5502686Sksewell@umich.edu{ 5512573SN/A instQueue.rescheduleMemInst(inst); 5522686Sksewell@umich.edu} 5532686Sksewell@umich.edu 5542686Sksewell@umich.edutemplate<class Impl> 5552686Sksewell@umich.eduvoid 5562750Sksewell@umich.eduDefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5572686Sksewell@umich.edu{ 5582686Sksewell@umich.edu instQueue.replayMemInst(inst); 5592686Sksewell@umich.edu} 5602686Sksewell@umich.edu 5612686Sksewell@umich.edutemplate<class Impl> 5622686Sksewell@umich.eduvoid 5632686Sksewell@umich.eduDefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5642686Sksewell@umich.edu{ 5652686Sksewell@umich.edu // This function should not be called after writebackInsts in a 5662686Sksewell@umich.edu // single cycle. That will cause problems with an instruction 5672686Sksewell@umich.edu // being added to the queue to commit without being processed by 5682686Sksewell@umich.edu // writebackInsts prior to being sent to commit. 5694661Sksewell@umich.edu 5702686Sksewell@umich.edu // First check the time slot that this instruction will write 5712686Sksewell@umich.edu // to. If there are free write ports at the time, then go ahead 5722686Sksewell@umich.edu // and write the instruction to that time. If there are not, 5732686Sksewell@umich.edu // keep looking back to see where's the first time there's a 5742686Sksewell@umich.edu // free slot. 5752686Sksewell@umich.edu while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5762686Sksewell@umich.edu ++wbNumInst; 5772686Sksewell@umich.edu if (wbNumInst == wbWidth) { 5782686Sksewell@umich.edu ++wbCycle; 5796739Sgblack@eecs.umich.edu wbNumInst = 0; 5807725SAli.Saidi@ARM.com } 5812686Sksewell@umich.edu 5822686Sksewell@umich.edu assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5832686Sksewell@umich.edu } 5847725SAli.Saidi@ARM.com 5852686Sksewell@umich.edu DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 5862686Sksewell@umich.edu wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 5872686Sksewell@umich.edu // Add finished instruction to queue to commit. 5882686Sksewell@umich.edu (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5892686Sksewell@umich.edu (*iewQueue)[wbCycle].size++; 5902686Sksewell@umich.edu} 5912495SN/A 5922495SN/Atemplate <class Impl> 5932495SN/Aunsigned 5942935Sksewell@umich.eduDefaultIEW<Impl>::validInstsFromRename() 5952495SN/A{ 596 unsigned inst_count = 0; 597 598 for (int i=0; i<fromRename->size; i++) { 599 if (!fromRename->insts[i]->isSquashed()) 600 inst_count++; 601 } 602 603 return inst_count; 604} 605 606template<class Impl> 607void 608DefaultIEW<Impl>::skidInsert(unsigned tid) 609{ 610 DynInstPtr inst = NULL; 611 612 while (!insts[tid].empty()) { 613 inst = insts[tid].front(); 614 615 insts[tid].pop(); 616 617 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 618 "dispatch skidBuffer %i\n",tid, inst->seqNum, 619 inst->readPC(),tid); 620 621 skidBuffer[tid].push(inst); 622 } 623 624 assert(skidBuffer[tid].size() <= skidBufferMax && 625 "Skidbuffer Exceeded Max Size"); 626} 627 628template<class Impl> 629int 630DefaultIEW<Impl>::skidCount() 631{ 632 int max=0; 633 634 std::list<unsigned>::iterator threads = activeThreads->begin(); 635 std::list<unsigned>::iterator end = activeThreads->end(); 636 637 while (threads != end) { 638 unsigned tid = *threads++; 639 unsigned thread_count = skidBuffer[tid].size(); 640 if (max < thread_count) 641 max = thread_count; 642 } 643 644 return max; 645} 646 647template<class Impl> 648bool 649DefaultIEW<Impl>::skidsEmpty() 650{ 651 std::list<unsigned>::iterator threads = activeThreads->begin(); 652 std::list<unsigned>::iterator end = activeThreads->end(); 653 654 while (threads != end) { 655 unsigned tid = *threads++; 656 657 if (!skidBuffer[tid].empty()) 658 return false; 659 } 660 661 return true; 662} 663 664template <class Impl> 665void 666DefaultIEW<Impl>::updateStatus() 667{ 668 bool any_unblocking = false; 669 670 std::list<unsigned>::iterator threads = activeThreads->begin(); 671 std::list<unsigned>::iterator end = activeThreads->end(); 672 673 while (threads != end) { 674 unsigned tid = *threads++; 675 676 if (dispatchStatus[tid] == Unblocking) { 677 any_unblocking = true; 678 break; 679 } 680 } 681 682 // If there are no ready instructions waiting to be scheduled by the IQ, 683 // and there's no stores waiting to write back, and dispatch is not 684 // unblocking, then there is no internal activity for the IEW stage. 685 if (_status == Active && !instQueue.hasReadyInsts() && 686 !ldstQueue.willWB() && !any_unblocking) { 687 DPRINTF(IEW, "IEW switching to idle\n"); 688 689 deactivateStage(); 690 691 _status = Inactive; 692 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 693 ldstQueue.willWB() || 694 any_unblocking)) { 695 // Otherwise there is internal activity. Set to active. 696 DPRINTF(IEW, "IEW switching to active\n"); 697 698 activateStage(); 699 700 _status = Active; 701 } 702} 703 704template <class Impl> 705void 706DefaultIEW<Impl>::resetEntries() 707{ 708 instQueue.resetEntries(); 709 ldstQueue.resetEntries(); 710} 711 712template <class Impl> 713void 714DefaultIEW<Impl>::readStallSignals(unsigned tid) 715{ 716 if (fromCommit->commitBlock[tid]) { 717 stalls[tid].commit = true; 718 } 719 720 if (fromCommit->commitUnblock[tid]) { 721 assert(stalls[tid].commit); 722 stalls[tid].commit = false; 723 } 724} 725 726template <class Impl> 727bool 728DefaultIEW<Impl>::checkStall(unsigned tid) 729{ 730 bool ret_val(false); 731 732 if (stalls[tid].commit) { 733 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 734 ret_val = true; 735 } else if (instQueue.isFull(tid)) { 736 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 737 ret_val = true; 738 } else if (ldstQueue.isFull(tid)) { 739 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 740 741 if (ldstQueue.numLoads(tid) > 0 ) { 742 743 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 744 tid,ldstQueue.getLoadHeadSeqNum(tid)); 745 } 746 747 if (ldstQueue.numStores(tid) > 0) { 748 749 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 750 tid,ldstQueue.getStoreHeadSeqNum(tid)); 751 } 752 753 ret_val = true; 754 } else if (ldstQueue.isStalled(tid)) { 755 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 756 ret_val = true; 757 } 758 759 return ret_val; 760} 761 762template <class Impl> 763void 764DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 765{ 766 // Check if there's a squash signal, squash if there is 767 // Check stall signals, block if there is. 768 // If status was Blocked 769 // if so then go to unblocking 770 // If status was Squashing 771 // check if squashing is not high. Switch to running this cycle. 772 773 readStallSignals(tid); 774 775 if (fromCommit->commitInfo[tid].squash) { 776 squash(tid); 777 778 if (dispatchStatus[tid] == Blocked || 779 dispatchStatus[tid] == Unblocking) { 780 toRename->iewUnblock[tid] = true; 781 wroteToTimeBuffer = true; 782 } 783 784 dispatchStatus[tid] = Squashing; 785 786 fetchRedirect[tid] = false; 787 return; 788 } 789 790 if (fromCommit->commitInfo[tid].robSquashing) { 791 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 792 793 dispatchStatus[tid] = Squashing; 794 795 emptyRenameInsts(tid); 796 wroteToTimeBuffer = true; 797 return; 798 } 799 800 if (checkStall(tid)) { 801 block(tid); 802 dispatchStatus[tid] = Blocked; 803 return; 804 } 805 806 if (dispatchStatus[tid] == Blocked) { 807 // Status from previous cycle was blocked, but there are no more stall 808 // conditions. Switch over to unblocking. 809 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 810 tid); 811 812 dispatchStatus[tid] = Unblocking; 813 814 unblock(tid); 815 816 return; 817 } 818 819 if (dispatchStatus[tid] == Squashing) { 820 // Switch status to running if rename isn't being told to block or 821 // squash this cycle. 822 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 823 tid); 824 825 dispatchStatus[tid] = Running; 826 827 return; 828 } 829} 830 831template <class Impl> 832void 833DefaultIEW<Impl>::sortInsts() 834{ 835 int insts_from_rename = fromRename->size; 836#ifdef DEBUG 837 for (int i = 0; i < numThreads; i++) 838 assert(insts[i].empty()); 839#endif 840 for (int i = 0; i < insts_from_rename; ++i) { 841 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 842 } 843} 844 845template <class Impl> 846void 847DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 848{ 849 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 850 851 while (!insts[tid].empty()) { 852 853 if (insts[tid].front()->isLoad() || 854 insts[tid].front()->isStore() ) { 855 toRename->iewInfo[tid].dispatchedToLSQ++; 856 } 857 858 toRename->iewInfo[tid].dispatched++; 859 860 insts[tid].pop(); 861 } 862} 863 864template <class Impl> 865void 866DefaultIEW<Impl>::wakeCPU() 867{ 868 cpu->wakeCPU(); 869} 870 871template <class Impl> 872void 873DefaultIEW<Impl>::activityThisCycle() 874{ 875 DPRINTF(Activity, "Activity this cycle.\n"); 876 cpu->activityThisCycle(); 877} 878 879template <class Impl> 880inline void 881DefaultIEW<Impl>::activateStage() 882{ 883 DPRINTF(Activity, "Activating stage.\n"); 884 cpu->activateStage(O3CPU::IEWIdx); 885} 886 887template <class Impl> 888inline void 889DefaultIEW<Impl>::deactivateStage() 890{ 891 DPRINTF(Activity, "Deactivating stage.\n"); 892 cpu->deactivateStage(O3CPU::IEWIdx); 893} 894 895template<class Impl> 896void 897DefaultIEW<Impl>::dispatch(unsigned tid) 898{ 899 // If status is Running or idle, 900 // call dispatchInsts() 901 // If status is Unblocking, 902 // buffer any instructions coming from rename 903 // continue trying to empty skid buffer 904 // check if stall conditions have passed 905 906 if (dispatchStatus[tid] == Blocked) { 907 ++iewBlockCycles; 908 909 } else if (dispatchStatus[tid] == Squashing) { 910 ++iewSquashCycles; 911 } 912 913 // Dispatch should try to dispatch as many instructions as its bandwidth 914 // will allow, as long as it is not currently blocked. 915 if (dispatchStatus[tid] == Running || 916 dispatchStatus[tid] == Idle) { 917 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 918 "dispatch.\n", tid); 919 920 dispatchInsts(tid); 921 } else if (dispatchStatus[tid] == Unblocking) { 922 // Make sure that the skid buffer has something in it if the 923 // status is unblocking. 924 assert(!skidsEmpty()); 925 926 // If the status was unblocking, then instructions from the skid 927 // buffer were used. Remove those instructions and handle 928 // the rest of unblocking. 929 dispatchInsts(tid); 930 931 ++iewUnblockCycles; 932 933 if (validInstsFromRename()) { 934 // Add the current inputs to the skid buffer so they can be 935 // reprocessed when this stage unblocks. 936 skidInsert(tid); 937 } 938 939 unblock(tid); 940 } 941} 942 943template <class Impl> 944void 945DefaultIEW<Impl>::dispatchInsts(unsigned tid) 946{ 947 // Obtain instructions from skid buffer if unblocking, or queue from rename 948 // otherwise. 949 std::queue<DynInstPtr> &insts_to_dispatch = 950 dispatchStatus[tid] == Unblocking ? 951 skidBuffer[tid] : insts[tid]; 952 953 int insts_to_add = insts_to_dispatch.size(); 954 955 DynInstPtr inst; 956 bool add_to_iq = false; 957 int dis_num_inst = 0; 958 959 // Loop through the instructions, putting them in the instruction 960 // queue. 961 for ( ; dis_num_inst < insts_to_add && 962 dis_num_inst < dispatchWidth; 963 ++dis_num_inst) 964 { 965 inst = insts_to_dispatch.front(); 966 967 if (dispatchStatus[tid] == Unblocking) { 968 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 969 "buffer\n", tid); 970 } 971 972 // Make sure there's a valid instruction there. 973 assert(inst); 974 975 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 976 "IQ.\n", 977 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 978 979 // Be sure to mark these instructions as ready so that the 980 // commit stage can go ahead and execute them, and mark 981 // them as issued so the IQ doesn't reprocess them. 982 983 // Check for squashed instructions. 984 if (inst->isSquashed()) { 985 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 986 "not adding to IQ.\n", tid); 987 988 ++iewDispSquashedInsts; 989 990 insts_to_dispatch.pop(); 991 992 //Tell Rename That An Instruction has been processed 993 if (inst->isLoad() || inst->isStore()) { 994 toRename->iewInfo[tid].dispatchedToLSQ++; 995 } 996 toRename->iewInfo[tid].dispatched++; 997 998 continue; 999 } 1000 1001 // Check for full conditions. 1002 if (instQueue.isFull(tid)) { 1003 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1004 1005 // Call function to start blocking. 1006 block(tid); 1007 1008 // Set unblock to false. Special case where we are using 1009 // skidbuffer (unblocking) instructions but then we still 1010 // get full in the IQ. 1011 toRename->iewUnblock[tid] = false; 1012 1013 ++iewIQFullEvents; 1014 break; 1015 } else if (ldstQueue.isFull(tid)) { 1016 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1017 1018 // Call function to start blocking. 1019 block(tid); 1020 1021 // Set unblock to false. Special case where we are using 1022 // skidbuffer (unblocking) instructions but then we still 1023 // get full in the IQ. 1024 toRename->iewUnblock[tid] = false; 1025 1026 ++iewLSQFullEvents; 1027 break; 1028 } 1029 1030 // Otherwise issue the instruction just fine. 1031 if (inst->isLoad()) { 1032 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1033 "encountered, adding to LSQ.\n", tid); 1034 1035 // Reserve a spot in the load store queue for this 1036 // memory access. 1037 ldstQueue.insertLoad(inst); 1038 1039 ++iewDispLoadInsts; 1040 1041 add_to_iq = true; 1042 1043 toRename->iewInfo[tid].dispatchedToLSQ++; 1044 } else if (inst->isStore()) { 1045 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1046 "encountered, adding to LSQ.\n", tid); 1047 1048 ldstQueue.insertStore(inst); 1049 1050 ++iewDispStoreInsts; 1051 1052 if (inst->isStoreConditional()) { 1053 // Store conditionals need to be set as "canCommit()" 1054 // so that commit can process them when they reach the 1055 // head of commit. 1056 // @todo: This is somewhat specific to Alpha. 1057 inst->setCanCommit(); 1058 instQueue.insertNonSpec(inst); 1059 add_to_iq = false; 1060 1061 ++iewDispNonSpecInsts; 1062 } else { 1063 add_to_iq = true; 1064 } 1065 1066 toRename->iewInfo[tid].dispatchedToLSQ++; 1067 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1068 // Same as non-speculative stores. 1069 inst->setCanCommit(); 1070 instQueue.insertBarrier(inst); 1071 add_to_iq = false; 1072 } else if (inst->isNop()) { 1073 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1074 "skipping.\n", tid); 1075 1076 inst->setIssued(); 1077 inst->setExecuted(); 1078 inst->setCanCommit(); 1079 1080 instQueue.recordProducer(inst); 1081 1082 iewExecutedNop[tid]++; 1083 1084 add_to_iq = false; 1085 } else if (inst->isExecuted()) { 1086 assert(0 && "Instruction shouldn't be executed.\n"); 1087 DPRINTF(IEW, "Issue: Executed branch encountered, " 1088 "skipping.\n"); 1089 1090 inst->setIssued(); 1091 inst->setCanCommit(); 1092 1093 instQueue.recordProducer(inst); 1094 1095 add_to_iq = false; 1096 } else { 1097 add_to_iq = true; 1098 } 1099 if (inst->isNonSpeculative()) { 1100 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1101 "encountered, skipping.\n", tid); 1102 1103 // Same as non-speculative stores. 1104 inst->setCanCommit(); 1105 1106 // Specifically insert it as nonspeculative. 1107 instQueue.insertNonSpec(inst); 1108 1109 ++iewDispNonSpecInsts; 1110 1111 add_to_iq = false; 1112 } 1113 1114 // If the instruction queue is not full, then add the 1115 // instruction. 1116 if (add_to_iq) { 1117 instQueue.insert(inst); 1118 } 1119 1120 insts_to_dispatch.pop(); 1121 1122 toRename->iewInfo[tid].dispatched++; 1123 1124 ++iewDispatchedInsts; 1125 } 1126 1127 if (!insts_to_dispatch.empty()) { 1128 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1129 block(tid); 1130 toRename->iewUnblock[tid] = false; 1131 } 1132 1133 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1134 dispatchStatus[tid] = Running; 1135 1136 updatedQueues = true; 1137 } 1138 1139 dis_num_inst = 0; 1140} 1141 1142template <class Impl> 1143void 1144DefaultIEW<Impl>::printAvailableInsts() 1145{ 1146 int inst = 0; 1147 1148 std::cout << "Available Instructions: "; 1149 1150 while (fromIssue->insts[inst]) { 1151 1152 if (inst%3==0) std::cout << "\n\t"; 1153 1154 std::cout << "PC: " << fromIssue->insts[inst]->readPC() 1155 << " TN: " << fromIssue->insts[inst]->threadNumber 1156 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1157 1158 inst++; 1159 1160 } 1161 1162 std::cout << "\n"; 1163} 1164 1165template <class Impl> 1166void 1167DefaultIEW<Impl>::executeInsts() 1168{ 1169 wbNumInst = 0; 1170 wbCycle = 0; 1171 1172 std::list<unsigned>::iterator threads = activeThreads->begin(); 1173 std::list<unsigned>::iterator end = activeThreads->end(); 1174 1175 while (threads != end) { 1176 unsigned tid = *threads++; 1177 fetchRedirect[tid] = false; 1178 } 1179 1180 // Uncomment this if you want to see all available instructions. 1181// printAvailableInsts(); 1182 1183 // Execute/writeback any instructions that are available. 1184 int insts_to_execute = fromIssue->size; 1185 int inst_num = 0; 1186 for (; inst_num < insts_to_execute; 1187 ++inst_num) { 1188 1189 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1190 1191 DynInstPtr inst = instQueue.getInstToExecute(); 1192 1193 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1194 inst->readPC(), inst->threadNumber,inst->seqNum); 1195 1196 // Check if the instruction is squashed; if so then skip it 1197 if (inst->isSquashed()) { 1198 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1199 1200 // Consider this instruction executed so that commit can go 1201 // ahead and retire the instruction. 1202 inst->setExecuted(); 1203 1204 // Not sure if I should set this here or just let commit try to 1205 // commit any squashed instructions. I like the latter a bit more. 1206 inst->setCanCommit(); 1207 1208 ++iewExecSquashedInsts; 1209 1210 decrWb(inst->seqNum); 1211 continue; 1212 } 1213 1214 Fault fault = NoFault; 1215 1216 // Execute instruction. 1217 // Note that if the instruction faults, it will be handled 1218 // at the commit stage. 1219 if (inst->isMemRef() && 1220 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1221 DPRINTF(IEW, "Execute: Calculating address for memory " 1222 "reference.\n"); 1223 1224 // Tell the LDSTQ to execute this instruction (if it is a load). 1225 if (inst->isLoad()) { 1226 // Loads will mark themselves as executed, and their writeback 1227 // event adds the instruction to the queue to commit 1228 fault = ldstQueue.executeLoad(inst); 1229 } else if (inst->isStore()) { 1230 fault = ldstQueue.executeStore(inst); 1231 1232 // If the store had a fault then it may not have a mem req 1233 if (!inst->isStoreConditional() && fault == NoFault) { 1234 inst->setExecuted(); 1235 1236 instToCommit(inst); 1237 } else if (fault != NoFault) { 1238 // If the instruction faulted, then we need to send it along to commit 1239 // without the instruction completing. 1240 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 1241 fault->name(), inst->seqNum); 1242 1243 // Send this instruction to commit, also make sure iew stage 1244 // realizes there is activity. 1245 inst->setExecuted(); 1246 1247 instToCommit(inst); 1248 activityThisCycle(); 1249 } 1250 1251 // Store conditionals will mark themselves as 1252 // executed, and their writeback event will add the 1253 // instruction to the queue to commit. 1254 } else { 1255 panic("Unexpected memory type!\n"); 1256 } 1257 1258 } else { 1259 inst->execute(); 1260 1261 inst->setExecuted(); 1262 1263 instToCommit(inst); 1264 } 1265 1266 updateExeInstStats(inst); 1267 1268 // Check if branch prediction was correct, if not then we need 1269 // to tell commit to squash in flight instructions. Only 1270 // handle this if there hasn't already been something that 1271 // redirects fetch in this group of instructions. 1272 1273 // This probably needs to prioritize the redirects if a different 1274 // scheduler is used. Currently the scheduler schedules the oldest 1275 // instruction first, so the branch resolution order will be correct. 1276 unsigned tid = inst->threadNumber; 1277 1278 if (!fetchRedirect[tid] || 1279 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1280 1281 if (inst->mispredicted()) { 1282 fetchRedirect[tid] = true; 1283 1284 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1285 DPRINTF(IEW, "Predicted target was %#x, %#x.\n", 1286 inst->readPredPC(), inst->readPredNPC()); 1287 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1288 " NPC: %#x.\n", inst->readNextPC(), 1289 inst->readNextNPC()); 1290 // If incorrect, then signal the ROB that it must be squashed. 1291 squashDueToBranch(inst, tid); 1292 1293 if (inst->readPredTaken()) { 1294 predictedTakenIncorrect++; 1295 } else { 1296 predictedNotTakenIncorrect++; 1297 } 1298 } else if (ldstQueue.violation(tid)) { 1299 assert(inst->isMemRef()); 1300 // If there was an ordering violation, then get the 1301 // DynInst that caused the violation. Note that this 1302 // clears the violation signal. 1303 DynInstPtr violator; 1304 violator = ldstQueue.getMemDepViolator(tid); 1305 1306 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1307 "%#x, inst PC: %#x. Addr is: %#x.\n", 1308 violator->readPC(), inst->readPC(), inst->physEffAddr); 1309 1310 // Ensure the violating instruction is older than 1311 // current squash 1312/* if (fetchRedirect[tid] && 1313 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 1314 continue; 1315*/ 1316 fetchRedirect[tid] = true; 1317 1318 // Tell the instruction queue that a violation has occured. 1319 instQueue.violation(inst, violator); 1320 1321 // Squash. 1322 squashDueToMemOrder(inst,tid); 1323 1324 ++memOrderViolationEvents; 1325 } else if (ldstQueue.loadBlocked(tid) && 1326 !ldstQueue.isLoadBlockedHandled(tid)) { 1327 fetchRedirect[tid] = true; 1328 1329 DPRINTF(IEW, "Load operation couldn't execute because the " 1330 "memory system is blocked. PC: %#x [sn:%lli]\n", 1331 inst->readPC(), inst->seqNum); 1332 1333 squashDueToMemBlocked(inst, tid); 1334 } 1335 } else { 1336 // Reset any state associated with redirects that will not 1337 // be used. 1338 if (ldstQueue.violation(tid)) { 1339 assert(inst->isMemRef()); 1340 1341 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1342 1343 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1344 "%#x, inst PC: %#x. Addr is: %#x.\n", 1345 violator->readPC(), inst->readPC(), inst->physEffAddr); 1346 DPRINTF(IEW, "Violation will not be handled because " 1347 "already squashing\n"); 1348 1349 ++memOrderViolationEvents; 1350 } 1351 if (ldstQueue.loadBlocked(tid) && 1352 !ldstQueue.isLoadBlockedHandled(tid)) { 1353 DPRINTF(IEW, "Load operation couldn't execute because the " 1354 "memory system is blocked. PC: %#x [sn:%lli]\n", 1355 inst->readPC(), inst->seqNum); 1356 DPRINTF(IEW, "Blocked load will not be handled because " 1357 "already squashing\n"); 1358 1359 ldstQueue.setLoadBlockedHandled(tid); 1360 } 1361 1362 } 1363 } 1364 1365 // Update and record activity if we processed any instructions. 1366 if (inst_num) { 1367 if (exeStatus == Idle) { 1368 exeStatus = Running; 1369 } 1370 1371 updatedQueues = true; 1372 1373 cpu->activityThisCycle(); 1374 } 1375 1376 // Need to reset this in case a writeback event needs to write into the 1377 // iew queue. That way the writeback event will write into the correct 1378 // spot in the queue. 1379 wbNumInst = 0; 1380} 1381 1382template <class Impl> 1383void 1384DefaultIEW<Impl>::writebackInsts() 1385{ 1386 // Loop through the head of the time buffer and wake any 1387 // dependents. These instructions are about to write back. Also 1388 // mark scoreboard that this instruction is finally complete. 1389 // Either have IEW have direct access to scoreboard, or have this 1390 // as part of backwards communication. 1391 for (int inst_num = 0; inst_num < wbWidth && 1392 toCommit->insts[inst_num]; inst_num++) { 1393 DynInstPtr inst = toCommit->insts[inst_num]; 1394 int tid = inst->threadNumber; 1395 1396 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1397 inst->seqNum, inst->readPC()); 1398 1399 iewInstsToCommit[tid]++; 1400 1401 // Some instructions will be sent to commit without having 1402 // executed because they need commit to handle them. 1403 // E.g. Uncached loads have not actually executed when they 1404 // are first sent to commit. Instead commit must tell the LSQ 1405 // when it's ready to execute the uncached load. 1406 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1407 int dependents = instQueue.wakeDependents(inst); 1408 1409 for (int i = 0; i < inst->numDestRegs(); i++) { 1410 //mark as Ready 1411 DPRINTF(IEW,"Setting Destination Register %i\n", 1412 inst->renamedDestRegIdx(i)); 1413 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1414 } 1415 1416 if (dependents) { 1417 producerInst[tid]++; 1418 consumerInst[tid]+= dependents; 1419 } 1420 writebackCount[tid]++; 1421 } 1422 1423 decrWb(inst->seqNum); 1424 } 1425} 1426 1427template<class Impl> 1428void 1429DefaultIEW<Impl>::tick() 1430{ 1431 wbNumInst = 0; 1432 wbCycle = 0; 1433 1434 wroteToTimeBuffer = false; 1435 updatedQueues = false; 1436 1437 sortInsts(); 1438 1439 // Free function units marked as being freed this cycle. 1440 fuPool->processFreeUnits(); 1441 1442 std::list<unsigned>::iterator threads = activeThreads->begin(); 1443 std::list<unsigned>::iterator end = activeThreads->end(); 1444 1445 // Check stall and squash signals, dispatch any instructions. 1446 while (threads != end) { 1447 unsigned tid = *threads++; 1448 1449 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1450 1451 checkSignalsAndUpdate(tid); 1452 dispatch(tid); 1453 } 1454 1455 if (exeStatus != Squashing) { 1456 executeInsts(); 1457 1458 writebackInsts(); 1459 1460 // Have the instruction queue try to schedule any ready instructions. 1461 // (In actuality, this scheduling is for instructions that will 1462 // be executed next cycle.) 1463 instQueue.scheduleReadyInsts(); 1464 1465 // Also should advance its own time buffers if the stage ran. 1466 // Not the best place for it, but this works (hopefully). 1467 issueToExecQueue.advance(); 1468 } 1469 1470 bool broadcast_free_entries = false; 1471 1472 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1473 exeStatus = Idle; 1474 updateLSQNextCycle = false; 1475 1476 broadcast_free_entries = true; 1477 } 1478 1479 // Writeback any stores using any leftover bandwidth. 1480 ldstQueue.writebackStores(); 1481 1482 // Check the committed load/store signals to see if there's a load 1483 // or store to commit. Also check if it's being told to execute a 1484 // nonspeculative instruction. 1485 // This is pretty inefficient... 1486 1487 threads = activeThreads->begin(); 1488 while (threads != end) { 1489 unsigned tid = (*threads++); 1490 1491 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1492 1493 // Update structures based on instructions committed. 1494 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1495 !fromCommit->commitInfo[tid].squash && 1496 !fromCommit->commitInfo[tid].robSquashing) { 1497 1498 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1499 1500 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1501 1502 updateLSQNextCycle = true; 1503 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1504 } 1505 1506 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1507 1508 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1509 if (fromCommit->commitInfo[tid].uncached) { 1510 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1511 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1512 } else { 1513 instQueue.scheduleNonSpec( 1514 fromCommit->commitInfo[tid].nonSpecSeqNum); 1515 } 1516 } 1517 1518 if (broadcast_free_entries) { 1519 toFetch->iewInfo[tid].iqCount = 1520 instQueue.getCount(tid); 1521 toFetch->iewInfo[tid].ldstqCount = 1522 ldstQueue.getCount(tid); 1523 1524 toRename->iewInfo[tid].usedIQ = true; 1525 toRename->iewInfo[tid].freeIQEntries = 1526 instQueue.numFreeEntries(); 1527 toRename->iewInfo[tid].usedLSQ = true; 1528 toRename->iewInfo[tid].freeLSQEntries = 1529 ldstQueue.numFreeEntries(tid); 1530 1531 wroteToTimeBuffer = true; 1532 } 1533 1534 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1535 tid, toRename->iewInfo[tid].dispatched); 1536 } 1537 1538 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1539 "LSQ has %i free entries.\n", 1540 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1541 ldstQueue.numFreeEntries()); 1542 1543 updateStatus(); 1544 1545 if (wroteToTimeBuffer) { 1546 DPRINTF(Activity, "Activity this cycle.\n"); 1547 cpu->activityThisCycle(); 1548 } 1549} 1550 1551template <class Impl> 1552void 1553DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1554{ 1555 int thread_number = inst->threadNumber; 1556 1557 // 1558 // Pick off the software prefetches 1559 // 1560#ifdef TARGET_ALPHA 1561 if (inst->isDataPrefetch()) 1562 iewExecutedSwp[thread_number]++; 1563 else 1564 iewIewExecutedcutedInsts++; 1565#else 1566 iewExecutedInsts++; 1567#endif 1568 1569 // 1570 // Control operations 1571 // 1572 if (inst->isControl()) 1573 iewExecutedBranches[thread_number]++; 1574 1575 // 1576 // Memory operations 1577 // 1578 if (inst->isMemRef()) { 1579 iewExecutedRefs[thread_number]++; 1580 1581 if (inst->isLoad()) { 1582 iewExecLoadInsts[thread_number]++; 1583 } 1584 } 1585} 1586