iew_impl.hh revision 5215
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 310239Sbinhpham@cs.rutgers.edu * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * Redistribution and use in source and binary forms, with or without 67598Sminkyu.jeong@arm.com * modification, are permitted provided that the following conditions are 77598Sminkyu.jeong@arm.com * met: redistributions of source code must retain the above copyright 87598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer; 97598Sminkyu.jeong@arm.com * redistributions in binary form must reproduce the above copyright 107598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer in the 117598Sminkyu.jeong@arm.com * documentation and/or other materials provided with the distribution; 127598Sminkyu.jeong@arm.com * neither the name of the copyright holders nor the names of its 137598Sminkyu.jeong@arm.com * contributors may be used to endorse or promote products derived from 147598Sminkyu.jeong@arm.com * this software without specific prior written permission. 152326SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A * 281689SN/A * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311689SN/A// @todo: Fix the instantaneous communication among all the stages within 321689SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341689SN/A 351689SN/A#include <queue> 361689SN/A 371689SN/A#include "base/timebuf.hh" 381689SN/A#include "cpu/o3/fu_pool.hh" 391689SN/A#include "cpu/o3/iew.hh" 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.edutemplate<class Impl> 421689SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params) 431689SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 449944Smatt.horsnell@ARM.com cpu(_cpu), 459944Smatt.horsnell@ARM.com instQueue(_cpu, this, params), 469944Smatt.horsnell@ARM.com ldstQueue(_cpu, this, params), 471060SN/A fuPool(params->fuPool), 481060SN/A commitToIEWDelay(params->commitToIEWDelay), 491689SN/A renameToIEWDelay(params->renameToIEWDelay), 501060SN/A issueToExecuteDelay(params->issueToExecuteDelay), 511060SN/A dispatchWidth(params->dispatchWidth), 521060SN/A issueWidth(params->issueWidth), 538230Snate@binkert.org wbOutstanding(0), 546658Snate@binkert.org wbWidth(params->wbWidth), 558887Sgeoffrey.blake@arm.com numThreads(params->numberOfThreads), 562292SN/A switchedOut(false) 571717SN/A{ 588229Snate@binkert.org _status = Active; 598232Snate@binkert.org exeStatus = Running; 609444SAndreas.Sandberg@ARM.com wbStatus = Idle; 618232Snate@binkert.org 629527SMatt.Horsnell@arm.com // Setup wire to read instructions coming from issue. 635529Snate@binkert.org fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 641060SN/A 656221Snate@binkert.org // Instruction queue needs the queue between issue and execute. 666221Snate@binkert.org instQueue.setIssueToExecuteQueue(&issueToExecQueue); 671681SN/A 685529Snate@binkert.org for (int i=0; i < numThreads; i++) { 692873Sktlim@umich.edu dispatchStatus[i] = Running; 704329Sktlim@umich.edu stalls[i].commit = false; 714329Sktlim@umich.edu fetchRedirect[i] = false; 724329Sktlim@umich.edu } 732292SN/A 742292SN/A wbMax = wbWidth * params->wbDepth; 752292SN/A 762292SN/A updateLSQNextCycle = false; 772820Sktlim@umich.edu 782292SN/A ableToIssue = true; 792820Sktlim@umich.edu 802820Sktlim@umich.edu skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 819444SAndreas.Sandberg@ARM.com} 821060SN/A 8310172Sdam.sunwoo@arm.comtemplate <class Impl> 8410172Sdam.sunwoo@arm.comstd::string 8510172Sdam.sunwoo@arm.comDefaultIEW<Impl>::name() const 8610172Sdam.sunwoo@arm.com{ 8710172Sdam.sunwoo@arm.com return cpu->name() + ".iew"; 8810172Sdam.sunwoo@arm.com} 8910172Sdam.sunwoo@arm.com 9010172Sdam.sunwoo@arm.comtemplate <class Impl> 9110172Sdam.sunwoo@arm.comvoid 9210172Sdam.sunwoo@arm.comDefaultIEW<Impl>::regStats() 9310172Sdam.sunwoo@arm.com{ 9410172Sdam.sunwoo@arm.com using namespace Stats; 9510172Sdam.sunwoo@arm.com 962292SN/A instQueue.regStats(); 972292SN/A ldstQueue.regStats(); 982292SN/A 991060SN/A iewIdleCycles 1001060SN/A .name(name() + ".iewIdleCycles") 1011060SN/A .desc("Number of cycles IEW is idle"); 1021060SN/A 1031060SN/A iewSquashCycles 1041060SN/A .name(name() + ".iewSquashCycles") 1051681SN/A .desc("Number of cycles IEW is squashing"); 1066221Snate@binkert.org 1076221Snate@binkert.org iewBlockCycles 1086221Snate@binkert.org .name(name() + ".iewBlockCycles") 1096221Snate@binkert.org .desc("Number of cycles IEW is blocking"); 1102292SN/A 1112292SN/A iewUnblockCycles 1122820Sktlim@umich.edu .name(name() + ".iewUnblockCycles") 1132820Sktlim@umich.edu .desc("Number of cycles IEW is unblocking"); 1142292SN/A 1152292SN/A iewDispatchedInsts 1162820Sktlim@umich.edu .name(name() + ".iewDispatchedInsts") 1172820Sktlim@umich.edu .desc("Number of instructions dispatched to IQ"); 1182292SN/A 1192292SN/A iewDispSquashedInsts 1202292SN/A .name(name() + ".iewDispSquashedInsts") 1212292SN/A .desc("Number of squashed instructions skipped by dispatch"); 1222292SN/A 1232292SN/A iewDispLoadInsts 1242292SN/A .name(name() + ".iewDispLoadInsts") 1252292SN/A .desc("Number of dispatched load instructions"); 1261060SN/A 1271060SN/A iewDispStoreInsts 1281681SN/A .name(name() + ".iewDispStoreInsts") 1291062SN/A .desc("Number of dispatched store instructions"); 13010023Smatt.horsnell@ARM.com 13110023Smatt.horsnell@ARM.com iewDispNonSpecInsts 13210023Smatt.horsnell@ARM.com .name(name() + ".iewDispNonSpecInsts") 13310023Smatt.horsnell@ARM.com .desc("Number of dispatched non-speculative instructions"); 13410023Smatt.horsnell@ARM.com 13510023Smatt.horsnell@ARM.com iewIQFullEvents 13610023Smatt.horsnell@ARM.com .name(name() + ".iewIQFullEvents") 13710023Smatt.horsnell@ARM.com .desc("Number of times the IQ has become full, causing a stall"); 1382292SN/A 1391062SN/A iewLSQFullEvents 1402301SN/A .name(name() + ".iewLSQFullEvents") 1412301SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1421062SN/A 1432727Sktlim@umich.edu memOrderViolationEvents 1441062SN/A .name(name() + ".memOrderViolationEvents") 1451062SN/A .desc("Number of memory order violations"); 1461062SN/A 1471062SN/A predictedTakenIncorrect 1481062SN/A .name(name() + ".predictedTakenIncorrect") 1491062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1501062SN/A 1511062SN/A predictedNotTakenIncorrect 1521062SN/A .name(name() + ".predictedNotTakenIncorrect") 1531062SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1541062SN/A 1551062SN/A branchMispredicts 1561062SN/A .name(name() + ".branchMispredicts") 1571062SN/A .desc("Number of branch mispredicts detected at execute"); 1581062SN/A 1591062SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1601062SN/A 1611062SN/A iewExecutedInsts 1621062SN/A .name(name() + ".iewExecutedInsts") 1631062SN/A .desc("Number of executed instructions"); 1641062SN/A 1651062SN/A iewExecLoadInsts 1661062SN/A .init(cpu->number_of_threads) 1671062SN/A .name(name() + ".iewExecLoadInsts") 1681062SN/A .desc("Number of load instructions executed") 1691062SN/A .flags(total); 1701062SN/A 1711062SN/A iewExecSquashedInsts 1721062SN/A .name(name() + ".iewExecSquashedInsts") 1731062SN/A .desc("Number of squashed instructions skipped in execute"); 1741062SN/A 1751062SN/A iewExecutedSwp 1761062SN/A .init(cpu->number_of_threads) 1771062SN/A .name(name() + ".EXEC:swp") 1781062SN/A .desc("number of swp insts executed") 1791062SN/A .flags(total); 1801062SN/A 1811062SN/A iewExecutedNop 1821062SN/A .init(cpu->number_of_threads) 1831062SN/A .name(name() + ".EXEC:nop") 1841062SN/A .desc("number of nop insts executed") 1852292SN/A .flags(total); 1862292SN/A 1872292SN/A iewExecutedRefs 1882292SN/A .init(cpu->number_of_threads) 1891062SN/A .name(name() + ".EXEC:refs") 1901062SN/A .desc("number of memory reference insts executed") 1911062SN/A .flags(total); 1921062SN/A 1931062SN/A iewExecutedBranches 1941062SN/A .init(cpu->number_of_threads) 1951062SN/A .name(name() + ".EXEC:branches") 1962292SN/A .desc("Number of branches executed") 1972292SN/A .flags(total); 1982292SN/A 1992292SN/A iewExecStoreInsts 2002292SN/A .name(name() + ".EXEC:stores") 2012292SN/A .desc("Number of stores executed") 2022292SN/A .flags(total); 2032292SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2042292SN/A 2052292SN/A iewExecRate 2062301SN/A .name(name() + ".EXEC:rate") 2072727Sktlim@umich.edu .desc("Inst execution rate") 2082353SN/A .flags(total); 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2112727Sktlim@umich.edu 2126221Snate@binkert.org iewInstsToCommit 2132353SN/A .init(cpu->number_of_threads) 2142727Sktlim@umich.edu .name(name() + ".WB:sent") 2152727Sktlim@umich.edu .desc("cumulative count of insts sent to commit") 2162727Sktlim@umich.edu .flags(total); 2172727Sktlim@umich.edu 2182353SN/A writebackCount 2192727Sktlim@umich.edu .init(cpu->number_of_threads) 2202727Sktlim@umich.edu .name(name() + ".WB:count") 2212727Sktlim@umich.edu .desc("cumulative count of insts written-back") 2226221Snate@binkert.org .flags(total); 2238240Snate@binkert.org 2242301SN/A producerInst 2252727Sktlim@umich.edu .init(cpu->number_of_threads) 2262301SN/A .name(name() + ".WB:producers") 2272727Sktlim@umich.edu .desc("num instructions producing a value") 2286221Snate@binkert.org .flags(total); 2298240Snate@binkert.org 2302301SN/A consumerInst 2312727Sktlim@umich.edu .init(cpu->number_of_threads) 2322301SN/A .name(name() + ".WB:consumers") 2332727Sktlim@umich.edu .desc("num instructions consuming a value") 2346221Snate@binkert.org .flags(total); 2358240Snate@binkert.org 2362301SN/A wbPenalized 2372727Sktlim@umich.edu .init(cpu->number_of_threads) 2382301SN/A .name(name() + ".WB:penalized") 2392727Sktlim@umich.edu .desc("number of instrctions required to write to 'other' IQ") 2406221Snate@binkert.org .flags(total); 2418240Snate@binkert.org 2422301SN/A wbPenalizedRate 2432727Sktlim@umich.edu .name(name() + ".WB:penalized_rate") 2442301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2452301SN/A .flags(total); 2468240Snate@binkert.org 2472301SN/A wbPenalizedRate = wbPenalized / writebackCount; 2482727Sktlim@umich.edu 2492727Sktlim@umich.edu wbFanout 2502727Sktlim@umich.edu .name(name() + ".WB:fanout") 2512727Sktlim@umich.edu .desc("average fanout of values written-back") 2528240Snate@binkert.org .flags(total); 2532727Sktlim@umich.edu 2542727Sktlim@umich.edu wbFanout = producerInst / consumerInst; 2552727Sktlim@umich.edu 2562727Sktlim@umich.edu wbRate 2572301SN/A .name(name() + ".WB:rate") 2582301SN/A .desc("insts written-back per cycle") 2596221Snate@binkert.org .flags(total); 2608240Snate@binkert.org wbRate = writebackCount / cpu->numCycles; 2612301SN/A} 2622727Sktlim@umich.edu 2632301SN/Atemplate<class Impl> 2642326SN/Avoid 2656221Snate@binkert.orgDefaultIEW<Impl>::initStage() 2668240Snate@binkert.org{ 2672301SN/A for (int tid=0; tid < numThreads; tid++) { 2682727Sktlim@umich.edu toRename->iewInfo[tid].usedIQ = true; 2692301SN/A toRename->iewInfo[tid].freeIQEntries = 2702326SN/A instQueue.numFreeEntries(tid); 2716221Snate@binkert.org 2728240Snate@binkert.org toRename->iewInfo[tid].usedLSQ = true; 2732301SN/A toRename->iewInfo[tid].freeLSQEntries = 2742727Sktlim@umich.edu ldstQueue.numFreeEntries(tid); 2752301SN/A } 2762326SN/A 2776221Snate@binkert.org cpu->activateStage(O3CPU::IEWIdx); 2788240Snate@binkert.org} 2792301SN/A 2802727Sktlim@umich.edutemplate<class Impl> 2812301SN/Avoid 2822326SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2836221Snate@binkert.org{ 2848240Snate@binkert.org timeBuffer = tb_ptr; 2852301SN/A 2862727Sktlim@umich.edu // Setup wire to read information from time buffer, from commit. 2872301SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2882326SN/A 2898240Snate@binkert.org // Setup wire to write information back to previous stages. 2902301SN/A toRename = timeBuffer->getWire(0); 2912727Sktlim@umich.edu 2922301SN/A toFetch = timeBuffer->getWire(0); 2932326SN/A 2942301SN/A // Instruction queue also needs main time buffer. 2952326SN/A instQueue.setTimeBuffer(tb_ptr); 2968240Snate@binkert.org} 2972301SN/A 2982727Sktlim@umich.edutemplate<class Impl> 2992301SN/Avoid 3002326SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3012301SN/A{ 3022326SN/A renameQueue = rq_ptr; 3038240Snate@binkert.org 3042301SN/A // Setup wire to read information from rename queue. 3052727Sktlim@umich.edu fromRename = renameQueue->getWire(-renameToIEWDelay); 3062326SN/A} 3071062SN/A 3081062SN/Atemplate<class Impl> 3091681SN/Avoid 3101060SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3119427SAndreas.Sandberg@ARM.com{ 3121060SN/A iewQueue = iq_ptr; 3136221Snate@binkert.org 3142292SN/A // Setup wire to write instructions to commit. 3152292SN/A toCommit = iewQueue->getWire(0); 3162292SN/A} 3172292SN/A 3182292SN/Atemplate<class Impl> 31910239Sbinhpham@cs.rutgers.eduvoid 32010239Sbinhpham@cs.rutgers.eduDefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3212292SN/A{ 3222292SN/A activeThreads = at_ptr; 3238887Sgeoffrey.blake@arm.com 3248733Sgeoffrey.blake@arm.com ldstQueue.setActiveThreads(at_ptr); 3258850Sandreas.hansson@arm.com instQueue.setActiveThreads(at_ptr); 3268887Sgeoffrey.blake@arm.com} 3278733Sgeoffrey.blake@arm.com 3282733Sktlim@umich.edutemplate<class Impl> 3291060SN/Avoid 3301060SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3311681SN/A{ 3321060SN/A scoreboard = sb_ptr; 3332292SN/A} 3341060SN/A 3351060SN/Atemplate <class Impl> 3361060SN/Abool 3371060SN/ADefaultIEW<Impl>::drain() 3381060SN/A{ 3391060SN/A // IEW is ready to drain at any time. 3401060SN/A cpu->signalDrained(); 3411060SN/A return true; 3421060SN/A} 3432292SN/A 3442292SN/Atemplate <class Impl> 3451060SN/Avoid 3461060SN/ADefaultIEW<Impl>::resume() 3471060SN/A{ 3481060SN/A} 3491681SN/A 3501060SN/Atemplate <class Impl> 3512292SN/Avoid 3521060SN/ADefaultIEW<Impl>::switchOut() 3531060SN/A{ 3541060SN/A // Clear any state. 3551060SN/A switchedOut = true; 3561060SN/A assert(insts[0].empty()); 3571060SN/A assert(skidBuffer[0].empty()); 3581060SN/A 3591681SN/A instQueue.switchOut(); 3601060SN/A ldstQueue.switchOut(); 3612292SN/A fuPool->switchOut(); 3621060SN/A 3631060SN/A for (int i = 0; i < numThreads; i++) { 3641060SN/A while (!insts[i].empty()) 3651060SN/A insts[i].pop(); 3661060SN/A while (!skidBuffer[i].empty()) 3671060SN/A skidBuffer[i].pop(); 3681060SN/A } 3691681SN/A} 3701060SN/A 3716221Snate@binkert.orgtemplate <class Impl> 3721060SN/Avoid 3732292SN/ADefaultIEW<Impl>::takeOverFrom() 3742292SN/A{ 3752292SN/A // Reset all state. 3762292SN/A _status = Active; 3771060SN/A exeStatus = Running; 3781060SN/A wbStatus = Idle; 3791681SN/A switchedOut = false; 3801060SN/A 3812292SN/A instQueue.takeOverFrom(); 3821060SN/A ldstQueue.takeOverFrom(); 3832292SN/A fuPool->takeOverFrom(); 3841060SN/A 3851060SN/A initStage(); 3862307SN/A cpu->activityThisCycle(); 3872863Sktlim@umich.edu 3889444SAndreas.Sandberg@ARM.com for (int i=0; i < numThreads; i++) { 3892307SN/A dispatchStatus[i] = Running; 3909444SAndreas.Sandberg@ARM.com stalls[i].commit = false; 3919444SAndreas.Sandberg@ARM.com fetchRedirect[i] = false; 3929444SAndreas.Sandberg@ARM.com } 3939444SAndreas.Sandberg@ARM.com 3949444SAndreas.Sandberg@ARM.com updateLSQNextCycle = false; 3959444SAndreas.Sandberg@ARM.com 3969444SAndreas.Sandberg@ARM.com for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 3979444SAndreas.Sandberg@ARM.com issueToExecQueue.advance(); 3989444SAndreas.Sandberg@ARM.com } 3999444SAndreas.Sandberg@ARM.com} 4009444SAndreas.Sandberg@ARM.com 4019444SAndreas.Sandberg@ARM.comtemplate<class Impl> 4029444SAndreas.Sandberg@ARM.comvoid 4039783Sandreas.hansson@arm.comDefaultIEW<Impl>::squash(unsigned tid) 4049783Sandreas.hansson@arm.com{ 4059783Sandreas.hansson@arm.com DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4069783Sandreas.hansson@arm.com tid); 4079783Sandreas.hansson@arm.com 4089783Sandreas.hansson@arm.com // Tell the IQ to start squashing. 4099783Sandreas.hansson@arm.com instQueue.squash(tid); 4109783Sandreas.hansson@arm.com 4119444SAndreas.Sandberg@ARM.com // Tell the LDSTQ to start squashing. 4121681SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4131681SN/A updatedQueues = true; 4142316SN/A 4151681SN/A // Clear the skid buffer in case it has any data in it. 4169444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4172843Sktlim@umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4189444SAndreas.Sandberg@ARM.com 4192843Sktlim@umich.edu while (!skidBuffer[tid].empty()) { 4209444SAndreas.Sandberg@ARM.com if (skidBuffer[tid].front()->isLoad() || 4219444SAndreas.Sandberg@ARM.com skidBuffer[tid].front()->isStore() ) { 4221681SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4231681SN/A } 4242307SN/A 4251681SN/A toRename->iewInfo[tid].dispatched++; 4262307SN/A 4271060SN/A skidBuffer[tid].pop(); 4282348SN/A } 4292307SN/A 4302307SN/A emptyRenameInsts(tid); 4312307SN/A} 4321060SN/A 4332307SN/Atemplate<class Impl> 4342307SN/Avoid 4359444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4361060SN/A{ 4379427SAndreas.Sandberg@ARM.com DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4382307SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4391060SN/A 4406221Snate@binkert.org toCommit->squash[tid] = true; 4416221Snate@binkert.org toCommit->squashedSeqNum[tid] = inst->seqNum; 4426221Snate@binkert.org toCommit->mispredPC[tid] = inst->readPC(); 4436221Snate@binkert.org toCommit->branchMispredict[tid] = true; 4442307SN/A 4451060SN/A#if ISA_HAS_DELAY_SLOT 4462307SN/A int instSize = sizeof(TheISA::MachInst); 4472307SN/A toCommit->branchTaken[tid] = 4482873Sktlim@umich.edu !(inst->readNextPC() + instSize == inst->readNextNPC() && 4492307SN/A (inst->readNextPC() == inst->readPC() + instSize || 4501060SN/A inst->readNextPC() == inst->readPC() + 2 * instSize)); 4511060SN/A#else 4521060SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4531681SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4541060SN/A#endif 4556221Snate@binkert.org toCommit->nextPC[tid] = inst->readNextPC(); 4562107SN/A toCommit->nextNPC[tid] = inst->readNextNPC(); 4576221Snate@binkert.org toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 4582107SN/A 4592292SN/A toCommit->includeSquashInst[tid] = false; 4602292SN/A 4612107SN/A wroteToTimeBuffer = true; 4622292SN/A} 4632326SN/A 4642292SN/Atemplate<class Impl> 4652107SN/Avoid 4662292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4672935Sksewell@umich.edu{ 4684632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4692935Sksewell@umich.edu "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4702292SN/A 47110239Sbinhpham@cs.rutgers.edu toCommit->squash[tid] = true; 47210239Sbinhpham@cs.rutgers.edu toCommit->squashedSeqNum[tid] = inst->seqNum; 47310239Sbinhpham@cs.rutgers.edu toCommit->nextPC[tid] = inst->readNextPC(); 47410239Sbinhpham@cs.rutgers.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 47510239Sbinhpham@cs.rutgers.edu toCommit->branchMispredict[tid] = false; 4762292SN/A 4772107SN/A toCommit->includeSquashInst[tid] = false; 4782292SN/A 4792107SN/A wroteToTimeBuffer = true; 4802292SN/A} 4812292SN/A 4822107SN/Atemplate<class Impl> 4832702Sktlim@umich.eduvoid 4842107SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 4852107SN/A{ 4862107SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4872107SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4886221Snate@binkert.org 4892292SN/A toCommit->squash[tid] = true; 4907720Sgblack@eecs.umich.edu toCommit->squashedSeqNum[tid] = inst->seqNum; 4917720Sgblack@eecs.umich.edu toCommit->nextPC[tid] = inst->readPC(); 4922292SN/A toCommit->nextNPC[tid] = inst->readNextPC(); 49310231Ssteve.reinhardt@amd.com toCommit->branchMispredict[tid] = false; 4947852SMatt.Horsnell@arm.com 4957852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 4967852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 4977852SMatt.Horsnell@arm.com 4982935Sksewell@umich.edu ldstQueue.setLoadBlockedHandled(tid); 4997852SMatt.Horsnell@arm.com 5007852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5012292SN/A} 5027852SMatt.Horsnell@arm.com 5037852SMatt.Horsnell@arm.comtemplate<class Impl> 5047852SMatt.Horsnell@arm.comvoid 5052292SN/ADefaultIEW<Impl>::block(unsigned tid) 5067852SMatt.Horsnell@arm.com{ 5077852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5087852SMatt.Horsnell@arm.com 5092292SN/A if (dispatchStatus[tid] != Blocked && 5102292SN/A dispatchStatus[tid] != Unblocking) { 5112292SN/A toRename->iewBlock[tid] = true; 5122292SN/A wroteToTimeBuffer = true; 5136221Snate@binkert.org } 5142292SN/A 5158513SGiacomo.Gabrielli@arm.com // Add the current inputs to the skid buffer so they can be 5168513SGiacomo.Gabrielli@arm.com // reprocessed when this stage unblocks. 5178513SGiacomo.Gabrielli@arm.com skidInsert(tid); 5188513SGiacomo.Gabrielli@arm.com 5198513SGiacomo.Gabrielli@arm.com dispatchStatus[tid] = Blocked; 5208513SGiacomo.Gabrielli@arm.com} 5218513SGiacomo.Gabrielli@arm.com 5228513SGiacomo.Gabrielli@arm.comtemplate<class Impl> 52310231Ssteve.reinhardt@amd.comvoid 5248513SGiacomo.Gabrielli@arm.comDefaultIEW<Impl>::unblock(unsigned tid) 5258513SGiacomo.Gabrielli@arm.com{ 5262292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5277852SMatt.Horsnell@arm.com "buffer %u.\n",tid, tid); 5288513SGiacomo.Gabrielli@arm.com 5298137SAli.Saidi@ARM.com // If the skid bufffer is empty, signal back to previous stages to unblock. 5302292SN/A // Also switch status to running. 5318513SGiacomo.Gabrielli@arm.com if (skidBuffer[tid].empty()) { 5328513SGiacomo.Gabrielli@arm.com toRename->iewUnblock[tid] = true; 5332292SN/A wroteToTimeBuffer = true; 5347852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5357852SMatt.Horsnell@arm.com dispatchStatus[tid] = Running; 5362292SN/A } 5372292SN/A} 5382292SN/A 5392292SN/Atemplate<class Impl> 5406221Snate@binkert.orgvoid 5412292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5422292SN/A{ 5437720Sgblack@eecs.umich.edu instQueue.wakeDependents(inst); 54410231Ssteve.reinhardt@amd.com} 5457852SMatt.Horsnell@arm.com 5467852SMatt.Horsnell@arm.comtemplate<class Impl> 5472292SN/Avoid 5487852SMatt.Horsnell@arm.comDefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5497852SMatt.Horsnell@arm.com{ 5508137SAli.Saidi@ARM.com instQueue.rescheduleMemInst(inst); 5512292SN/A} 5527852SMatt.Horsnell@arm.com 5537852SMatt.Horsnell@arm.comtemplate<class Impl> 5542292SN/Avoid 5557852SMatt.Horsnell@arm.comDefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5562292SN/A{ 5577852SMatt.Horsnell@arm.com instQueue.replayMemInst(inst); 5587852SMatt.Horsnell@arm.com} 5592292SN/A 5602292SN/Atemplate<class Impl> 5612292SN/Avoid 5622292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5636221Snate@binkert.org{ 5642292SN/A // This function should not be called after writebackInsts in a 5652292SN/A // single cycle. That will cause problems with an instruction 5662292SN/A // being added to the queue to commit without being processed by 5672292SN/A // writebackInsts prior to being sent to commit. 5682292SN/A 5692292SN/A // First check the time slot that this instruction will write 5702292SN/A // to. If there are free write ports at the time, then go ahead 5712292SN/A // and write the instruction to that time. If there are not, 5722292SN/A // keep looking back to see where's the first time there's a 5732292SN/A // free slot. 5742292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5752292SN/A ++wbNumInst; 5762292SN/A if (wbNumInst == wbWidth) { 5772292SN/A ++wbCycle; 5782292SN/A wbNumInst = 0; 5792292SN/A } 5802292SN/A 5812292SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5826221Snate@binkert.org } 5832292SN/A 5842292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 5852292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 5862292SN/A // Add finished instruction to queue to commit. 5872292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5882292SN/A (*iewQueue)[wbCycle].size++; 5892292SN/A} 5902292SN/A 5912292SN/Atemplate <class Impl> 5922292SN/Aunsigned 5932292SN/ADefaultIEW<Impl>::validInstsFromRename() 5942292SN/A{ 5952292SN/A unsigned inst_count = 0; 5962292SN/A 5972292SN/A for (int i=0; i<fromRename->size; i++) { 5982292SN/A if (!fromRename->insts[i]->isSquashed()) 5992292SN/A inst_count++; 6001060SN/A } 6011681SN/A 6021060SN/A return inst_count; 6031060SN/A} 6042292SN/A 6052292SN/Atemplate<class Impl> 6062292SN/Avoid 6072292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6082292SN/A{ 6092292SN/A DynInstPtr inst = NULL; 6101681SN/A 6111681SN/A while (!insts[tid].empty()) { 6121060SN/A inst = insts[tid].front(); 6132292SN/A 6141060SN/A insts[tid].pop(); 6152292SN/A 6162292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6171060SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6182292SN/A inst->readPC(),tid); 6192292SN/A 6202292SN/A skidBuffer[tid].push(inst); 6212292SN/A } 6223221Sktlim@umich.edu 6233221Sktlim@umich.edu assert(skidBuffer[tid].size() <= skidBufferMax && 6243221Sktlim@umich.edu "Skidbuffer Exceeded Max Size"); 6253221Sktlim@umich.edu} 6263221Sktlim@umich.edu 6272292SN/Atemplate<class Impl> 6282292SN/Aint 6292292SN/ADefaultIEW<Impl>::skidCount() 6302292SN/A{ 6312326SN/A int max=0; 6322292SN/A 6332292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 6342820Sktlim@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 6352292SN/A 6362292SN/A while (threads != end) { 6372292SN/A unsigned tid = *threads++; 6382292SN/A unsigned thread_count = skidBuffer[tid].size(); 6392353SN/A if (max < thread_count) 6402292SN/A max = thread_count; 6412292SN/A } 6422353SN/A 6432353SN/A return max; 6442292SN/A} 6452292SN/A 6462292SN/Atemplate<class Impl> 6472292SN/Abool 6482292SN/ADefaultIEW<Impl>::skidsEmpty() 6492292SN/A{ 6502292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 6512292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 6522292SN/A 6532292SN/A while (threads != end) { 6542292SN/A unsigned tid = *threads++; 6552292SN/A 6562731Sktlim@umich.edu if (!skidBuffer[tid].empty()) 6572292SN/A return false; 6582292SN/A } 6592292SN/A 6602292SN/A return true; 6612292SN/A} 6622292SN/A 6632292SN/Atemplate <class Impl> 6642292SN/Avoid 6656221Snate@binkert.orgDefaultIEW<Impl>::updateStatus() 6662292SN/A{ 6672292SN/A bool any_unblocking = false; 6682292SN/A 6692292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 6702292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 6712292SN/A 6722292SN/A while (threads != end) { 6732292SN/A unsigned tid = *threads++; 6749937SFaissal.Sleiman@arm.com 6752292SN/A if (dispatchStatus[tid] == Unblocking) { 6767720Sgblack@eecs.umich.edu any_unblocking = true; 6772292SN/A break; 6782292SN/A } 6792292SN/A } 6802292SN/A 6812292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6822292SN/A // and there's no stores waiting to write back, and dispatch is not 6832292SN/A // unblocking, then there is no internal activity for the IEW stage. 6842292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6852292SN/A !ldstQueue.willWB() && !any_unblocking) { 6862292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6872292SN/A 6882292SN/A deactivateStage(); 6892292SN/A 6902292SN/A _status = Inactive; 6916221Snate@binkert.org } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6926221Snate@binkert.org ldstQueue.willWB() || 6932292SN/A any_unblocking)) { 6943867Sbinkertn@umich.edu // Otherwise there is internal activity. Set to active. 6956221Snate@binkert.org DPRINTF(IEW, "IEW switching to active\n"); 6963867Sbinkertn@umich.edu 6972292SN/A activateStage(); 6982292SN/A 6992292SN/A _status = Active; 7002292SN/A } 7012292SN/A} 7022292SN/A 7032292SN/Atemplate <class Impl> 7042292SN/Avoid 7052292SN/ADefaultIEW<Impl>::resetEntries() 7062292SN/A{ 7072292SN/A instQueue.resetEntries(); 7086221Snate@binkert.org ldstQueue.resetEntries(); 7096221Snate@binkert.org} 7102292SN/A 7113867Sbinkertn@umich.edutemplate <class Impl> 7126221Snate@binkert.orgvoid 7133867Sbinkertn@umich.eduDefaultIEW<Impl>::readStallSignals(unsigned tid) 7143867Sbinkertn@umich.edu{ 7152292SN/A if (fromCommit->commitBlock[tid]) { 7162292SN/A stalls[tid].commit = true; 7172292SN/A } 7182292SN/A 7191062SN/A if (fromCommit->commitUnblock[tid]) { 7201062SN/A assert(stalls[tid].commit); 7211681SN/A stalls[tid].commit = false; 7221062SN/A } 7232292SN/A} 7241062SN/A 7252292SN/Atemplate <class Impl> 7261062SN/Abool 7276221Snate@binkert.orgDefaultIEW<Impl>::checkStall(unsigned tid) 7286221Snate@binkert.org{ 7291062SN/A bool ret_val(false); 7303867Sbinkertn@umich.edu 7316221Snate@binkert.org if (stalls[tid].commit) { 7321062SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7332292SN/A ret_val = true; 7342292SN/A } else if (instQueue.isFull(tid)) { 7352292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7362292SN/A ret_val = true; 7372292SN/A } else if (ldstQueue.isFull(tid)) { 7381062SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7392292SN/A 7402292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7412292SN/A 7427897Shestness@cs.utexas.edu DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7432292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7442292SN/A } 7452292SN/A 7461062SN/A if (ldstQueue.numStores(tid) > 0) { 7472292SN/A 7481062SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7492292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7502292SN/A } 7512292SN/A 7522292SN/A ret_val = true; 7532292SN/A } else if (ldstQueue.isStalled(tid)) { 7542292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7551062SN/A ret_val = true; 7562292SN/A } 7571062SN/A 7582292SN/A return ret_val; 7591062SN/A} 7601062SN/A 7611062SN/Atemplate <class Impl> 7621681SN/Avoid 7631062SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7642292SN/A{ 7651062SN/A // Check if there's a squash signal, squash if there is 7662292SN/A // Check stall signals, block if there is. 7672292SN/A // If status was Blocked 7682292SN/A // if so then go to unblocking 7691062SN/A // If status was Squashing 7702292SN/A // check if squashing is not high. Switch to running this cycle. 7712292SN/A 7726221Snate@binkert.org readStallSignals(tid); 7732292SN/A 7742292SN/A if (fromCommit->commitInfo[tid].squash) { 7752292SN/A squash(tid); 7762292SN/A 7771062SN/A if (dispatchStatus[tid] == Blocked || 7782292SN/A dispatchStatus[tid] == Unblocking) { 7792292SN/A toRename->iewUnblock[tid] = true; 7802292SN/A wroteToTimeBuffer = true; 7812292SN/A } 7822292SN/A 7832292SN/A dispatchStatus[tid] = Squashing; 7842292SN/A 7852292SN/A fetchRedirect[tid] = false; 7866221Snate@binkert.org return; 7872292SN/A } 7882292SN/A 7892292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7902292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7912292SN/A 7922292SN/A dispatchStatus[tid] = Squashing; 7932292SN/A 7942292SN/A emptyRenameInsts(tid); 7952292SN/A wroteToTimeBuffer = true; 7962292SN/A return; 7972292SN/A } 7982292SN/A 7992292SN/A if (checkStall(tid)) { 8002292SN/A block(tid); 8012292SN/A dispatchStatus[tid] = Blocked; 8022292SN/A return; 8032292SN/A } 8042292SN/A 8052292SN/A if (dispatchStatus[tid] == Blocked) { 8062292SN/A // Status from previous cycle was blocked, but there are no more stall 8072292SN/A // conditions. Switch over to unblocking. 8082292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8092292SN/A tid); 8102292SN/A 8112292SN/A dispatchStatus[tid] = Unblocking; 8122292SN/A 8132292SN/A unblock(tid); 8142292SN/A 8152292SN/A return; 8162292SN/A } 8172292SN/A 8182292SN/A if (dispatchStatus[tid] == Squashing) { 8192292SN/A // Switch status to running if rename isn't being told to block or 8202292SN/A // squash this cycle. 8212292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8226221Snate@binkert.org tid); 8232292SN/A 8242292SN/A dispatchStatus[tid] = Running; 8252292SN/A 8262292SN/A return; 8272292SN/A } 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Avoid 8322292SN/ADefaultIEW<Impl>::sortInsts() 8332292SN/A{ 8342292SN/A int insts_from_rename = fromRename->size; 8352292SN/A#ifdef DEBUG 8362292SN/A for (int i = 0; i < numThreads; i++) 8372292SN/A assert(insts[i].empty()); 8382292SN/A#endif 8392292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8402292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8412292SN/A } 8422292SN/A} 8432292SN/A 8442292SN/Atemplate <class Impl> 8452292SN/Avoid 8462292SN/ADefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8472292SN/A{ 8482702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8492292SN/A 8502292SN/A while (!insts[tid].empty()) { 8512702Sktlim@umich.edu 8522702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8532292SN/A insts[tid].front()->isStore() ) { 8542292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 8552292SN/A } 8562292SN/A 8572292SN/A toRename->iewInfo[tid].dispatched++; 8582292SN/A 8592292SN/A insts[tid].pop(); 8602292SN/A } 8612292SN/A} 8622292SN/A 8632292SN/Atemplate <class Impl> 8642292SN/Avoid 8652292SN/ADefaultIEW<Impl>::wakeCPU() 8662292SN/A{ 8672292SN/A cpu->wakeCPU(); 8682292SN/A} 8692292SN/A 8702292SN/Atemplate <class Impl> 8712292SN/Avoid 8722292SN/ADefaultIEW<Impl>::activityThisCycle() 8732292SN/A{ 8742292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8752292SN/A cpu->activityThisCycle(); 8762292SN/A} 8772292SN/A 8782292SN/Atemplate <class Impl> 8792292SN/Ainline void 8802292SN/ADefaultIEW<Impl>::activateStage() 8812292SN/A{ 8822292SN/A DPRINTF(Activity, "Activating stage.\n"); 8832292SN/A cpu->activateStage(O3CPU::IEWIdx); 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Ainline void 8882292SN/ADefaultIEW<Impl>::deactivateStage() 8892292SN/A{ 8902292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8912292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 8922326SN/A} 8936221Snate@binkert.org 8946221Snate@binkert.orgtemplate<class Impl> 8952326SN/Avoid 8962292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8972292SN/A{ 8982292SN/A // If status is Running or idle, 8992292SN/A // call dispatchInsts() 9002292SN/A // If status is Unblocking, 9012292SN/A // buffer any instructions coming from rename 9022292SN/A // continue trying to empty skid buffer 9036221Snate@binkert.org // check if stall conditions have passed 9042702Sktlim@umich.edu 9054632Sgblack@eecs.umich.edu if (dispatchStatus[tid] == Blocked) { 9062935Sksewell@umich.edu ++iewBlockCycles; 9072702Sktlim@umich.edu 9082935Sksewell@umich.edu } else if (dispatchStatus[tid] == Squashing) { 90910239Sbinhpham@cs.rutgers.edu ++iewSquashCycles; 91010239Sbinhpham@cs.rutgers.edu } 91110239Sbinhpham@cs.rutgers.edu 91210239Sbinhpham@cs.rutgers.edu // Dispatch should try to dispatch as many instructions as its bandwidth 91310239Sbinhpham@cs.rutgers.edu // will allow, as long as it is not currently blocked. 9142702Sktlim@umich.edu if (dispatchStatus[tid] == Running || 9152702Sktlim@umich.edu dispatchStatus[tid] == Idle) { 9162702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9172702Sktlim@umich.edu "dispatch.\n", tid); 9182702Sktlim@umich.edu 9192702Sktlim@umich.edu dispatchInsts(tid); 9202702Sktlim@umich.edu } else if (dispatchStatus[tid] == Unblocking) { 9212702Sktlim@umich.edu // Make sure that the skid buffer has something in it if the 9222702Sktlim@umich.edu // status is unblocking. 9232702Sktlim@umich.edu assert(!skidsEmpty()); 9242292SN/A 9252292SN/A // If the status was unblocking, then instructions from the skid 9262292SN/A // buffer were used. Remove those instructions and handle 9272292SN/A // the rest of unblocking. 9282292SN/A dispatchInsts(tid); 9292292SN/A 9302292SN/A ++iewUnblockCycles; 9312292SN/A 9322292SN/A if (validInstsFromRename()) { 9332292SN/A // Add the current inputs to the skid buffer so they can be 9342292SN/A // reprocessed when this stage unblocks. 9352292SN/A skidInsert(tid); 9362292SN/A } 9372292SN/A 9382292SN/A unblock(tid); 9392292SN/A } 9402292SN/A} 9412292SN/A 9422733Sktlim@umich.edutemplate <class Impl> 9432292SN/Avoid 9442292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9452292SN/A{ 9462292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9472292SN/A // otherwise. 9482292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9492292SN/A dispatchStatus[tid] == Unblocking ? 9502733Sktlim@umich.edu skidBuffer[tid] : insts[tid]; 9512292SN/A 9522292SN/A int insts_to_add = insts_to_dispatch.size(); 9532292SN/A 9542292SN/A DynInstPtr inst; 9556221Snate@binkert.org bool add_to_iq = false; 9562292SN/A int dis_num_inst = 0; 9572292SN/A 9582292SN/A // Loop through the instructions, putting them in the instruction 9592292SN/A // queue. 9602292SN/A for ( ; dis_num_inst < insts_to_add && 9612292SN/A dis_num_inst < dispatchWidth; 9622292SN/A ++dis_num_inst) 9632292SN/A { 9642292SN/A inst = insts_to_dispatch.front(); 9652292SN/A 9662292SN/A if (dispatchStatus[tid] == Unblocking) { 9672292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9682292SN/A "buffer\n", tid); 9692292SN/A } 9702292SN/A 9712292SN/A // Make sure there's a valid instruction there. 9722292SN/A assert(inst); 9732292SN/A 9742292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9752292SN/A "IQ.\n", 9762292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9772292SN/A 9782292SN/A // Be sure to mark these instructions as ready so that the 9792292SN/A // commit stage can go ahead and execute them, and mark 9802292SN/A // them as issued so the IQ doesn't reprocess them. 9812292SN/A 9822292SN/A // Check for squashed instructions. 9832292SN/A if (inst->isSquashed()) { 9842292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9852292SN/A "not adding to IQ.\n", tid); 9862292SN/A 9872292SN/A ++iewDispSquashedInsts; 9882292SN/A 9892292SN/A insts_to_dispatch.pop(); 9902292SN/A 9915215Sgblack@eecs.umich.edu //Tell Rename That An Instruction has been processed 9922292SN/A if (inst->isLoad() || inst->isStore()) { 9932292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9942292SN/A } 9952292SN/A toRename->iewInfo[tid].dispatched++; 9962292SN/A 9972292SN/A continue; 9982292SN/A } 9992292SN/A 10002292SN/A // Check for full conditions. 10012292SN/A if (instQueue.isFull(tid)) { 10022292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10036221Snate@binkert.org 10042292SN/A // Call function to start blocking. 10052292SN/A block(tid); 10062292SN/A 10072292SN/A // Set unblock to false. Special case where we are using 10082292SN/A // skidbuffer (unblocking) instructions but then we still 10092292SN/A // get full in the IQ. 10102292SN/A toRename->iewUnblock[tid] = false; 10112292SN/A 10122292SN/A ++iewIQFullEvents; 10132292SN/A break; 10142292SN/A } else if (ldstQueue.isFull(tid)) { 10152292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10162292SN/A 10172292SN/A // Call function to start blocking. 10182292SN/A block(tid); 10192292SN/A 10202820Sktlim@umich.edu // Set unblock to false. Special case where we are using 10212292SN/A // skidbuffer (unblocking) instructions but then we still 10222292SN/A // get full in the IQ. 10232292SN/A toRename->iewUnblock[tid] = false; 10242292SN/A 10252292SN/A ++iewLSQFullEvents; 10262292SN/A break; 10272292SN/A } 10282292SN/A 10292292SN/A // Otherwise issue the instruction just fine. 10302292SN/A if (inst->isLoad()) { 10312292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10322292SN/A "encountered, adding to LSQ.\n", tid); 10337720Sgblack@eecs.umich.edu 10342292SN/A // Reserve a spot in the load store queue for this 10357720Sgblack@eecs.umich.edu // memory access. 10362292SN/A ldstQueue.insertLoad(inst); 10372292SN/A 10382292SN/A ++iewDispLoadInsts; 10392292SN/A 10402292SN/A add_to_iq = true; 10412292SN/A 10422292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10432292SN/A } else if (inst->isStore()) { 10442292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10452292SN/A "encountered, adding to LSQ.\n", tid); 10462292SN/A 10472292SN/A ldstQueue.insertStore(inst); 10482292SN/A 10492292SN/A ++iewDispStoreInsts; 10502292SN/A 105110239Sbinhpham@cs.rutgers.edu if (inst->isStoreConditional()) { 105210239Sbinhpham@cs.rutgers.edu // Store conditionals need to be set as "canCommit()" 10532292SN/A // so that commit can process them when they reach the 105410239Sbinhpham@cs.rutgers.edu // head of commit. 105510239Sbinhpham@cs.rutgers.edu // @todo: This is somewhat specific to Alpha. 105610239Sbinhpham@cs.rutgers.edu inst->setCanCommit(); 105710239Sbinhpham@cs.rutgers.edu instQueue.insertNonSpec(inst); 10582292SN/A add_to_iq = false; 10592292SN/A 10602292SN/A ++iewDispNonSpecInsts; 10612292SN/A } else { 10622292SN/A add_to_iq = true; 10632292SN/A } 10642292SN/A 10652292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10662292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10672292SN/A // Same as non-speculative stores. 10682292SN/A inst->setCanCommit(); 10692292SN/A instQueue.insertBarrier(inst); 10702292SN/A add_to_iq = false; 10712292SN/A } else if (inst->isNop()) { 10722292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10732292SN/A "skipping.\n", tid); 10742292SN/A 10752292SN/A inst->setIssued(); 10762292SN/A inst->setExecuted(); 10772292SN/A inst->setCanCommit(); 10782292SN/A 10792292SN/A instQueue.recordProducer(inst); 10802292SN/A 10812292SN/A iewExecutedNop[tid]++; 10822292SN/A 10832292SN/A add_to_iq = false; 10842292SN/A } else if (inst->isExecuted()) { 10852292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10862292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10872292SN/A "skipping.\n"); 10882292SN/A 10892292SN/A inst->setIssued(); 10902292SN/A inst->setCanCommit(); 10912292SN/A 10922292SN/A instQueue.recordProducer(inst); 10932292SN/A 10942292SN/A add_to_iq = false; 10952292SN/A } else { 10962292SN/A add_to_iq = true; 10972292SN/A } 10982292SN/A if (inst->isNonSpeculative()) { 10992292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11002292SN/A "encountered, skipping.\n", tid); 11012292SN/A 11022292SN/A // Same as non-speculative stores. 11032292SN/A inst->setCanCommit(); 11042292SN/A 110510239Sbinhpham@cs.rutgers.edu // Specifically insert it as nonspeculative. 11062292SN/A instQueue.insertNonSpec(inst); 11072292SN/A 11082292SN/A ++iewDispNonSpecInsts; 11092292SN/A 11102292SN/A add_to_iq = false; 11112292SN/A } 11122292SN/A 11132292SN/A // If the instruction queue is not full, then add the 11142336SN/A // instruction. 11152336SN/A if (add_to_iq) { 11162336SN/A instQueue.insert(inst); 11172336SN/A } 11182348SN/A 11192292SN/A insts_to_dispatch.pop(); 11202292SN/A 11212292SN/A toRename->iewInfo[tid].dispatched++; 11222292SN/A 11232292SN/A ++iewDispatchedInsts; 11242292SN/A } 11252292SN/A 11262292SN/A if (!insts_to_dispatch.empty()) { 11272292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 112810239Sbinhpham@cs.rutgers.edu block(tid); 11292292SN/A toRename->iewUnblock[tid] = false; 11302326SN/A } 11312292SN/A 11322292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11332292SN/A dispatchStatus[tid] = Running; 11342292SN/A 11352292SN/A updatedQueues = true; 11362292SN/A } 11372292SN/A 11382292SN/A dis_num_inst = 0; 11392292SN/A} 11402292SN/A 11412292SN/Atemplate <class Impl> 11422326SN/Avoid 11432292SN/ADefaultIEW<Impl>::printAvailableInsts() 11442727Sktlim@umich.edu{ 11452301SN/A int inst = 0; 11462292SN/A 11472292SN/A std::cout << "Available Instructions: "; 11482292SN/A 11492292SN/A while (fromIssue->insts[inst]) { 11502292SN/A 11512292SN/A if (inst%3==0) std::cout << "\n\t"; 11522292SN/A 11532292SN/A std::cout << "PC: " << fromIssue->insts[inst]->readPC() 11542292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11552326SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11562292SN/A 11572292SN/A inst++; 11582292SN/A 11592292SN/A } 11602292SN/A 11614033Sktlim@umich.edu std::cout << "\n"; 11624033Sktlim@umich.edu} 11634033Sktlim@umich.edu 11644033Sktlim@umich.edutemplate <class Impl> 11654033Sktlim@umich.eduvoid 11664033Sktlim@umich.eduDefaultIEW<Impl>::executeInsts() 11674033Sktlim@umich.edu{ 11684033Sktlim@umich.edu wbNumInst = 0; 11694033Sktlim@umich.edu wbCycle = 0; 11704033Sktlim@umich.edu 11714033Sktlim@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 11724033Sktlim@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 11734033Sktlim@umich.edu 11744033Sktlim@umich.edu while (threads != end) { 11752292SN/A unsigned tid = *threads++; 11762292SN/A fetchRedirect[tid] = false; 11772292SN/A } 11782292SN/A 11792292SN/A // Uncomment this if you want to see all available instructions. 11802292SN/A// printAvailableInsts(); 11812292SN/A 11822292SN/A // Execute/writeback any instructions that are available. 11832292SN/A int insts_to_execute = fromIssue->size; 11842292SN/A int inst_num = 0; 11852292SN/A for (; inst_num < insts_to_execute; 11862292SN/A ++inst_num) { 11878471SGiacomo.Gabrielli@arm.com 11888471SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11899046SAli.Saidi@ARM.com 11908471SGiacomo.Gabrielli@arm.com DynInstPtr inst = instQueue.getInstToExecute(); 119110023Smatt.horsnell@ARM.com 11922292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11932292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11942292SN/A 11952935Sksewell@umich.edu // Check if the instruction is squashed; if so then skip it 11962292SN/A if (inst->isSquashed()) { 11972292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 11982292SN/A 11992292SN/A // Consider this instruction executed so that commit can go 12002292SN/A // ahead and retire the instruction. 12012292SN/A inst->setExecuted(); 12022292SN/A 12032292SN/A // Not sure if I should set this here or just let commit try to 12042292SN/A // commit any squashed instructions. I like the latter a bit more. 12052292SN/A inst->setCanCommit(); 12062292SN/A 12072292SN/A ++iewExecSquashedInsts; 12082292SN/A 12092292SN/A decrWb(inst->seqNum); 12102292SN/A continue; 12112292SN/A } 12122292SN/A 12132292SN/A Fault fault = NoFault; 12142292SN/A 12152980Sgblack@eecs.umich.edu // Execute instruction. 12162292SN/A // Note that if the instruction faults, it will be handled 12172292SN/A // at the commit stage. 12182292SN/A if (inst->isMemRef() && 12192980Sgblack@eecs.umich.edu (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12202292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12217720Sgblack@eecs.umich.edu "reference.\n"); 12222292SN/A 12232292SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12242292SN/A if (inst->isLoad()) { 12252292SN/A // Loads will mark themselves as executed, and their writeback 12262292SN/A // event adds the instruction to the queue to commit 12272292SN/A fault = ldstQueue.executeLoad(inst); 12282292SN/A } else if (inst->isStore()) { 12292980Sgblack@eecs.umich.edu fault = ldstQueue.executeStore(inst); 12302292SN/A 12312292SN/A // If the store had a fault then it may not have a mem req 12322292SN/A if (!inst->isStoreConditional() && fault == NoFault) { 12332292SN/A inst->setExecuted(); 12342292SN/A 12352292SN/A instToCommit(inst); 12362292SN/A } else if (fault != NoFault) { 12372292SN/A // If the instruction faulted, then we need to send it along to commit 12382292SN/A // without the instruction completing. 12396221Snate@binkert.org DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 12406221Snate@binkert.org fault->name(), inst->seqNum); 12412292SN/A 12423867Sbinkertn@umich.edu // Send this instruction to commit, also make sure iew stage 12436221Snate@binkert.org // realizes there is activity. 12442292SN/A inst->setExecuted(); 12452292SN/A 12462292SN/A instToCommit(inst); 12472698Sktlim@umich.edu activityThisCycle(); 12487599Sminkyu.jeong@arm.com } 12492698Sktlim@umich.edu 12501062SN/A // Store conditionals will mark themselves as 12511062SN/A // executed, and their writeback event will add the 12522333SN/A // instruction to the queue to commit. 12532292SN/A } else { 12542333SN/A panic("Unexpected memory type!\n"); 12552326SN/A } 12561062SN/A 12572292SN/A } else { 12581062SN/A inst->execute(); 12592333SN/A 12601062SN/A inst->setExecuted(); 12617720Sgblack@eecs.umich.edu 12627720Sgblack@eecs.umich.edu instToCommit(inst); 12631062SN/A } 12641062SN/A 12651062SN/A updateExeInstStats(inst); 12668315Sgeoffrey.blake@arm.com 12678315Sgeoffrey.blake@arm.com // Check if branch prediction was correct, if not then we need 12688315Sgeoffrey.blake@arm.com // to tell commit to squash in flight instructions. Only 12691062SN/A // handle this if there hasn't already been something that 12701062SN/A // redirects fetch in this group of instructions. 12711062SN/A 12721062SN/A // This probably needs to prioritize the redirects if a different 12731062SN/A // scheduler is used. Currently the scheduler schedules the oldest 12742292SN/A // instruction first, so the branch resolution order will be correct. 12752292SN/A unsigned tid = inst->threadNumber; 12762292SN/A 12771062SN/A if (!fetchRedirect[tid] || 12781062SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 12791062SN/A 12802820Sktlim@umich.edu if (inst->mispredicted()) { 12811062SN/A fetchRedirect[tid] = true; 12821062SN/A 12831062SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12842292SN/A DPRINTF(IEW, "Predicted target was %#x, %#x.\n", 12851062SN/A inst->readPredPC(), inst->readPredNPC()); 12861062SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 12871062SN/A " NPC: %#x.\n", inst->readNextPC(), 12881062SN/A inst->readNextNPC()); 12897850SMatt.Horsnell@arm.com // If incorrect, then signal the ROB that it must be squashed. 12902292SN/A squashDueToBranch(inst, tid); 12911062SN/A 12921062SN/A if (inst->readPredTaken()) { 12931062SN/A predictedTakenIncorrect++; 12941062SN/A } else { 12952292SN/A predictedNotTakenIncorrect++; 12962292SN/A } 12972292SN/A } else if (ldstQueue.violation(tid)) { 12987944SGiacomo.Gabrielli@arm.com assert(inst->isMemRef()); 12997944SGiacomo.Gabrielli@arm.com // If there was an ordering violation, then get the 13007944SGiacomo.Gabrielli@arm.com // DynInst that caused the violation. Note that this 13017944SGiacomo.Gabrielli@arm.com // clears the violation signal. 13027944SGiacomo.Gabrielli@arm.com DynInstPtr violator; 13037944SGiacomo.Gabrielli@arm.com violator = ldstQueue.getMemDepViolator(tid); 13047944SGiacomo.Gabrielli@arm.com 13057944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13067944SGiacomo.Gabrielli@arm.com "%#x, inst PC: %#x. Addr is: %#x.\n", 13077944SGiacomo.Gabrielli@arm.com violator->readPC(), inst->readPC(), inst->physEffAddr); 13087944SGiacomo.Gabrielli@arm.com 13097850SMatt.Horsnell@arm.com // Ensure the violating instruction is older than 13108073SAli.Saidi@ARM.com // current squash 13117850SMatt.Horsnell@arm.com/* if (fetchRedirect[tid] && 13121062SN/A violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 13132367SN/A continue; 13141062SN/A*/ 13157944SGiacomo.Gabrielli@arm.com fetchRedirect[tid] = true; 13167944SGiacomo.Gabrielli@arm.com 13177944SGiacomo.Gabrielli@arm.com // Tell the instruction queue that a violation has occured. 13187944SGiacomo.Gabrielli@arm.com instQueue.violation(inst, violator); 13197944SGiacomo.Gabrielli@arm.com 13207944SGiacomo.Gabrielli@arm.com // Squash. 13217944SGiacomo.Gabrielli@arm.com squashDueToMemOrder(inst,tid); 13227944SGiacomo.Gabrielli@arm.com 13237944SGiacomo.Gabrielli@arm.com ++memOrderViolationEvents; 13247944SGiacomo.Gabrielli@arm.com } else if (ldstQueue.loadBlocked(tid) && 13252292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 132610231Ssteve.reinhardt@amd.com fetchRedirect[tid] = true; 13277782Sminkyu.jeong@arm.com 13287782Sminkyu.jeong@arm.com DPRINTF(IEW, "Load operation couldn't execute because the " 13297782Sminkyu.jeong@arm.com "memory system is blocked. PC: %#x [sn:%lli]\n", 13302367SN/A inst->readPC(), inst->seqNum); 13312367SN/A 13322367SN/A squashDueToMemBlocked(inst, tid); 13332367SN/A } 13342367SN/A } else { 13352292SN/A // Reset any state associated with redirects that will not 13362326SN/A // be used. 13372326SN/A if (ldstQueue.violation(tid)) { 13382326SN/A assert(inst->isMemRef()); 13392326SN/A 13401062SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13412292SN/A 13421062SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13431062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13441062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13457847Sminkyu.jeong@arm.com DPRINTF(IEW, "Violation will not be handled because " 13467847Sminkyu.jeong@arm.com "already squashing\n"); 13477847Sminkyu.jeong@arm.com 13487847Sminkyu.jeong@arm.com ++memOrderViolationEvents; 13497847Sminkyu.jeong@arm.com } 13507847Sminkyu.jeong@arm.com if (ldstQueue.loadBlocked(tid) && 135110231Ssteve.reinhardt@amd.com !ldstQueue.isLoadBlockedHandled(tid)) { 13527848SAli.Saidi@ARM.com DPRINTF(IEW, "Load operation couldn't execute because the " 13537847Sminkyu.jeong@arm.com "memory system is blocked. PC: %#x [sn:%lli]\n", 13541062SN/A inst->readPC(), inst->seqNum); 13552292SN/A DPRINTF(IEW, "Blocked load will not be handled because " 13562292SN/A "already squashing\n"); 13572292SN/A 13581062SN/A ldstQueue.setLoadBlockedHandled(tid); 13591062SN/A } 13602301SN/A 13611681SN/A } 13622326SN/A } 13632326SN/A 13642326SN/A // Update and record activity if we processed any instructions. 13652107SN/A if (inst_num) { 13661681SN/A if (exeStatus == Idle) { 13672292SN/A exeStatus = Running; 13682292SN/A } 13692292SN/A 13706221Snate@binkert.org updatedQueues = true; 13711062SN/A 13723732Sktlim@umich.edu cpu->activityThisCycle(); 13737852SMatt.Horsnell@arm.com } 13743732Sktlim@umich.edu 13751062SN/A // Need to reset this in case a writeback event needs to write into the 13767856SMatt.Horsnell@arm.com // iew queue. That way the writeback event will write into the correct 13777856SMatt.Horsnell@arm.com // spot in the queue. 13787856SMatt.Horsnell@arm.com wbNumInst = 0; 13797856SMatt.Horsnell@arm.com} 13807856SMatt.Horsnell@arm.com 13812292SN/Atemplate <class Impl> 13821062SN/Avoid 13832292SN/ADefaultIEW<Impl>::writebackInsts() 13848674Snilay@cs.wisc.edu{ 13858674Snilay@cs.wisc.edu // Loop through the head of the time buffer and wake any 13867720Sgblack@eecs.umich.edu // dependents. These instructions are about to write back. Also 13878674Snilay@cs.wisc.edu // mark scoreboard that this instruction is finally complete. 13881062SN/A // Either have IEW have direct access to scoreboard, or have this 13892292SN/A // as part of backwards communication. 13901062SN/A for (int inst_num = 0; inst_num < wbWidth && 139110023Smatt.horsnell@ARM.com toCommit->insts[inst_num]; inst_num++) { 139210023Smatt.horsnell@ARM.com DynInstPtr inst = toCommit->insts[inst_num]; 13933795Sgblack@eecs.umich.edu int tid = inst->threadNumber; 13941062SN/A 13952292SN/A DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13962292SN/A inst->seqNum, inst->readPC()); 13971062SN/A 13982292SN/A iewInstsToCommit[tid]++; 13994033Sktlim@umich.edu 14002326SN/A // Some instructions will be sent to commit without having 14012326SN/A // executed because they need commit to handle them. 14022292SN/A // E.g. Uncached loads have not actually executed when they 14032292SN/A // are first sent to commit. Instead commit must tell the LSQ 14042292SN/A // when it's ready to execute the uncached load. 14051062SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14067720Sgblack@eecs.umich.edu int dependents = instQueue.wakeDependents(inst); 14077720Sgblack@eecs.umich.edu 14087720Sgblack@eecs.umich.edu for (int i = 0; i < inst->numDestRegs(); i++) { 14097720Sgblack@eecs.umich.edu //mark as Ready 14107720Sgblack@eecs.umich.edu DPRINTF(IEW,"Setting Destination Register %i\n", 14113732Sktlim@umich.edu inst->renamedDestRegIdx(i)); 14123732Sktlim@umich.edu scoreboard->setReg(inst->renamedDestRegIdx(i)); 14131062SN/A } 14141062SN/A 14151062SN/A if (dependents) { 14161062SN/A producerInst[tid]++; 14178513SGiacomo.Gabrielli@arm.com consumerInst[tid]+= dependents; 14181062SN/A } 14191062SN/A writebackCount[tid]++; 14202292SN/A } 14212292SN/A 14222292SN/A decrWb(inst->seqNum); 14232292SN/A } 14242292SN/A} 14257720Sgblack@eecs.umich.edu 14267720Sgblack@eecs.umich.edutemplate<class Impl> 14272292SN/Avoid 14282292SN/ADefaultIEW<Impl>::tick() 14291062SN/A{ 14304033Sktlim@umich.edu wbNumInst = 0; 14314033Sktlim@umich.edu wbCycle = 0; 14324033Sktlim@umich.edu 14334033Sktlim@umich.edu wroteToTimeBuffer = false; 14344033Sktlim@umich.edu updatedQueues = false; 14354033Sktlim@umich.edu 14364033Sktlim@umich.edu sortInsts(); 14374033Sktlim@umich.edu 14384033Sktlim@umich.edu // Free function units marked as being freed this cycle. 14397720Sgblack@eecs.umich.edu fuPool->processFreeUnits(); 14407720Sgblack@eecs.umich.edu 14417720Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 14424033Sktlim@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 14434033Sktlim@umich.edu 14444033Sktlim@umich.edu // Check stall and squash signals, dispatch any instructions. 14454033Sktlim@umich.edu while (threads != end) { 14464033Sktlim@umich.edu unsigned tid = *threads++; 14474033Sktlim@umich.edu 14484033Sktlim@umich.edu DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14494033Sktlim@umich.edu 14507720Sgblack@eecs.umich.edu checkSignalsAndUpdate(tid); 14517720Sgblack@eecs.umich.edu dispatch(tid); 14524033Sktlim@umich.edu } 14534033Sktlim@umich.edu 14544033Sktlim@umich.edu if (exeStatus != Squashing) { 14554033Sktlim@umich.edu executeInsts(); 14564033Sktlim@umich.edu 14574033Sktlim@umich.edu writebackInsts(); 14581062SN/A 14591062SN/A // Have the instruction queue try to schedule any ready instructions. 14602292SN/A // (In actuality, this scheduling is for instructions that will 14612348SN/A // be executed next cycle.) 14622292SN/A instQueue.scheduleReadyInsts(); 14632292SN/A 14642292SN/A // Also should advance its own time buffers if the stage ran. 14652292SN/A // Not the best place for it, but this works (hopefully). 14662292SN/A issueToExecQueue.advance(); 14672292SN/A } 14682292SN/A 14692292SN/A bool broadcast_free_entries = false; 14702292SN/A 14712292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14722292SN/A exeStatus = Idle; 14732292SN/A updateLSQNextCycle = false; 14742292SN/A 14752292SN/A broadcast_free_entries = true; 14767852SMatt.Horsnell@arm.com } 14772107SN/A 14782107SN/A // Writeback any stores using any leftover bandwidth. 14792292SN/A ldstQueue.writebackStores(); 14802107SN/A 14812292SN/A // Check the committed load/store signals to see if there's a load 14822107SN/A // or store to commit. Also check if it's being told to execute a 14832326SN/A // nonspeculative instruction. 14842326SN/A // This is pretty inefficient... 14852326SN/A 14862326SN/A threads = activeThreads->begin(); 14872326SN/A while (threads != end) { 14883958Sgblack@eecs.umich.edu unsigned tid = (*threads++); 14892292SN/A 14902107SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14916221Snate@binkert.org 14922107SN/A // Update structures based on instructions committed. 14937720Sgblack@eecs.umich.edu if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14947720Sgblack@eecs.umich.edu !fromCommit->commitInfo[tid].squash && 14952107SN/A !fromCommit->commitInfo[tid].robSquashing) { 14962301SN/A 14972301SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14982292SN/A 14992292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15002292SN/A 15012292SN/A updateLSQNextCycle = true; 15022292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15032367SN/A } 15042301SN/A 15052107SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15062292SN/A 15072292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15082292SN/A if (fromCommit->commitInfo[tid].uncached) { 15092292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15102292SN/A fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15112107SN/A } else { 15122301SN/A instQueue.scheduleNonSpec( 15132348SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15142348SN/A } 15152348SN/A } 15162348SN/A 15172326SN/A if (broadcast_free_entries) { 15182107SN/A toFetch->iewInfo[tid].iqCount = 15192820Sktlim@umich.edu instQueue.getCount(tid); 15202820Sktlim@umich.edu toFetch->iewInfo[tid].ldstqCount = 15212107SN/A ldstQueue.getCount(tid); 15221060SN/A 15231060SN/A toRename->iewInfo[tid].usedIQ = true; 15241681SN/A toRename->iewInfo[tid].freeIQEntries = 15251060SN/A instQueue.numFreeEntries(); 15262292SN/A toRename->iewInfo[tid].usedLSQ = true; 15271060SN/A toRename->iewInfo[tid].freeLSQEntries = 15282292SN/A ldstQueue.numFreeEntries(tid); 15292292SN/A 15301060SN/A wroteToTimeBuffer = true; 15312292SN/A } 15322292SN/A 15331060SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15342292SN/A tid, toRename->iewInfo[tid].dispatched); 15351060SN/A } 15362326SN/A 15372326SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15381062SN/A "LSQ has %i free entries.\n", 15396221Snate@binkert.org instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15406221Snate@binkert.org ldstQueue.numFreeEntries()); 15411060SN/A 15422326SN/A updateStatus(); 15433867Sbinkertn@umich.edu 15446221Snate@binkert.org if (wroteToTimeBuffer) { 15451060SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15462292SN/A cpu->activityThisCycle(); 15471060SN/A } 15482292SN/A} 15492292SN/A 15501060SN/Atemplate <class Impl> 15511060SN/Avoid 15522292SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15532292SN/A{ 15541060SN/A int thread_number = inst->threadNumber; 15552292SN/A 15562292SN/A // 15572292SN/A // Pick off the software prefetches 15582292SN/A // 15592292SN/A#ifdef TARGET_ALPHA 15602292SN/A if (inst->isDataPrefetch()) 15612292SN/A iewExecutedSwp[thread_number]++; 15622292SN/A else 15632292SN/A iewIewExecutedcutedInsts++; 15642292SN/A#else 15652292SN/A iewExecutedInsts++; 15662292SN/A#endif 15672292SN/A 15682292SN/A // 15692292SN/A // Control operations 15702292SN/A // 15712292SN/A if (inst->isControl()) 15722292SN/A iewExecutedBranches[thread_number]++; 15732292SN/A 15742292SN/A // 15752292SN/A // Memory operations 15762292SN/A // 15771681SN/A if (inst->isMemRef()) { 15781681SN/A iewExecutedRefs[thread_number]++; 15791061SN/A 15801061SN/A if (inst->isLoad()) { 15811061SN/A iewExecLoadInsts[thread_number]++; 15821681SN/A } 15832292SN/A } 15843867Sbinkertn@umich.edu} 15853867Sbinkertn@umich.edu