iew_impl.hh revision 4329
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 411681SN/Atemplate<class Impl> 424329Sktlim@umich.eduDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params) 432873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 444329Sktlim@umich.edu cpu(_cpu), 454329Sktlim@umich.edu instQueue(_cpu, this, params), 464329Sktlim@umich.edu ldstQueue(_cpu, this, params), 472292SN/A fuPool(params->fuPool), 482292SN/A commitToIEWDelay(params->commitToIEWDelay), 492292SN/A renameToIEWDelay(params->renameToIEWDelay), 502292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 512820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 522292SN/A issueWidth(params->issueWidth), 532820Sktlim@umich.edu wbOutstanding(0), 542820Sktlim@umich.edu wbWidth(params->wbWidth), 552307SN/A numThreads(params->numberOfThreads), 562307SN/A switchedOut(false) 571060SN/A{ 582292SN/A _status = Active; 592292SN/A exeStatus = Running; 602292SN/A wbStatus = Idle; 611060SN/A 621060SN/A // Setup wire to read instructions coming from issue. 631060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 641060SN/A 651060SN/A // Instruction queue needs the queue between issue and execute. 661060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 671681SN/A 682292SN/A for (int i=0; i < numThreads; i++) { 692292SN/A dispatchStatus[i] = Running; 702292SN/A stalls[i].commit = false; 712292SN/A fetchRedirect[i] = false; 722935Sksewell@umich.edu bdelayDoneSeqNum[i] = 0; 732292SN/A } 742292SN/A 752820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 762820Sktlim@umich.edu 772292SN/A updateLSQNextCycle = false; 782292SN/A 792820Sktlim@umich.edu ableToIssue = true; 802820Sktlim@umich.edu 812292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 822292SN/A} 832292SN/A 842292SN/Atemplate <class Impl> 852292SN/Astd::string 862292SN/ADefaultIEW<Impl>::name() const 872292SN/A{ 882292SN/A return cpu->name() + ".iew"; 891060SN/A} 901060SN/A 911681SN/Atemplate <class Impl> 921062SN/Avoid 932292SN/ADefaultIEW<Impl>::regStats() 941062SN/A{ 952301SN/A using namespace Stats; 962301SN/A 971062SN/A instQueue.regStats(); 982727Sktlim@umich.edu ldstQueue.regStats(); 991062SN/A 1001062SN/A iewIdleCycles 1011062SN/A .name(name() + ".iewIdleCycles") 1021062SN/A .desc("Number of cycles IEW is idle"); 1031062SN/A 1041062SN/A iewSquashCycles 1051062SN/A .name(name() + ".iewSquashCycles") 1061062SN/A .desc("Number of cycles IEW is squashing"); 1071062SN/A 1081062SN/A iewBlockCycles 1091062SN/A .name(name() + ".iewBlockCycles") 1101062SN/A .desc("Number of cycles IEW is blocking"); 1111062SN/A 1121062SN/A iewUnblockCycles 1131062SN/A .name(name() + ".iewUnblockCycles") 1141062SN/A .desc("Number of cycles IEW is unblocking"); 1151062SN/A 1161062SN/A iewDispatchedInsts 1171062SN/A .name(name() + ".iewDispatchedInsts") 1181062SN/A .desc("Number of instructions dispatched to IQ"); 1191062SN/A 1201062SN/A iewDispSquashedInsts 1211062SN/A .name(name() + ".iewDispSquashedInsts") 1221062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1231062SN/A 1241062SN/A iewDispLoadInsts 1251062SN/A .name(name() + ".iewDispLoadInsts") 1261062SN/A .desc("Number of dispatched load instructions"); 1271062SN/A 1281062SN/A iewDispStoreInsts 1291062SN/A .name(name() + ".iewDispStoreInsts") 1301062SN/A .desc("Number of dispatched store instructions"); 1311062SN/A 1321062SN/A iewDispNonSpecInsts 1331062SN/A .name(name() + ".iewDispNonSpecInsts") 1341062SN/A .desc("Number of dispatched non-speculative instructions"); 1351062SN/A 1361062SN/A iewIQFullEvents 1371062SN/A .name(name() + ".iewIQFullEvents") 1381062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1391062SN/A 1402292SN/A iewLSQFullEvents 1412292SN/A .name(name() + ".iewLSQFullEvents") 1422292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1432292SN/A 1441062SN/A memOrderViolationEvents 1451062SN/A .name(name() + ".memOrderViolationEvents") 1461062SN/A .desc("Number of memory order violations"); 1471062SN/A 1481062SN/A predictedTakenIncorrect 1491062SN/A .name(name() + ".predictedTakenIncorrect") 1501062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1512292SN/A 1522292SN/A predictedNotTakenIncorrect 1532292SN/A .name(name() + ".predictedNotTakenIncorrect") 1542292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1552292SN/A 1562292SN/A branchMispredicts 1572292SN/A .name(name() + ".branchMispredicts") 1582292SN/A .desc("Number of branch mispredicts detected at execute"); 1592292SN/A 1602292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1612301SN/A 1622727Sktlim@umich.edu iewExecutedInsts 1632353SN/A .name(name() + ".iewExecutedInsts") 1642727Sktlim@umich.edu .desc("Number of executed instructions"); 1652727Sktlim@umich.edu 1662727Sktlim@umich.edu iewExecLoadInsts 1672727Sktlim@umich.edu .init(cpu->number_of_threads) 1682353SN/A .name(name() + ".iewExecLoadInsts") 1692727Sktlim@umich.edu .desc("Number of load instructions executed") 1702727Sktlim@umich.edu .flags(total); 1712727Sktlim@umich.edu 1722727Sktlim@umich.edu iewExecSquashedInsts 1732353SN/A .name(name() + ".iewExecSquashedInsts") 1742727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1752727Sktlim@umich.edu 1762727Sktlim@umich.edu iewExecutedSwp 1772301SN/A .init(cpu->number_of_threads) 1782301SN/A .name(name() + ".EXEC:swp") 1792301SN/A .desc("number of swp insts executed") 1802727Sktlim@umich.edu .flags(total); 1812301SN/A 1822727Sktlim@umich.edu iewExecutedNop 1832301SN/A .init(cpu->number_of_threads) 1842301SN/A .name(name() + ".EXEC:nop") 1852301SN/A .desc("number of nop insts executed") 1862727Sktlim@umich.edu .flags(total); 1872301SN/A 1882727Sktlim@umich.edu iewExecutedRefs 1892301SN/A .init(cpu->number_of_threads) 1902301SN/A .name(name() + ".EXEC:refs") 1912301SN/A .desc("number of memory reference insts executed") 1922727Sktlim@umich.edu .flags(total); 1932301SN/A 1942727Sktlim@umich.edu iewExecutedBranches 1952301SN/A .init(cpu->number_of_threads) 1962301SN/A .name(name() + ".EXEC:branches") 1972301SN/A .desc("Number of branches executed") 1982727Sktlim@umich.edu .flags(total); 1992301SN/A 2002301SN/A iewExecStoreInsts 2012301SN/A .name(name() + ".EXEC:stores") 2022301SN/A .desc("Number of stores executed") 2032727Sktlim@umich.edu .flags(total); 2042727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2052727Sktlim@umich.edu 2062727Sktlim@umich.edu iewExecRate 2072727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2082727Sktlim@umich.edu .desc("Inst execution rate") 2092727Sktlim@umich.edu .flags(total); 2102727Sktlim@umich.edu 2112727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2122301SN/A 2132301SN/A iewInstsToCommit 2142301SN/A .init(cpu->number_of_threads) 2152301SN/A .name(name() + ".WB:sent") 2162301SN/A .desc("cumulative count of insts sent to commit") 2172727Sktlim@umich.edu .flags(total); 2182301SN/A 2192326SN/A writebackCount 2202301SN/A .init(cpu->number_of_threads) 2212301SN/A .name(name() + ".WB:count") 2222301SN/A .desc("cumulative count of insts written-back") 2232727Sktlim@umich.edu .flags(total); 2242301SN/A 2252326SN/A producerInst 2262301SN/A .init(cpu->number_of_threads) 2272301SN/A .name(name() + ".WB:producers") 2282301SN/A .desc("num instructions producing a value") 2292727Sktlim@umich.edu .flags(total); 2302301SN/A 2312326SN/A consumerInst 2322301SN/A .init(cpu->number_of_threads) 2332301SN/A .name(name() + ".WB:consumers") 2342301SN/A .desc("num instructions consuming a value") 2352727Sktlim@umich.edu .flags(total); 2362301SN/A 2372326SN/A wbPenalized 2382301SN/A .init(cpu->number_of_threads) 2392301SN/A .name(name() + ".WB:penalized") 2402301SN/A .desc("number of instrctions required to write to 'other' IQ") 2412727Sktlim@umich.edu .flags(total); 2422301SN/A 2432326SN/A wbPenalizedRate 2442301SN/A .name(name() + ".WB:penalized_rate") 2452301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2462727Sktlim@umich.edu .flags(total); 2472301SN/A 2482326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2492301SN/A 2502326SN/A wbFanout 2512301SN/A .name(name() + ".WB:fanout") 2522301SN/A .desc("average fanout of values written-back") 2532727Sktlim@umich.edu .flags(total); 2542301SN/A 2552326SN/A wbFanout = producerInst / consumerInst; 2562301SN/A 2572326SN/A wbRate 2582301SN/A .name(name() + ".WB:rate") 2592301SN/A .desc("insts written-back per cycle") 2602727Sktlim@umich.edu .flags(total); 2612326SN/A wbRate = writebackCount / cpu->numCycles; 2621062SN/A} 2631062SN/A 2641681SN/Atemplate<class Impl> 2651060SN/Avoid 2662292SN/ADefaultIEW<Impl>::initStage() 2671060SN/A{ 2682292SN/A for (int tid=0; tid < numThreads; tid++) { 2692292SN/A toRename->iewInfo[tid].usedIQ = true; 2702292SN/A toRename->iewInfo[tid].freeIQEntries = 2712292SN/A instQueue.numFreeEntries(tid); 2722292SN/A 2732292SN/A toRename->iewInfo[tid].usedLSQ = true; 2742292SN/A toRename->iewInfo[tid].freeLSQEntries = 2752292SN/A ldstQueue.numFreeEntries(tid); 2762292SN/A } 2772292SN/A 2782733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2791060SN/A} 2801060SN/A 2811681SN/Atemplate<class Impl> 2821060SN/Avoid 2832292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2841060SN/A{ 2851060SN/A timeBuffer = tb_ptr; 2861060SN/A 2871060SN/A // Setup wire to read information from time buffer, from commit. 2881060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2891060SN/A 2901060SN/A // Setup wire to write information back to previous stages. 2911060SN/A toRename = timeBuffer->getWire(0); 2921060SN/A 2932292SN/A toFetch = timeBuffer->getWire(0); 2942292SN/A 2951060SN/A // Instruction queue also needs main time buffer. 2961060SN/A instQueue.setTimeBuffer(tb_ptr); 2971060SN/A} 2981060SN/A 2991681SN/Atemplate<class Impl> 3001060SN/Avoid 3012292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3021060SN/A{ 3031060SN/A renameQueue = rq_ptr; 3041060SN/A 3051060SN/A // Setup wire to read information from rename queue. 3061060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3071060SN/A} 3081060SN/A 3091681SN/Atemplate<class Impl> 3101060SN/Avoid 3112292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3121060SN/A{ 3131060SN/A iewQueue = iq_ptr; 3141060SN/A 3151060SN/A // Setup wire to write instructions to commit. 3161060SN/A toCommit = iewQueue->getWire(0); 3171060SN/A} 3181060SN/A 3191681SN/Atemplate<class Impl> 3201060SN/Avoid 3212980Sgblack@eecs.umich.eduDefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3221060SN/A{ 3232292SN/A activeThreads = at_ptr; 3242292SN/A 3252292SN/A ldstQueue.setActiveThreads(at_ptr); 3262292SN/A instQueue.setActiveThreads(at_ptr); 3271060SN/A} 3281060SN/A 3291681SN/Atemplate<class Impl> 3301060SN/Avoid 3312292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3321060SN/A{ 3332292SN/A scoreboard = sb_ptr; 3341060SN/A} 3351060SN/A 3362307SN/Atemplate <class Impl> 3372863Sktlim@umich.edubool 3382843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3392307SN/A{ 3402843Sktlim@umich.edu // IEW is ready to drain at any time. 3412843Sktlim@umich.edu cpu->signalDrained(); 3422863Sktlim@umich.edu return true; 3431681SN/A} 3441681SN/A 3452316SN/Atemplate <class Impl> 3461681SN/Avoid 3472843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3482843Sktlim@umich.edu{ 3492843Sktlim@umich.edu} 3502843Sktlim@umich.edu 3512843Sktlim@umich.edutemplate <class Impl> 3522843Sktlim@umich.eduvoid 3532843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3541681SN/A{ 3552348SN/A // Clear any state. 3562307SN/A switchedOut = true; 3572367SN/A assert(insts[0].empty()); 3582367SN/A assert(skidBuffer[0].empty()); 3591681SN/A 3602307SN/A instQueue.switchOut(); 3612307SN/A ldstQueue.switchOut(); 3622307SN/A fuPool->switchOut(); 3632307SN/A 3642307SN/A for (int i = 0; i < numThreads; i++) { 3652307SN/A while (!insts[i].empty()) 3662307SN/A insts[i].pop(); 3672307SN/A while (!skidBuffer[i].empty()) 3682307SN/A skidBuffer[i].pop(); 3692307SN/A } 3701681SN/A} 3711681SN/A 3722307SN/Atemplate <class Impl> 3731681SN/Avoid 3742307SN/ADefaultIEW<Impl>::takeOverFrom() 3751060SN/A{ 3762348SN/A // Reset all state. 3772307SN/A _status = Active; 3782307SN/A exeStatus = Running; 3792307SN/A wbStatus = Idle; 3802307SN/A switchedOut = false; 3811060SN/A 3822307SN/A instQueue.takeOverFrom(); 3832307SN/A ldstQueue.takeOverFrom(); 3842307SN/A fuPool->takeOverFrom(); 3851060SN/A 3862307SN/A initStage(); 3872307SN/A cpu->activityThisCycle(); 3881060SN/A 3892307SN/A for (int i=0; i < numThreads; i++) { 3902307SN/A dispatchStatus[i] = Running; 3912307SN/A stalls[i].commit = false; 3922307SN/A fetchRedirect[i] = false; 3932307SN/A } 3941060SN/A 3952307SN/A updateLSQNextCycle = false; 3962307SN/A 3972873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 3982307SN/A issueToExecQueue.advance(); 3991060SN/A } 4001060SN/A} 4011060SN/A 4021681SN/Atemplate<class Impl> 4031060SN/Avoid 4042292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4052107SN/A{ 4062292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4072292SN/A tid); 4082107SN/A 4092292SN/A // Tell the IQ to start squashing. 4102292SN/A instQueue.squash(tid); 4112107SN/A 4122292SN/A // Tell the LDSTQ to start squashing. 4133093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 4143093Sksewell@umich.edu ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid); 4153093Sksewell@umich.edu#else 4162326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4172935Sksewell@umich.edu#endif 4182292SN/A updatedQueues = true; 4192107SN/A 4202292SN/A // Clear the skid buffer in case it has any data in it. 4212935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4222935Sksewell@umich.edu tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum); 4232935Sksewell@umich.edu 4242292SN/A while (!skidBuffer[tid].empty()) { 4253093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 4262935Sksewell@umich.edu if (skidBuffer[tid].front()->seqNum <= 4272935Sksewell@umich.edu fromCommit->commitInfo[tid].bdelayDoneSeqNum) { 4282935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions " 4292935Sksewell@umich.edu "that occur before delay slot [sn:%i].\n", 4302935Sksewell@umich.edu fromCommit->commitInfo[tid].bdelayDoneSeqNum, 4312935Sksewell@umich.edu tid); 4322935Sksewell@umich.edu break; 4332935Sksewell@umich.edu } else { 4342935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from " 4352935Sksewell@umich.edu "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum); 4362935Sksewell@umich.edu } 4372935Sksewell@umich.edu#endif 4382292SN/A if (skidBuffer[tid].front()->isLoad() || 4392292SN/A skidBuffer[tid].front()->isStore() ) { 4402292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4412292SN/A } 4422107SN/A 4432292SN/A toRename->iewInfo[tid].dispatched++; 4442107SN/A 4452292SN/A skidBuffer[tid].pop(); 4462292SN/A } 4472107SN/A 4482935Sksewell@umich.edu bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 4492935Sksewell@umich.edu 4502702Sktlim@umich.edu emptyRenameInsts(tid); 4512107SN/A} 4522107SN/A 4532107SN/Atemplate<class Impl> 4542107SN/Avoid 4552292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4562292SN/A{ 4572292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4582292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4592292SN/A 4602292SN/A toCommit->squash[tid] = true; 4612292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4622292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4632292SN/A toCommit->branchMispredict[tid] = true; 4642935Sksewell@umich.edu 4653969Sgblack@eecs.umich.edu int instSize = sizeof(TheISA::MachInst); 4663093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 4673771Sgblack@eecs.umich.edu bool branch_taken = 4683795Sgblack@eecs.umich.edu !(inst->readNextPC() + instSize == inst->readNextNPC() && 4693795Sgblack@eecs.umich.edu (inst->readNextPC() == inst->readPC() + instSize || 4703795Sgblack@eecs.umich.edu inst->readNextPC() == inst->readPC() + 2 * instSize)); 4713771Sgblack@eecs.umich.edu DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n", 4723771Sgblack@eecs.umich.edu branch_taken ? "true": "false", inst->seqNum); 4732935Sksewell@umich.edu 4742935Sksewell@umich.edu toCommit->branchTaken[tid] = branch_taken; 4752935Sksewell@umich.edu 4763795Sgblack@eecs.umich.edu bool squashDelaySlot = true; 4773795Sgblack@eecs.umich.edu// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst)); 4783771Sgblack@eecs.umich.edu DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n", 4793771Sgblack@eecs.umich.edu squashDelaySlot ? "true": "false", inst->seqNum); 4803771Sgblack@eecs.umich.edu toCommit->squashDelaySlot[tid] = squashDelaySlot; 4813771Sgblack@eecs.umich.edu //If we're squashing the delay slot, we need to pick back up at NextPC. 4823771Sgblack@eecs.umich.edu //Otherwise, NextPC isn't being squashed, so we should pick back up at 4833771Sgblack@eecs.umich.edu //NextNPC. 4843795Sgblack@eecs.umich.edu if (squashDelaySlot) { 4852935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4863795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4872935Sksewell@umich.edu } else { 4882935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextNPC(); 4893969Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC() + instSize; 4902935Sksewell@umich.edu } 4913093Sksewell@umich.edu#else 4923093Sksewell@umich.edu toCommit->branchTaken[tid] = inst->readNextPC() != 4933093Sksewell@umich.edu (inst->readPC() + sizeof(TheISA::MachInst)); 4943093Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4953969Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextPC() + instSize; 4962935Sksewell@umich.edu#endif 4972292SN/A 4982292SN/A toCommit->includeSquashInst[tid] = false; 4992292SN/A 5002292SN/A wroteToTimeBuffer = true; 5012292SN/A} 5022292SN/A 5032292SN/Atemplate<class Impl> 5042292SN/Avoid 5052292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 5062292SN/A{ 5072292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 5082292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5092292SN/A 5102292SN/A toCommit->squash[tid] = true; 5112292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5122292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 5133795Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 5143795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 5153969Sgblack@eecs.umich.edu#else 5163969Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst); 5173795Sgblack@eecs.umich.edu#endif 5183732Sktlim@umich.edu toCommit->branchMispredict[tid] = false; 5192292SN/A 5202292SN/A toCommit->includeSquashInst[tid] = false; 5212292SN/A 5222292SN/A wroteToTimeBuffer = true; 5232292SN/A} 5242292SN/A 5252292SN/Atemplate<class Impl> 5262292SN/Avoid 5272292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5282292SN/A{ 5292292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5302292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5312292SN/A 5322292SN/A toCommit->squash[tid] = true; 5332292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5342292SN/A toCommit->nextPC[tid] = inst->readPC(); 5353795Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 5363958Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextPC(); 5373969Sgblack@eecs.umich.edu#else 5383969Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst); 5393795Sgblack@eecs.umich.edu#endif 5403732Sktlim@umich.edu toCommit->branchMispredict[tid] = false; 5412292SN/A 5422348SN/A // Must include the broadcasted SN in the squash. 5432292SN/A toCommit->includeSquashInst[tid] = true; 5442292SN/A 5452292SN/A ldstQueue.setLoadBlockedHandled(tid); 5462292SN/A 5472292SN/A wroteToTimeBuffer = true; 5482292SN/A} 5492292SN/A 5502292SN/Atemplate<class Impl> 5512292SN/Avoid 5522292SN/ADefaultIEW<Impl>::block(unsigned tid) 5532292SN/A{ 5542292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5552292SN/A 5562292SN/A if (dispatchStatus[tid] != Blocked && 5572292SN/A dispatchStatus[tid] != Unblocking) { 5582292SN/A toRename->iewBlock[tid] = true; 5592292SN/A wroteToTimeBuffer = true; 5602292SN/A } 5612292SN/A 5622292SN/A // Add the current inputs to the skid buffer so they can be 5632292SN/A // reprocessed when this stage unblocks. 5642292SN/A skidInsert(tid); 5652292SN/A 5662292SN/A dispatchStatus[tid] = Blocked; 5672292SN/A} 5682292SN/A 5692292SN/Atemplate<class Impl> 5702292SN/Avoid 5712292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5722292SN/A{ 5732292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5742292SN/A "buffer %u.\n",tid, tid); 5752292SN/A 5762292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5772292SN/A // Also switch status to running. 5782292SN/A if (skidBuffer[tid].empty()) { 5792292SN/A toRename->iewUnblock[tid] = true; 5802292SN/A wroteToTimeBuffer = true; 5812292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5822292SN/A dispatchStatus[tid] = Running; 5832292SN/A } 5842292SN/A} 5852292SN/A 5862292SN/Atemplate<class Impl> 5872292SN/Avoid 5882292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5891060SN/A{ 5901681SN/A instQueue.wakeDependents(inst); 5911060SN/A} 5921060SN/A 5932292SN/Atemplate<class Impl> 5942292SN/Avoid 5952292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5962292SN/A{ 5972292SN/A instQueue.rescheduleMemInst(inst); 5982292SN/A} 5991681SN/A 6001681SN/Atemplate<class Impl> 6011060SN/Avoid 6022292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6031060SN/A{ 6042292SN/A instQueue.replayMemInst(inst); 6052292SN/A} 6061060SN/A 6072292SN/Atemplate<class Impl> 6082292SN/Avoid 6092292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6102292SN/A{ 6113221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6123221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6133221Sktlim@umich.edu // being added to the queue to commit without being processed by 6143221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6153221Sktlim@umich.edu 6162292SN/A // First check the time slot that this instruction will write 6172292SN/A // to. If there are free write ports at the time, then go ahead 6182292SN/A // and write the instruction to that time. If there are not, 6192292SN/A // keep looking back to see where's the first time there's a 6202326SN/A // free slot. 6212292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6222292SN/A ++wbNumInst; 6232820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6242292SN/A ++wbCycle; 6252292SN/A wbNumInst = 0; 6262292SN/A } 6272292SN/A 6282353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6292292SN/A } 6302292SN/A 6312353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6322353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6332292SN/A // Add finished instruction to queue to commit. 6342292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6352292SN/A (*iewQueue)[wbCycle].size++; 6362292SN/A} 6372292SN/A 6382292SN/Atemplate <class Impl> 6392292SN/Aunsigned 6402292SN/ADefaultIEW<Impl>::validInstsFromRename() 6412292SN/A{ 6422292SN/A unsigned inst_count = 0; 6432292SN/A 6442292SN/A for (int i=0; i<fromRename->size; i++) { 6452731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6462292SN/A inst_count++; 6472292SN/A } 6482292SN/A 6492292SN/A return inst_count; 6502292SN/A} 6512292SN/A 6522292SN/Atemplate<class Impl> 6532292SN/Avoid 6542292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6552292SN/A{ 6562292SN/A DynInstPtr inst = NULL; 6572292SN/A 6582292SN/A while (!insts[tid].empty()) { 6592292SN/A inst = insts[tid].front(); 6602292SN/A 6612292SN/A insts[tid].pop(); 6622292SN/A 6632292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6642292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6652292SN/A inst->readPC(),tid); 6662292SN/A 6672292SN/A skidBuffer[tid].push(inst); 6682292SN/A } 6692292SN/A 6702292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6712292SN/A "Skidbuffer Exceeded Max Size"); 6722292SN/A} 6732292SN/A 6742292SN/Atemplate<class Impl> 6752292SN/Aint 6762292SN/ADefaultIEW<Impl>::skidCount() 6772292SN/A{ 6782292SN/A int max=0; 6792292SN/A 6803867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 6813867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 6822292SN/A 6833867Sbinkertn@umich.edu while (threads != end) { 6843867Sbinkertn@umich.edu unsigned tid = *threads++; 6853867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6862292SN/A if (max < thread_count) 6872292SN/A max = thread_count; 6882292SN/A } 6892292SN/A 6902292SN/A return max; 6912292SN/A} 6922292SN/A 6932292SN/Atemplate<class Impl> 6942292SN/Abool 6952292SN/ADefaultIEW<Impl>::skidsEmpty() 6962292SN/A{ 6973867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 6983867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 6992292SN/A 7003867Sbinkertn@umich.edu while (threads != end) { 7013867Sbinkertn@umich.edu unsigned tid = *threads++; 7023867Sbinkertn@umich.edu 7033867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7042292SN/A return false; 7052292SN/A } 7062292SN/A 7072292SN/A return true; 7081062SN/A} 7091062SN/A 7101681SN/Atemplate <class Impl> 7111062SN/Avoid 7122292SN/ADefaultIEW<Impl>::updateStatus() 7131062SN/A{ 7142292SN/A bool any_unblocking = false; 7151062SN/A 7163867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7173867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7181062SN/A 7193867Sbinkertn@umich.edu while (threads != end) { 7202292SN/A unsigned tid = *threads++; 7211062SN/A 7222292SN/A if (dispatchStatus[tid] == Unblocking) { 7232292SN/A any_unblocking = true; 7242292SN/A break; 7252292SN/A } 7262292SN/A } 7271062SN/A 7282292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7292292SN/A // and there's no stores waiting to write back, and dispatch is not 7302292SN/A // unblocking, then there is no internal activity for the IEW stage. 7312292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7322292SN/A !ldstQueue.willWB() && !any_unblocking) { 7332292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7341062SN/A 7352292SN/A deactivateStage(); 7361062SN/A 7372292SN/A _status = Inactive; 7382292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7392292SN/A ldstQueue.willWB() || 7402292SN/A any_unblocking)) { 7412292SN/A // Otherwise there is internal activity. Set to active. 7422292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7431062SN/A 7442292SN/A activateStage(); 7451062SN/A 7462292SN/A _status = Active; 7471062SN/A } 7481062SN/A} 7491062SN/A 7501681SN/Atemplate <class Impl> 7511062SN/Avoid 7522292SN/ADefaultIEW<Impl>::resetEntries() 7531062SN/A{ 7542292SN/A instQueue.resetEntries(); 7552292SN/A ldstQueue.resetEntries(); 7562292SN/A} 7571062SN/A 7582292SN/Atemplate <class Impl> 7592292SN/Avoid 7602292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7612292SN/A{ 7622292SN/A if (fromCommit->commitBlock[tid]) { 7632292SN/A stalls[tid].commit = true; 7642292SN/A } 7651062SN/A 7662292SN/A if (fromCommit->commitUnblock[tid]) { 7672292SN/A assert(stalls[tid].commit); 7682292SN/A stalls[tid].commit = false; 7692292SN/A } 7702292SN/A} 7712292SN/A 7722292SN/Atemplate <class Impl> 7732292SN/Abool 7742292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7752292SN/A{ 7762292SN/A bool ret_val(false); 7772292SN/A 7782292SN/A if (stalls[tid].commit) { 7792292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7802292SN/A ret_val = true; 7812292SN/A } else if (instQueue.isFull(tid)) { 7822292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7832292SN/A ret_val = true; 7842292SN/A } else if (ldstQueue.isFull(tid)) { 7852292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7862292SN/A 7872292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7882292SN/A 7892292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7902292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7912292SN/A } 7922292SN/A 7932292SN/A if (ldstQueue.numStores(tid) > 0) { 7942292SN/A 7952292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7962292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7972292SN/A } 7982292SN/A 7992292SN/A ret_val = true; 8002292SN/A } else if (ldstQueue.isStalled(tid)) { 8012292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8022292SN/A ret_val = true; 8032292SN/A } 8042292SN/A 8052292SN/A return ret_val; 8062292SN/A} 8072292SN/A 8082292SN/Atemplate <class Impl> 8092292SN/Avoid 8102292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 8112292SN/A{ 8122292SN/A // Check if there's a squash signal, squash if there is 8132292SN/A // Check stall signals, block if there is. 8142292SN/A // If status was Blocked 8152292SN/A // if so then go to unblocking 8162292SN/A // If status was Squashing 8172292SN/A // check if squashing is not high. Switch to running this cycle. 8182292SN/A 8192292SN/A readStallSignals(tid); 8202292SN/A 8212292SN/A if (fromCommit->commitInfo[tid].squash) { 8222292SN/A squash(tid); 8232292SN/A 8242292SN/A if (dispatchStatus[tid] == Blocked || 8252292SN/A dispatchStatus[tid] == Unblocking) { 8262292SN/A toRename->iewUnblock[tid] = true; 8272292SN/A wroteToTimeBuffer = true; 8282292SN/A } 8292292SN/A 8302292SN/A dispatchStatus[tid] = Squashing; 8312292SN/A 8322292SN/A fetchRedirect[tid] = false; 8332292SN/A return; 8342292SN/A } 8352292SN/A 8362292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8372702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8382292SN/A 8392292SN/A dispatchStatus[tid] = Squashing; 8402292SN/A 8412702Sktlim@umich.edu emptyRenameInsts(tid); 8422702Sktlim@umich.edu wroteToTimeBuffer = true; 8432292SN/A return; 8442292SN/A } 8452292SN/A 8462292SN/A if (checkStall(tid)) { 8472292SN/A block(tid); 8482292SN/A dispatchStatus[tid] = Blocked; 8492292SN/A return; 8502292SN/A } 8512292SN/A 8522292SN/A if (dispatchStatus[tid] == Blocked) { 8532292SN/A // Status from previous cycle was blocked, but there are no more stall 8542292SN/A // conditions. Switch over to unblocking. 8552292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8562292SN/A tid); 8572292SN/A 8582292SN/A dispatchStatus[tid] = Unblocking; 8592292SN/A 8602292SN/A unblock(tid); 8612292SN/A 8622292SN/A return; 8632292SN/A } 8642292SN/A 8652292SN/A if (dispatchStatus[tid] == Squashing) { 8662292SN/A // Switch status to running if rename isn't being told to block or 8672292SN/A // squash this cycle. 8682292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8692292SN/A tid); 8702292SN/A 8712292SN/A dispatchStatus[tid] = Running; 8722292SN/A 8732292SN/A return; 8742292SN/A } 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Avoid 8792292SN/ADefaultIEW<Impl>::sortInsts() 8802292SN/A{ 8812292SN/A int insts_from_rename = fromRename->size; 8822326SN/A#ifdef DEBUG 8833093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 8842292SN/A for (int i = 0; i < numThreads; i++) 8852292SN/A assert(insts[i].empty()); 8862326SN/A#endif 8872935Sksewell@umich.edu#endif 8882292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8892292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8902292SN/A } 8912292SN/A} 8922292SN/A 8932292SN/Atemplate <class Impl> 8942292SN/Avoid 8952702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8962702Sktlim@umich.edu{ 8972935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until " 8982935Sksewell@umich.edu "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]); 8992935Sksewell@umich.edu 9002702Sktlim@umich.edu while (!insts[tid].empty()) { 9013093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 9022935Sksewell@umich.edu if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) { 9032935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction" 9042935Sksewell@umich.edu " that occurs at or before delay slot [sn:%i].\n", 9052935Sksewell@umich.edu tid, bdelayDoneSeqNum[tid]); 9062935Sksewell@umich.edu break; 9072935Sksewell@umich.edu } else { 9082935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction " 9092935Sksewell@umich.edu "[sn:%i].\n", tid, insts[tid].front()->seqNum); 9102935Sksewell@umich.edu } 9112935Sksewell@umich.edu#endif 9122935Sksewell@umich.edu 9132702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 9142702Sktlim@umich.edu insts[tid].front()->isStore() ) { 9152702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 9162702Sktlim@umich.edu } 9172702Sktlim@umich.edu 9182702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 9192702Sktlim@umich.edu 9202702Sktlim@umich.edu insts[tid].pop(); 9212702Sktlim@umich.edu } 9222702Sktlim@umich.edu} 9232702Sktlim@umich.edu 9242702Sktlim@umich.edutemplate <class Impl> 9252702Sktlim@umich.eduvoid 9262292SN/ADefaultIEW<Impl>::wakeCPU() 9272292SN/A{ 9282292SN/A cpu->wakeCPU(); 9292292SN/A} 9302292SN/A 9312292SN/Atemplate <class Impl> 9322292SN/Avoid 9332292SN/ADefaultIEW<Impl>::activityThisCycle() 9342292SN/A{ 9352292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9362292SN/A cpu->activityThisCycle(); 9372292SN/A} 9382292SN/A 9392292SN/Atemplate <class Impl> 9402292SN/Ainline void 9412292SN/ADefaultIEW<Impl>::activateStage() 9422292SN/A{ 9432292SN/A DPRINTF(Activity, "Activating stage.\n"); 9442733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9452292SN/A} 9462292SN/A 9472292SN/Atemplate <class Impl> 9482292SN/Ainline void 9492292SN/ADefaultIEW<Impl>::deactivateStage() 9502292SN/A{ 9512292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9522733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9532292SN/A} 9542292SN/A 9552292SN/Atemplate<class Impl> 9562292SN/Avoid 9572292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 9582292SN/A{ 9592292SN/A // If status is Running or idle, 9602292SN/A // call dispatchInsts() 9612292SN/A // If status is Unblocking, 9622292SN/A // buffer any instructions coming from rename 9632292SN/A // continue trying to empty skid buffer 9642292SN/A // check if stall conditions have passed 9652292SN/A 9662292SN/A if (dispatchStatus[tid] == Blocked) { 9672292SN/A ++iewBlockCycles; 9682292SN/A 9692292SN/A } else if (dispatchStatus[tid] == Squashing) { 9702292SN/A ++iewSquashCycles; 9712292SN/A } 9722292SN/A 9732292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9742292SN/A // will allow, as long as it is not currently blocked. 9752292SN/A if (dispatchStatus[tid] == Running || 9762292SN/A dispatchStatus[tid] == Idle) { 9772292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9782292SN/A "dispatch.\n", tid); 9792292SN/A 9802292SN/A dispatchInsts(tid); 9812292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9822292SN/A // Make sure that the skid buffer has something in it if the 9832292SN/A // status is unblocking. 9842292SN/A assert(!skidsEmpty()); 9852292SN/A 9862292SN/A // If the status was unblocking, then instructions from the skid 9872292SN/A // buffer were used. Remove those instructions and handle 9882292SN/A // the rest of unblocking. 9892292SN/A dispatchInsts(tid); 9902292SN/A 9912292SN/A ++iewUnblockCycles; 9922292SN/A 9932292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9942292SN/A // Add the current inputs to the skid buffer so they can be 9952292SN/A // reprocessed when this stage unblocks. 9962292SN/A skidInsert(tid); 9972292SN/A } 9982292SN/A 9992292SN/A unblock(tid); 10002292SN/A } 10012292SN/A} 10022292SN/A 10032292SN/Atemplate <class Impl> 10042292SN/Avoid 10052292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 10062292SN/A{ 10072292SN/A dispatchedAllInsts = true; 10082292SN/A 10092292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 10102292SN/A // otherwise. 10112292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 10122292SN/A dispatchStatus[tid] == Unblocking ? 10132292SN/A skidBuffer[tid] : insts[tid]; 10142292SN/A 10152292SN/A int insts_to_add = insts_to_dispatch.size(); 10162292SN/A 10172292SN/A DynInstPtr inst; 10182292SN/A bool add_to_iq = false; 10192292SN/A int dis_num_inst = 0; 10202292SN/A 10212292SN/A // Loop through the instructions, putting them in the instruction 10222292SN/A // queue. 10232292SN/A for ( ; dis_num_inst < insts_to_add && 10242820Sktlim@umich.edu dis_num_inst < dispatchWidth; 10252292SN/A ++dis_num_inst) 10262292SN/A { 10272292SN/A inst = insts_to_dispatch.front(); 10282292SN/A 10292292SN/A if (dispatchStatus[tid] == Unblocking) { 10302292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10312292SN/A "buffer\n", tid); 10322292SN/A } 10332292SN/A 10342292SN/A // Make sure there's a valid instruction there. 10352292SN/A assert(inst); 10362292SN/A 10372292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 10382292SN/A "IQ.\n", 10392292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 10402292SN/A 10412292SN/A // Be sure to mark these instructions as ready so that the 10422292SN/A // commit stage can go ahead and execute them, and mark 10432292SN/A // them as issued so the IQ doesn't reprocess them. 10442292SN/A 10452292SN/A // Check for squashed instructions. 10462292SN/A if (inst->isSquashed()) { 10472292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10482292SN/A "not adding to IQ.\n", tid); 10492292SN/A 10502292SN/A ++iewDispSquashedInsts; 10512292SN/A 10522292SN/A insts_to_dispatch.pop(); 10532292SN/A 10542292SN/A //Tell Rename That An Instruction has been processed 10552292SN/A if (inst->isLoad() || inst->isStore()) { 10562292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10572292SN/A } 10582292SN/A toRename->iewInfo[tid].dispatched++; 10592292SN/A 10602292SN/A continue; 10612292SN/A } 10622292SN/A 10632292SN/A // Check for full conditions. 10642292SN/A if (instQueue.isFull(tid)) { 10652292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10662292SN/A 10672292SN/A // Call function to start blocking. 10682292SN/A block(tid); 10692292SN/A 10702292SN/A // Set unblock to false. Special case where we are using 10712292SN/A // skidbuffer (unblocking) instructions but then we still 10722292SN/A // get full in the IQ. 10732292SN/A toRename->iewUnblock[tid] = false; 10742292SN/A 10752292SN/A dispatchedAllInsts = false; 10762292SN/A 10772292SN/A ++iewIQFullEvents; 10782292SN/A break; 10792292SN/A } else if (ldstQueue.isFull(tid)) { 10802292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10812292SN/A 10822292SN/A // Call function to start blocking. 10832292SN/A block(tid); 10842292SN/A 10852292SN/A // Set unblock to false. Special case where we are using 10862292SN/A // skidbuffer (unblocking) instructions but then we still 10872292SN/A // get full in the IQ. 10882292SN/A toRename->iewUnblock[tid] = false; 10892292SN/A 10902292SN/A dispatchedAllInsts = false; 10912292SN/A 10922292SN/A ++iewLSQFullEvents; 10932292SN/A break; 10942292SN/A } 10952292SN/A 10962292SN/A // Otherwise issue the instruction just fine. 10972292SN/A if (inst->isLoad()) { 10982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10992292SN/A "encountered, adding to LSQ.\n", tid); 11002292SN/A 11012292SN/A // Reserve a spot in the load store queue for this 11022292SN/A // memory access. 11032292SN/A ldstQueue.insertLoad(inst); 11042292SN/A 11052292SN/A ++iewDispLoadInsts; 11062292SN/A 11072292SN/A add_to_iq = true; 11082292SN/A 11092292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11102292SN/A } else if (inst->isStore()) { 11112292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 11122292SN/A "encountered, adding to LSQ.\n", tid); 11132292SN/A 11142292SN/A ldstQueue.insertStore(inst); 11152292SN/A 11162292SN/A ++iewDispStoreInsts; 11172292SN/A 11182336SN/A if (inst->isStoreConditional()) { 11192336SN/A // Store conditionals need to be set as "canCommit()" 11202336SN/A // so that commit can process them when they reach the 11212336SN/A // head of commit. 11222348SN/A // @todo: This is somewhat specific to Alpha. 11232292SN/A inst->setCanCommit(); 11242292SN/A instQueue.insertNonSpec(inst); 11252292SN/A add_to_iq = false; 11262292SN/A 11272292SN/A ++iewDispNonSpecInsts; 11282292SN/A } else { 11292292SN/A add_to_iq = true; 11302292SN/A } 11312292SN/A 11322292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11332292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11342326SN/A // Same as non-speculative stores. 11352292SN/A inst->setCanCommit(); 11362292SN/A instQueue.insertBarrier(inst); 11372292SN/A add_to_iq = false; 11382292SN/A } else if (inst->isNop()) { 11392292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11402292SN/A "skipping.\n", tid); 11412292SN/A 11422292SN/A inst->setIssued(); 11432292SN/A inst->setExecuted(); 11442292SN/A inst->setCanCommit(); 11452292SN/A 11462326SN/A instQueue.recordProducer(inst); 11472292SN/A 11482727Sktlim@umich.edu iewExecutedNop[tid]++; 11492301SN/A 11502292SN/A add_to_iq = false; 11512292SN/A } else if (inst->isExecuted()) { 11522292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11532292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11542292SN/A "skipping.\n"); 11552292SN/A 11562292SN/A inst->setIssued(); 11572292SN/A inst->setCanCommit(); 11582292SN/A 11592326SN/A instQueue.recordProducer(inst); 11602292SN/A 11612292SN/A add_to_iq = false; 11622292SN/A } else { 11632292SN/A add_to_iq = true; 11642292SN/A } 11654033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11664033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11674033Sktlim@umich.edu "encountered, skipping.\n", tid); 11684033Sktlim@umich.edu 11694033Sktlim@umich.edu // Same as non-speculative stores. 11704033Sktlim@umich.edu inst->setCanCommit(); 11714033Sktlim@umich.edu 11724033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11734033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11744033Sktlim@umich.edu 11754033Sktlim@umich.edu ++iewDispNonSpecInsts; 11764033Sktlim@umich.edu 11774033Sktlim@umich.edu add_to_iq = false; 11784033Sktlim@umich.edu } 11792292SN/A 11802292SN/A // If the instruction queue is not full, then add the 11812292SN/A // instruction. 11822292SN/A if (add_to_iq) { 11832292SN/A instQueue.insert(inst); 11842292SN/A } 11852292SN/A 11862292SN/A insts_to_dispatch.pop(); 11872292SN/A 11882292SN/A toRename->iewInfo[tid].dispatched++; 11892292SN/A 11902292SN/A ++iewDispatchedInsts; 11912292SN/A } 11922292SN/A 11932292SN/A if (!insts_to_dispatch.empty()) { 11942935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11952292SN/A block(tid); 11962292SN/A toRename->iewUnblock[tid] = false; 11972292SN/A } 11982292SN/A 11992292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 12002292SN/A dispatchStatus[tid] = Running; 12012292SN/A 12022292SN/A updatedQueues = true; 12032292SN/A } 12042292SN/A 12052292SN/A dis_num_inst = 0; 12062292SN/A} 12072292SN/A 12082292SN/Atemplate <class Impl> 12092292SN/Avoid 12102292SN/ADefaultIEW<Impl>::printAvailableInsts() 12112292SN/A{ 12122292SN/A int inst = 0; 12132292SN/A 12142980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 12152292SN/A 12162292SN/A while (fromIssue->insts[inst]) { 12172292SN/A 12182980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 12192292SN/A 12202980Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->readPC() 12212292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12222292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12232292SN/A 12242292SN/A inst++; 12252292SN/A 12262292SN/A } 12272292SN/A 12282980Sgblack@eecs.umich.edu std::cout << "\n"; 12292292SN/A} 12302292SN/A 12312292SN/Atemplate <class Impl> 12322292SN/Avoid 12332292SN/ADefaultIEW<Impl>::executeInsts() 12342292SN/A{ 12352292SN/A wbNumInst = 0; 12362292SN/A wbCycle = 0; 12372292SN/A 12383867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 12393867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 12402292SN/A 12413867Sbinkertn@umich.edu while (threads != end) { 12422292SN/A unsigned tid = *threads++; 12432292SN/A fetchRedirect[tid] = false; 12442292SN/A } 12452292SN/A 12462698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12472698Sktlim@umich.edu// printAvailableInsts(); 12481062SN/A 12491062SN/A // Execute/writeback any instructions that are available. 12502333SN/A int insts_to_execute = fromIssue->size; 12512292SN/A int inst_num = 0; 12522333SN/A for (; inst_num < insts_to_execute; 12532326SN/A ++inst_num) { 12541062SN/A 12552292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12561062SN/A 12572333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12581062SN/A 12592292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 12602292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 12611062SN/A 12621062SN/A // Check if the instruction is squashed; if so then skip it 12631062SN/A if (inst->isSquashed()) { 12642292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12651062SN/A 12661062SN/A // Consider this instruction executed so that commit can go 12671062SN/A // ahead and retire the instruction. 12681062SN/A inst->setExecuted(); 12691062SN/A 12702292SN/A // Not sure if I should set this here or just let commit try to 12712292SN/A // commit any squashed instructions. I like the latter a bit more. 12722292SN/A inst->setCanCommit(); 12731062SN/A 12741062SN/A ++iewExecSquashedInsts; 12751062SN/A 12762820Sktlim@umich.edu decrWb(inst->seqNum); 12771062SN/A continue; 12781062SN/A } 12791062SN/A 12802292SN/A Fault fault = NoFault; 12811062SN/A 12821062SN/A // Execute instruction. 12831062SN/A // Note that if the instruction faults, it will be handled 12841062SN/A // at the commit stage. 12852292SN/A if (inst->isMemRef() && 12862292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12872292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12881062SN/A "reference.\n"); 12891062SN/A 12901062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12911062SN/A if (inst->isLoad()) { 12922292SN/A // Loads will mark themselves as executed, and their writeback 12932292SN/A // event adds the instruction to the queue to commit 12942292SN/A fault = ldstQueue.executeLoad(inst); 12951062SN/A } else if (inst->isStore()) { 12962367SN/A fault = ldstQueue.executeStore(inst); 12971062SN/A 12982292SN/A // If the store had a fault then it may not have a mem req 12992367SN/A if (!inst->isStoreConditional() && fault == NoFault) { 13002292SN/A inst->setExecuted(); 13012292SN/A 13022292SN/A instToCommit(inst); 13032367SN/A } else if (fault != NoFault) { 13042367SN/A // If the instruction faulted, then we need to send it along to commit 13052367SN/A // without the instruction completing. 13063732Sktlim@umich.edu DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 13073732Sktlim@umich.edu fault->name(), inst->seqNum); 13082367SN/A 13092367SN/A // Send this instruction to commit, also make sure iew stage 13102367SN/A // realizes there is activity. 13112367SN/A inst->setExecuted(); 13122367SN/A 13132367SN/A instToCommit(inst); 13142367SN/A activityThisCycle(); 13152292SN/A } 13162326SN/A 13172326SN/A // Store conditionals will mark themselves as 13182326SN/A // executed, and their writeback event will add the 13192326SN/A // instruction to the queue to commit. 13201062SN/A } else { 13212292SN/A panic("Unexpected memory type!\n"); 13221062SN/A } 13231062SN/A 13241062SN/A } else { 13251062SN/A inst->execute(); 13261062SN/A 13272292SN/A inst->setExecuted(); 13282292SN/A 13292292SN/A instToCommit(inst); 13301062SN/A } 13311062SN/A 13322301SN/A updateExeInstStats(inst); 13331681SN/A 13342326SN/A // Check if branch prediction was correct, if not then we need 13352326SN/A // to tell commit to squash in flight instructions. Only 13362326SN/A // handle this if there hasn't already been something that 13372107SN/A // redirects fetch in this group of instructions. 13381681SN/A 13392292SN/A // This probably needs to prioritize the redirects if a different 13402292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13412292SN/A // instruction first, so the branch resolution order will be correct. 13422292SN/A unsigned tid = inst->threadNumber; 13431062SN/A 13443732Sktlim@umich.edu if (!fetchRedirect[tid] || 13453732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13461062SN/A 13471062SN/A if (inst->mispredicted()) { 13482292SN/A fetchRedirect[tid] = true; 13491062SN/A 13502292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13513969Sgblack@eecs.umich.edu DPRINTF(IEW, "Predicted target was %#x, %#x.\n", 13523969Sgblack@eecs.umich.edu inst->readPredPC(), inst->readPredNPC()); 13533969Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 13543969Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->readNextPC(), 13553969Sgblack@eecs.umich.edu inst->readNextNPC()); 13561062SN/A // If incorrect, then signal the ROB that it must be squashed. 13572292SN/A squashDueToBranch(inst, tid); 13581062SN/A 13593795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13601062SN/A predictedTakenIncorrect++; 13612292SN/A } else { 13622292SN/A predictedNotTakenIncorrect++; 13631062SN/A } 13642292SN/A } else if (ldstQueue.violation(tid)) { 13654033Sktlim@umich.edu assert(inst->isMemRef()); 13662326SN/A // If there was an ordering violation, then get the 13672326SN/A // DynInst that caused the violation. Note that this 13682292SN/A // clears the violation signal. 13692292SN/A DynInstPtr violator; 13702292SN/A violator = ldstQueue.getMemDepViolator(tid); 13711062SN/A 13722292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13731062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13741062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13751062SN/A 13763732Sktlim@umich.edu // Ensure the violating instruction is older than 13773732Sktlim@umich.edu // current squash 13784033Sktlim@umich.edu/* if (fetchRedirect[tid] && 13794033Sktlim@umich.edu violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 13803732Sktlim@umich.edu continue; 13814033Sktlim@umich.edu*/ 13823732Sktlim@umich.edu fetchRedirect[tid] = true; 13833732Sktlim@umich.edu 13841062SN/A // Tell the instruction queue that a violation has occured. 13851062SN/A instQueue.violation(inst, violator); 13861062SN/A 13871062SN/A // Squash. 13882292SN/A squashDueToMemOrder(inst,tid); 13891062SN/A 13901062SN/A ++memOrderViolationEvents; 13912292SN/A } else if (ldstQueue.loadBlocked(tid) && 13922292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13932292SN/A fetchRedirect[tid] = true; 13942292SN/A 13952292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13962292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13972292SN/A inst->readPC(), inst->seqNum); 13982292SN/A 13992292SN/A squashDueToMemBlocked(inst, tid); 14001062SN/A } 14014033Sktlim@umich.edu } else { 14024033Sktlim@umich.edu // Reset any state associated with redirects that will not 14034033Sktlim@umich.edu // be used. 14044033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14054033Sktlim@umich.edu assert(inst->isMemRef()); 14064033Sktlim@umich.edu 14074033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14084033Sktlim@umich.edu 14094033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14104033Sktlim@umich.edu "%#x, inst PC: %#x. Addr is: %#x.\n", 14114033Sktlim@umich.edu violator->readPC(), inst->readPC(), inst->physEffAddr); 14124033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14134033Sktlim@umich.edu "already squashing\n"); 14144033Sktlim@umich.edu 14154033Sktlim@umich.edu ++memOrderViolationEvents; 14164033Sktlim@umich.edu } 14174033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14184033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14194033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14204033Sktlim@umich.edu "memory system is blocked. PC: %#x [sn:%lli]\n", 14214033Sktlim@umich.edu inst->readPC(), inst->seqNum); 14224033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14234033Sktlim@umich.edu "already squashing\n"); 14244033Sktlim@umich.edu 14254033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14264033Sktlim@umich.edu } 14274033Sktlim@umich.edu 14281062SN/A } 14291062SN/A } 14302292SN/A 14312348SN/A // Update and record activity if we processed any instructions. 14322292SN/A if (inst_num) { 14332292SN/A if (exeStatus == Idle) { 14342292SN/A exeStatus = Running; 14352292SN/A } 14362292SN/A 14372292SN/A updatedQueues = true; 14382292SN/A 14392292SN/A cpu->activityThisCycle(); 14402292SN/A } 14412292SN/A 14422292SN/A // Need to reset this in case a writeback event needs to write into the 14432292SN/A // iew queue. That way the writeback event will write into the correct 14442292SN/A // spot in the queue. 14452292SN/A wbNumInst = 0; 14462107SN/A} 14472107SN/A 14482292SN/Atemplate <class Impl> 14492107SN/Avoid 14502292SN/ADefaultIEW<Impl>::writebackInsts() 14512107SN/A{ 14522326SN/A // Loop through the head of the time buffer and wake any 14532326SN/A // dependents. These instructions are about to write back. Also 14542326SN/A // mark scoreboard that this instruction is finally complete. 14552326SN/A // Either have IEW have direct access to scoreboard, or have this 14562326SN/A // as part of backwards communication. 14573958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14582292SN/A toCommit->insts[inst_num]; inst_num++) { 14592107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14602301SN/A int tid = inst->threadNumber; 14612107SN/A 14622698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 14632698Sktlim@umich.edu inst->seqNum, inst->readPC()); 14642107SN/A 14652301SN/A iewInstsToCommit[tid]++; 14662301SN/A 14672292SN/A // Some instructions will be sent to commit without having 14682292SN/A // executed because they need commit to handle them. 14692292SN/A // E.g. Uncached loads have not actually executed when they 14702292SN/A // are first sent to commit. Instead commit must tell the LSQ 14712292SN/A // when it's ready to execute the uncached load. 14722367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14732301SN/A int dependents = instQueue.wakeDependents(inst); 14742107SN/A 14752292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14762292SN/A //mark as Ready 14772292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14782292SN/A inst->renamedDestRegIdx(i)); 14792292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14802107SN/A } 14812301SN/A 14822348SN/A if (dependents) { 14832348SN/A producerInst[tid]++; 14842348SN/A consumerInst[tid]+= dependents; 14852348SN/A } 14862326SN/A writebackCount[tid]++; 14872107SN/A } 14882820Sktlim@umich.edu 14892820Sktlim@umich.edu decrWb(inst->seqNum); 14902107SN/A } 14911060SN/A} 14921060SN/A 14931681SN/Atemplate<class Impl> 14941060SN/Avoid 14952292SN/ADefaultIEW<Impl>::tick() 14961060SN/A{ 14972292SN/A wbNumInst = 0; 14982292SN/A wbCycle = 0; 14991060SN/A 15002292SN/A wroteToTimeBuffer = false; 15012292SN/A updatedQueues = false; 15021060SN/A 15032292SN/A sortInsts(); 15041060SN/A 15052326SN/A // Free function units marked as being freed this cycle. 15062326SN/A fuPool->processFreeUnits(); 15071062SN/A 15083867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 15093867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 15101060SN/A 15112326SN/A // Check stall and squash signals, dispatch any instructions. 15123867Sbinkertn@umich.edu while (threads != end) { 15133867Sbinkertn@umich.edu unsigned tid = *threads++; 15141060SN/A 15152292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15161060SN/A 15172292SN/A checkSignalsAndUpdate(tid); 15182292SN/A dispatch(tid); 15191060SN/A } 15201060SN/A 15212292SN/A if (exeStatus != Squashing) { 15222292SN/A executeInsts(); 15231060SN/A 15242292SN/A writebackInsts(); 15252292SN/A 15262292SN/A // Have the instruction queue try to schedule any ready instructions. 15272292SN/A // (In actuality, this scheduling is for instructions that will 15282292SN/A // be executed next cycle.) 15292292SN/A instQueue.scheduleReadyInsts(); 15302292SN/A 15312292SN/A // Also should advance its own time buffers if the stage ran. 15322292SN/A // Not the best place for it, but this works (hopefully). 15332292SN/A issueToExecQueue.advance(); 15342292SN/A } 15352292SN/A 15362292SN/A bool broadcast_free_entries = false; 15372292SN/A 15382292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15392292SN/A exeStatus = Idle; 15402292SN/A updateLSQNextCycle = false; 15412292SN/A 15422292SN/A broadcast_free_entries = true; 15432292SN/A } 15442292SN/A 15452292SN/A // Writeback any stores using any leftover bandwidth. 15461681SN/A ldstQueue.writebackStores(); 15471681SN/A 15481061SN/A // Check the committed load/store signals to see if there's a load 15491061SN/A // or store to commit. Also check if it's being told to execute a 15501061SN/A // nonspeculative instruction. 15511681SN/A // This is pretty inefficient... 15522292SN/A 15533867Sbinkertn@umich.edu threads = activeThreads->begin(); 15543867Sbinkertn@umich.edu while (threads != end) { 15552292SN/A unsigned tid = (*threads++); 15562292SN/A 15572292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15582292SN/A 15592348SN/A // Update structures based on instructions committed. 15602292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15612292SN/A !fromCommit->commitInfo[tid].squash && 15622292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15632292SN/A 15642292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15652292SN/A 15662292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15672292SN/A 15682292SN/A updateLSQNextCycle = true; 15692292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15702292SN/A } 15712292SN/A 15722292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15732292SN/A 15742292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15752292SN/A if (fromCommit->commitInfo[tid].uncached) { 15762292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15774033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15782292SN/A } else { 15792292SN/A instQueue.scheduleNonSpec( 15802292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15812292SN/A } 15822292SN/A } 15832292SN/A 15842292SN/A if (broadcast_free_entries) { 15852292SN/A toFetch->iewInfo[tid].iqCount = 15862292SN/A instQueue.getCount(tid); 15872292SN/A toFetch->iewInfo[tid].ldstqCount = 15882292SN/A ldstQueue.getCount(tid); 15892292SN/A 15902292SN/A toRename->iewInfo[tid].usedIQ = true; 15912292SN/A toRename->iewInfo[tid].freeIQEntries = 15922292SN/A instQueue.numFreeEntries(); 15932292SN/A toRename->iewInfo[tid].usedLSQ = true; 15942292SN/A toRename->iewInfo[tid].freeLSQEntries = 15952292SN/A ldstQueue.numFreeEntries(tid); 15962292SN/A 15972292SN/A wroteToTimeBuffer = true; 15982292SN/A } 15992292SN/A 16002292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 16012292SN/A tid, toRename->iewInfo[tid].dispatched); 16021061SN/A } 16031061SN/A 16042292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 16052292SN/A "LSQ has %i free entries.\n", 16062292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 16072292SN/A ldstQueue.numFreeEntries()); 16082292SN/A 16092292SN/A updateStatus(); 16102292SN/A 16112292SN/A if (wroteToTimeBuffer) { 16122292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16132292SN/A cpu->activityThisCycle(); 16141061SN/A } 16151060SN/A} 16161060SN/A 16172301SN/Atemplate <class Impl> 16181060SN/Avoid 16192301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16201060SN/A{ 16212301SN/A int thread_number = inst->threadNumber; 16221060SN/A 16232301SN/A // 16242301SN/A // Pick off the software prefetches 16252301SN/A // 16262301SN/A#ifdef TARGET_ALPHA 16272301SN/A if (inst->isDataPrefetch()) 16282727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 16292301SN/A else 16302727Sktlim@umich.edu iewIewExecutedcutedInsts++; 16312301SN/A#else 16322669Sktlim@umich.edu iewExecutedInsts++; 16332301SN/A#endif 16341060SN/A 16352301SN/A // 16362301SN/A // Control operations 16372301SN/A // 16382301SN/A if (inst->isControl()) 16392727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 16401060SN/A 16412301SN/A // 16422301SN/A // Memory operations 16432301SN/A // 16442301SN/A if (inst->isMemRef()) { 16452727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 16461060SN/A 16472301SN/A if (inst->isLoad()) { 16482301SN/A iewExecLoadInsts[thread_number]++; 16491060SN/A } 16501060SN/A } 16511060SN/A} 1652