iew_impl.hh revision 3795
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 411681SN/Atemplate<class Impl> 422292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 432873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 441060SN/A instQueue(params), 451061SN/A ldstQueue(params), 462292SN/A fuPool(params->fuPool), 472292SN/A commitToIEWDelay(params->commitToIEWDelay), 482292SN/A renameToIEWDelay(params->renameToIEWDelay), 492292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 502820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 512292SN/A issueWidth(params->issueWidth), 522820Sktlim@umich.edu wbOutstanding(0), 532820Sktlim@umich.edu wbWidth(params->wbWidth), 542307SN/A numThreads(params->numberOfThreads), 552307SN/A switchedOut(false) 561060SN/A{ 572292SN/A _status = Active; 582292SN/A exeStatus = Running; 592292SN/A wbStatus = Idle; 601060SN/A 611060SN/A // Setup wire to read instructions coming from issue. 621060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 631060SN/A 641060SN/A // Instruction queue needs the queue between issue and execute. 651060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 661681SN/A 672292SN/A instQueue.setIEW(this); 681681SN/A ldstQueue.setIEW(this); 692292SN/A 702292SN/A for (int i=0; i < numThreads; i++) { 712292SN/A dispatchStatus[i] = Running; 722292SN/A stalls[i].commit = false; 732292SN/A fetchRedirect[i] = false; 742935Sksewell@umich.edu bdelayDoneSeqNum[i] = 0; 752292SN/A } 762292SN/A 772820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 782820Sktlim@umich.edu 792292SN/A updateLSQNextCycle = false; 802292SN/A 812820Sktlim@umich.edu ableToIssue = true; 822820Sktlim@umich.edu 832292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 842292SN/A} 852292SN/A 862292SN/Atemplate <class Impl> 872292SN/Astd::string 882292SN/ADefaultIEW<Impl>::name() const 892292SN/A{ 902292SN/A return cpu->name() + ".iew"; 911060SN/A} 921060SN/A 931681SN/Atemplate <class Impl> 941062SN/Avoid 952292SN/ADefaultIEW<Impl>::regStats() 961062SN/A{ 972301SN/A using namespace Stats; 982301SN/A 991062SN/A instQueue.regStats(); 1002727Sktlim@umich.edu ldstQueue.regStats(); 1011062SN/A 1021062SN/A iewIdleCycles 1031062SN/A .name(name() + ".iewIdleCycles") 1041062SN/A .desc("Number of cycles IEW is idle"); 1051062SN/A 1061062SN/A iewSquashCycles 1071062SN/A .name(name() + ".iewSquashCycles") 1081062SN/A .desc("Number of cycles IEW is squashing"); 1091062SN/A 1101062SN/A iewBlockCycles 1111062SN/A .name(name() + ".iewBlockCycles") 1121062SN/A .desc("Number of cycles IEW is blocking"); 1131062SN/A 1141062SN/A iewUnblockCycles 1151062SN/A .name(name() + ".iewUnblockCycles") 1161062SN/A .desc("Number of cycles IEW is unblocking"); 1171062SN/A 1181062SN/A iewDispatchedInsts 1191062SN/A .name(name() + ".iewDispatchedInsts") 1201062SN/A .desc("Number of instructions dispatched to IQ"); 1211062SN/A 1221062SN/A iewDispSquashedInsts 1231062SN/A .name(name() + ".iewDispSquashedInsts") 1241062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1251062SN/A 1261062SN/A iewDispLoadInsts 1271062SN/A .name(name() + ".iewDispLoadInsts") 1281062SN/A .desc("Number of dispatched load instructions"); 1291062SN/A 1301062SN/A iewDispStoreInsts 1311062SN/A .name(name() + ".iewDispStoreInsts") 1321062SN/A .desc("Number of dispatched store instructions"); 1331062SN/A 1341062SN/A iewDispNonSpecInsts 1351062SN/A .name(name() + ".iewDispNonSpecInsts") 1361062SN/A .desc("Number of dispatched non-speculative instructions"); 1371062SN/A 1381062SN/A iewIQFullEvents 1391062SN/A .name(name() + ".iewIQFullEvents") 1401062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1411062SN/A 1422292SN/A iewLSQFullEvents 1432292SN/A .name(name() + ".iewLSQFullEvents") 1442292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1452292SN/A 1461062SN/A memOrderViolationEvents 1471062SN/A .name(name() + ".memOrderViolationEvents") 1481062SN/A .desc("Number of memory order violations"); 1491062SN/A 1501062SN/A predictedTakenIncorrect 1511062SN/A .name(name() + ".predictedTakenIncorrect") 1521062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1532292SN/A 1542292SN/A predictedNotTakenIncorrect 1552292SN/A .name(name() + ".predictedNotTakenIncorrect") 1562292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1572292SN/A 1582292SN/A branchMispredicts 1592292SN/A .name(name() + ".branchMispredicts") 1602292SN/A .desc("Number of branch mispredicts detected at execute"); 1612292SN/A 1622292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1632301SN/A 1642727Sktlim@umich.edu iewExecutedInsts 1652353SN/A .name(name() + ".iewExecutedInsts") 1662727Sktlim@umich.edu .desc("Number of executed instructions"); 1672727Sktlim@umich.edu 1682727Sktlim@umich.edu iewExecLoadInsts 1692727Sktlim@umich.edu .init(cpu->number_of_threads) 1702353SN/A .name(name() + ".iewExecLoadInsts") 1712727Sktlim@umich.edu .desc("Number of load instructions executed") 1722727Sktlim@umich.edu .flags(total); 1732727Sktlim@umich.edu 1742727Sktlim@umich.edu iewExecSquashedInsts 1752353SN/A .name(name() + ".iewExecSquashedInsts") 1762727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1772727Sktlim@umich.edu 1782727Sktlim@umich.edu iewExecutedSwp 1792301SN/A .init(cpu->number_of_threads) 1802301SN/A .name(name() + ".EXEC:swp") 1812301SN/A .desc("number of swp insts executed") 1822727Sktlim@umich.edu .flags(total); 1832301SN/A 1842727Sktlim@umich.edu iewExecutedNop 1852301SN/A .init(cpu->number_of_threads) 1862301SN/A .name(name() + ".EXEC:nop") 1872301SN/A .desc("number of nop insts executed") 1882727Sktlim@umich.edu .flags(total); 1892301SN/A 1902727Sktlim@umich.edu iewExecutedRefs 1912301SN/A .init(cpu->number_of_threads) 1922301SN/A .name(name() + ".EXEC:refs") 1932301SN/A .desc("number of memory reference insts executed") 1942727Sktlim@umich.edu .flags(total); 1952301SN/A 1962727Sktlim@umich.edu iewExecutedBranches 1972301SN/A .init(cpu->number_of_threads) 1982301SN/A .name(name() + ".EXEC:branches") 1992301SN/A .desc("Number of branches executed") 2002727Sktlim@umich.edu .flags(total); 2012301SN/A 2022301SN/A iewExecStoreInsts 2032301SN/A .name(name() + ".EXEC:stores") 2042301SN/A .desc("Number of stores executed") 2052727Sktlim@umich.edu .flags(total); 2062727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2072727Sktlim@umich.edu 2082727Sktlim@umich.edu iewExecRate 2092727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2102727Sktlim@umich.edu .desc("Inst execution rate") 2112727Sktlim@umich.edu .flags(total); 2122727Sktlim@umich.edu 2132727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2142301SN/A 2152301SN/A iewInstsToCommit 2162301SN/A .init(cpu->number_of_threads) 2172301SN/A .name(name() + ".WB:sent") 2182301SN/A .desc("cumulative count of insts sent to commit") 2192727Sktlim@umich.edu .flags(total); 2202301SN/A 2212326SN/A writebackCount 2222301SN/A .init(cpu->number_of_threads) 2232301SN/A .name(name() + ".WB:count") 2242301SN/A .desc("cumulative count of insts written-back") 2252727Sktlim@umich.edu .flags(total); 2262301SN/A 2272326SN/A producerInst 2282301SN/A .init(cpu->number_of_threads) 2292301SN/A .name(name() + ".WB:producers") 2302301SN/A .desc("num instructions producing a value") 2312727Sktlim@umich.edu .flags(total); 2322301SN/A 2332326SN/A consumerInst 2342301SN/A .init(cpu->number_of_threads) 2352301SN/A .name(name() + ".WB:consumers") 2362301SN/A .desc("num instructions consuming a value") 2372727Sktlim@umich.edu .flags(total); 2382301SN/A 2392326SN/A wbPenalized 2402301SN/A .init(cpu->number_of_threads) 2412301SN/A .name(name() + ".WB:penalized") 2422301SN/A .desc("number of instrctions required to write to 'other' IQ") 2432727Sktlim@umich.edu .flags(total); 2442301SN/A 2452326SN/A wbPenalizedRate 2462301SN/A .name(name() + ".WB:penalized_rate") 2472301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2482727Sktlim@umich.edu .flags(total); 2492301SN/A 2502326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2512301SN/A 2522326SN/A wbFanout 2532301SN/A .name(name() + ".WB:fanout") 2542301SN/A .desc("average fanout of values written-back") 2552727Sktlim@umich.edu .flags(total); 2562301SN/A 2572326SN/A wbFanout = producerInst / consumerInst; 2582301SN/A 2592326SN/A wbRate 2602301SN/A .name(name() + ".WB:rate") 2612301SN/A .desc("insts written-back per cycle") 2622727Sktlim@umich.edu .flags(total); 2632326SN/A wbRate = writebackCount / cpu->numCycles; 2641062SN/A} 2651062SN/A 2661681SN/Atemplate<class Impl> 2671060SN/Avoid 2682292SN/ADefaultIEW<Impl>::initStage() 2691060SN/A{ 2702292SN/A for (int tid=0; tid < numThreads; tid++) { 2712292SN/A toRename->iewInfo[tid].usedIQ = true; 2722292SN/A toRename->iewInfo[tid].freeIQEntries = 2732292SN/A instQueue.numFreeEntries(tid); 2742292SN/A 2752292SN/A toRename->iewInfo[tid].usedLSQ = true; 2762292SN/A toRename->iewInfo[tid].freeLSQEntries = 2772292SN/A ldstQueue.numFreeEntries(tid); 2782292SN/A } 2792292SN/A} 2802292SN/A 2812292SN/Atemplate<class Impl> 2822292SN/Avoid 2832733Sktlim@umich.eduDefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 2842292SN/A{ 2852292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 2861060SN/A cpu = cpu_ptr; 2871060SN/A 2881060SN/A instQueue.setCPU(cpu_ptr); 2891061SN/A ldstQueue.setCPU(cpu_ptr); 2902292SN/A 2912733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2921060SN/A} 2931060SN/A 2941681SN/Atemplate<class Impl> 2951060SN/Avoid 2962292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2971060SN/A{ 2982292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 2991060SN/A timeBuffer = tb_ptr; 3001060SN/A 3011060SN/A // Setup wire to read information from time buffer, from commit. 3021060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3031060SN/A 3041060SN/A // Setup wire to write information back to previous stages. 3051060SN/A toRename = timeBuffer->getWire(0); 3061060SN/A 3072292SN/A toFetch = timeBuffer->getWire(0); 3082292SN/A 3091060SN/A // Instruction queue also needs main time buffer. 3101060SN/A instQueue.setTimeBuffer(tb_ptr); 3111060SN/A} 3121060SN/A 3131681SN/Atemplate<class Impl> 3141060SN/Avoid 3152292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3161060SN/A{ 3172292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3181060SN/A renameQueue = rq_ptr; 3191060SN/A 3201060SN/A // Setup wire to read information from rename queue. 3211060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3221060SN/A} 3231060SN/A 3241681SN/Atemplate<class Impl> 3251060SN/Avoid 3262292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3271060SN/A{ 3282292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3291060SN/A iewQueue = iq_ptr; 3301060SN/A 3311060SN/A // Setup wire to write instructions to commit. 3321060SN/A toCommit = iewQueue->getWire(0); 3331060SN/A} 3341060SN/A 3351681SN/Atemplate<class Impl> 3361060SN/Avoid 3372980Sgblack@eecs.umich.eduDefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3381060SN/A{ 3392292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3402292SN/A activeThreads = at_ptr; 3412292SN/A 3422292SN/A ldstQueue.setActiveThreads(at_ptr); 3432292SN/A instQueue.setActiveThreads(at_ptr); 3441060SN/A} 3451060SN/A 3461681SN/Atemplate<class Impl> 3471060SN/Avoid 3482292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3491060SN/A{ 3502292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3512292SN/A scoreboard = sb_ptr; 3521060SN/A} 3531060SN/A 3542307SN/Atemplate <class Impl> 3552863Sktlim@umich.edubool 3562843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3572307SN/A{ 3582843Sktlim@umich.edu // IEW is ready to drain at any time. 3592843Sktlim@umich.edu cpu->signalDrained(); 3602863Sktlim@umich.edu return true; 3611681SN/A} 3621681SN/A 3632316SN/Atemplate <class Impl> 3641681SN/Avoid 3652843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3662843Sktlim@umich.edu{ 3672843Sktlim@umich.edu} 3682843Sktlim@umich.edu 3692843Sktlim@umich.edutemplate <class Impl> 3702843Sktlim@umich.eduvoid 3712843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3721681SN/A{ 3732348SN/A // Clear any state. 3742307SN/A switchedOut = true; 3752367SN/A assert(insts[0].empty()); 3762367SN/A assert(skidBuffer[0].empty()); 3771681SN/A 3782307SN/A instQueue.switchOut(); 3792307SN/A ldstQueue.switchOut(); 3802307SN/A fuPool->switchOut(); 3812307SN/A 3822307SN/A for (int i = 0; i < numThreads; i++) { 3832307SN/A while (!insts[i].empty()) 3842307SN/A insts[i].pop(); 3852307SN/A while (!skidBuffer[i].empty()) 3862307SN/A skidBuffer[i].pop(); 3872307SN/A } 3881681SN/A} 3891681SN/A 3902307SN/Atemplate <class Impl> 3911681SN/Avoid 3922307SN/ADefaultIEW<Impl>::takeOverFrom() 3931060SN/A{ 3942348SN/A // Reset all state. 3952307SN/A _status = Active; 3962307SN/A exeStatus = Running; 3972307SN/A wbStatus = Idle; 3982307SN/A switchedOut = false; 3991060SN/A 4002307SN/A instQueue.takeOverFrom(); 4012307SN/A ldstQueue.takeOverFrom(); 4022307SN/A fuPool->takeOverFrom(); 4031060SN/A 4042307SN/A initStage(); 4052307SN/A cpu->activityThisCycle(); 4061060SN/A 4072307SN/A for (int i=0; i < numThreads; i++) { 4082307SN/A dispatchStatus[i] = Running; 4092307SN/A stalls[i].commit = false; 4102307SN/A fetchRedirect[i] = false; 4112307SN/A } 4121060SN/A 4132307SN/A updateLSQNextCycle = false; 4142307SN/A 4152873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4162307SN/A issueToExecQueue.advance(); 4171060SN/A } 4181060SN/A} 4191060SN/A 4201681SN/Atemplate<class Impl> 4211060SN/Avoid 4222292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4232107SN/A{ 4242292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4252292SN/A tid); 4262107SN/A 4272292SN/A // Tell the IQ to start squashing. 4282292SN/A instQueue.squash(tid); 4292107SN/A 4302292SN/A // Tell the LDSTQ to start squashing. 4313093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 4323093Sksewell@umich.edu ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid); 4333093Sksewell@umich.edu#else 4342326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4352935Sksewell@umich.edu#endif 4362292SN/A updatedQueues = true; 4372107SN/A 4382292SN/A // Clear the skid buffer in case it has any data in it. 4392935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4402935Sksewell@umich.edu tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum); 4412935Sksewell@umich.edu 4422292SN/A while (!skidBuffer[tid].empty()) { 4433093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 4442935Sksewell@umich.edu if (skidBuffer[tid].front()->seqNum <= 4452935Sksewell@umich.edu fromCommit->commitInfo[tid].bdelayDoneSeqNum) { 4462935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions " 4472935Sksewell@umich.edu "that occur before delay slot [sn:%i].\n", 4482935Sksewell@umich.edu fromCommit->commitInfo[tid].bdelayDoneSeqNum, 4492935Sksewell@umich.edu tid); 4502935Sksewell@umich.edu break; 4512935Sksewell@umich.edu } else { 4522935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from " 4532935Sksewell@umich.edu "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum); 4542935Sksewell@umich.edu } 4552935Sksewell@umich.edu#endif 4562292SN/A if (skidBuffer[tid].front()->isLoad() || 4572292SN/A skidBuffer[tid].front()->isStore() ) { 4582292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4592292SN/A } 4602107SN/A 4612292SN/A toRename->iewInfo[tid].dispatched++; 4622107SN/A 4632292SN/A skidBuffer[tid].pop(); 4642292SN/A } 4652107SN/A 4662935Sksewell@umich.edu bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 4672935Sksewell@umich.edu 4682702Sktlim@umich.edu emptyRenameInsts(tid); 4692107SN/A} 4702107SN/A 4712107SN/Atemplate<class Impl> 4722107SN/Avoid 4732292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4742292SN/A{ 4752292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4762292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4772292SN/A 4782292SN/A toCommit->squash[tid] = true; 4792292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4802292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4812292SN/A toCommit->branchMispredict[tid] = true; 4822935Sksewell@umich.edu 4833093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 4843795Sgblack@eecs.umich.edu int instSize = sizeof(TheISA::MachInst); 4853771Sgblack@eecs.umich.edu bool branch_taken = 4863795Sgblack@eecs.umich.edu !(inst->readNextPC() + instSize == inst->readNextNPC() && 4873795Sgblack@eecs.umich.edu (inst->readNextPC() == inst->readPC() + instSize || 4883795Sgblack@eecs.umich.edu inst->readNextPC() == inst->readPC() + 2 * instSize)); 4893771Sgblack@eecs.umich.edu DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n", 4903771Sgblack@eecs.umich.edu branch_taken ? "true": "false", inst->seqNum); 4912935Sksewell@umich.edu 4922935Sksewell@umich.edu toCommit->branchTaken[tid] = branch_taken; 4932935Sksewell@umich.edu 4943795Sgblack@eecs.umich.edu bool squashDelaySlot = true; 4953795Sgblack@eecs.umich.edu// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst)); 4963771Sgblack@eecs.umich.edu DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n", 4973771Sgblack@eecs.umich.edu squashDelaySlot ? "true": "false", inst->seqNum); 4983771Sgblack@eecs.umich.edu toCommit->squashDelaySlot[tid] = squashDelaySlot; 4993771Sgblack@eecs.umich.edu //If we're squashing the delay slot, we need to pick back up at NextPC. 5003771Sgblack@eecs.umich.edu //Otherwise, NextPC isn't being squashed, so we should pick back up at 5013771Sgblack@eecs.umich.edu //NextNPC. 5023795Sgblack@eecs.umich.edu if (squashDelaySlot) { 5032935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 5043795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 5053795Sgblack@eecs.umich.edu } else 5062935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextNPC(); 5073093Sksewell@umich.edu#else 5083093Sksewell@umich.edu toCommit->branchTaken[tid] = inst->readNextPC() != 5093093Sksewell@umich.edu (inst->readPC() + sizeof(TheISA::MachInst)); 5103093Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 5112935Sksewell@umich.edu#endif 5122292SN/A 5132292SN/A toCommit->includeSquashInst[tid] = false; 5142292SN/A 5152292SN/A wroteToTimeBuffer = true; 5162292SN/A} 5172292SN/A 5182292SN/Atemplate<class Impl> 5192292SN/Avoid 5202292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 5212292SN/A{ 5222292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 5232292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5242292SN/A 5252292SN/A toCommit->squash[tid] = true; 5262292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5272292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 5283795Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 5293795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 5303795Sgblack@eecs.umich.edu#endif 5312292SN/A 5322292SN/A toCommit->includeSquashInst[tid] = false; 5332292SN/A 5342292SN/A wroteToTimeBuffer = true; 5352292SN/A} 5362292SN/A 5372292SN/Atemplate<class Impl> 5382292SN/Avoid 5392292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5402292SN/A{ 5412292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5422292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5432292SN/A 5442292SN/A toCommit->squash[tid] = true; 5452292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5462292SN/A toCommit->nextPC[tid] = inst->readPC(); 5473795Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 5483795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 5493795Sgblack@eecs.umich.edu#endif 5502292SN/A 5512348SN/A // Must include the broadcasted SN in the squash. 5522292SN/A toCommit->includeSquashInst[tid] = true; 5532292SN/A 5542292SN/A ldstQueue.setLoadBlockedHandled(tid); 5552292SN/A 5562292SN/A wroteToTimeBuffer = true; 5572292SN/A} 5582292SN/A 5592292SN/Atemplate<class Impl> 5602292SN/Avoid 5612292SN/ADefaultIEW<Impl>::block(unsigned tid) 5622292SN/A{ 5632292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5642292SN/A 5652292SN/A if (dispatchStatus[tid] != Blocked && 5662292SN/A dispatchStatus[tid] != Unblocking) { 5672292SN/A toRename->iewBlock[tid] = true; 5682292SN/A wroteToTimeBuffer = true; 5692292SN/A } 5702292SN/A 5712292SN/A // Add the current inputs to the skid buffer so they can be 5722292SN/A // reprocessed when this stage unblocks. 5732292SN/A skidInsert(tid); 5742292SN/A 5752292SN/A dispatchStatus[tid] = Blocked; 5762292SN/A} 5772292SN/A 5782292SN/Atemplate<class Impl> 5792292SN/Avoid 5802292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5812292SN/A{ 5822292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5832292SN/A "buffer %u.\n",tid, tid); 5842292SN/A 5852292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5862292SN/A // Also switch status to running. 5872292SN/A if (skidBuffer[tid].empty()) { 5882292SN/A toRename->iewUnblock[tid] = true; 5892292SN/A wroteToTimeBuffer = true; 5902292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5912292SN/A dispatchStatus[tid] = Running; 5922292SN/A } 5932292SN/A} 5942292SN/A 5952292SN/Atemplate<class Impl> 5962292SN/Avoid 5972292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5981060SN/A{ 5991681SN/A instQueue.wakeDependents(inst); 6001060SN/A} 6011060SN/A 6022292SN/Atemplate<class Impl> 6032292SN/Avoid 6042292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6052292SN/A{ 6062292SN/A instQueue.rescheduleMemInst(inst); 6072292SN/A} 6081681SN/A 6091681SN/Atemplate<class Impl> 6101060SN/Avoid 6112292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6121060SN/A{ 6132292SN/A instQueue.replayMemInst(inst); 6142292SN/A} 6151060SN/A 6162292SN/Atemplate<class Impl> 6172292SN/Avoid 6182292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6192292SN/A{ 6203221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6213221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6223221Sktlim@umich.edu // being added to the queue to commit without being processed by 6233221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6243221Sktlim@umich.edu 6252292SN/A // First check the time slot that this instruction will write 6262292SN/A // to. If there are free write ports at the time, then go ahead 6272292SN/A // and write the instruction to that time. If there are not, 6282292SN/A // keep looking back to see where's the first time there's a 6292326SN/A // free slot. 6302292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6312292SN/A ++wbNumInst; 6322820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6332292SN/A ++wbCycle; 6342292SN/A wbNumInst = 0; 6352292SN/A } 6362292SN/A 6372353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6382292SN/A } 6392292SN/A 6402353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6412353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6422292SN/A // Add finished instruction to queue to commit. 6432292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6442292SN/A (*iewQueue)[wbCycle].size++; 6452292SN/A} 6462292SN/A 6472292SN/Atemplate <class Impl> 6482292SN/Aunsigned 6492292SN/ADefaultIEW<Impl>::validInstsFromRename() 6502292SN/A{ 6512292SN/A unsigned inst_count = 0; 6522292SN/A 6532292SN/A for (int i=0; i<fromRename->size; i++) { 6542731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6552292SN/A inst_count++; 6562292SN/A } 6572292SN/A 6582292SN/A return inst_count; 6592292SN/A} 6602292SN/A 6612292SN/Atemplate<class Impl> 6622292SN/Avoid 6632292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6642292SN/A{ 6652292SN/A DynInstPtr inst = NULL; 6662292SN/A 6672292SN/A while (!insts[tid].empty()) { 6682292SN/A inst = insts[tid].front(); 6692292SN/A 6702292SN/A insts[tid].pop(); 6712292SN/A 6722292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6732292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6742292SN/A inst->readPC(),tid); 6752292SN/A 6762292SN/A skidBuffer[tid].push(inst); 6772292SN/A } 6782292SN/A 6792292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6802292SN/A "Skidbuffer Exceeded Max Size"); 6812292SN/A} 6822292SN/A 6832292SN/Atemplate<class Impl> 6842292SN/Aint 6852292SN/ADefaultIEW<Impl>::skidCount() 6862292SN/A{ 6872292SN/A int max=0; 6882292SN/A 6892980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 6902292SN/A 6912292SN/A while (threads != (*activeThreads).end()) { 6922292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6932292SN/A if (max < thread_count) 6942292SN/A max = thread_count; 6952292SN/A } 6962292SN/A 6972292SN/A return max; 6982292SN/A} 6992292SN/A 7002292SN/Atemplate<class Impl> 7012292SN/Abool 7022292SN/ADefaultIEW<Impl>::skidsEmpty() 7032292SN/A{ 7042980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 7052292SN/A 7062292SN/A while (threads != (*activeThreads).end()) { 7072292SN/A if (!skidBuffer[*threads++].empty()) 7082292SN/A return false; 7092292SN/A } 7102292SN/A 7112292SN/A return true; 7121062SN/A} 7131062SN/A 7141681SN/Atemplate <class Impl> 7151062SN/Avoid 7162292SN/ADefaultIEW<Impl>::updateStatus() 7171062SN/A{ 7182292SN/A bool any_unblocking = false; 7191062SN/A 7202980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 7211062SN/A 7222292SN/A threads = (*activeThreads).begin(); 7231062SN/A 7242292SN/A while (threads != (*activeThreads).end()) { 7252292SN/A unsigned tid = *threads++; 7261062SN/A 7272292SN/A if (dispatchStatus[tid] == Unblocking) { 7282292SN/A any_unblocking = true; 7292292SN/A break; 7302292SN/A } 7312292SN/A } 7321062SN/A 7332292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7342292SN/A // and there's no stores waiting to write back, and dispatch is not 7352292SN/A // unblocking, then there is no internal activity for the IEW stage. 7362292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7372292SN/A !ldstQueue.willWB() && !any_unblocking) { 7382292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7391062SN/A 7402292SN/A deactivateStage(); 7411062SN/A 7422292SN/A _status = Inactive; 7432292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7442292SN/A ldstQueue.willWB() || 7452292SN/A any_unblocking)) { 7462292SN/A // Otherwise there is internal activity. Set to active. 7472292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7481062SN/A 7492292SN/A activateStage(); 7501062SN/A 7512292SN/A _status = Active; 7521062SN/A } 7531062SN/A} 7541062SN/A 7551681SN/Atemplate <class Impl> 7561062SN/Avoid 7572292SN/ADefaultIEW<Impl>::resetEntries() 7581062SN/A{ 7592292SN/A instQueue.resetEntries(); 7602292SN/A ldstQueue.resetEntries(); 7612292SN/A} 7621062SN/A 7632292SN/Atemplate <class Impl> 7642292SN/Avoid 7652292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7662292SN/A{ 7672292SN/A if (fromCommit->commitBlock[tid]) { 7682292SN/A stalls[tid].commit = true; 7692292SN/A } 7701062SN/A 7712292SN/A if (fromCommit->commitUnblock[tid]) { 7722292SN/A assert(stalls[tid].commit); 7732292SN/A stalls[tid].commit = false; 7742292SN/A } 7752292SN/A} 7762292SN/A 7772292SN/Atemplate <class Impl> 7782292SN/Abool 7792292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7802292SN/A{ 7812292SN/A bool ret_val(false); 7822292SN/A 7832292SN/A if (stalls[tid].commit) { 7842292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7852292SN/A ret_val = true; 7862292SN/A } else if (instQueue.isFull(tid)) { 7872292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7882292SN/A ret_val = true; 7892292SN/A } else if (ldstQueue.isFull(tid)) { 7902292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7912292SN/A 7922292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7932292SN/A 7942292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7952292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7962292SN/A } 7972292SN/A 7982292SN/A if (ldstQueue.numStores(tid) > 0) { 7992292SN/A 8002292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8012292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8022292SN/A } 8032292SN/A 8042292SN/A ret_val = true; 8052292SN/A } else if (ldstQueue.isStalled(tid)) { 8062292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8072292SN/A ret_val = true; 8082292SN/A } 8092292SN/A 8102292SN/A return ret_val; 8112292SN/A} 8122292SN/A 8132292SN/Atemplate <class Impl> 8142292SN/Avoid 8152292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 8162292SN/A{ 8172292SN/A // Check if there's a squash signal, squash if there is 8182292SN/A // Check stall signals, block if there is. 8192292SN/A // If status was Blocked 8202292SN/A // if so then go to unblocking 8212292SN/A // If status was Squashing 8222292SN/A // check if squashing is not high. Switch to running this cycle. 8232292SN/A 8242292SN/A readStallSignals(tid); 8252292SN/A 8262292SN/A if (fromCommit->commitInfo[tid].squash) { 8272292SN/A squash(tid); 8282292SN/A 8292292SN/A if (dispatchStatus[tid] == Blocked || 8302292SN/A dispatchStatus[tid] == Unblocking) { 8312292SN/A toRename->iewUnblock[tid] = true; 8322292SN/A wroteToTimeBuffer = true; 8332292SN/A } 8342292SN/A 8352292SN/A dispatchStatus[tid] = Squashing; 8362292SN/A 8372292SN/A fetchRedirect[tid] = false; 8382292SN/A return; 8392292SN/A } 8402292SN/A 8412292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8422702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8432292SN/A 8442292SN/A dispatchStatus[tid] = Squashing; 8452292SN/A 8462702Sktlim@umich.edu emptyRenameInsts(tid); 8472702Sktlim@umich.edu wroteToTimeBuffer = true; 8482292SN/A return; 8492292SN/A } 8502292SN/A 8512292SN/A if (checkStall(tid)) { 8522292SN/A block(tid); 8532292SN/A dispatchStatus[tid] = Blocked; 8542292SN/A return; 8552292SN/A } 8562292SN/A 8572292SN/A if (dispatchStatus[tid] == Blocked) { 8582292SN/A // Status from previous cycle was blocked, but there are no more stall 8592292SN/A // conditions. Switch over to unblocking. 8602292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8612292SN/A tid); 8622292SN/A 8632292SN/A dispatchStatus[tid] = Unblocking; 8642292SN/A 8652292SN/A unblock(tid); 8662292SN/A 8672292SN/A return; 8682292SN/A } 8692292SN/A 8702292SN/A if (dispatchStatus[tid] == Squashing) { 8712292SN/A // Switch status to running if rename isn't being told to block or 8722292SN/A // squash this cycle. 8732292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8742292SN/A tid); 8752292SN/A 8762292SN/A dispatchStatus[tid] = Running; 8772292SN/A 8782292SN/A return; 8792292SN/A } 8802292SN/A} 8812292SN/A 8822292SN/Atemplate <class Impl> 8832292SN/Avoid 8842292SN/ADefaultIEW<Impl>::sortInsts() 8852292SN/A{ 8862292SN/A int insts_from_rename = fromRename->size; 8872326SN/A#ifdef DEBUG 8883093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 8892292SN/A for (int i = 0; i < numThreads; i++) 8902292SN/A assert(insts[i].empty()); 8912326SN/A#endif 8922935Sksewell@umich.edu#endif 8932292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8942292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8952292SN/A } 8962292SN/A} 8972292SN/A 8982292SN/Atemplate <class Impl> 8992292SN/Avoid 9002702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 9012702Sktlim@umich.edu{ 9022935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until " 9032935Sksewell@umich.edu "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]); 9042935Sksewell@umich.edu 9052702Sktlim@umich.edu while (!insts[tid].empty()) { 9063093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 9072935Sksewell@umich.edu if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) { 9082935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction" 9092935Sksewell@umich.edu " that occurs at or before delay slot [sn:%i].\n", 9102935Sksewell@umich.edu tid, bdelayDoneSeqNum[tid]); 9112935Sksewell@umich.edu break; 9122935Sksewell@umich.edu } else { 9132935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction " 9142935Sksewell@umich.edu "[sn:%i].\n", tid, insts[tid].front()->seqNum); 9152935Sksewell@umich.edu } 9162935Sksewell@umich.edu#endif 9172935Sksewell@umich.edu 9182702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 9192702Sktlim@umich.edu insts[tid].front()->isStore() ) { 9202702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 9212702Sktlim@umich.edu } 9222702Sktlim@umich.edu 9232702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 9242702Sktlim@umich.edu 9252702Sktlim@umich.edu insts[tid].pop(); 9262702Sktlim@umich.edu } 9272702Sktlim@umich.edu} 9282702Sktlim@umich.edu 9292702Sktlim@umich.edutemplate <class Impl> 9302702Sktlim@umich.eduvoid 9312292SN/ADefaultIEW<Impl>::wakeCPU() 9322292SN/A{ 9332292SN/A cpu->wakeCPU(); 9342292SN/A} 9352292SN/A 9362292SN/Atemplate <class Impl> 9372292SN/Avoid 9382292SN/ADefaultIEW<Impl>::activityThisCycle() 9392292SN/A{ 9402292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9412292SN/A cpu->activityThisCycle(); 9422292SN/A} 9432292SN/A 9442292SN/Atemplate <class Impl> 9452292SN/Ainline void 9462292SN/ADefaultIEW<Impl>::activateStage() 9472292SN/A{ 9482292SN/A DPRINTF(Activity, "Activating stage.\n"); 9492733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9502292SN/A} 9512292SN/A 9522292SN/Atemplate <class Impl> 9532292SN/Ainline void 9542292SN/ADefaultIEW<Impl>::deactivateStage() 9552292SN/A{ 9562292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9572733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9582292SN/A} 9592292SN/A 9602292SN/Atemplate<class Impl> 9612292SN/Avoid 9622292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 9632292SN/A{ 9642292SN/A // If status is Running or idle, 9652292SN/A // call dispatchInsts() 9662292SN/A // If status is Unblocking, 9672292SN/A // buffer any instructions coming from rename 9682292SN/A // continue trying to empty skid buffer 9692292SN/A // check if stall conditions have passed 9702292SN/A 9712292SN/A if (dispatchStatus[tid] == Blocked) { 9722292SN/A ++iewBlockCycles; 9732292SN/A 9742292SN/A } else if (dispatchStatus[tid] == Squashing) { 9752292SN/A ++iewSquashCycles; 9762292SN/A } 9772292SN/A 9782292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9792292SN/A // will allow, as long as it is not currently blocked. 9802292SN/A if (dispatchStatus[tid] == Running || 9812292SN/A dispatchStatus[tid] == Idle) { 9822292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9832292SN/A "dispatch.\n", tid); 9842292SN/A 9852292SN/A dispatchInsts(tid); 9862292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9872292SN/A // Make sure that the skid buffer has something in it if the 9882292SN/A // status is unblocking. 9892292SN/A assert(!skidsEmpty()); 9902292SN/A 9912292SN/A // If the status was unblocking, then instructions from the skid 9922292SN/A // buffer were used. Remove those instructions and handle 9932292SN/A // the rest of unblocking. 9942292SN/A dispatchInsts(tid); 9952292SN/A 9962292SN/A ++iewUnblockCycles; 9972292SN/A 9982292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9992292SN/A // Add the current inputs to the skid buffer so they can be 10002292SN/A // reprocessed when this stage unblocks. 10012292SN/A skidInsert(tid); 10022292SN/A } 10032292SN/A 10042292SN/A unblock(tid); 10052292SN/A } 10062292SN/A} 10072292SN/A 10082292SN/Atemplate <class Impl> 10092292SN/Avoid 10102292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 10112292SN/A{ 10122292SN/A dispatchedAllInsts = true; 10132292SN/A 10142292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 10152292SN/A // otherwise. 10162292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 10172292SN/A dispatchStatus[tid] == Unblocking ? 10182292SN/A skidBuffer[tid] : insts[tid]; 10192292SN/A 10202292SN/A int insts_to_add = insts_to_dispatch.size(); 10212292SN/A 10222292SN/A DynInstPtr inst; 10232292SN/A bool add_to_iq = false; 10242292SN/A int dis_num_inst = 0; 10252292SN/A 10262292SN/A // Loop through the instructions, putting them in the instruction 10272292SN/A // queue. 10282292SN/A for ( ; dis_num_inst < insts_to_add && 10292820Sktlim@umich.edu dis_num_inst < dispatchWidth; 10302292SN/A ++dis_num_inst) 10312292SN/A { 10322292SN/A inst = insts_to_dispatch.front(); 10332292SN/A 10342292SN/A if (dispatchStatus[tid] == Unblocking) { 10352292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10362292SN/A "buffer\n", tid); 10372292SN/A } 10382292SN/A 10392292SN/A // Make sure there's a valid instruction there. 10402292SN/A assert(inst); 10412292SN/A 10422292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 10432292SN/A "IQ.\n", 10442292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 10452292SN/A 10462292SN/A // Be sure to mark these instructions as ready so that the 10472292SN/A // commit stage can go ahead and execute them, and mark 10482292SN/A // them as issued so the IQ doesn't reprocess them. 10492292SN/A 10502292SN/A // Check for squashed instructions. 10512292SN/A if (inst->isSquashed()) { 10522292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10532292SN/A "not adding to IQ.\n", tid); 10542292SN/A 10552292SN/A ++iewDispSquashedInsts; 10562292SN/A 10572292SN/A insts_to_dispatch.pop(); 10582292SN/A 10592292SN/A //Tell Rename That An Instruction has been processed 10602292SN/A if (inst->isLoad() || inst->isStore()) { 10612292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10622292SN/A } 10632292SN/A toRename->iewInfo[tid].dispatched++; 10642292SN/A 10652292SN/A continue; 10662292SN/A } 10672292SN/A 10682292SN/A // Check for full conditions. 10692292SN/A if (instQueue.isFull(tid)) { 10702292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10712292SN/A 10722292SN/A // Call function to start blocking. 10732292SN/A block(tid); 10742292SN/A 10752292SN/A // Set unblock to false. Special case where we are using 10762292SN/A // skidbuffer (unblocking) instructions but then we still 10772292SN/A // get full in the IQ. 10782292SN/A toRename->iewUnblock[tid] = false; 10792292SN/A 10802292SN/A dispatchedAllInsts = false; 10812292SN/A 10822292SN/A ++iewIQFullEvents; 10832292SN/A break; 10842292SN/A } else if (ldstQueue.isFull(tid)) { 10852292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10862292SN/A 10872292SN/A // Call function to start blocking. 10882292SN/A block(tid); 10892292SN/A 10902292SN/A // Set unblock to false. Special case where we are using 10912292SN/A // skidbuffer (unblocking) instructions but then we still 10922292SN/A // get full in the IQ. 10932292SN/A toRename->iewUnblock[tid] = false; 10942292SN/A 10952292SN/A dispatchedAllInsts = false; 10962292SN/A 10972292SN/A ++iewLSQFullEvents; 10982292SN/A break; 10992292SN/A } 11002292SN/A 11012292SN/A // Otherwise issue the instruction just fine. 11022292SN/A if (inst->isLoad()) { 11032292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 11042292SN/A "encountered, adding to LSQ.\n", tid); 11052292SN/A 11062292SN/A // Reserve a spot in the load store queue for this 11072292SN/A // memory access. 11082292SN/A ldstQueue.insertLoad(inst); 11092292SN/A 11102292SN/A ++iewDispLoadInsts; 11112292SN/A 11122292SN/A add_to_iq = true; 11132292SN/A 11142292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11152292SN/A } else if (inst->isStore()) { 11162292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 11172292SN/A "encountered, adding to LSQ.\n", tid); 11182292SN/A 11192292SN/A ldstQueue.insertStore(inst); 11202292SN/A 11212292SN/A ++iewDispStoreInsts; 11222292SN/A 11232336SN/A if (inst->isStoreConditional()) { 11242336SN/A // Store conditionals need to be set as "canCommit()" 11252336SN/A // so that commit can process them when they reach the 11262336SN/A // head of commit. 11272348SN/A // @todo: This is somewhat specific to Alpha. 11282292SN/A inst->setCanCommit(); 11292292SN/A instQueue.insertNonSpec(inst); 11302292SN/A add_to_iq = false; 11312292SN/A 11322292SN/A ++iewDispNonSpecInsts; 11332292SN/A } else { 11342292SN/A add_to_iq = true; 11352292SN/A } 11362292SN/A 11372292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11382292SN/A#if FULL_SYSTEM 11392292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11402326SN/A // Same as non-speculative stores. 11412292SN/A inst->setCanCommit(); 11422292SN/A instQueue.insertBarrier(inst); 11432292SN/A add_to_iq = false; 11442292SN/A#endif 11452292SN/A } else if (inst->isNonSpeculative()) { 11462292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11472292SN/A "encountered, skipping.\n", tid); 11482292SN/A 11492326SN/A // Same as non-speculative stores. 11502292SN/A inst->setCanCommit(); 11512292SN/A 11522292SN/A // Specifically insert it as nonspeculative. 11532292SN/A instQueue.insertNonSpec(inst); 11542292SN/A 11552292SN/A ++iewDispNonSpecInsts; 11562292SN/A 11572292SN/A add_to_iq = false; 11582292SN/A } else if (inst->isNop()) { 11592292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11602292SN/A "skipping.\n", tid); 11612292SN/A 11622292SN/A inst->setIssued(); 11632292SN/A inst->setExecuted(); 11642292SN/A inst->setCanCommit(); 11652292SN/A 11662326SN/A instQueue.recordProducer(inst); 11672292SN/A 11682727Sktlim@umich.edu iewExecutedNop[tid]++; 11692301SN/A 11702292SN/A add_to_iq = false; 11712292SN/A } else if (inst->isExecuted()) { 11722292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11732292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11742292SN/A "skipping.\n"); 11752292SN/A 11762292SN/A inst->setIssued(); 11772292SN/A inst->setCanCommit(); 11782292SN/A 11792326SN/A instQueue.recordProducer(inst); 11802292SN/A 11812292SN/A add_to_iq = false; 11822292SN/A } else { 11832292SN/A add_to_iq = true; 11842292SN/A } 11852292SN/A 11862292SN/A // If the instruction queue is not full, then add the 11872292SN/A // instruction. 11882292SN/A if (add_to_iq) { 11892292SN/A instQueue.insert(inst); 11902292SN/A } 11912292SN/A 11922292SN/A insts_to_dispatch.pop(); 11932292SN/A 11942292SN/A toRename->iewInfo[tid].dispatched++; 11952292SN/A 11962292SN/A ++iewDispatchedInsts; 11972292SN/A } 11982292SN/A 11992292SN/A if (!insts_to_dispatch.empty()) { 12002935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 12012292SN/A block(tid); 12022292SN/A toRename->iewUnblock[tid] = false; 12032292SN/A } 12042292SN/A 12052292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 12062292SN/A dispatchStatus[tid] = Running; 12072292SN/A 12082292SN/A updatedQueues = true; 12092292SN/A } 12102292SN/A 12112292SN/A dis_num_inst = 0; 12122292SN/A} 12132292SN/A 12142292SN/Atemplate <class Impl> 12152292SN/Avoid 12162292SN/ADefaultIEW<Impl>::printAvailableInsts() 12172292SN/A{ 12182292SN/A int inst = 0; 12192292SN/A 12202980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 12212292SN/A 12222292SN/A while (fromIssue->insts[inst]) { 12232292SN/A 12242980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 12252292SN/A 12262980Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->readPC() 12272292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12282292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12292292SN/A 12302292SN/A inst++; 12312292SN/A 12322292SN/A } 12332292SN/A 12342980Sgblack@eecs.umich.edu std::cout << "\n"; 12352292SN/A} 12362292SN/A 12372292SN/Atemplate <class Impl> 12382292SN/Avoid 12392292SN/ADefaultIEW<Impl>::executeInsts() 12402292SN/A{ 12412292SN/A wbNumInst = 0; 12422292SN/A wbCycle = 0; 12432292SN/A 12442980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 12452292SN/A 12462292SN/A while (threads != (*activeThreads).end()) { 12472292SN/A unsigned tid = *threads++; 12482292SN/A fetchRedirect[tid] = false; 12492292SN/A } 12502292SN/A 12512698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12522698Sktlim@umich.edu// printAvailableInsts(); 12531062SN/A 12541062SN/A // Execute/writeback any instructions that are available. 12552333SN/A int insts_to_execute = fromIssue->size; 12562292SN/A int inst_num = 0; 12572333SN/A for (; inst_num < insts_to_execute; 12582326SN/A ++inst_num) { 12591062SN/A 12602292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12611062SN/A 12622333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12631062SN/A 12642292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 12652292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 12661062SN/A 12671062SN/A // Check if the instruction is squashed; if so then skip it 12681062SN/A if (inst->isSquashed()) { 12692292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12701062SN/A 12711062SN/A // Consider this instruction executed so that commit can go 12721062SN/A // ahead and retire the instruction. 12731062SN/A inst->setExecuted(); 12741062SN/A 12752292SN/A // Not sure if I should set this here or just let commit try to 12762292SN/A // commit any squashed instructions. I like the latter a bit more. 12772292SN/A inst->setCanCommit(); 12781062SN/A 12791062SN/A ++iewExecSquashedInsts; 12801062SN/A 12812820Sktlim@umich.edu decrWb(inst->seqNum); 12821062SN/A continue; 12831062SN/A } 12841062SN/A 12852292SN/A Fault fault = NoFault; 12861062SN/A 12871062SN/A // Execute instruction. 12881062SN/A // Note that if the instruction faults, it will be handled 12891062SN/A // at the commit stage. 12902292SN/A if (inst->isMemRef() && 12912292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12922292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12931062SN/A "reference.\n"); 12941062SN/A 12951062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12961062SN/A if (inst->isLoad()) { 12972292SN/A // Loads will mark themselves as executed, and their writeback 12982292SN/A // event adds the instruction to the queue to commit 12992292SN/A fault = ldstQueue.executeLoad(inst); 13001062SN/A } else if (inst->isStore()) { 13012367SN/A fault = ldstQueue.executeStore(inst); 13021062SN/A 13032292SN/A // If the store had a fault then it may not have a mem req 13042367SN/A if (!inst->isStoreConditional() && fault == NoFault) { 13052292SN/A inst->setExecuted(); 13062292SN/A 13072292SN/A instToCommit(inst); 13082367SN/A } else if (fault != NoFault) { 13092367SN/A // If the instruction faulted, then we need to send it along to commit 13102367SN/A // without the instruction completing. 13113221Sktlim@umich.edu DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum); 13122367SN/A 13132367SN/A // Send this instruction to commit, also make sure iew stage 13142367SN/A // realizes there is activity. 13152367SN/A inst->setExecuted(); 13162367SN/A 13172367SN/A instToCommit(inst); 13182367SN/A activityThisCycle(); 13192292SN/A } 13202326SN/A 13212326SN/A // Store conditionals will mark themselves as 13222326SN/A // executed, and their writeback event will add the 13232326SN/A // instruction to the queue to commit. 13241062SN/A } else { 13252292SN/A panic("Unexpected memory type!\n"); 13261062SN/A } 13271062SN/A 13281062SN/A } else { 13291062SN/A inst->execute(); 13301062SN/A 13312292SN/A inst->setExecuted(); 13322292SN/A 13332292SN/A instToCommit(inst); 13341062SN/A } 13351062SN/A 13362301SN/A updateExeInstStats(inst); 13371681SN/A 13382326SN/A // Check if branch prediction was correct, if not then we need 13392326SN/A // to tell commit to squash in flight instructions. Only 13402326SN/A // handle this if there hasn't already been something that 13412107SN/A // redirects fetch in this group of instructions. 13421681SN/A 13432292SN/A // This probably needs to prioritize the redirects if a different 13442292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13452292SN/A // instruction first, so the branch resolution order will be correct. 13462292SN/A unsigned tid = inst->threadNumber; 13471062SN/A 13482292SN/A if (!fetchRedirect[tid]) { 13491062SN/A 13501062SN/A if (inst->mispredicted()) { 13512292SN/A fetchRedirect[tid] = true; 13521062SN/A 13532292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13543795Sgblack@eecs.umich.edu DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC); 13553093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 13563093Sksewell@umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 13573093Sksewell@umich.edu inst->nextNPC); 13583093Sksewell@umich.edu#else 13592292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 13601062SN/A inst->nextPC); 13612935Sksewell@umich.edu#endif 13621062SN/A // If incorrect, then signal the ROB that it must be squashed. 13632292SN/A squashDueToBranch(inst, tid); 13641062SN/A 13653795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13661062SN/A predictedTakenIncorrect++; 13672292SN/A } else { 13682292SN/A predictedNotTakenIncorrect++; 13691062SN/A } 13702292SN/A } else if (ldstQueue.violation(tid)) { 13712292SN/A fetchRedirect[tid] = true; 13721062SN/A 13732326SN/A // If there was an ordering violation, then get the 13742326SN/A // DynInst that caused the violation. Note that this 13752292SN/A // clears the violation signal. 13762292SN/A DynInstPtr violator; 13772292SN/A violator = ldstQueue.getMemDepViolator(tid); 13781062SN/A 13792292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13801062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13811062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13821062SN/A 13831062SN/A // Tell the instruction queue that a violation has occured. 13841062SN/A instQueue.violation(inst, violator); 13851062SN/A 13861062SN/A // Squash. 13872292SN/A squashDueToMemOrder(inst,tid); 13881062SN/A 13891062SN/A ++memOrderViolationEvents; 13902292SN/A } else if (ldstQueue.loadBlocked(tid) && 13912292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13922292SN/A fetchRedirect[tid] = true; 13932292SN/A 13942292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13952292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13962292SN/A inst->readPC(), inst->seqNum); 13972292SN/A 13982292SN/A squashDueToMemBlocked(inst, tid); 13991062SN/A } 14001062SN/A } 14011062SN/A } 14022292SN/A 14032348SN/A // Update and record activity if we processed any instructions. 14042292SN/A if (inst_num) { 14052292SN/A if (exeStatus == Idle) { 14062292SN/A exeStatus = Running; 14072292SN/A } 14082292SN/A 14092292SN/A updatedQueues = true; 14102292SN/A 14112292SN/A cpu->activityThisCycle(); 14122292SN/A } 14132292SN/A 14142292SN/A // Need to reset this in case a writeback event needs to write into the 14152292SN/A // iew queue. That way the writeback event will write into the correct 14162292SN/A // spot in the queue. 14172292SN/A wbNumInst = 0; 14182107SN/A} 14192107SN/A 14202292SN/Atemplate <class Impl> 14212107SN/Avoid 14222292SN/ADefaultIEW<Impl>::writebackInsts() 14232107SN/A{ 14242326SN/A // Loop through the head of the time buffer and wake any 14252326SN/A // dependents. These instructions are about to write back. Also 14262326SN/A // mark scoreboard that this instruction is finally complete. 14272326SN/A // Either have IEW have direct access to scoreboard, or have this 14282326SN/A // as part of backwards communication. 14292107SN/A for (int inst_num = 0; inst_num < issueWidth && 14302292SN/A toCommit->insts[inst_num]; inst_num++) { 14312107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14322301SN/A int tid = inst->threadNumber; 14332107SN/A 14342698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 14352698Sktlim@umich.edu inst->seqNum, inst->readPC()); 14362107SN/A 14372301SN/A iewInstsToCommit[tid]++; 14382301SN/A 14392292SN/A // Some instructions will be sent to commit without having 14402292SN/A // executed because they need commit to handle them. 14412292SN/A // E.g. Uncached loads have not actually executed when they 14422292SN/A // are first sent to commit. Instead commit must tell the LSQ 14432292SN/A // when it's ready to execute the uncached load. 14442367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14452301SN/A int dependents = instQueue.wakeDependents(inst); 14462107SN/A 14472292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14482292SN/A //mark as Ready 14492292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14502292SN/A inst->renamedDestRegIdx(i)); 14512292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14522107SN/A } 14532301SN/A 14542348SN/A if (dependents) { 14552348SN/A producerInst[tid]++; 14562348SN/A consumerInst[tid]+= dependents; 14572348SN/A } 14582326SN/A writebackCount[tid]++; 14592107SN/A } 14602820Sktlim@umich.edu 14612820Sktlim@umich.edu decrWb(inst->seqNum); 14622107SN/A } 14631060SN/A} 14641060SN/A 14651681SN/Atemplate<class Impl> 14661060SN/Avoid 14672292SN/ADefaultIEW<Impl>::tick() 14681060SN/A{ 14692292SN/A wbNumInst = 0; 14702292SN/A wbCycle = 0; 14711060SN/A 14722292SN/A wroteToTimeBuffer = false; 14732292SN/A updatedQueues = false; 14741060SN/A 14752292SN/A sortInsts(); 14761060SN/A 14772326SN/A // Free function units marked as being freed this cycle. 14782326SN/A fuPool->processFreeUnits(); 14791062SN/A 14802980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 14811060SN/A 14822326SN/A // Check stall and squash signals, dispatch any instructions. 14832292SN/A while (threads != (*activeThreads).end()) { 14842292SN/A unsigned tid = *threads++; 14851060SN/A 14862292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14871060SN/A 14882292SN/A checkSignalsAndUpdate(tid); 14892292SN/A dispatch(tid); 14901060SN/A } 14911060SN/A 14922292SN/A if (exeStatus != Squashing) { 14932292SN/A executeInsts(); 14941060SN/A 14952292SN/A writebackInsts(); 14962292SN/A 14972292SN/A // Have the instruction queue try to schedule any ready instructions. 14982292SN/A // (In actuality, this scheduling is for instructions that will 14992292SN/A // be executed next cycle.) 15002292SN/A instQueue.scheduleReadyInsts(); 15012292SN/A 15022292SN/A // Also should advance its own time buffers if the stage ran. 15032292SN/A // Not the best place for it, but this works (hopefully). 15042292SN/A issueToExecQueue.advance(); 15052292SN/A } 15062292SN/A 15072292SN/A bool broadcast_free_entries = false; 15082292SN/A 15092292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15102292SN/A exeStatus = Idle; 15112292SN/A updateLSQNextCycle = false; 15122292SN/A 15132292SN/A broadcast_free_entries = true; 15142292SN/A } 15152292SN/A 15162292SN/A // Writeback any stores using any leftover bandwidth. 15171681SN/A ldstQueue.writebackStores(); 15181681SN/A 15191061SN/A // Check the committed load/store signals to see if there's a load 15201061SN/A // or store to commit. Also check if it's being told to execute a 15211061SN/A // nonspeculative instruction. 15221681SN/A // This is pretty inefficient... 15232292SN/A 15242292SN/A threads = (*activeThreads).begin(); 15252292SN/A while (threads != (*activeThreads).end()) { 15262292SN/A unsigned tid = (*threads++); 15272292SN/A 15282292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15292292SN/A 15302348SN/A // Update structures based on instructions committed. 15312292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15322292SN/A !fromCommit->commitInfo[tid].squash && 15332292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15342292SN/A 15352292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15362292SN/A 15372292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15382292SN/A 15392292SN/A updateLSQNextCycle = true; 15402292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15412292SN/A } 15422292SN/A 15432292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15442292SN/A 15452292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15462292SN/A if (fromCommit->commitInfo[tid].uncached) { 15472292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15482292SN/A } else { 15492292SN/A instQueue.scheduleNonSpec( 15502292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15512292SN/A } 15522292SN/A } 15532292SN/A 15542292SN/A if (broadcast_free_entries) { 15552292SN/A toFetch->iewInfo[tid].iqCount = 15562292SN/A instQueue.getCount(tid); 15572292SN/A toFetch->iewInfo[tid].ldstqCount = 15582292SN/A ldstQueue.getCount(tid); 15592292SN/A 15602292SN/A toRename->iewInfo[tid].usedIQ = true; 15612292SN/A toRename->iewInfo[tid].freeIQEntries = 15622292SN/A instQueue.numFreeEntries(); 15632292SN/A toRename->iewInfo[tid].usedLSQ = true; 15642292SN/A toRename->iewInfo[tid].freeLSQEntries = 15652292SN/A ldstQueue.numFreeEntries(tid); 15662292SN/A 15672292SN/A wroteToTimeBuffer = true; 15682292SN/A } 15692292SN/A 15702292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15712292SN/A tid, toRename->iewInfo[tid].dispatched); 15721061SN/A } 15731061SN/A 15742292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15752292SN/A "LSQ has %i free entries.\n", 15762292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15772292SN/A ldstQueue.numFreeEntries()); 15782292SN/A 15792292SN/A updateStatus(); 15802292SN/A 15812292SN/A if (wroteToTimeBuffer) { 15822292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15832292SN/A cpu->activityThisCycle(); 15841061SN/A } 15851060SN/A} 15861060SN/A 15872301SN/Atemplate <class Impl> 15881060SN/Avoid 15892301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15901060SN/A{ 15912301SN/A int thread_number = inst->threadNumber; 15921060SN/A 15932301SN/A // 15942301SN/A // Pick off the software prefetches 15952301SN/A // 15962301SN/A#ifdef TARGET_ALPHA 15972301SN/A if (inst->isDataPrefetch()) 15982727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 15992301SN/A else 16002727Sktlim@umich.edu iewIewExecutedcutedInsts++; 16012301SN/A#else 16022669Sktlim@umich.edu iewExecutedInsts++; 16032301SN/A#endif 16041060SN/A 16052301SN/A // 16062301SN/A // Control operations 16072301SN/A // 16082301SN/A if (inst->isControl()) 16092727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 16101060SN/A 16112301SN/A // 16122301SN/A // Memory operations 16132301SN/A // 16142301SN/A if (inst->isMemRef()) { 16152727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 16161060SN/A 16172301SN/A if (inst->isLoad()) { 16182301SN/A iewExecLoadInsts[thread_number]++; 16191060SN/A } 16201060SN/A } 16211060SN/A} 1622