iew_impl.hh revision 2935
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 412292SN/Ausing namespace std; 421681SN/A 431681SN/Atemplate<class Impl> 442292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 452873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 461060SN/A instQueue(params), 471061SN/A ldstQueue(params), 482292SN/A fuPool(params->fuPool), 492292SN/A commitToIEWDelay(params->commitToIEWDelay), 502292SN/A renameToIEWDelay(params->renameToIEWDelay), 512292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 522820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 532292SN/A issueWidth(params->issueWidth), 542820Sktlim@umich.edu wbOutstanding(0), 552820Sktlim@umich.edu wbWidth(params->wbWidth), 562307SN/A numThreads(params->numberOfThreads), 572307SN/A switchedOut(false) 581060SN/A{ 592292SN/A _status = Active; 602292SN/A exeStatus = Running; 612292SN/A wbStatus = Idle; 621060SN/A 631060SN/A // Setup wire to read instructions coming from issue. 641060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 651060SN/A 661060SN/A // Instruction queue needs the queue between issue and execute. 671060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 681681SN/A 692292SN/A instQueue.setIEW(this); 701681SN/A ldstQueue.setIEW(this); 712292SN/A 722292SN/A for (int i=0; i < numThreads; i++) { 732292SN/A dispatchStatus[i] = Running; 742292SN/A stalls[i].commit = false; 752292SN/A fetchRedirect[i] = false; 762935Sksewell@umich.edu bdelayDoneSeqNum[i] = 0; 772292SN/A } 782292SN/A 792820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 802820Sktlim@umich.edu 812292SN/A updateLSQNextCycle = false; 822292SN/A 832820Sktlim@umich.edu ableToIssue = true; 842820Sktlim@umich.edu 852292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 862292SN/A} 872292SN/A 882292SN/Atemplate <class Impl> 892292SN/Astd::string 902292SN/ADefaultIEW<Impl>::name() const 912292SN/A{ 922292SN/A return cpu->name() + ".iew"; 931060SN/A} 941060SN/A 951681SN/Atemplate <class Impl> 961062SN/Avoid 972292SN/ADefaultIEW<Impl>::regStats() 981062SN/A{ 992301SN/A using namespace Stats; 1002301SN/A 1011062SN/A instQueue.regStats(); 1022727Sktlim@umich.edu ldstQueue.regStats(); 1031062SN/A 1041062SN/A iewIdleCycles 1051062SN/A .name(name() + ".iewIdleCycles") 1061062SN/A .desc("Number of cycles IEW is idle"); 1071062SN/A 1081062SN/A iewSquashCycles 1091062SN/A .name(name() + ".iewSquashCycles") 1101062SN/A .desc("Number of cycles IEW is squashing"); 1111062SN/A 1121062SN/A iewBlockCycles 1131062SN/A .name(name() + ".iewBlockCycles") 1141062SN/A .desc("Number of cycles IEW is blocking"); 1151062SN/A 1161062SN/A iewUnblockCycles 1171062SN/A .name(name() + ".iewUnblockCycles") 1181062SN/A .desc("Number of cycles IEW is unblocking"); 1191062SN/A 1201062SN/A iewDispatchedInsts 1211062SN/A .name(name() + ".iewDispatchedInsts") 1221062SN/A .desc("Number of instructions dispatched to IQ"); 1231062SN/A 1241062SN/A iewDispSquashedInsts 1251062SN/A .name(name() + ".iewDispSquashedInsts") 1261062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1271062SN/A 1281062SN/A iewDispLoadInsts 1291062SN/A .name(name() + ".iewDispLoadInsts") 1301062SN/A .desc("Number of dispatched load instructions"); 1311062SN/A 1321062SN/A iewDispStoreInsts 1331062SN/A .name(name() + ".iewDispStoreInsts") 1341062SN/A .desc("Number of dispatched store instructions"); 1351062SN/A 1361062SN/A iewDispNonSpecInsts 1371062SN/A .name(name() + ".iewDispNonSpecInsts") 1381062SN/A .desc("Number of dispatched non-speculative instructions"); 1391062SN/A 1401062SN/A iewIQFullEvents 1411062SN/A .name(name() + ".iewIQFullEvents") 1421062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1431062SN/A 1442292SN/A iewLSQFullEvents 1452292SN/A .name(name() + ".iewLSQFullEvents") 1462292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1472292SN/A 1481062SN/A memOrderViolationEvents 1491062SN/A .name(name() + ".memOrderViolationEvents") 1501062SN/A .desc("Number of memory order violations"); 1511062SN/A 1521062SN/A predictedTakenIncorrect 1531062SN/A .name(name() + ".predictedTakenIncorrect") 1541062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1552292SN/A 1562292SN/A predictedNotTakenIncorrect 1572292SN/A .name(name() + ".predictedNotTakenIncorrect") 1582292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1592292SN/A 1602292SN/A branchMispredicts 1612292SN/A .name(name() + ".branchMispredicts") 1622292SN/A .desc("Number of branch mispredicts detected at execute"); 1632292SN/A 1642292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1652301SN/A 1662727Sktlim@umich.edu iewExecutedInsts 1672727Sktlim@umich.edu .name(name() + ".EXEC:insts") 1682727Sktlim@umich.edu .desc("Number of executed instructions"); 1692727Sktlim@umich.edu 1702727Sktlim@umich.edu iewExecLoadInsts 1712727Sktlim@umich.edu .init(cpu->number_of_threads) 1722727Sktlim@umich.edu .name(name() + ".EXEC:loads") 1732727Sktlim@umich.edu .desc("Number of load instructions executed") 1742727Sktlim@umich.edu .flags(total); 1752727Sktlim@umich.edu 1762727Sktlim@umich.edu iewExecSquashedInsts 1772727Sktlim@umich.edu .name(name() + ".EXEC:squashedInsts") 1782727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1792727Sktlim@umich.edu 1802727Sktlim@umich.edu iewExecutedSwp 1812301SN/A .init(cpu->number_of_threads) 1822301SN/A .name(name() + ".EXEC:swp") 1832301SN/A .desc("number of swp insts executed") 1842727Sktlim@umich.edu .flags(total); 1852301SN/A 1862727Sktlim@umich.edu iewExecutedNop 1872301SN/A .init(cpu->number_of_threads) 1882301SN/A .name(name() + ".EXEC:nop") 1892301SN/A .desc("number of nop insts executed") 1902727Sktlim@umich.edu .flags(total); 1912301SN/A 1922727Sktlim@umich.edu iewExecutedRefs 1932301SN/A .init(cpu->number_of_threads) 1942301SN/A .name(name() + ".EXEC:refs") 1952301SN/A .desc("number of memory reference insts executed") 1962727Sktlim@umich.edu .flags(total); 1972301SN/A 1982727Sktlim@umich.edu iewExecutedBranches 1992301SN/A .init(cpu->number_of_threads) 2002301SN/A .name(name() + ".EXEC:branches") 2012301SN/A .desc("Number of branches executed") 2022727Sktlim@umich.edu .flags(total); 2032301SN/A 2042301SN/A iewExecStoreInsts 2052301SN/A .name(name() + ".EXEC:stores") 2062301SN/A .desc("Number of stores executed") 2072727Sktlim@umich.edu .flags(total); 2082727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu iewExecRate 2112727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2122727Sktlim@umich.edu .desc("Inst execution rate") 2132727Sktlim@umich.edu .flags(total); 2142727Sktlim@umich.edu 2152727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2162301SN/A 2172301SN/A iewInstsToCommit 2182301SN/A .init(cpu->number_of_threads) 2192301SN/A .name(name() + ".WB:sent") 2202301SN/A .desc("cumulative count of insts sent to commit") 2212727Sktlim@umich.edu .flags(total); 2222301SN/A 2232326SN/A writebackCount 2242301SN/A .init(cpu->number_of_threads) 2252301SN/A .name(name() + ".WB:count") 2262301SN/A .desc("cumulative count of insts written-back") 2272727Sktlim@umich.edu .flags(total); 2282301SN/A 2292326SN/A producerInst 2302301SN/A .init(cpu->number_of_threads) 2312301SN/A .name(name() + ".WB:producers") 2322301SN/A .desc("num instructions producing a value") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352326SN/A consumerInst 2362301SN/A .init(cpu->number_of_threads) 2372301SN/A .name(name() + ".WB:consumers") 2382301SN/A .desc("num instructions consuming a value") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412326SN/A wbPenalized 2422301SN/A .init(cpu->number_of_threads) 2432301SN/A .name(name() + ".WB:penalized") 2442301SN/A .desc("number of instrctions required to write to 'other' IQ") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472326SN/A wbPenalizedRate 2482301SN/A .name(name() + ".WB:penalized_rate") 2492301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2502727Sktlim@umich.edu .flags(total); 2512301SN/A 2522326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2532301SN/A 2542326SN/A wbFanout 2552301SN/A .name(name() + ".WB:fanout") 2562301SN/A .desc("average fanout of values written-back") 2572727Sktlim@umich.edu .flags(total); 2582301SN/A 2592326SN/A wbFanout = producerInst / consumerInst; 2602301SN/A 2612326SN/A wbRate 2622301SN/A .name(name() + ".WB:rate") 2632301SN/A .desc("insts written-back per cycle") 2642727Sktlim@umich.edu .flags(total); 2652326SN/A wbRate = writebackCount / cpu->numCycles; 2661062SN/A} 2671062SN/A 2681681SN/Atemplate<class Impl> 2691060SN/Avoid 2702292SN/ADefaultIEW<Impl>::initStage() 2711060SN/A{ 2722292SN/A for (int tid=0; tid < numThreads; tid++) { 2732292SN/A toRename->iewInfo[tid].usedIQ = true; 2742292SN/A toRename->iewInfo[tid].freeIQEntries = 2752292SN/A instQueue.numFreeEntries(tid); 2762292SN/A 2772292SN/A toRename->iewInfo[tid].usedLSQ = true; 2782292SN/A toRename->iewInfo[tid].freeLSQEntries = 2792292SN/A ldstQueue.numFreeEntries(tid); 2802292SN/A } 2812292SN/A} 2822292SN/A 2832292SN/Atemplate<class Impl> 2842292SN/Avoid 2852733Sktlim@umich.eduDefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 2862292SN/A{ 2872292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 2881060SN/A cpu = cpu_ptr; 2891060SN/A 2901060SN/A instQueue.setCPU(cpu_ptr); 2911061SN/A ldstQueue.setCPU(cpu_ptr); 2922292SN/A 2932733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2941060SN/A} 2951060SN/A 2961681SN/Atemplate<class Impl> 2971060SN/Avoid 2982292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2991060SN/A{ 3002292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 3011060SN/A timeBuffer = tb_ptr; 3021060SN/A 3031060SN/A // Setup wire to read information from time buffer, from commit. 3041060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3051060SN/A 3061060SN/A // Setup wire to write information back to previous stages. 3071060SN/A toRename = timeBuffer->getWire(0); 3081060SN/A 3092292SN/A toFetch = timeBuffer->getWire(0); 3102292SN/A 3111060SN/A // Instruction queue also needs main time buffer. 3121060SN/A instQueue.setTimeBuffer(tb_ptr); 3131060SN/A} 3141060SN/A 3151681SN/Atemplate<class Impl> 3161060SN/Avoid 3172292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3181060SN/A{ 3192292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3201060SN/A renameQueue = rq_ptr; 3211060SN/A 3221060SN/A // Setup wire to read information from rename queue. 3231060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3241060SN/A} 3251060SN/A 3261681SN/Atemplate<class Impl> 3271060SN/Avoid 3282292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3291060SN/A{ 3302292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3311060SN/A iewQueue = iq_ptr; 3321060SN/A 3331060SN/A // Setup wire to write instructions to commit. 3341060SN/A toCommit = iewQueue->getWire(0); 3351060SN/A} 3361060SN/A 3371681SN/Atemplate<class Impl> 3381060SN/Avoid 3392292SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3401060SN/A{ 3412292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3422292SN/A activeThreads = at_ptr; 3432292SN/A 3442292SN/A ldstQueue.setActiveThreads(at_ptr); 3452292SN/A instQueue.setActiveThreads(at_ptr); 3461060SN/A} 3471060SN/A 3481681SN/Atemplate<class Impl> 3491060SN/Avoid 3502292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3511060SN/A{ 3522292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3532292SN/A scoreboard = sb_ptr; 3541060SN/A} 3551060SN/A 3562307SN/Atemplate <class Impl> 3572863Sktlim@umich.edubool 3582843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3592307SN/A{ 3602843Sktlim@umich.edu // IEW is ready to drain at any time. 3612843Sktlim@umich.edu cpu->signalDrained(); 3622863Sktlim@umich.edu return true; 3631681SN/A} 3641681SN/A 3652316SN/Atemplate <class Impl> 3661681SN/Avoid 3672843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3682843Sktlim@umich.edu{ 3692843Sktlim@umich.edu} 3702843Sktlim@umich.edu 3712843Sktlim@umich.edutemplate <class Impl> 3722843Sktlim@umich.eduvoid 3732843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3741681SN/A{ 3752348SN/A // Clear any state. 3762307SN/A switchedOut = true; 3771681SN/A 3782307SN/A instQueue.switchOut(); 3792307SN/A ldstQueue.switchOut(); 3802307SN/A fuPool->switchOut(); 3812307SN/A 3822307SN/A for (int i = 0; i < numThreads; i++) { 3832307SN/A while (!insts[i].empty()) 3842307SN/A insts[i].pop(); 3852307SN/A while (!skidBuffer[i].empty()) 3862307SN/A skidBuffer[i].pop(); 3872307SN/A } 3881681SN/A} 3891681SN/A 3902307SN/Atemplate <class Impl> 3911681SN/Avoid 3922307SN/ADefaultIEW<Impl>::takeOverFrom() 3931060SN/A{ 3942348SN/A // Reset all state. 3952307SN/A _status = Active; 3962307SN/A exeStatus = Running; 3972307SN/A wbStatus = Idle; 3982307SN/A switchedOut = false; 3991060SN/A 4002307SN/A instQueue.takeOverFrom(); 4012307SN/A ldstQueue.takeOverFrom(); 4022307SN/A fuPool->takeOverFrom(); 4031060SN/A 4042307SN/A initStage(); 4052307SN/A cpu->activityThisCycle(); 4061060SN/A 4072307SN/A for (int i=0; i < numThreads; i++) { 4082307SN/A dispatchStatus[i] = Running; 4092307SN/A stalls[i].commit = false; 4102307SN/A fetchRedirect[i] = false; 4112307SN/A } 4121060SN/A 4132307SN/A updateLSQNextCycle = false; 4142307SN/A 4152307SN/A // @todo: Fix hardcoded number 4162873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4172307SN/A issueToExecQueue.advance(); 4181060SN/A } 4191060SN/A} 4201060SN/A 4211681SN/Atemplate<class Impl> 4221060SN/Avoid 4232292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4242107SN/A{ 4252292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4262292SN/A tid); 4272107SN/A 4282292SN/A // Tell the IQ to start squashing. 4292292SN/A instQueue.squash(tid); 4302107SN/A 4312292SN/A // Tell the LDSTQ to start squashing. 4322935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 4332326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4342935Sksewell@umich.edu#else 4352935Sksewell@umich.edu ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid); 4362935Sksewell@umich.edu#endif 4372292SN/A updatedQueues = true; 4382107SN/A 4392292SN/A // Clear the skid buffer in case it has any data in it. 4402935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4412935Sksewell@umich.edu tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum); 4422935Sksewell@umich.edu 4432292SN/A while (!skidBuffer[tid].empty()) { 4442935Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 4452935Sksewell@umich.edu if (skidBuffer[tid].front()->seqNum <= 4462935Sksewell@umich.edu fromCommit->commitInfo[tid].bdelayDoneSeqNum) { 4472935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions " 4482935Sksewell@umich.edu "that occur before delay slot [sn:%i].\n", 4492935Sksewell@umich.edu fromCommit->commitInfo[tid].bdelayDoneSeqNum, 4502935Sksewell@umich.edu tid); 4512935Sksewell@umich.edu break; 4522935Sksewell@umich.edu } else { 4532935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from " 4542935Sksewell@umich.edu "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum); 4552935Sksewell@umich.edu } 4562935Sksewell@umich.edu#endif 4572292SN/A if (skidBuffer[tid].front()->isLoad() || 4582292SN/A skidBuffer[tid].front()->isStore() ) { 4592292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4602292SN/A } 4612107SN/A 4622292SN/A toRename->iewInfo[tid].dispatched++; 4632107SN/A 4642292SN/A skidBuffer[tid].pop(); 4652292SN/A } 4662107SN/A 4672935Sksewell@umich.edu bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 4682935Sksewell@umich.edu 4692702Sktlim@umich.edu emptyRenameInsts(tid); 4702107SN/A} 4712107SN/A 4722107SN/Atemplate<class Impl> 4732107SN/Avoid 4742292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4752292SN/A{ 4762292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4772292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4782292SN/A 4792292SN/A toCommit->squash[tid] = true; 4802292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4812292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4822292SN/A toCommit->branchMispredict[tid] = true; 4832935Sksewell@umich.edu 4842935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 4852292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4862292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4872935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4882935Sksewell@umich.edu#else 4892935Sksewell@umich.edu bool branch_taken = inst->readNextNPC() != 4902935Sksewell@umich.edu (inst->readNextPC() + sizeof(TheISA::MachInst)); 4912935Sksewell@umich.edu 4922935Sksewell@umich.edu toCommit->branchTaken[tid] = branch_taken; 4932935Sksewell@umich.edu 4942935Sksewell@umich.edu toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot(); 4952935Sksewell@umich.edu 4962935Sksewell@umich.edu if (inst->isCondDelaySlot() && branch_taken) { 4972935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4982935Sksewell@umich.edu } else { 4992935Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextNPC(); 5002935Sksewell@umich.edu } 5012935Sksewell@umich.edu#endif 5022292SN/A 5032292SN/A toCommit->includeSquashInst[tid] = false; 5042292SN/A 5052292SN/A wroteToTimeBuffer = true; 5062292SN/A} 5072292SN/A 5082292SN/Atemplate<class Impl> 5092292SN/Avoid 5102292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 5112292SN/A{ 5122292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 5132292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5142292SN/A 5152292SN/A toCommit->squash[tid] = true; 5162292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5172292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 5182292SN/A 5192292SN/A toCommit->includeSquashInst[tid] = false; 5202292SN/A 5212292SN/A wroteToTimeBuffer = true; 5222292SN/A} 5232292SN/A 5242292SN/Atemplate<class Impl> 5252292SN/Avoid 5262292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5272292SN/A{ 5282292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5292292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5302292SN/A 5312292SN/A toCommit->squash[tid] = true; 5322292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5332292SN/A toCommit->nextPC[tid] = inst->readPC(); 5342292SN/A 5352348SN/A // Must include the broadcasted SN in the squash. 5362292SN/A toCommit->includeSquashInst[tid] = true; 5372292SN/A 5382292SN/A ldstQueue.setLoadBlockedHandled(tid); 5392292SN/A 5402292SN/A wroteToTimeBuffer = true; 5412292SN/A} 5422292SN/A 5432292SN/Atemplate<class Impl> 5442292SN/Avoid 5452292SN/ADefaultIEW<Impl>::block(unsigned tid) 5462292SN/A{ 5472292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5482292SN/A 5492292SN/A if (dispatchStatus[tid] != Blocked && 5502292SN/A dispatchStatus[tid] != Unblocking) { 5512292SN/A toRename->iewBlock[tid] = true; 5522292SN/A wroteToTimeBuffer = true; 5532292SN/A } 5542292SN/A 5552292SN/A // Add the current inputs to the skid buffer so they can be 5562292SN/A // reprocessed when this stage unblocks. 5572292SN/A skidInsert(tid); 5582292SN/A 5592292SN/A dispatchStatus[tid] = Blocked; 5602292SN/A} 5612292SN/A 5622292SN/Atemplate<class Impl> 5632292SN/Avoid 5642292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5652292SN/A{ 5662292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5672292SN/A "buffer %u.\n",tid, tid); 5682292SN/A 5692292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5702292SN/A // Also switch status to running. 5712292SN/A if (skidBuffer[tid].empty()) { 5722292SN/A toRename->iewUnblock[tid] = true; 5732292SN/A wroteToTimeBuffer = true; 5742292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5752292SN/A dispatchStatus[tid] = Running; 5762292SN/A } 5772292SN/A} 5782292SN/A 5792292SN/Atemplate<class Impl> 5802292SN/Avoid 5812292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5821060SN/A{ 5831681SN/A instQueue.wakeDependents(inst); 5841060SN/A} 5851060SN/A 5862292SN/Atemplate<class Impl> 5872292SN/Avoid 5882292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5892292SN/A{ 5902292SN/A instQueue.rescheduleMemInst(inst); 5912292SN/A} 5921681SN/A 5931681SN/Atemplate<class Impl> 5941060SN/Avoid 5952292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5961060SN/A{ 5972292SN/A instQueue.replayMemInst(inst); 5982292SN/A} 5991060SN/A 6002292SN/Atemplate<class Impl> 6012292SN/Avoid 6022292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6032292SN/A{ 6042292SN/A // First check the time slot that this instruction will write 6052292SN/A // to. If there are free write ports at the time, then go ahead 6062292SN/A // and write the instruction to that time. If there are not, 6072292SN/A // keep looking back to see where's the first time there's a 6082326SN/A // free slot. 6092292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6102292SN/A ++wbNumInst; 6112820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6122292SN/A ++wbCycle; 6132292SN/A wbNumInst = 0; 6142292SN/A } 6152292SN/A 6162820Sktlim@umich.edu assert((wbCycle * wbWidth + wbNumInst) < wbMax); 6172292SN/A } 6182292SN/A 6192292SN/A // Add finished instruction to queue to commit. 6202292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6212292SN/A (*iewQueue)[wbCycle].size++; 6222292SN/A} 6232292SN/A 6242292SN/Atemplate <class Impl> 6252292SN/Aunsigned 6262292SN/ADefaultIEW<Impl>::validInstsFromRename() 6272292SN/A{ 6282292SN/A unsigned inst_count = 0; 6292292SN/A 6302292SN/A for (int i=0; i<fromRename->size; i++) { 6312731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6322292SN/A inst_count++; 6332292SN/A } 6342292SN/A 6352292SN/A return inst_count; 6362292SN/A} 6372292SN/A 6382292SN/Atemplate<class Impl> 6392292SN/Avoid 6402292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6412292SN/A{ 6422292SN/A DynInstPtr inst = NULL; 6432292SN/A 6442292SN/A while (!insts[tid].empty()) { 6452292SN/A inst = insts[tid].front(); 6462292SN/A 6472292SN/A insts[tid].pop(); 6482292SN/A 6492292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6502292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6512292SN/A inst->readPC(),tid); 6522292SN/A 6532292SN/A skidBuffer[tid].push(inst); 6542292SN/A } 6552292SN/A 6562292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6572292SN/A "Skidbuffer Exceeded Max Size"); 6582292SN/A} 6592292SN/A 6602292SN/Atemplate<class Impl> 6612292SN/Aint 6622292SN/ADefaultIEW<Impl>::skidCount() 6632292SN/A{ 6642292SN/A int max=0; 6652292SN/A 6662292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6672292SN/A 6682292SN/A while (threads != (*activeThreads).end()) { 6692292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6702292SN/A if (max < thread_count) 6712292SN/A max = thread_count; 6722292SN/A } 6732292SN/A 6742292SN/A return max; 6752292SN/A} 6762292SN/A 6772292SN/Atemplate<class Impl> 6782292SN/Abool 6792292SN/ADefaultIEW<Impl>::skidsEmpty() 6802292SN/A{ 6812292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6822292SN/A 6832292SN/A while (threads != (*activeThreads).end()) { 6842292SN/A if (!skidBuffer[*threads++].empty()) 6852292SN/A return false; 6862292SN/A } 6872292SN/A 6882292SN/A return true; 6891062SN/A} 6901062SN/A 6911681SN/Atemplate <class Impl> 6921062SN/Avoid 6932292SN/ADefaultIEW<Impl>::updateStatus() 6941062SN/A{ 6952292SN/A bool any_unblocking = false; 6961062SN/A 6972292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6981062SN/A 6992292SN/A threads = (*activeThreads).begin(); 7001062SN/A 7012292SN/A while (threads != (*activeThreads).end()) { 7022292SN/A unsigned tid = *threads++; 7031062SN/A 7042292SN/A if (dispatchStatus[tid] == Unblocking) { 7052292SN/A any_unblocking = true; 7062292SN/A break; 7072292SN/A } 7082292SN/A } 7091062SN/A 7102292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7112292SN/A // and there's no stores waiting to write back, and dispatch is not 7122292SN/A // unblocking, then there is no internal activity for the IEW stage. 7132292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7142292SN/A !ldstQueue.willWB() && !any_unblocking) { 7152292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7161062SN/A 7172292SN/A deactivateStage(); 7181062SN/A 7192292SN/A _status = Inactive; 7202292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7212292SN/A ldstQueue.willWB() || 7222292SN/A any_unblocking)) { 7232292SN/A // Otherwise there is internal activity. Set to active. 7242292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7251062SN/A 7262292SN/A activateStage(); 7271062SN/A 7282292SN/A _status = Active; 7291062SN/A } 7301062SN/A} 7311062SN/A 7321681SN/Atemplate <class Impl> 7331062SN/Avoid 7342292SN/ADefaultIEW<Impl>::resetEntries() 7351062SN/A{ 7362292SN/A instQueue.resetEntries(); 7372292SN/A ldstQueue.resetEntries(); 7382292SN/A} 7391062SN/A 7402292SN/Atemplate <class Impl> 7412292SN/Avoid 7422292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7432292SN/A{ 7442292SN/A if (fromCommit->commitBlock[tid]) { 7452292SN/A stalls[tid].commit = true; 7462292SN/A } 7471062SN/A 7482292SN/A if (fromCommit->commitUnblock[tid]) { 7492292SN/A assert(stalls[tid].commit); 7502292SN/A stalls[tid].commit = false; 7512292SN/A } 7522292SN/A} 7532292SN/A 7542292SN/Atemplate <class Impl> 7552292SN/Abool 7562292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7572292SN/A{ 7582292SN/A bool ret_val(false); 7592292SN/A 7602292SN/A if (stalls[tid].commit) { 7612292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7622292SN/A ret_val = true; 7632292SN/A } else if (instQueue.isFull(tid)) { 7642292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7652292SN/A ret_val = true; 7662292SN/A } else if (ldstQueue.isFull(tid)) { 7672292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7682292SN/A 7692292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7702292SN/A 7712292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7722292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7732292SN/A } 7742292SN/A 7752292SN/A if (ldstQueue.numStores(tid) > 0) { 7762292SN/A 7772292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7782292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7792292SN/A } 7802292SN/A 7812292SN/A ret_val = true; 7822292SN/A } else if (ldstQueue.isStalled(tid)) { 7832292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7842292SN/A ret_val = true; 7852292SN/A } 7862292SN/A 7872292SN/A return ret_val; 7882292SN/A} 7892292SN/A 7902292SN/Atemplate <class Impl> 7912292SN/Avoid 7922292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7932292SN/A{ 7942292SN/A // Check if there's a squash signal, squash if there is 7952292SN/A // Check stall signals, block if there is. 7962292SN/A // If status was Blocked 7972292SN/A // if so then go to unblocking 7982292SN/A // If status was Squashing 7992292SN/A // check if squashing is not high. Switch to running this cycle. 8002292SN/A 8012292SN/A readStallSignals(tid); 8022292SN/A 8032292SN/A if (fromCommit->commitInfo[tid].squash) { 8042292SN/A squash(tid); 8052292SN/A 8062292SN/A if (dispatchStatus[tid] == Blocked || 8072292SN/A dispatchStatus[tid] == Unblocking) { 8082292SN/A toRename->iewUnblock[tid] = true; 8092292SN/A wroteToTimeBuffer = true; 8102292SN/A } 8112292SN/A 8122292SN/A dispatchStatus[tid] = Squashing; 8132292SN/A 8142292SN/A fetchRedirect[tid] = false; 8152292SN/A return; 8162292SN/A } 8172292SN/A 8182292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8192702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8202292SN/A 8212292SN/A dispatchStatus[tid] = Squashing; 8222292SN/A 8232702Sktlim@umich.edu emptyRenameInsts(tid); 8242702Sktlim@umich.edu wroteToTimeBuffer = true; 8252292SN/A return; 8262292SN/A } 8272292SN/A 8282292SN/A if (checkStall(tid)) { 8292292SN/A block(tid); 8302292SN/A dispatchStatus[tid] = Blocked; 8312292SN/A return; 8322292SN/A } 8332292SN/A 8342292SN/A if (dispatchStatus[tid] == Blocked) { 8352292SN/A // Status from previous cycle was blocked, but there are no more stall 8362292SN/A // conditions. Switch over to unblocking. 8372292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8382292SN/A tid); 8392292SN/A 8402292SN/A dispatchStatus[tid] = Unblocking; 8412292SN/A 8422292SN/A unblock(tid); 8432292SN/A 8442292SN/A return; 8452292SN/A } 8462292SN/A 8472292SN/A if (dispatchStatus[tid] == Squashing) { 8482292SN/A // Switch status to running if rename isn't being told to block or 8492292SN/A // squash this cycle. 8502292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8512292SN/A tid); 8522292SN/A 8532292SN/A dispatchStatus[tid] = Running; 8542292SN/A 8552292SN/A return; 8562292SN/A } 8572292SN/A} 8582292SN/A 8592292SN/Atemplate <class Impl> 8602292SN/Avoid 8612292SN/ADefaultIEW<Impl>::sortInsts() 8622292SN/A{ 8632292SN/A int insts_from_rename = fromRename->size; 8642326SN/A#ifdef DEBUG 8652935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 8662292SN/A for (int i = 0; i < numThreads; i++) 8672292SN/A assert(insts[i].empty()); 8682326SN/A#endif 8692935Sksewell@umich.edu#endif 8702292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8712292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8722292SN/A } 8732292SN/A} 8742292SN/A 8752292SN/Atemplate <class Impl> 8762292SN/Avoid 8772702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8782702Sktlim@umich.edu{ 8792935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until " 8802935Sksewell@umich.edu "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]); 8812935Sksewell@umich.edu 8822702Sktlim@umich.edu while (!insts[tid].empty()) { 8832935Sksewell@umich.edu 8842935Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 8852935Sksewell@umich.edu if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) { 8862935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction" 8872935Sksewell@umich.edu " that occurs at or before delay slot [sn:%i].\n", 8882935Sksewell@umich.edu tid, bdelayDoneSeqNum[tid]); 8892935Sksewell@umich.edu break; 8902935Sksewell@umich.edu } else { 8912935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction " 8922935Sksewell@umich.edu "[sn:%i].\n", tid, insts[tid].front()->seqNum); 8932935Sksewell@umich.edu } 8942935Sksewell@umich.edu#endif 8952935Sksewell@umich.edu 8962702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8972702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8982702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8992702Sktlim@umich.edu } 9002702Sktlim@umich.edu 9012702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 9022702Sktlim@umich.edu 9032702Sktlim@umich.edu insts[tid].pop(); 9042702Sktlim@umich.edu } 9052702Sktlim@umich.edu} 9062702Sktlim@umich.edu 9072702Sktlim@umich.edutemplate <class Impl> 9082702Sktlim@umich.eduvoid 9092292SN/ADefaultIEW<Impl>::wakeCPU() 9102292SN/A{ 9112292SN/A cpu->wakeCPU(); 9122292SN/A} 9132292SN/A 9142292SN/Atemplate <class Impl> 9152292SN/Avoid 9162292SN/ADefaultIEW<Impl>::activityThisCycle() 9172292SN/A{ 9182292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9192292SN/A cpu->activityThisCycle(); 9202292SN/A} 9212292SN/A 9222292SN/Atemplate <class Impl> 9232292SN/Ainline void 9242292SN/ADefaultIEW<Impl>::activateStage() 9252292SN/A{ 9262292SN/A DPRINTF(Activity, "Activating stage.\n"); 9272733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9282292SN/A} 9292292SN/A 9302292SN/Atemplate <class Impl> 9312292SN/Ainline void 9322292SN/ADefaultIEW<Impl>::deactivateStage() 9332292SN/A{ 9342292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9352733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9362292SN/A} 9372292SN/A 9382292SN/Atemplate<class Impl> 9392292SN/Avoid 9402292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 9412292SN/A{ 9422292SN/A // If status is Running or idle, 9432292SN/A // call dispatchInsts() 9442292SN/A // If status is Unblocking, 9452292SN/A // buffer any instructions coming from rename 9462292SN/A // continue trying to empty skid buffer 9472292SN/A // check if stall conditions have passed 9482292SN/A 9492292SN/A if (dispatchStatus[tid] == Blocked) { 9502292SN/A ++iewBlockCycles; 9512292SN/A 9522292SN/A } else if (dispatchStatus[tid] == Squashing) { 9532292SN/A ++iewSquashCycles; 9542292SN/A } 9552292SN/A 9562292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9572292SN/A // will allow, as long as it is not currently blocked. 9582292SN/A if (dispatchStatus[tid] == Running || 9592292SN/A dispatchStatus[tid] == Idle) { 9602292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9612292SN/A "dispatch.\n", tid); 9622292SN/A 9632292SN/A dispatchInsts(tid); 9642292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9652292SN/A // Make sure that the skid buffer has something in it if the 9662292SN/A // status is unblocking. 9672292SN/A assert(!skidsEmpty()); 9682292SN/A 9692292SN/A // If the status was unblocking, then instructions from the skid 9702292SN/A // buffer were used. Remove those instructions and handle 9712292SN/A // the rest of unblocking. 9722292SN/A dispatchInsts(tid); 9732292SN/A 9742292SN/A ++iewUnblockCycles; 9752292SN/A 9762292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9772292SN/A // Add the current inputs to the skid buffer so they can be 9782292SN/A // reprocessed when this stage unblocks. 9792292SN/A skidInsert(tid); 9802292SN/A } 9812292SN/A 9822292SN/A unblock(tid); 9832292SN/A } 9842292SN/A} 9852292SN/A 9862292SN/Atemplate <class Impl> 9872292SN/Avoid 9882292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9892292SN/A{ 9902292SN/A dispatchedAllInsts = true; 9912292SN/A 9922292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9932292SN/A // otherwise. 9942292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9952292SN/A dispatchStatus[tid] == Unblocking ? 9962292SN/A skidBuffer[tid] : insts[tid]; 9972292SN/A 9982292SN/A int insts_to_add = insts_to_dispatch.size(); 9992292SN/A 10002292SN/A DynInstPtr inst; 10012292SN/A bool add_to_iq = false; 10022292SN/A int dis_num_inst = 0; 10032292SN/A 10042292SN/A // Loop through the instructions, putting them in the instruction 10052292SN/A // queue. 10062292SN/A for ( ; dis_num_inst < insts_to_add && 10072820Sktlim@umich.edu dis_num_inst < dispatchWidth; 10082292SN/A ++dis_num_inst) 10092292SN/A { 10102292SN/A inst = insts_to_dispatch.front(); 10112292SN/A 10122292SN/A if (dispatchStatus[tid] == Unblocking) { 10132292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10142292SN/A "buffer\n", tid); 10152292SN/A } 10162292SN/A 10172292SN/A // Make sure there's a valid instruction there. 10182292SN/A assert(inst); 10192292SN/A 10202292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 10212292SN/A "IQ.\n", 10222292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 10232292SN/A 10242292SN/A // Be sure to mark these instructions as ready so that the 10252292SN/A // commit stage can go ahead and execute them, and mark 10262292SN/A // them as issued so the IQ doesn't reprocess them. 10272292SN/A 10282292SN/A // Check for squashed instructions. 10292292SN/A if (inst->isSquashed()) { 10302292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10312292SN/A "not adding to IQ.\n", tid); 10322292SN/A 10332292SN/A ++iewDispSquashedInsts; 10342292SN/A 10352292SN/A insts_to_dispatch.pop(); 10362292SN/A 10372292SN/A //Tell Rename That An Instruction has been processed 10382292SN/A if (inst->isLoad() || inst->isStore()) { 10392292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10402292SN/A } 10412292SN/A toRename->iewInfo[tid].dispatched++; 10422292SN/A 10432292SN/A continue; 10442292SN/A } 10452292SN/A 10462292SN/A // Check for full conditions. 10472292SN/A if (instQueue.isFull(tid)) { 10482292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10492292SN/A 10502292SN/A // Call function to start blocking. 10512292SN/A block(tid); 10522292SN/A 10532292SN/A // Set unblock to false. Special case where we are using 10542292SN/A // skidbuffer (unblocking) instructions but then we still 10552292SN/A // get full in the IQ. 10562292SN/A toRename->iewUnblock[tid] = false; 10572292SN/A 10582292SN/A dispatchedAllInsts = false; 10592292SN/A 10602292SN/A ++iewIQFullEvents; 10612292SN/A break; 10622292SN/A } else if (ldstQueue.isFull(tid)) { 10632292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10642292SN/A 10652292SN/A // Call function to start blocking. 10662292SN/A block(tid); 10672292SN/A 10682292SN/A // Set unblock to false. Special case where we are using 10692292SN/A // skidbuffer (unblocking) instructions but then we still 10702292SN/A // get full in the IQ. 10712292SN/A toRename->iewUnblock[tid] = false; 10722292SN/A 10732292SN/A dispatchedAllInsts = false; 10742292SN/A 10752292SN/A ++iewLSQFullEvents; 10762292SN/A break; 10772292SN/A } 10782292SN/A 10792292SN/A // Otherwise issue the instruction just fine. 10802292SN/A if (inst->isLoad()) { 10812292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10822292SN/A "encountered, adding to LSQ.\n", tid); 10832292SN/A 10842292SN/A // Reserve a spot in the load store queue for this 10852292SN/A // memory access. 10862292SN/A ldstQueue.insertLoad(inst); 10872292SN/A 10882292SN/A ++iewDispLoadInsts; 10892292SN/A 10902292SN/A add_to_iq = true; 10912292SN/A 10922292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10932292SN/A } else if (inst->isStore()) { 10942292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10952292SN/A "encountered, adding to LSQ.\n", tid); 10962292SN/A 10972292SN/A ldstQueue.insertStore(inst); 10982292SN/A 10992292SN/A ++iewDispStoreInsts; 11002292SN/A 11012336SN/A if (inst->isStoreConditional()) { 11022336SN/A // Store conditionals need to be set as "canCommit()" 11032336SN/A // so that commit can process them when they reach the 11042336SN/A // head of commit. 11052348SN/A // @todo: This is somewhat specific to Alpha. 11062292SN/A inst->setCanCommit(); 11072292SN/A instQueue.insertNonSpec(inst); 11082292SN/A add_to_iq = false; 11092292SN/A 11102292SN/A ++iewDispNonSpecInsts; 11112292SN/A } else { 11122292SN/A add_to_iq = true; 11132292SN/A } 11142292SN/A 11152292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11162292SN/A#if FULL_SYSTEM 11172292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11182326SN/A // Same as non-speculative stores. 11192292SN/A inst->setCanCommit(); 11202292SN/A instQueue.insertBarrier(inst); 11212292SN/A add_to_iq = false; 11222292SN/A#endif 11232292SN/A } else if (inst->isNonSpeculative()) { 11242292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11252292SN/A "encountered, skipping.\n", tid); 11262292SN/A 11272326SN/A // Same as non-speculative stores. 11282292SN/A inst->setCanCommit(); 11292292SN/A 11302292SN/A // Specifically insert it as nonspeculative. 11312292SN/A instQueue.insertNonSpec(inst); 11322292SN/A 11332292SN/A ++iewDispNonSpecInsts; 11342292SN/A 11352292SN/A add_to_iq = false; 11362292SN/A } else if (inst->isNop()) { 11372292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11382292SN/A "skipping.\n", tid); 11392292SN/A 11402292SN/A inst->setIssued(); 11412292SN/A inst->setExecuted(); 11422292SN/A inst->setCanCommit(); 11432292SN/A 11442326SN/A instQueue.recordProducer(inst); 11452292SN/A 11462727Sktlim@umich.edu iewExecutedNop[tid]++; 11472301SN/A 11482292SN/A add_to_iq = false; 11492292SN/A } else if (inst->isExecuted()) { 11502292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11512292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11522292SN/A "skipping.\n"); 11532292SN/A 11542292SN/A inst->setIssued(); 11552292SN/A inst->setCanCommit(); 11562292SN/A 11572326SN/A instQueue.recordProducer(inst); 11582292SN/A 11592292SN/A add_to_iq = false; 11602292SN/A } else { 11612292SN/A add_to_iq = true; 11622292SN/A } 11632292SN/A 11642292SN/A // If the instruction queue is not full, then add the 11652292SN/A // instruction. 11662292SN/A if (add_to_iq) { 11672292SN/A instQueue.insert(inst); 11682292SN/A } 11692292SN/A 11702292SN/A insts_to_dispatch.pop(); 11712292SN/A 11722292SN/A toRename->iewInfo[tid].dispatched++; 11732292SN/A 11742292SN/A ++iewDispatchedInsts; 11752292SN/A } 11762292SN/A 11772292SN/A if (!insts_to_dispatch.empty()) { 11782935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11792292SN/A block(tid); 11802292SN/A toRename->iewUnblock[tid] = false; 11812292SN/A } 11822292SN/A 11832292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11842292SN/A dispatchStatus[tid] = Running; 11852292SN/A 11862292SN/A updatedQueues = true; 11872292SN/A } 11882292SN/A 11892292SN/A dis_num_inst = 0; 11902292SN/A} 11912292SN/A 11922292SN/Atemplate <class Impl> 11932292SN/Avoid 11942292SN/ADefaultIEW<Impl>::printAvailableInsts() 11952292SN/A{ 11962292SN/A int inst = 0; 11972292SN/A 11982292SN/A cout << "Available Instructions: "; 11992292SN/A 12002292SN/A while (fromIssue->insts[inst]) { 12012292SN/A 12022292SN/A if (inst%3==0) cout << "\n\t"; 12032292SN/A 12042292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 12052292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12062292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12072292SN/A 12082292SN/A inst++; 12092292SN/A 12102292SN/A } 12112292SN/A 12122292SN/A cout << "\n"; 12132292SN/A} 12142292SN/A 12152292SN/Atemplate <class Impl> 12162292SN/Avoid 12172292SN/ADefaultIEW<Impl>::executeInsts() 12182292SN/A{ 12192292SN/A wbNumInst = 0; 12202292SN/A wbCycle = 0; 12212292SN/A 12222292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12232292SN/A 12242292SN/A while (threads != (*activeThreads).end()) { 12252292SN/A unsigned tid = *threads++; 12262292SN/A fetchRedirect[tid] = false; 12272292SN/A } 12282292SN/A 12292698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12302698Sktlim@umich.edu// printAvailableInsts(); 12311062SN/A 12321062SN/A // Execute/writeback any instructions that are available. 12332333SN/A int insts_to_execute = fromIssue->size; 12342292SN/A int inst_num = 0; 12352333SN/A for (; inst_num < insts_to_execute; 12362326SN/A ++inst_num) { 12371062SN/A 12382292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12391062SN/A 12402333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12411062SN/A 12422292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 12432292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 12441062SN/A 12451062SN/A // Check if the instruction is squashed; if so then skip it 12461062SN/A if (inst->isSquashed()) { 12472292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12481062SN/A 12491062SN/A // Consider this instruction executed so that commit can go 12501062SN/A // ahead and retire the instruction. 12511062SN/A inst->setExecuted(); 12521062SN/A 12532292SN/A // Not sure if I should set this here or just let commit try to 12542292SN/A // commit any squashed instructions. I like the latter a bit more. 12552292SN/A inst->setCanCommit(); 12561062SN/A 12571062SN/A ++iewExecSquashedInsts; 12581062SN/A 12592820Sktlim@umich.edu decrWb(inst->seqNum); 12601062SN/A continue; 12611062SN/A } 12621062SN/A 12632292SN/A Fault fault = NoFault; 12641062SN/A 12651062SN/A // Execute instruction. 12661062SN/A // Note that if the instruction faults, it will be handled 12671062SN/A // at the commit stage. 12682292SN/A if (inst->isMemRef() && 12692292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12702292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12711062SN/A "reference.\n"); 12721062SN/A 12731062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12741062SN/A if (inst->isLoad()) { 12752292SN/A // Loads will mark themselves as executed, and their writeback 12762292SN/A // event adds the instruction to the queue to commit 12772292SN/A fault = ldstQueue.executeLoad(inst); 12781062SN/A } else if (inst->isStore()) { 12791681SN/A ldstQueue.executeStore(inst); 12801062SN/A 12812292SN/A // If the store had a fault then it may not have a mem req 12822669Sktlim@umich.edu if (inst->req && !(inst->req->getFlags() & LOCKED)) { 12832292SN/A inst->setExecuted(); 12842292SN/A 12852292SN/A instToCommit(inst); 12862292SN/A } 12872326SN/A 12882326SN/A // Store conditionals will mark themselves as 12892326SN/A // executed, and their writeback event will add the 12902326SN/A // instruction to the queue to commit. 12911062SN/A } else { 12922292SN/A panic("Unexpected memory type!\n"); 12931062SN/A } 12941062SN/A 12951062SN/A } else { 12961062SN/A inst->execute(); 12971062SN/A 12982292SN/A inst->setExecuted(); 12992292SN/A 13002292SN/A instToCommit(inst); 13011062SN/A } 13021062SN/A 13032301SN/A updateExeInstStats(inst); 13041681SN/A 13052326SN/A // Check if branch prediction was correct, if not then we need 13062326SN/A // to tell commit to squash in flight instructions. Only 13072326SN/A // handle this if there hasn't already been something that 13082107SN/A // redirects fetch in this group of instructions. 13091681SN/A 13102292SN/A // This probably needs to prioritize the redirects if a different 13112292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13122292SN/A // instruction first, so the branch resolution order will be correct. 13132292SN/A unsigned tid = inst->threadNumber; 13141062SN/A 13152292SN/A if (!fetchRedirect[tid]) { 13161062SN/A 13171062SN/A if (inst->mispredicted()) { 13182292SN/A fetchRedirect[tid] = true; 13191062SN/A 13202292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13212935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 13222292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 13231062SN/A inst->nextPC); 13242935Sksewell@umich.edu#else 13252935Sksewell@umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 13262935Sksewell@umich.edu inst->nextNPC); 13272935Sksewell@umich.edu#endif 13281062SN/A // If incorrect, then signal the ROB that it must be squashed. 13292292SN/A squashDueToBranch(inst, tid); 13301062SN/A 13311062SN/A if (inst->predTaken()) { 13321062SN/A predictedTakenIncorrect++; 13332292SN/A } else { 13342292SN/A predictedNotTakenIncorrect++; 13351062SN/A } 13362292SN/A } else if (ldstQueue.violation(tid)) { 13372292SN/A fetchRedirect[tid] = true; 13381062SN/A 13392326SN/A // If there was an ordering violation, then get the 13402326SN/A // DynInst that caused the violation. Note that this 13412292SN/A // clears the violation signal. 13422292SN/A DynInstPtr violator; 13432292SN/A violator = ldstQueue.getMemDepViolator(tid); 13441062SN/A 13452292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13461062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13471062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13481062SN/A 13491062SN/A // Tell the instruction queue that a violation has occured. 13501062SN/A instQueue.violation(inst, violator); 13511062SN/A 13521062SN/A // Squash. 13532292SN/A squashDueToMemOrder(inst,tid); 13541062SN/A 13551062SN/A ++memOrderViolationEvents; 13562292SN/A } else if (ldstQueue.loadBlocked(tid) && 13572292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13582292SN/A fetchRedirect[tid] = true; 13592292SN/A 13602292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13612292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13622292SN/A inst->readPC(), inst->seqNum); 13632292SN/A 13642292SN/A squashDueToMemBlocked(inst, tid); 13651062SN/A } 13661062SN/A } 13671062SN/A } 13682292SN/A 13692348SN/A // Update and record activity if we processed any instructions. 13702292SN/A if (inst_num) { 13712292SN/A if (exeStatus == Idle) { 13722292SN/A exeStatus = Running; 13732292SN/A } 13742292SN/A 13752292SN/A updatedQueues = true; 13762292SN/A 13772292SN/A cpu->activityThisCycle(); 13782292SN/A } 13792292SN/A 13802292SN/A // Need to reset this in case a writeback event needs to write into the 13812292SN/A // iew queue. That way the writeback event will write into the correct 13822292SN/A // spot in the queue. 13832292SN/A wbNumInst = 0; 13842107SN/A} 13852107SN/A 13862292SN/Atemplate <class Impl> 13872107SN/Avoid 13882292SN/ADefaultIEW<Impl>::writebackInsts() 13892107SN/A{ 13902326SN/A // Loop through the head of the time buffer and wake any 13912326SN/A // dependents. These instructions are about to write back. Also 13922326SN/A // mark scoreboard that this instruction is finally complete. 13932326SN/A // Either have IEW have direct access to scoreboard, or have this 13942326SN/A // as part of backwards communication. 13952107SN/A for (int inst_num = 0; inst_num < issueWidth && 13962292SN/A toCommit->insts[inst_num]; inst_num++) { 13972107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13982301SN/A int tid = inst->threadNumber; 13992107SN/A 14002698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 14012698Sktlim@umich.edu inst->seqNum, inst->readPC()); 14022107SN/A 14032301SN/A iewInstsToCommit[tid]++; 14042301SN/A 14052292SN/A // Some instructions will be sent to commit without having 14062292SN/A // executed because they need commit to handle them. 14072292SN/A // E.g. Uncached loads have not actually executed when they 14082292SN/A // are first sent to commit. Instead commit must tell the LSQ 14092292SN/A // when it's ready to execute the uncached load. 14102292SN/A if (!inst->isSquashed() && inst->isExecuted()) { 14112301SN/A int dependents = instQueue.wakeDependents(inst); 14122107SN/A 14132292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14142292SN/A //mark as Ready 14152292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14162292SN/A inst->renamedDestRegIdx(i)); 14172292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14182107SN/A } 14192301SN/A 14202348SN/A if (dependents) { 14212348SN/A producerInst[tid]++; 14222348SN/A consumerInst[tid]+= dependents; 14232348SN/A } 14242326SN/A writebackCount[tid]++; 14252107SN/A } 14262820Sktlim@umich.edu 14272820Sktlim@umich.edu decrWb(inst->seqNum); 14282107SN/A } 14291060SN/A} 14301060SN/A 14311681SN/Atemplate<class Impl> 14321060SN/Avoid 14332292SN/ADefaultIEW<Impl>::tick() 14341060SN/A{ 14352292SN/A wbNumInst = 0; 14362292SN/A wbCycle = 0; 14371060SN/A 14382292SN/A wroteToTimeBuffer = false; 14392292SN/A updatedQueues = false; 14401060SN/A 14412292SN/A sortInsts(); 14421060SN/A 14432326SN/A // Free function units marked as being freed this cycle. 14442326SN/A fuPool->processFreeUnits(); 14451062SN/A 14462292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 14471060SN/A 14482326SN/A // Check stall and squash signals, dispatch any instructions. 14492292SN/A while (threads != (*activeThreads).end()) { 14502292SN/A unsigned tid = *threads++; 14511060SN/A 14522292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14531060SN/A 14542292SN/A checkSignalsAndUpdate(tid); 14552292SN/A dispatch(tid); 14561060SN/A } 14571060SN/A 14582292SN/A if (exeStatus != Squashing) { 14592292SN/A executeInsts(); 14601060SN/A 14612292SN/A writebackInsts(); 14622292SN/A 14632292SN/A // Have the instruction queue try to schedule any ready instructions. 14642292SN/A // (In actuality, this scheduling is for instructions that will 14652292SN/A // be executed next cycle.) 14662292SN/A instQueue.scheduleReadyInsts(); 14672292SN/A 14682292SN/A // Also should advance its own time buffers if the stage ran. 14692292SN/A // Not the best place for it, but this works (hopefully). 14702292SN/A issueToExecQueue.advance(); 14712292SN/A } 14722292SN/A 14732292SN/A bool broadcast_free_entries = false; 14742292SN/A 14752292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14762292SN/A exeStatus = Idle; 14772292SN/A updateLSQNextCycle = false; 14782292SN/A 14792292SN/A broadcast_free_entries = true; 14802292SN/A } 14812292SN/A 14822292SN/A // Writeback any stores using any leftover bandwidth. 14831681SN/A ldstQueue.writebackStores(); 14841681SN/A 14851061SN/A // Check the committed load/store signals to see if there's a load 14861061SN/A // or store to commit. Also check if it's being told to execute a 14871061SN/A // nonspeculative instruction. 14881681SN/A // This is pretty inefficient... 14892292SN/A 14902292SN/A threads = (*activeThreads).begin(); 14912292SN/A while (threads != (*activeThreads).end()) { 14922292SN/A unsigned tid = (*threads++); 14932292SN/A 14942292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14952292SN/A 14962348SN/A // Update structures based on instructions committed. 14972292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14982292SN/A !fromCommit->commitInfo[tid].squash && 14992292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15002292SN/A 15012292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15022292SN/A 15032292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15042292SN/A 15052292SN/A updateLSQNextCycle = true; 15062292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15072292SN/A } 15082292SN/A 15092292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15102292SN/A 15112292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15122292SN/A if (fromCommit->commitInfo[tid].uncached) { 15132292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15142292SN/A } else { 15152292SN/A instQueue.scheduleNonSpec( 15162292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15172292SN/A } 15182292SN/A } 15192292SN/A 15202292SN/A if (broadcast_free_entries) { 15212292SN/A toFetch->iewInfo[tid].iqCount = 15222292SN/A instQueue.getCount(tid); 15232292SN/A toFetch->iewInfo[tid].ldstqCount = 15242292SN/A ldstQueue.getCount(tid); 15252292SN/A 15262292SN/A toRename->iewInfo[tid].usedIQ = true; 15272292SN/A toRename->iewInfo[tid].freeIQEntries = 15282292SN/A instQueue.numFreeEntries(); 15292292SN/A toRename->iewInfo[tid].usedLSQ = true; 15302292SN/A toRename->iewInfo[tid].freeLSQEntries = 15312292SN/A ldstQueue.numFreeEntries(tid); 15322292SN/A 15332292SN/A wroteToTimeBuffer = true; 15342292SN/A } 15352292SN/A 15362292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15372292SN/A tid, toRename->iewInfo[tid].dispatched); 15381061SN/A } 15391061SN/A 15402292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15412292SN/A "LSQ has %i free entries.\n", 15422292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15432292SN/A ldstQueue.numFreeEntries()); 15442292SN/A 15452292SN/A updateStatus(); 15462292SN/A 15472292SN/A if (wroteToTimeBuffer) { 15482292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15492292SN/A cpu->activityThisCycle(); 15501061SN/A } 15511060SN/A} 15521060SN/A 15532301SN/Atemplate <class Impl> 15541060SN/Avoid 15552301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15561060SN/A{ 15572301SN/A int thread_number = inst->threadNumber; 15581060SN/A 15592301SN/A // 15602301SN/A // Pick off the software prefetches 15612301SN/A // 15622301SN/A#ifdef TARGET_ALPHA 15632301SN/A if (inst->isDataPrefetch()) 15642727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 15652301SN/A else 15662727Sktlim@umich.edu iewIewExecutedcutedInsts++; 15672301SN/A#else 15682669Sktlim@umich.edu iewExecutedInsts++; 15692301SN/A#endif 15701060SN/A 15712301SN/A // 15722301SN/A // Control operations 15732301SN/A // 15742301SN/A if (inst->isControl()) 15752727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 15761060SN/A 15772301SN/A // 15782301SN/A // Memory operations 15792301SN/A // 15802301SN/A if (inst->isMemRef()) { 15812727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 15821060SN/A 15832301SN/A if (inst->isLoad()) { 15842301SN/A iewExecLoadInsts[thread_number]++; 15851060SN/A } 15861060SN/A } 15871060SN/A} 1588