iew_impl.hh revision 2873
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 412292SN/Ausing namespace std; 421681SN/A 431681SN/Atemplate<class Impl> 442292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 452873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 461060SN/A instQueue(params), 471061SN/A ldstQueue(params), 482292SN/A fuPool(params->fuPool), 492292SN/A commitToIEWDelay(params->commitToIEWDelay), 502292SN/A renameToIEWDelay(params->renameToIEWDelay), 512292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 522820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 532292SN/A issueWidth(params->issueWidth), 542820Sktlim@umich.edu wbOutstanding(0), 552820Sktlim@umich.edu wbWidth(params->wbWidth), 562307SN/A numThreads(params->numberOfThreads), 572307SN/A switchedOut(false) 581060SN/A{ 592292SN/A _status = Active; 602292SN/A exeStatus = Running; 612292SN/A wbStatus = Idle; 621060SN/A 631060SN/A // Setup wire to read instructions coming from issue. 641060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 651060SN/A 661060SN/A // Instruction queue needs the queue between issue and execute. 671060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 681681SN/A 692292SN/A instQueue.setIEW(this); 701681SN/A ldstQueue.setIEW(this); 712292SN/A 722292SN/A for (int i=0; i < numThreads; i++) { 732292SN/A dispatchStatus[i] = Running; 742292SN/A stalls[i].commit = false; 752292SN/A fetchRedirect[i] = false; 762292SN/A } 772292SN/A 782820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 792820Sktlim@umich.edu 802292SN/A updateLSQNextCycle = false; 812292SN/A 822820Sktlim@umich.edu ableToIssue = true; 832820Sktlim@umich.edu 842292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 882292SN/Astd::string 892292SN/ADefaultIEW<Impl>::name() const 902292SN/A{ 912292SN/A return cpu->name() + ".iew"; 921060SN/A} 931060SN/A 941681SN/Atemplate <class Impl> 951062SN/Avoid 962292SN/ADefaultIEW<Impl>::regStats() 971062SN/A{ 982301SN/A using namespace Stats; 992301SN/A 1001062SN/A instQueue.regStats(); 1012727Sktlim@umich.edu ldstQueue.regStats(); 1021062SN/A 1031062SN/A iewIdleCycles 1041062SN/A .name(name() + ".iewIdleCycles") 1051062SN/A .desc("Number of cycles IEW is idle"); 1061062SN/A 1071062SN/A iewSquashCycles 1081062SN/A .name(name() + ".iewSquashCycles") 1091062SN/A .desc("Number of cycles IEW is squashing"); 1101062SN/A 1111062SN/A iewBlockCycles 1121062SN/A .name(name() + ".iewBlockCycles") 1131062SN/A .desc("Number of cycles IEW is blocking"); 1141062SN/A 1151062SN/A iewUnblockCycles 1161062SN/A .name(name() + ".iewUnblockCycles") 1171062SN/A .desc("Number of cycles IEW is unblocking"); 1181062SN/A 1191062SN/A iewDispatchedInsts 1201062SN/A .name(name() + ".iewDispatchedInsts") 1211062SN/A .desc("Number of instructions dispatched to IQ"); 1221062SN/A 1231062SN/A iewDispSquashedInsts 1241062SN/A .name(name() + ".iewDispSquashedInsts") 1251062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1261062SN/A 1271062SN/A iewDispLoadInsts 1281062SN/A .name(name() + ".iewDispLoadInsts") 1291062SN/A .desc("Number of dispatched load instructions"); 1301062SN/A 1311062SN/A iewDispStoreInsts 1321062SN/A .name(name() + ".iewDispStoreInsts") 1331062SN/A .desc("Number of dispatched store instructions"); 1341062SN/A 1351062SN/A iewDispNonSpecInsts 1361062SN/A .name(name() + ".iewDispNonSpecInsts") 1371062SN/A .desc("Number of dispatched non-speculative instructions"); 1381062SN/A 1391062SN/A iewIQFullEvents 1401062SN/A .name(name() + ".iewIQFullEvents") 1411062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1421062SN/A 1432292SN/A iewLSQFullEvents 1442292SN/A .name(name() + ".iewLSQFullEvents") 1452292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1462292SN/A 1471062SN/A memOrderViolationEvents 1481062SN/A .name(name() + ".memOrderViolationEvents") 1491062SN/A .desc("Number of memory order violations"); 1501062SN/A 1511062SN/A predictedTakenIncorrect 1521062SN/A .name(name() + ".predictedTakenIncorrect") 1531062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1542292SN/A 1552292SN/A predictedNotTakenIncorrect 1562292SN/A .name(name() + ".predictedNotTakenIncorrect") 1572292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1582292SN/A 1592292SN/A branchMispredicts 1602292SN/A .name(name() + ".branchMispredicts") 1612292SN/A .desc("Number of branch mispredicts detected at execute"); 1622292SN/A 1632292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1642301SN/A 1652727Sktlim@umich.edu iewExecutedInsts 1662727Sktlim@umich.edu .name(name() + ".EXEC:insts") 1672727Sktlim@umich.edu .desc("Number of executed instructions"); 1682727Sktlim@umich.edu 1692727Sktlim@umich.edu iewExecLoadInsts 1702727Sktlim@umich.edu .init(cpu->number_of_threads) 1712727Sktlim@umich.edu .name(name() + ".EXEC:loads") 1722727Sktlim@umich.edu .desc("Number of load instructions executed") 1732727Sktlim@umich.edu .flags(total); 1742727Sktlim@umich.edu 1752727Sktlim@umich.edu iewExecSquashedInsts 1762727Sktlim@umich.edu .name(name() + ".EXEC:squashedInsts") 1772727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1782727Sktlim@umich.edu 1792727Sktlim@umich.edu iewExecutedSwp 1802301SN/A .init(cpu->number_of_threads) 1812301SN/A .name(name() + ".EXEC:swp") 1822301SN/A .desc("number of swp insts executed") 1832727Sktlim@umich.edu .flags(total); 1842301SN/A 1852727Sktlim@umich.edu iewExecutedNop 1862301SN/A .init(cpu->number_of_threads) 1872301SN/A .name(name() + ".EXEC:nop") 1882301SN/A .desc("number of nop insts executed") 1892727Sktlim@umich.edu .flags(total); 1902301SN/A 1912727Sktlim@umich.edu iewExecutedRefs 1922301SN/A .init(cpu->number_of_threads) 1932301SN/A .name(name() + ".EXEC:refs") 1942301SN/A .desc("number of memory reference insts executed") 1952727Sktlim@umich.edu .flags(total); 1962301SN/A 1972727Sktlim@umich.edu iewExecutedBranches 1982301SN/A .init(cpu->number_of_threads) 1992301SN/A .name(name() + ".EXEC:branches") 2002301SN/A .desc("Number of branches executed") 2012727Sktlim@umich.edu .flags(total); 2022301SN/A 2032301SN/A iewExecStoreInsts 2042301SN/A .name(name() + ".EXEC:stores") 2052301SN/A .desc("Number of stores executed") 2062727Sktlim@umich.edu .flags(total); 2072727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu iewExecRate 2102727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2112727Sktlim@umich.edu .desc("Inst execution rate") 2122727Sktlim@umich.edu .flags(total); 2132727Sktlim@umich.edu 2142727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2152301SN/A 2162301SN/A iewInstsToCommit 2172301SN/A .init(cpu->number_of_threads) 2182301SN/A .name(name() + ".WB:sent") 2192301SN/A .desc("cumulative count of insts sent to commit") 2202727Sktlim@umich.edu .flags(total); 2212301SN/A 2222326SN/A writebackCount 2232301SN/A .init(cpu->number_of_threads) 2242301SN/A .name(name() + ".WB:count") 2252301SN/A .desc("cumulative count of insts written-back") 2262727Sktlim@umich.edu .flags(total); 2272301SN/A 2282326SN/A producerInst 2292301SN/A .init(cpu->number_of_threads) 2302301SN/A .name(name() + ".WB:producers") 2312301SN/A .desc("num instructions producing a value") 2322727Sktlim@umich.edu .flags(total); 2332301SN/A 2342326SN/A consumerInst 2352301SN/A .init(cpu->number_of_threads) 2362301SN/A .name(name() + ".WB:consumers") 2372301SN/A .desc("num instructions consuming a value") 2382727Sktlim@umich.edu .flags(total); 2392301SN/A 2402326SN/A wbPenalized 2412301SN/A .init(cpu->number_of_threads) 2422301SN/A .name(name() + ".WB:penalized") 2432301SN/A .desc("number of instrctions required to write to 'other' IQ") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A wbPenalizedRate 2472301SN/A .name(name() + ".WB:penalized_rate") 2482301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2492727Sktlim@umich.edu .flags(total); 2502301SN/A 2512326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2522301SN/A 2532326SN/A wbFanout 2542301SN/A .name(name() + ".WB:fanout") 2552301SN/A .desc("average fanout of values written-back") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A wbFanout = producerInst / consumerInst; 2592301SN/A 2602326SN/A wbRate 2612301SN/A .name(name() + ".WB:rate") 2622301SN/A .desc("insts written-back per cycle") 2632727Sktlim@umich.edu .flags(total); 2642326SN/A wbRate = writebackCount / cpu->numCycles; 2651062SN/A} 2661062SN/A 2671681SN/Atemplate<class Impl> 2681060SN/Avoid 2692292SN/ADefaultIEW<Impl>::initStage() 2701060SN/A{ 2712292SN/A for (int tid=0; tid < numThreads; tid++) { 2722292SN/A toRename->iewInfo[tid].usedIQ = true; 2732292SN/A toRename->iewInfo[tid].freeIQEntries = 2742292SN/A instQueue.numFreeEntries(tid); 2752292SN/A 2762292SN/A toRename->iewInfo[tid].usedLSQ = true; 2772292SN/A toRename->iewInfo[tid].freeLSQEntries = 2782292SN/A ldstQueue.numFreeEntries(tid); 2792292SN/A } 2802292SN/A} 2812292SN/A 2822292SN/Atemplate<class Impl> 2832292SN/Avoid 2842733Sktlim@umich.eduDefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 2852292SN/A{ 2862292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 2871060SN/A cpu = cpu_ptr; 2881060SN/A 2891060SN/A instQueue.setCPU(cpu_ptr); 2901061SN/A ldstQueue.setCPU(cpu_ptr); 2912292SN/A 2922733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2931060SN/A} 2941060SN/A 2951681SN/Atemplate<class Impl> 2961060SN/Avoid 2972292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2981060SN/A{ 2992292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 3001060SN/A timeBuffer = tb_ptr; 3011060SN/A 3021060SN/A // Setup wire to read information from time buffer, from commit. 3031060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3041060SN/A 3051060SN/A // Setup wire to write information back to previous stages. 3061060SN/A toRename = timeBuffer->getWire(0); 3071060SN/A 3082292SN/A toFetch = timeBuffer->getWire(0); 3092292SN/A 3101060SN/A // Instruction queue also needs main time buffer. 3111060SN/A instQueue.setTimeBuffer(tb_ptr); 3121060SN/A} 3131060SN/A 3141681SN/Atemplate<class Impl> 3151060SN/Avoid 3162292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3171060SN/A{ 3182292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3191060SN/A renameQueue = rq_ptr; 3201060SN/A 3211060SN/A // Setup wire to read information from rename queue. 3221060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3231060SN/A} 3241060SN/A 3251681SN/Atemplate<class Impl> 3261060SN/Avoid 3272292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3281060SN/A{ 3292292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3301060SN/A iewQueue = iq_ptr; 3311060SN/A 3321060SN/A // Setup wire to write instructions to commit. 3331060SN/A toCommit = iewQueue->getWire(0); 3341060SN/A} 3351060SN/A 3361681SN/Atemplate<class Impl> 3371060SN/Avoid 3382292SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3391060SN/A{ 3402292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3412292SN/A activeThreads = at_ptr; 3422292SN/A 3432292SN/A ldstQueue.setActiveThreads(at_ptr); 3442292SN/A instQueue.setActiveThreads(at_ptr); 3451060SN/A} 3461060SN/A 3471681SN/Atemplate<class Impl> 3481060SN/Avoid 3492292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3501060SN/A{ 3512292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3522292SN/A scoreboard = sb_ptr; 3531060SN/A} 3541060SN/A 3552307SN/Atemplate <class Impl> 3562863Sktlim@umich.edubool 3572843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3582307SN/A{ 3592843Sktlim@umich.edu // IEW is ready to drain at any time. 3602843Sktlim@umich.edu cpu->signalDrained(); 3612863Sktlim@umich.edu return true; 3621681SN/A} 3631681SN/A 3642316SN/Atemplate <class Impl> 3651681SN/Avoid 3662843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3672843Sktlim@umich.edu{ 3682843Sktlim@umich.edu} 3692843Sktlim@umich.edu 3702843Sktlim@umich.edutemplate <class Impl> 3712843Sktlim@umich.eduvoid 3722843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3731681SN/A{ 3742348SN/A // Clear any state. 3752307SN/A switchedOut = true; 3761681SN/A 3772307SN/A instQueue.switchOut(); 3782307SN/A ldstQueue.switchOut(); 3792307SN/A fuPool->switchOut(); 3802307SN/A 3812307SN/A for (int i = 0; i < numThreads; i++) { 3822307SN/A while (!insts[i].empty()) 3832307SN/A insts[i].pop(); 3842307SN/A while (!skidBuffer[i].empty()) 3852307SN/A skidBuffer[i].pop(); 3862307SN/A } 3871681SN/A} 3881681SN/A 3892307SN/Atemplate <class Impl> 3901681SN/Avoid 3912307SN/ADefaultIEW<Impl>::takeOverFrom() 3921060SN/A{ 3932348SN/A // Reset all state. 3942307SN/A _status = Active; 3952307SN/A exeStatus = Running; 3962307SN/A wbStatus = Idle; 3972307SN/A switchedOut = false; 3981060SN/A 3992307SN/A instQueue.takeOverFrom(); 4002307SN/A ldstQueue.takeOverFrom(); 4012307SN/A fuPool->takeOverFrom(); 4021060SN/A 4032307SN/A initStage(); 4042307SN/A cpu->activityThisCycle(); 4051060SN/A 4062307SN/A for (int i=0; i < numThreads; i++) { 4072307SN/A dispatchStatus[i] = Running; 4082307SN/A stalls[i].commit = false; 4092307SN/A fetchRedirect[i] = false; 4102307SN/A } 4111060SN/A 4122307SN/A updateLSQNextCycle = false; 4132307SN/A 4142307SN/A // @todo: Fix hardcoded number 4152873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4162307SN/A issueToExecQueue.advance(); 4171060SN/A } 4181060SN/A} 4191060SN/A 4201681SN/Atemplate<class Impl> 4211060SN/Avoid 4222292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4232107SN/A{ 4242292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4252292SN/A tid); 4262107SN/A 4272292SN/A // Tell the IQ to start squashing. 4282292SN/A instQueue.squash(tid); 4292107SN/A 4302292SN/A // Tell the LDSTQ to start squashing. 4312326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4322107SN/A 4332292SN/A updatedQueues = true; 4342107SN/A 4352292SN/A // Clear the skid buffer in case it has any data in it. 4362292SN/A while (!skidBuffer[tid].empty()) { 4372107SN/A 4382292SN/A if (skidBuffer[tid].front()->isLoad() || 4392292SN/A skidBuffer[tid].front()->isStore() ) { 4402292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4412292SN/A } 4422107SN/A 4432292SN/A toRename->iewInfo[tid].dispatched++; 4442107SN/A 4452292SN/A skidBuffer[tid].pop(); 4462292SN/A } 4472107SN/A 4482702Sktlim@umich.edu emptyRenameInsts(tid); 4492107SN/A} 4502107SN/A 4512107SN/Atemplate<class Impl> 4522107SN/Avoid 4532292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4542292SN/A{ 4552292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4562292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4572292SN/A 4582292SN/A toCommit->squash[tid] = true; 4592292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4602292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4612292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4622292SN/A toCommit->branchMispredict[tid] = true; 4632292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4642292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4652292SN/A 4662292SN/A toCommit->includeSquashInst[tid] = false; 4672292SN/A 4682292SN/A wroteToTimeBuffer = true; 4692292SN/A} 4702292SN/A 4712292SN/Atemplate<class Impl> 4722292SN/Avoid 4732292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4742292SN/A{ 4752292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4762292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4772292SN/A 4782292SN/A toCommit->squash[tid] = true; 4792292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4802292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4812292SN/A 4822292SN/A toCommit->includeSquashInst[tid] = false; 4832292SN/A 4842292SN/A wroteToTimeBuffer = true; 4852292SN/A} 4862292SN/A 4872292SN/Atemplate<class Impl> 4882292SN/Avoid 4892292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 4902292SN/A{ 4912292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4922292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4932292SN/A 4942292SN/A toCommit->squash[tid] = true; 4952292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4962292SN/A toCommit->nextPC[tid] = inst->readPC(); 4972292SN/A 4982348SN/A // Must include the broadcasted SN in the squash. 4992292SN/A toCommit->includeSquashInst[tid] = true; 5002292SN/A 5012292SN/A ldstQueue.setLoadBlockedHandled(tid); 5022292SN/A 5032292SN/A wroteToTimeBuffer = true; 5042292SN/A} 5052292SN/A 5062292SN/Atemplate<class Impl> 5072292SN/Avoid 5082292SN/ADefaultIEW<Impl>::block(unsigned tid) 5092292SN/A{ 5102292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5112292SN/A 5122292SN/A if (dispatchStatus[tid] != Blocked && 5132292SN/A dispatchStatus[tid] != Unblocking) { 5142292SN/A toRename->iewBlock[tid] = true; 5152292SN/A wroteToTimeBuffer = true; 5162292SN/A } 5172292SN/A 5182292SN/A // Add the current inputs to the skid buffer so they can be 5192292SN/A // reprocessed when this stage unblocks. 5202292SN/A skidInsert(tid); 5212292SN/A 5222292SN/A dispatchStatus[tid] = Blocked; 5232292SN/A} 5242292SN/A 5252292SN/Atemplate<class Impl> 5262292SN/Avoid 5272292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5282292SN/A{ 5292292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5302292SN/A "buffer %u.\n",tid, tid); 5312292SN/A 5322292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5332292SN/A // Also switch status to running. 5342292SN/A if (skidBuffer[tid].empty()) { 5352292SN/A toRename->iewUnblock[tid] = true; 5362292SN/A wroteToTimeBuffer = true; 5372292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5382292SN/A dispatchStatus[tid] = Running; 5392292SN/A } 5402292SN/A} 5412292SN/A 5422292SN/Atemplate<class Impl> 5432292SN/Avoid 5442292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5451060SN/A{ 5461681SN/A instQueue.wakeDependents(inst); 5471060SN/A} 5481060SN/A 5492292SN/Atemplate<class Impl> 5502292SN/Avoid 5512292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5522292SN/A{ 5532292SN/A instQueue.rescheduleMemInst(inst); 5542292SN/A} 5551681SN/A 5561681SN/Atemplate<class Impl> 5571060SN/Avoid 5582292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5591060SN/A{ 5602292SN/A instQueue.replayMemInst(inst); 5612292SN/A} 5621060SN/A 5632292SN/Atemplate<class Impl> 5642292SN/Avoid 5652292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5662292SN/A{ 5672292SN/A // First check the time slot that this instruction will write 5682292SN/A // to. If there are free write ports at the time, then go ahead 5692292SN/A // and write the instruction to that time. If there are not, 5702292SN/A // keep looking back to see where's the first time there's a 5712326SN/A // free slot. 5722292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5732292SN/A ++wbNumInst; 5742820Sktlim@umich.edu if (wbNumInst == wbWidth) { 5752292SN/A ++wbCycle; 5762292SN/A wbNumInst = 0; 5772292SN/A } 5782292SN/A 5792820Sktlim@umich.edu assert((wbCycle * wbWidth + wbNumInst) < wbMax); 5802292SN/A } 5812292SN/A 5822292SN/A // Add finished instruction to queue to commit. 5832292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5842292SN/A (*iewQueue)[wbCycle].size++; 5852292SN/A} 5862292SN/A 5872292SN/Atemplate <class Impl> 5882292SN/Aunsigned 5892292SN/ADefaultIEW<Impl>::validInstsFromRename() 5902292SN/A{ 5912292SN/A unsigned inst_count = 0; 5922292SN/A 5932292SN/A for (int i=0; i<fromRename->size; i++) { 5942731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 5952292SN/A inst_count++; 5962292SN/A } 5972292SN/A 5982292SN/A return inst_count; 5992292SN/A} 6002292SN/A 6012292SN/Atemplate<class Impl> 6022292SN/Avoid 6032292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6042292SN/A{ 6052292SN/A DynInstPtr inst = NULL; 6062292SN/A 6072292SN/A while (!insts[tid].empty()) { 6082292SN/A inst = insts[tid].front(); 6092292SN/A 6102292SN/A insts[tid].pop(); 6112292SN/A 6122292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6132292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6142292SN/A inst->readPC(),tid); 6152292SN/A 6162292SN/A skidBuffer[tid].push(inst); 6172292SN/A } 6182292SN/A 6192292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6202292SN/A "Skidbuffer Exceeded Max Size"); 6212292SN/A} 6222292SN/A 6232292SN/Atemplate<class Impl> 6242292SN/Aint 6252292SN/ADefaultIEW<Impl>::skidCount() 6262292SN/A{ 6272292SN/A int max=0; 6282292SN/A 6292292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6302292SN/A 6312292SN/A while (threads != (*activeThreads).end()) { 6322292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6332292SN/A if (max < thread_count) 6342292SN/A max = thread_count; 6352292SN/A } 6362292SN/A 6372292SN/A return max; 6382292SN/A} 6392292SN/A 6402292SN/Atemplate<class Impl> 6412292SN/Abool 6422292SN/ADefaultIEW<Impl>::skidsEmpty() 6432292SN/A{ 6442292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6452292SN/A 6462292SN/A while (threads != (*activeThreads).end()) { 6472292SN/A if (!skidBuffer[*threads++].empty()) 6482292SN/A return false; 6492292SN/A } 6502292SN/A 6512292SN/A return true; 6521062SN/A} 6531062SN/A 6541681SN/Atemplate <class Impl> 6551062SN/Avoid 6562292SN/ADefaultIEW<Impl>::updateStatus() 6571062SN/A{ 6582292SN/A bool any_unblocking = false; 6591062SN/A 6602292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6611062SN/A 6622292SN/A threads = (*activeThreads).begin(); 6631062SN/A 6642292SN/A while (threads != (*activeThreads).end()) { 6652292SN/A unsigned tid = *threads++; 6661062SN/A 6672292SN/A if (dispatchStatus[tid] == Unblocking) { 6682292SN/A any_unblocking = true; 6692292SN/A break; 6702292SN/A } 6712292SN/A } 6721062SN/A 6732292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6742292SN/A // and there's no stores waiting to write back, and dispatch is not 6752292SN/A // unblocking, then there is no internal activity for the IEW stage. 6762292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6772292SN/A !ldstQueue.willWB() && !any_unblocking) { 6782292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6791062SN/A 6802292SN/A deactivateStage(); 6811062SN/A 6822292SN/A _status = Inactive; 6832292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6842292SN/A ldstQueue.willWB() || 6852292SN/A any_unblocking)) { 6862292SN/A // Otherwise there is internal activity. Set to active. 6872292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6881062SN/A 6892292SN/A activateStage(); 6901062SN/A 6912292SN/A _status = Active; 6921062SN/A } 6931062SN/A} 6941062SN/A 6951681SN/Atemplate <class Impl> 6961062SN/Avoid 6972292SN/ADefaultIEW<Impl>::resetEntries() 6981062SN/A{ 6992292SN/A instQueue.resetEntries(); 7002292SN/A ldstQueue.resetEntries(); 7012292SN/A} 7021062SN/A 7032292SN/Atemplate <class Impl> 7042292SN/Avoid 7052292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7062292SN/A{ 7072292SN/A if (fromCommit->commitBlock[tid]) { 7082292SN/A stalls[tid].commit = true; 7092292SN/A } 7101062SN/A 7112292SN/A if (fromCommit->commitUnblock[tid]) { 7122292SN/A assert(stalls[tid].commit); 7132292SN/A stalls[tid].commit = false; 7142292SN/A } 7152292SN/A} 7162292SN/A 7172292SN/Atemplate <class Impl> 7182292SN/Abool 7192292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7202292SN/A{ 7212292SN/A bool ret_val(false); 7222292SN/A 7232292SN/A if (stalls[tid].commit) { 7242292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7252292SN/A ret_val = true; 7262292SN/A } else if (instQueue.isFull(tid)) { 7272292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7282292SN/A ret_val = true; 7292292SN/A } else if (ldstQueue.isFull(tid)) { 7302292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7312292SN/A 7322292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7332292SN/A 7342292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7352292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7362292SN/A } 7372292SN/A 7382292SN/A if (ldstQueue.numStores(tid) > 0) { 7392292SN/A 7402292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7412292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7422292SN/A } 7432292SN/A 7442292SN/A ret_val = true; 7452292SN/A } else if (ldstQueue.isStalled(tid)) { 7462292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7472292SN/A ret_val = true; 7482292SN/A } 7492292SN/A 7502292SN/A return ret_val; 7512292SN/A} 7522292SN/A 7532292SN/Atemplate <class Impl> 7542292SN/Avoid 7552292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7562292SN/A{ 7572292SN/A // Check if there's a squash signal, squash if there is 7582292SN/A // Check stall signals, block if there is. 7592292SN/A // If status was Blocked 7602292SN/A // if so then go to unblocking 7612292SN/A // If status was Squashing 7622292SN/A // check if squashing is not high. Switch to running this cycle. 7632292SN/A 7642292SN/A readStallSignals(tid); 7652292SN/A 7662292SN/A if (fromCommit->commitInfo[tid].squash) { 7672292SN/A squash(tid); 7682292SN/A 7692292SN/A if (dispatchStatus[tid] == Blocked || 7702292SN/A dispatchStatus[tid] == Unblocking) { 7712292SN/A toRename->iewUnblock[tid] = true; 7722292SN/A wroteToTimeBuffer = true; 7732292SN/A } 7742292SN/A 7752292SN/A dispatchStatus[tid] = Squashing; 7762292SN/A 7772292SN/A fetchRedirect[tid] = false; 7782292SN/A return; 7792292SN/A } 7802292SN/A 7812292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7822702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7832292SN/A 7842292SN/A dispatchStatus[tid] = Squashing; 7852292SN/A 7862702Sktlim@umich.edu emptyRenameInsts(tid); 7872702Sktlim@umich.edu wroteToTimeBuffer = true; 7882292SN/A return; 7892292SN/A } 7902292SN/A 7912292SN/A if (checkStall(tid)) { 7922292SN/A block(tid); 7932292SN/A dispatchStatus[tid] = Blocked; 7942292SN/A return; 7952292SN/A } 7962292SN/A 7972292SN/A if (dispatchStatus[tid] == Blocked) { 7982292SN/A // Status from previous cycle was blocked, but there are no more stall 7992292SN/A // conditions. Switch over to unblocking. 8002292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8012292SN/A tid); 8022292SN/A 8032292SN/A dispatchStatus[tid] = Unblocking; 8042292SN/A 8052292SN/A unblock(tid); 8062292SN/A 8072292SN/A return; 8082292SN/A } 8092292SN/A 8102292SN/A if (dispatchStatus[tid] == Squashing) { 8112292SN/A // Switch status to running if rename isn't being told to block or 8122292SN/A // squash this cycle. 8132292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8142292SN/A tid); 8152292SN/A 8162292SN/A dispatchStatus[tid] = Running; 8172292SN/A 8182292SN/A return; 8192292SN/A } 8202292SN/A} 8212292SN/A 8222292SN/Atemplate <class Impl> 8232292SN/Avoid 8242292SN/ADefaultIEW<Impl>::sortInsts() 8252292SN/A{ 8262292SN/A int insts_from_rename = fromRename->size; 8272326SN/A#ifdef DEBUG 8282292SN/A for (int i = 0; i < numThreads; i++) 8292292SN/A assert(insts[i].empty()); 8302326SN/A#endif 8312292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8322292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8332292SN/A } 8342292SN/A} 8352292SN/A 8362292SN/Atemplate <class Impl> 8372292SN/Avoid 8382702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8392702Sktlim@umich.edu{ 8402702Sktlim@umich.edu while (!insts[tid].empty()) { 8412702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8422702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8432702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8442702Sktlim@umich.edu } 8452702Sktlim@umich.edu 8462702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8472702Sktlim@umich.edu 8482702Sktlim@umich.edu insts[tid].pop(); 8492702Sktlim@umich.edu } 8502702Sktlim@umich.edu} 8512702Sktlim@umich.edu 8522702Sktlim@umich.edutemplate <class Impl> 8532702Sktlim@umich.eduvoid 8542292SN/ADefaultIEW<Impl>::wakeCPU() 8552292SN/A{ 8562292SN/A cpu->wakeCPU(); 8572292SN/A} 8582292SN/A 8592292SN/Atemplate <class Impl> 8602292SN/Avoid 8612292SN/ADefaultIEW<Impl>::activityThisCycle() 8622292SN/A{ 8632292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8642292SN/A cpu->activityThisCycle(); 8652292SN/A} 8662292SN/A 8672292SN/Atemplate <class Impl> 8682292SN/Ainline void 8692292SN/ADefaultIEW<Impl>::activateStage() 8702292SN/A{ 8712292SN/A DPRINTF(Activity, "Activating stage.\n"); 8722733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8732292SN/A} 8742292SN/A 8752292SN/Atemplate <class Impl> 8762292SN/Ainline void 8772292SN/ADefaultIEW<Impl>::deactivateStage() 8782292SN/A{ 8792292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8802733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8812292SN/A} 8822292SN/A 8832292SN/Atemplate<class Impl> 8842292SN/Avoid 8852292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8862292SN/A{ 8872292SN/A // If status is Running or idle, 8882292SN/A // call dispatchInsts() 8892292SN/A // If status is Unblocking, 8902292SN/A // buffer any instructions coming from rename 8912292SN/A // continue trying to empty skid buffer 8922292SN/A // check if stall conditions have passed 8932292SN/A 8942292SN/A if (dispatchStatus[tid] == Blocked) { 8952292SN/A ++iewBlockCycles; 8962292SN/A 8972292SN/A } else if (dispatchStatus[tid] == Squashing) { 8982292SN/A ++iewSquashCycles; 8992292SN/A } 9002292SN/A 9012292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9022292SN/A // will allow, as long as it is not currently blocked. 9032292SN/A if (dispatchStatus[tid] == Running || 9042292SN/A dispatchStatus[tid] == Idle) { 9052292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9062292SN/A "dispatch.\n", tid); 9072292SN/A 9082292SN/A dispatchInsts(tid); 9092292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9102292SN/A // Make sure that the skid buffer has something in it if the 9112292SN/A // status is unblocking. 9122292SN/A assert(!skidsEmpty()); 9132292SN/A 9142292SN/A // If the status was unblocking, then instructions from the skid 9152292SN/A // buffer were used. Remove those instructions and handle 9162292SN/A // the rest of unblocking. 9172292SN/A dispatchInsts(tid); 9182292SN/A 9192292SN/A ++iewUnblockCycles; 9202292SN/A 9212292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9222292SN/A // Add the current inputs to the skid buffer so they can be 9232292SN/A // reprocessed when this stage unblocks. 9242292SN/A skidInsert(tid); 9252292SN/A } 9262292SN/A 9272292SN/A unblock(tid); 9282292SN/A } 9292292SN/A} 9302292SN/A 9312292SN/Atemplate <class Impl> 9322292SN/Avoid 9332292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9342292SN/A{ 9352292SN/A dispatchedAllInsts = true; 9362292SN/A 9372292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9382292SN/A // otherwise. 9392292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9402292SN/A dispatchStatus[tid] == Unblocking ? 9412292SN/A skidBuffer[tid] : insts[tid]; 9422292SN/A 9432292SN/A int insts_to_add = insts_to_dispatch.size(); 9442292SN/A 9452292SN/A DynInstPtr inst; 9462292SN/A bool add_to_iq = false; 9472292SN/A int dis_num_inst = 0; 9482292SN/A 9492292SN/A // Loop through the instructions, putting them in the instruction 9502292SN/A // queue. 9512292SN/A for ( ; dis_num_inst < insts_to_add && 9522820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9532292SN/A ++dis_num_inst) 9542292SN/A { 9552292SN/A inst = insts_to_dispatch.front(); 9562292SN/A 9572292SN/A if (dispatchStatus[tid] == Unblocking) { 9582292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9592292SN/A "buffer\n", tid); 9602292SN/A } 9612292SN/A 9622292SN/A // Make sure there's a valid instruction there. 9632292SN/A assert(inst); 9642292SN/A 9652292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9662292SN/A "IQ.\n", 9672292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9682292SN/A 9692292SN/A // Be sure to mark these instructions as ready so that the 9702292SN/A // commit stage can go ahead and execute them, and mark 9712292SN/A // them as issued so the IQ doesn't reprocess them. 9722292SN/A 9732292SN/A // Check for squashed instructions. 9742292SN/A if (inst->isSquashed()) { 9752292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9762292SN/A "not adding to IQ.\n", tid); 9772292SN/A 9782292SN/A ++iewDispSquashedInsts; 9792292SN/A 9802292SN/A insts_to_dispatch.pop(); 9812292SN/A 9822292SN/A //Tell Rename That An Instruction has been processed 9832292SN/A if (inst->isLoad() || inst->isStore()) { 9842292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9852292SN/A } 9862292SN/A toRename->iewInfo[tid].dispatched++; 9872292SN/A 9882292SN/A continue; 9892292SN/A } 9902292SN/A 9912292SN/A // Check for full conditions. 9922292SN/A if (instQueue.isFull(tid)) { 9932292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 9942292SN/A 9952292SN/A // Call function to start blocking. 9962292SN/A block(tid); 9972292SN/A 9982292SN/A // Set unblock to false. Special case where we are using 9992292SN/A // skidbuffer (unblocking) instructions but then we still 10002292SN/A // get full in the IQ. 10012292SN/A toRename->iewUnblock[tid] = false; 10022292SN/A 10032292SN/A dispatchedAllInsts = false; 10042292SN/A 10052292SN/A ++iewIQFullEvents; 10062292SN/A break; 10072292SN/A } else if (ldstQueue.isFull(tid)) { 10082292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10092292SN/A 10102292SN/A // Call function to start blocking. 10112292SN/A block(tid); 10122292SN/A 10132292SN/A // Set unblock to false. Special case where we are using 10142292SN/A // skidbuffer (unblocking) instructions but then we still 10152292SN/A // get full in the IQ. 10162292SN/A toRename->iewUnblock[tid] = false; 10172292SN/A 10182292SN/A dispatchedAllInsts = false; 10192292SN/A 10202292SN/A ++iewLSQFullEvents; 10212292SN/A break; 10222292SN/A } 10232292SN/A 10242292SN/A // Otherwise issue the instruction just fine. 10252292SN/A if (inst->isLoad()) { 10262292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10272292SN/A "encountered, adding to LSQ.\n", tid); 10282292SN/A 10292292SN/A // Reserve a spot in the load store queue for this 10302292SN/A // memory access. 10312292SN/A ldstQueue.insertLoad(inst); 10322292SN/A 10332292SN/A ++iewDispLoadInsts; 10342292SN/A 10352292SN/A add_to_iq = true; 10362292SN/A 10372292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10382292SN/A } else if (inst->isStore()) { 10392292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10402292SN/A "encountered, adding to LSQ.\n", tid); 10412292SN/A 10422292SN/A ldstQueue.insertStore(inst); 10432292SN/A 10442292SN/A ++iewDispStoreInsts; 10452292SN/A 10462336SN/A if (inst->isStoreConditional()) { 10472336SN/A // Store conditionals need to be set as "canCommit()" 10482336SN/A // so that commit can process them when they reach the 10492336SN/A // head of commit. 10502348SN/A // @todo: This is somewhat specific to Alpha. 10512292SN/A inst->setCanCommit(); 10522292SN/A instQueue.insertNonSpec(inst); 10532292SN/A add_to_iq = false; 10542292SN/A 10552292SN/A ++iewDispNonSpecInsts; 10562292SN/A } else { 10572292SN/A add_to_iq = true; 10582292SN/A } 10592292SN/A 10602292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10612292SN/A#if FULL_SYSTEM 10622292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10632326SN/A // Same as non-speculative stores. 10642292SN/A inst->setCanCommit(); 10652292SN/A instQueue.insertBarrier(inst); 10662292SN/A add_to_iq = false; 10672292SN/A#endif 10682292SN/A } else if (inst->isNonSpeculative()) { 10692292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 10702292SN/A "encountered, skipping.\n", tid); 10712292SN/A 10722326SN/A // Same as non-speculative stores. 10732292SN/A inst->setCanCommit(); 10742292SN/A 10752292SN/A // Specifically insert it as nonspeculative. 10762292SN/A instQueue.insertNonSpec(inst); 10772292SN/A 10782292SN/A ++iewDispNonSpecInsts; 10792292SN/A 10802292SN/A add_to_iq = false; 10812292SN/A } else if (inst->isNop()) { 10822292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10832292SN/A "skipping.\n", tid); 10842292SN/A 10852292SN/A inst->setIssued(); 10862292SN/A inst->setExecuted(); 10872292SN/A inst->setCanCommit(); 10882292SN/A 10892326SN/A instQueue.recordProducer(inst); 10902292SN/A 10912727Sktlim@umich.edu iewExecutedNop[tid]++; 10922301SN/A 10932292SN/A add_to_iq = false; 10942292SN/A } else if (inst->isExecuted()) { 10952292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10962292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10972292SN/A "skipping.\n"); 10982292SN/A 10992292SN/A inst->setIssued(); 11002292SN/A inst->setCanCommit(); 11012292SN/A 11022326SN/A instQueue.recordProducer(inst); 11032292SN/A 11042292SN/A add_to_iq = false; 11052292SN/A } else { 11062292SN/A add_to_iq = true; 11072292SN/A } 11082292SN/A 11092292SN/A // If the instruction queue is not full, then add the 11102292SN/A // instruction. 11112292SN/A if (add_to_iq) { 11122292SN/A instQueue.insert(inst); 11132292SN/A } 11142292SN/A 11152292SN/A insts_to_dispatch.pop(); 11162292SN/A 11172292SN/A toRename->iewInfo[tid].dispatched++; 11182292SN/A 11192292SN/A ++iewDispatchedInsts; 11202292SN/A } 11212292SN/A 11222292SN/A if (!insts_to_dispatch.empty()) { 11232292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11242292SN/A block(tid); 11252292SN/A toRename->iewUnblock[tid] = false; 11262292SN/A } 11272292SN/A 11282292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11292292SN/A dispatchStatus[tid] = Running; 11302292SN/A 11312292SN/A updatedQueues = true; 11322292SN/A } 11332292SN/A 11342292SN/A dis_num_inst = 0; 11352292SN/A} 11362292SN/A 11372292SN/Atemplate <class Impl> 11382292SN/Avoid 11392292SN/ADefaultIEW<Impl>::printAvailableInsts() 11402292SN/A{ 11412292SN/A int inst = 0; 11422292SN/A 11432292SN/A cout << "Available Instructions: "; 11442292SN/A 11452292SN/A while (fromIssue->insts[inst]) { 11462292SN/A 11472292SN/A if (inst%3==0) cout << "\n\t"; 11482292SN/A 11492292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 11502292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11512292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11522292SN/A 11532292SN/A inst++; 11542292SN/A 11552292SN/A } 11562292SN/A 11572292SN/A cout << "\n"; 11582292SN/A} 11592292SN/A 11602292SN/Atemplate <class Impl> 11612292SN/Avoid 11622292SN/ADefaultIEW<Impl>::executeInsts() 11632292SN/A{ 11642292SN/A wbNumInst = 0; 11652292SN/A wbCycle = 0; 11662292SN/A 11672292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11682292SN/A 11692292SN/A while (threads != (*activeThreads).end()) { 11702292SN/A unsigned tid = *threads++; 11712292SN/A fetchRedirect[tid] = false; 11722292SN/A } 11732292SN/A 11742698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11752698Sktlim@umich.edu// printAvailableInsts(); 11761062SN/A 11771062SN/A // Execute/writeback any instructions that are available. 11782333SN/A int insts_to_execute = fromIssue->size; 11792292SN/A int inst_num = 0; 11802333SN/A for (; inst_num < insts_to_execute; 11812326SN/A ++inst_num) { 11821062SN/A 11832292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11841062SN/A 11852333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11861062SN/A 11872292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11882292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11891062SN/A 11901062SN/A // Check if the instruction is squashed; if so then skip it 11911062SN/A if (inst->isSquashed()) { 11922292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 11931062SN/A 11941062SN/A // Consider this instruction executed so that commit can go 11951062SN/A // ahead and retire the instruction. 11961062SN/A inst->setExecuted(); 11971062SN/A 11982292SN/A // Not sure if I should set this here or just let commit try to 11992292SN/A // commit any squashed instructions. I like the latter a bit more. 12002292SN/A inst->setCanCommit(); 12011062SN/A 12021062SN/A ++iewExecSquashedInsts; 12031062SN/A 12042820Sktlim@umich.edu decrWb(inst->seqNum); 12051062SN/A continue; 12061062SN/A } 12071062SN/A 12082292SN/A Fault fault = NoFault; 12091062SN/A 12101062SN/A // Execute instruction. 12111062SN/A // Note that if the instruction faults, it will be handled 12121062SN/A // at the commit stage. 12132292SN/A if (inst->isMemRef() && 12142292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12152292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12161062SN/A "reference.\n"); 12171062SN/A 12181062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12191062SN/A if (inst->isLoad()) { 12202292SN/A // Loads will mark themselves as executed, and their writeback 12212292SN/A // event adds the instruction to the queue to commit 12222292SN/A fault = ldstQueue.executeLoad(inst); 12231062SN/A } else if (inst->isStore()) { 12241681SN/A ldstQueue.executeStore(inst); 12251062SN/A 12262292SN/A // If the store had a fault then it may not have a mem req 12272669Sktlim@umich.edu if (inst->req && !(inst->req->getFlags() & LOCKED)) { 12282292SN/A inst->setExecuted(); 12292292SN/A 12302292SN/A instToCommit(inst); 12312292SN/A } 12322326SN/A 12332326SN/A // Store conditionals will mark themselves as 12342326SN/A // executed, and their writeback event will add the 12352326SN/A // instruction to the queue to commit. 12361062SN/A } else { 12372292SN/A panic("Unexpected memory type!\n"); 12381062SN/A } 12391062SN/A 12401062SN/A } else { 12411062SN/A inst->execute(); 12421062SN/A 12432292SN/A inst->setExecuted(); 12442292SN/A 12452292SN/A instToCommit(inst); 12461062SN/A } 12471062SN/A 12482301SN/A updateExeInstStats(inst); 12491681SN/A 12502326SN/A // Check if branch prediction was correct, if not then we need 12512326SN/A // to tell commit to squash in flight instructions. Only 12522326SN/A // handle this if there hasn't already been something that 12532107SN/A // redirects fetch in this group of instructions. 12541681SN/A 12552292SN/A // This probably needs to prioritize the redirects if a different 12562292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12572292SN/A // instruction first, so the branch resolution order will be correct. 12582292SN/A unsigned tid = inst->threadNumber; 12591062SN/A 12602292SN/A if (!fetchRedirect[tid]) { 12611062SN/A 12621062SN/A if (inst->mispredicted()) { 12632292SN/A fetchRedirect[tid] = true; 12641062SN/A 12652292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12662292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 12671062SN/A inst->nextPC); 12681062SN/A 12691062SN/A // If incorrect, then signal the ROB that it must be squashed. 12702292SN/A squashDueToBranch(inst, tid); 12711062SN/A 12721062SN/A if (inst->predTaken()) { 12731062SN/A predictedTakenIncorrect++; 12742292SN/A } else { 12752292SN/A predictedNotTakenIncorrect++; 12761062SN/A } 12772292SN/A } else if (ldstQueue.violation(tid)) { 12782292SN/A fetchRedirect[tid] = true; 12791062SN/A 12802326SN/A // If there was an ordering violation, then get the 12812326SN/A // DynInst that caused the violation. Note that this 12822292SN/A // clears the violation signal. 12832292SN/A DynInstPtr violator; 12842292SN/A violator = ldstQueue.getMemDepViolator(tid); 12851062SN/A 12862292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 12871062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 12881062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 12891062SN/A 12901062SN/A // Tell the instruction queue that a violation has occured. 12911062SN/A instQueue.violation(inst, violator); 12921062SN/A 12931062SN/A // Squash. 12942292SN/A squashDueToMemOrder(inst,tid); 12951062SN/A 12961062SN/A ++memOrderViolationEvents; 12972292SN/A } else if (ldstQueue.loadBlocked(tid) && 12982292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 12992292SN/A fetchRedirect[tid] = true; 13002292SN/A 13012292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13022292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13032292SN/A inst->readPC(), inst->seqNum); 13042292SN/A 13052292SN/A squashDueToMemBlocked(inst, tid); 13061062SN/A } 13071062SN/A } 13081062SN/A } 13092292SN/A 13102348SN/A // Update and record activity if we processed any instructions. 13112292SN/A if (inst_num) { 13122292SN/A if (exeStatus == Idle) { 13132292SN/A exeStatus = Running; 13142292SN/A } 13152292SN/A 13162292SN/A updatedQueues = true; 13172292SN/A 13182292SN/A cpu->activityThisCycle(); 13192292SN/A } 13202292SN/A 13212292SN/A // Need to reset this in case a writeback event needs to write into the 13222292SN/A // iew queue. That way the writeback event will write into the correct 13232292SN/A // spot in the queue. 13242292SN/A wbNumInst = 0; 13252107SN/A} 13262107SN/A 13272292SN/Atemplate <class Impl> 13282107SN/Avoid 13292292SN/ADefaultIEW<Impl>::writebackInsts() 13302107SN/A{ 13312326SN/A // Loop through the head of the time buffer and wake any 13322326SN/A // dependents. These instructions are about to write back. Also 13332326SN/A // mark scoreboard that this instruction is finally complete. 13342326SN/A // Either have IEW have direct access to scoreboard, or have this 13352326SN/A // as part of backwards communication. 13362107SN/A for (int inst_num = 0; inst_num < issueWidth && 13372292SN/A toCommit->insts[inst_num]; inst_num++) { 13382107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13392301SN/A int tid = inst->threadNumber; 13402107SN/A 13412698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13422698Sktlim@umich.edu inst->seqNum, inst->readPC()); 13432107SN/A 13442301SN/A iewInstsToCommit[tid]++; 13452301SN/A 13462292SN/A // Some instructions will be sent to commit without having 13472292SN/A // executed because they need commit to handle them. 13482292SN/A // E.g. Uncached loads have not actually executed when they 13492292SN/A // are first sent to commit. Instead commit must tell the LSQ 13502292SN/A // when it's ready to execute the uncached load. 13512292SN/A if (!inst->isSquashed() && inst->isExecuted()) { 13522301SN/A int dependents = instQueue.wakeDependents(inst); 13532107SN/A 13542292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 13552292SN/A //mark as Ready 13562292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 13572292SN/A inst->renamedDestRegIdx(i)); 13582292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 13592107SN/A } 13602301SN/A 13612348SN/A if (dependents) { 13622348SN/A producerInst[tid]++; 13632348SN/A consumerInst[tid]+= dependents; 13642348SN/A } 13652326SN/A writebackCount[tid]++; 13662107SN/A } 13672820Sktlim@umich.edu 13682820Sktlim@umich.edu decrWb(inst->seqNum); 13692107SN/A } 13701060SN/A} 13711060SN/A 13721681SN/Atemplate<class Impl> 13731060SN/Avoid 13742292SN/ADefaultIEW<Impl>::tick() 13751060SN/A{ 13762292SN/A wbNumInst = 0; 13772292SN/A wbCycle = 0; 13781060SN/A 13792292SN/A wroteToTimeBuffer = false; 13802292SN/A updatedQueues = false; 13811060SN/A 13822292SN/A sortInsts(); 13831060SN/A 13842326SN/A // Free function units marked as being freed this cycle. 13852326SN/A fuPool->processFreeUnits(); 13861062SN/A 13872292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 13881060SN/A 13892326SN/A // Check stall and squash signals, dispatch any instructions. 13902292SN/A while (threads != (*activeThreads).end()) { 13912292SN/A unsigned tid = *threads++; 13921060SN/A 13932292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 13941060SN/A 13952292SN/A checkSignalsAndUpdate(tid); 13962292SN/A dispatch(tid); 13971060SN/A } 13981060SN/A 13992292SN/A if (exeStatus != Squashing) { 14002292SN/A executeInsts(); 14011060SN/A 14022292SN/A writebackInsts(); 14032292SN/A 14042292SN/A // Have the instruction queue try to schedule any ready instructions. 14052292SN/A // (In actuality, this scheduling is for instructions that will 14062292SN/A // be executed next cycle.) 14072292SN/A instQueue.scheduleReadyInsts(); 14082292SN/A 14092292SN/A // Also should advance its own time buffers if the stage ran. 14102292SN/A // Not the best place for it, but this works (hopefully). 14112292SN/A issueToExecQueue.advance(); 14122292SN/A } 14132292SN/A 14142292SN/A bool broadcast_free_entries = false; 14152292SN/A 14162292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14172292SN/A exeStatus = Idle; 14182292SN/A updateLSQNextCycle = false; 14192292SN/A 14202292SN/A broadcast_free_entries = true; 14212292SN/A } 14222292SN/A 14232292SN/A // Writeback any stores using any leftover bandwidth. 14241681SN/A ldstQueue.writebackStores(); 14251681SN/A 14261061SN/A // Check the committed load/store signals to see if there's a load 14271061SN/A // or store to commit. Also check if it's being told to execute a 14281061SN/A // nonspeculative instruction. 14291681SN/A // This is pretty inefficient... 14302292SN/A 14312292SN/A threads = (*activeThreads).begin(); 14322292SN/A while (threads != (*activeThreads).end()) { 14332292SN/A unsigned tid = (*threads++); 14342292SN/A 14352292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14362292SN/A 14372348SN/A // Update structures based on instructions committed. 14382292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14392292SN/A !fromCommit->commitInfo[tid].squash && 14402292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14412292SN/A 14422292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14432292SN/A 14442292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14452292SN/A 14462292SN/A updateLSQNextCycle = true; 14472292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14482292SN/A } 14492292SN/A 14502292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 14512292SN/A 14522292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 14532292SN/A if (fromCommit->commitInfo[tid].uncached) { 14542292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 14552292SN/A } else { 14562292SN/A instQueue.scheduleNonSpec( 14572292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 14582292SN/A } 14592292SN/A } 14602292SN/A 14612292SN/A if (broadcast_free_entries) { 14622292SN/A toFetch->iewInfo[tid].iqCount = 14632292SN/A instQueue.getCount(tid); 14642292SN/A toFetch->iewInfo[tid].ldstqCount = 14652292SN/A ldstQueue.getCount(tid); 14662292SN/A 14672292SN/A toRename->iewInfo[tid].usedIQ = true; 14682292SN/A toRename->iewInfo[tid].freeIQEntries = 14692292SN/A instQueue.numFreeEntries(); 14702292SN/A toRename->iewInfo[tid].usedLSQ = true; 14712292SN/A toRename->iewInfo[tid].freeLSQEntries = 14722292SN/A ldstQueue.numFreeEntries(tid); 14732292SN/A 14742292SN/A wroteToTimeBuffer = true; 14752292SN/A } 14762292SN/A 14772292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 14782292SN/A tid, toRename->iewInfo[tid].dispatched); 14791061SN/A } 14801061SN/A 14812292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 14822292SN/A "LSQ has %i free entries.\n", 14832292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 14842292SN/A ldstQueue.numFreeEntries()); 14852292SN/A 14862292SN/A updateStatus(); 14872292SN/A 14882292SN/A if (wroteToTimeBuffer) { 14892292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 14902292SN/A cpu->activityThisCycle(); 14911061SN/A } 14921060SN/A} 14931060SN/A 14942301SN/Atemplate <class Impl> 14951060SN/Avoid 14962301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 14971060SN/A{ 14982301SN/A int thread_number = inst->threadNumber; 14991060SN/A 15002301SN/A // 15012301SN/A // Pick off the software prefetches 15022301SN/A // 15032301SN/A#ifdef TARGET_ALPHA 15042301SN/A if (inst->isDataPrefetch()) 15052727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 15062301SN/A else 15072727Sktlim@umich.edu iewIewExecutedcutedInsts++; 15082301SN/A#else 15092669Sktlim@umich.edu iewExecutedInsts++; 15102301SN/A#endif 15111060SN/A 15122301SN/A // 15132301SN/A // Control operations 15142301SN/A // 15152301SN/A if (inst->isControl()) 15162727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 15171060SN/A 15182301SN/A // 15192301SN/A // Memory operations 15202301SN/A // 15212301SN/A if (inst->isMemRef()) { 15222727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 15231060SN/A 15242301SN/A if (inst->isLoad()) { 15252301SN/A iewExecLoadInsts[thread_number]++; 15261060SN/A } 15271060SN/A } 15281060SN/A} 1529