iew_impl.hh revision 2863
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 412292SN/Ausing namespace std; 421681SN/A 431681SN/Atemplate<class Impl> 442292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 452326SN/A : // @todo: Make this into a parameter. 461061SN/A issueToExecQueue(5, 5), 471060SN/A instQueue(params), 481061SN/A ldstQueue(params), 492292SN/A fuPool(params->fuPool), 502292SN/A commitToIEWDelay(params->commitToIEWDelay), 512292SN/A renameToIEWDelay(params->renameToIEWDelay), 522292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 532820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 542292SN/A issueWidth(params->issueWidth), 552820Sktlim@umich.edu wbOutstanding(0), 562820Sktlim@umich.edu wbWidth(params->wbWidth), 572307SN/A numThreads(params->numberOfThreads), 582307SN/A switchedOut(false) 591060SN/A{ 602292SN/A _status = Active; 612292SN/A exeStatus = Running; 622292SN/A wbStatus = Idle; 631060SN/A 641060SN/A // Setup wire to read instructions coming from issue. 651060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 661060SN/A 671060SN/A // Instruction queue needs the queue between issue and execute. 681060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 691681SN/A 702292SN/A instQueue.setIEW(this); 711681SN/A ldstQueue.setIEW(this); 722292SN/A 732292SN/A for (int i=0; i < numThreads; i++) { 742292SN/A dispatchStatus[i] = Running; 752292SN/A stalls[i].commit = false; 762292SN/A fetchRedirect[i] = false; 772292SN/A } 782292SN/A 792820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 802820Sktlim@umich.edu 812292SN/A updateLSQNextCycle = false; 822292SN/A 832820Sktlim@umich.edu ableToIssue = true; 842820Sktlim@umich.edu 852292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 862292SN/A} 872292SN/A 882292SN/Atemplate <class Impl> 892292SN/Astd::string 902292SN/ADefaultIEW<Impl>::name() const 912292SN/A{ 922292SN/A return cpu->name() + ".iew"; 931060SN/A} 941060SN/A 951681SN/Atemplate <class Impl> 961062SN/Avoid 972292SN/ADefaultIEW<Impl>::regStats() 981062SN/A{ 992301SN/A using namespace Stats; 1002301SN/A 1011062SN/A instQueue.regStats(); 1022727Sktlim@umich.edu ldstQueue.regStats(); 1031062SN/A 1041062SN/A iewIdleCycles 1051062SN/A .name(name() + ".iewIdleCycles") 1061062SN/A .desc("Number of cycles IEW is idle"); 1071062SN/A 1081062SN/A iewSquashCycles 1091062SN/A .name(name() + ".iewSquashCycles") 1101062SN/A .desc("Number of cycles IEW is squashing"); 1111062SN/A 1121062SN/A iewBlockCycles 1131062SN/A .name(name() + ".iewBlockCycles") 1141062SN/A .desc("Number of cycles IEW is blocking"); 1151062SN/A 1161062SN/A iewUnblockCycles 1171062SN/A .name(name() + ".iewUnblockCycles") 1181062SN/A .desc("Number of cycles IEW is unblocking"); 1191062SN/A 1201062SN/A iewDispatchedInsts 1211062SN/A .name(name() + ".iewDispatchedInsts") 1221062SN/A .desc("Number of instructions dispatched to IQ"); 1231062SN/A 1241062SN/A iewDispSquashedInsts 1251062SN/A .name(name() + ".iewDispSquashedInsts") 1261062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1271062SN/A 1281062SN/A iewDispLoadInsts 1291062SN/A .name(name() + ".iewDispLoadInsts") 1301062SN/A .desc("Number of dispatched load instructions"); 1311062SN/A 1321062SN/A iewDispStoreInsts 1331062SN/A .name(name() + ".iewDispStoreInsts") 1341062SN/A .desc("Number of dispatched store instructions"); 1351062SN/A 1361062SN/A iewDispNonSpecInsts 1371062SN/A .name(name() + ".iewDispNonSpecInsts") 1381062SN/A .desc("Number of dispatched non-speculative instructions"); 1391062SN/A 1401062SN/A iewIQFullEvents 1411062SN/A .name(name() + ".iewIQFullEvents") 1421062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1431062SN/A 1442292SN/A iewLSQFullEvents 1452292SN/A .name(name() + ".iewLSQFullEvents") 1462292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1472292SN/A 1481062SN/A memOrderViolationEvents 1491062SN/A .name(name() + ".memOrderViolationEvents") 1501062SN/A .desc("Number of memory order violations"); 1511062SN/A 1521062SN/A predictedTakenIncorrect 1531062SN/A .name(name() + ".predictedTakenIncorrect") 1541062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1552292SN/A 1562292SN/A predictedNotTakenIncorrect 1572292SN/A .name(name() + ".predictedNotTakenIncorrect") 1582292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1592292SN/A 1602292SN/A branchMispredicts 1612292SN/A .name(name() + ".branchMispredicts") 1622292SN/A .desc("Number of branch mispredicts detected at execute"); 1632292SN/A 1642292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1652301SN/A 1662727Sktlim@umich.edu iewExecutedInsts 1672727Sktlim@umich.edu .name(name() + ".EXEC:insts") 1682727Sktlim@umich.edu .desc("Number of executed instructions"); 1692727Sktlim@umich.edu 1702727Sktlim@umich.edu iewExecLoadInsts 1712727Sktlim@umich.edu .init(cpu->number_of_threads) 1722727Sktlim@umich.edu .name(name() + ".EXEC:loads") 1732727Sktlim@umich.edu .desc("Number of load instructions executed") 1742727Sktlim@umich.edu .flags(total); 1752727Sktlim@umich.edu 1762727Sktlim@umich.edu iewExecSquashedInsts 1772727Sktlim@umich.edu .name(name() + ".EXEC:squashedInsts") 1782727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1792727Sktlim@umich.edu 1802727Sktlim@umich.edu iewExecutedSwp 1812301SN/A .init(cpu->number_of_threads) 1822301SN/A .name(name() + ".EXEC:swp") 1832301SN/A .desc("number of swp insts executed") 1842727Sktlim@umich.edu .flags(total); 1852301SN/A 1862727Sktlim@umich.edu iewExecutedNop 1872301SN/A .init(cpu->number_of_threads) 1882301SN/A .name(name() + ".EXEC:nop") 1892301SN/A .desc("number of nop insts executed") 1902727Sktlim@umich.edu .flags(total); 1912301SN/A 1922727Sktlim@umich.edu iewExecutedRefs 1932301SN/A .init(cpu->number_of_threads) 1942301SN/A .name(name() + ".EXEC:refs") 1952301SN/A .desc("number of memory reference insts executed") 1962727Sktlim@umich.edu .flags(total); 1972301SN/A 1982727Sktlim@umich.edu iewExecutedBranches 1992301SN/A .init(cpu->number_of_threads) 2002301SN/A .name(name() + ".EXEC:branches") 2012301SN/A .desc("Number of branches executed") 2022727Sktlim@umich.edu .flags(total); 2032301SN/A 2042301SN/A iewExecStoreInsts 2052301SN/A .name(name() + ".EXEC:stores") 2062301SN/A .desc("Number of stores executed") 2072727Sktlim@umich.edu .flags(total); 2082727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu iewExecRate 2112727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2122727Sktlim@umich.edu .desc("Inst execution rate") 2132727Sktlim@umich.edu .flags(total); 2142727Sktlim@umich.edu 2152727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2162301SN/A 2172301SN/A iewInstsToCommit 2182301SN/A .init(cpu->number_of_threads) 2192301SN/A .name(name() + ".WB:sent") 2202301SN/A .desc("cumulative count of insts sent to commit") 2212727Sktlim@umich.edu .flags(total); 2222301SN/A 2232326SN/A writebackCount 2242301SN/A .init(cpu->number_of_threads) 2252301SN/A .name(name() + ".WB:count") 2262301SN/A .desc("cumulative count of insts written-back") 2272727Sktlim@umich.edu .flags(total); 2282301SN/A 2292326SN/A producerInst 2302301SN/A .init(cpu->number_of_threads) 2312301SN/A .name(name() + ".WB:producers") 2322301SN/A .desc("num instructions producing a value") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352326SN/A consumerInst 2362301SN/A .init(cpu->number_of_threads) 2372301SN/A .name(name() + ".WB:consumers") 2382301SN/A .desc("num instructions consuming a value") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412326SN/A wbPenalized 2422301SN/A .init(cpu->number_of_threads) 2432301SN/A .name(name() + ".WB:penalized") 2442301SN/A .desc("number of instrctions required to write to 'other' IQ") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472326SN/A wbPenalizedRate 2482301SN/A .name(name() + ".WB:penalized_rate") 2492301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2502727Sktlim@umich.edu .flags(total); 2512301SN/A 2522326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2532301SN/A 2542326SN/A wbFanout 2552301SN/A .name(name() + ".WB:fanout") 2562301SN/A .desc("average fanout of values written-back") 2572727Sktlim@umich.edu .flags(total); 2582301SN/A 2592326SN/A wbFanout = producerInst / consumerInst; 2602301SN/A 2612326SN/A wbRate 2622301SN/A .name(name() + ".WB:rate") 2632301SN/A .desc("insts written-back per cycle") 2642727Sktlim@umich.edu .flags(total); 2652326SN/A wbRate = writebackCount / cpu->numCycles; 2661062SN/A} 2671062SN/A 2681681SN/Atemplate<class Impl> 2691060SN/Avoid 2702292SN/ADefaultIEW<Impl>::initStage() 2711060SN/A{ 2722292SN/A for (int tid=0; tid < numThreads; tid++) { 2732292SN/A toRename->iewInfo[tid].usedIQ = true; 2742292SN/A toRename->iewInfo[tid].freeIQEntries = 2752292SN/A instQueue.numFreeEntries(tid); 2762292SN/A 2772292SN/A toRename->iewInfo[tid].usedLSQ = true; 2782292SN/A toRename->iewInfo[tid].freeLSQEntries = 2792292SN/A ldstQueue.numFreeEntries(tid); 2802292SN/A } 2812292SN/A} 2822292SN/A 2832292SN/Atemplate<class Impl> 2842292SN/Avoid 2852733Sktlim@umich.eduDefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 2862292SN/A{ 2872292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 2881060SN/A cpu = cpu_ptr; 2891060SN/A 2901060SN/A instQueue.setCPU(cpu_ptr); 2911061SN/A ldstQueue.setCPU(cpu_ptr); 2922292SN/A 2932733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2941060SN/A} 2951060SN/A 2961681SN/Atemplate<class Impl> 2971060SN/Avoid 2982292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2991060SN/A{ 3002292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 3011060SN/A timeBuffer = tb_ptr; 3021060SN/A 3031060SN/A // Setup wire to read information from time buffer, from commit. 3041060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3051060SN/A 3061060SN/A // Setup wire to write information back to previous stages. 3071060SN/A toRename = timeBuffer->getWire(0); 3081060SN/A 3092292SN/A toFetch = timeBuffer->getWire(0); 3102292SN/A 3111060SN/A // Instruction queue also needs main time buffer. 3121060SN/A instQueue.setTimeBuffer(tb_ptr); 3131060SN/A} 3141060SN/A 3151681SN/Atemplate<class Impl> 3161060SN/Avoid 3172292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3181060SN/A{ 3192292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3201060SN/A renameQueue = rq_ptr; 3211060SN/A 3221060SN/A // Setup wire to read information from rename queue. 3231060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3241060SN/A} 3251060SN/A 3261681SN/Atemplate<class Impl> 3271060SN/Avoid 3282292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3291060SN/A{ 3302292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3311060SN/A iewQueue = iq_ptr; 3321060SN/A 3331060SN/A // Setup wire to write instructions to commit. 3341060SN/A toCommit = iewQueue->getWire(0); 3351060SN/A} 3361060SN/A 3371681SN/Atemplate<class Impl> 3381060SN/Avoid 3392292SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3401060SN/A{ 3412292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3422292SN/A activeThreads = at_ptr; 3432292SN/A 3442292SN/A ldstQueue.setActiveThreads(at_ptr); 3452292SN/A instQueue.setActiveThreads(at_ptr); 3461060SN/A} 3471060SN/A 3481681SN/Atemplate<class Impl> 3491060SN/Avoid 3502292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3511060SN/A{ 3522292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3532292SN/A scoreboard = sb_ptr; 3541060SN/A} 3551060SN/A 3562307SN/Atemplate <class Impl> 3572863Sktlim@umich.edubool 3582843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3592307SN/A{ 3602843Sktlim@umich.edu // IEW is ready to drain at any time. 3612843Sktlim@umich.edu cpu->signalDrained(); 3622863Sktlim@umich.edu return true; 3631681SN/A} 3641681SN/A 3652316SN/Atemplate <class Impl> 3661681SN/Avoid 3672843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3682843Sktlim@umich.edu{ 3692843Sktlim@umich.edu} 3702843Sktlim@umich.edu 3712843Sktlim@umich.edutemplate <class Impl> 3722843Sktlim@umich.eduvoid 3732843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3741681SN/A{ 3752348SN/A // Clear any state. 3762307SN/A switchedOut = true; 3771681SN/A 3782307SN/A instQueue.switchOut(); 3792307SN/A ldstQueue.switchOut(); 3802307SN/A fuPool->switchOut(); 3812307SN/A 3822307SN/A for (int i = 0; i < numThreads; i++) { 3832307SN/A while (!insts[i].empty()) 3842307SN/A insts[i].pop(); 3852307SN/A while (!skidBuffer[i].empty()) 3862307SN/A skidBuffer[i].pop(); 3872307SN/A } 3881681SN/A} 3891681SN/A 3902307SN/Atemplate <class Impl> 3911681SN/Avoid 3922307SN/ADefaultIEW<Impl>::takeOverFrom() 3931060SN/A{ 3942348SN/A // Reset all state. 3952307SN/A _status = Active; 3962307SN/A exeStatus = Running; 3972307SN/A wbStatus = Idle; 3982307SN/A switchedOut = false; 3991060SN/A 4002307SN/A instQueue.takeOverFrom(); 4012307SN/A ldstQueue.takeOverFrom(); 4022307SN/A fuPool->takeOverFrom(); 4031060SN/A 4042307SN/A initStage(); 4052307SN/A cpu->activityThisCycle(); 4061060SN/A 4072307SN/A for (int i=0; i < numThreads; i++) { 4082307SN/A dispatchStatus[i] = Running; 4092307SN/A stalls[i].commit = false; 4102307SN/A fetchRedirect[i] = false; 4112307SN/A } 4121060SN/A 4132307SN/A updateLSQNextCycle = false; 4142307SN/A 4152307SN/A // @todo: Fix hardcoded number 4162307SN/A for (int i = 0; i < 6; ++i) { 4172307SN/A issueToExecQueue.advance(); 4181060SN/A } 4191060SN/A} 4201060SN/A 4211681SN/Atemplate<class Impl> 4221060SN/Avoid 4232292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4242107SN/A{ 4252292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4262292SN/A tid); 4272107SN/A 4282292SN/A // Tell the IQ to start squashing. 4292292SN/A instQueue.squash(tid); 4302107SN/A 4312292SN/A // Tell the LDSTQ to start squashing. 4322326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4332107SN/A 4342292SN/A updatedQueues = true; 4352107SN/A 4362292SN/A // Clear the skid buffer in case it has any data in it. 4372292SN/A while (!skidBuffer[tid].empty()) { 4382107SN/A 4392292SN/A if (skidBuffer[tid].front()->isLoad() || 4402292SN/A skidBuffer[tid].front()->isStore() ) { 4412292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4422292SN/A } 4432107SN/A 4442292SN/A toRename->iewInfo[tid].dispatched++; 4452107SN/A 4462292SN/A skidBuffer[tid].pop(); 4472292SN/A } 4482107SN/A 4492702Sktlim@umich.edu emptyRenameInsts(tid); 4502107SN/A} 4512107SN/A 4522107SN/Atemplate<class Impl> 4532107SN/Avoid 4542292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4552292SN/A{ 4562292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4572292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4582292SN/A 4592292SN/A toCommit->squash[tid] = true; 4602292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4612292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4622292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4632292SN/A toCommit->branchMispredict[tid] = true; 4642292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4652292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4662292SN/A 4672292SN/A toCommit->includeSquashInst[tid] = false; 4682292SN/A 4692292SN/A wroteToTimeBuffer = true; 4702292SN/A} 4712292SN/A 4722292SN/Atemplate<class Impl> 4732292SN/Avoid 4742292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4752292SN/A{ 4762292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4772292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4782292SN/A 4792292SN/A toCommit->squash[tid] = true; 4802292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4812292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4822292SN/A 4832292SN/A toCommit->includeSquashInst[tid] = false; 4842292SN/A 4852292SN/A wroteToTimeBuffer = true; 4862292SN/A} 4872292SN/A 4882292SN/Atemplate<class Impl> 4892292SN/Avoid 4902292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 4912292SN/A{ 4922292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4932292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4942292SN/A 4952292SN/A toCommit->squash[tid] = true; 4962292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4972292SN/A toCommit->nextPC[tid] = inst->readPC(); 4982292SN/A 4992348SN/A // Must include the broadcasted SN in the squash. 5002292SN/A toCommit->includeSquashInst[tid] = true; 5012292SN/A 5022292SN/A ldstQueue.setLoadBlockedHandled(tid); 5032292SN/A 5042292SN/A wroteToTimeBuffer = true; 5052292SN/A} 5062292SN/A 5072292SN/Atemplate<class Impl> 5082292SN/Avoid 5092292SN/ADefaultIEW<Impl>::block(unsigned tid) 5102292SN/A{ 5112292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5122292SN/A 5132292SN/A if (dispatchStatus[tid] != Blocked && 5142292SN/A dispatchStatus[tid] != Unblocking) { 5152292SN/A toRename->iewBlock[tid] = true; 5162292SN/A wroteToTimeBuffer = true; 5172292SN/A } 5182292SN/A 5192292SN/A // Add the current inputs to the skid buffer so they can be 5202292SN/A // reprocessed when this stage unblocks. 5212292SN/A skidInsert(tid); 5222292SN/A 5232292SN/A dispatchStatus[tid] = Blocked; 5242292SN/A} 5252292SN/A 5262292SN/Atemplate<class Impl> 5272292SN/Avoid 5282292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5292292SN/A{ 5302292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5312292SN/A "buffer %u.\n",tid, tid); 5322292SN/A 5332292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5342292SN/A // Also switch status to running. 5352292SN/A if (skidBuffer[tid].empty()) { 5362292SN/A toRename->iewUnblock[tid] = true; 5372292SN/A wroteToTimeBuffer = true; 5382292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5392292SN/A dispatchStatus[tid] = Running; 5402292SN/A } 5412292SN/A} 5422292SN/A 5432292SN/Atemplate<class Impl> 5442292SN/Avoid 5452292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5461060SN/A{ 5471681SN/A instQueue.wakeDependents(inst); 5481060SN/A} 5491060SN/A 5502292SN/Atemplate<class Impl> 5512292SN/Avoid 5522292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5532292SN/A{ 5542292SN/A instQueue.rescheduleMemInst(inst); 5552292SN/A} 5561681SN/A 5571681SN/Atemplate<class Impl> 5581060SN/Avoid 5592292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5601060SN/A{ 5612292SN/A instQueue.replayMemInst(inst); 5622292SN/A} 5631060SN/A 5642292SN/Atemplate<class Impl> 5652292SN/Avoid 5662292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5672292SN/A{ 5682292SN/A // First check the time slot that this instruction will write 5692292SN/A // to. If there are free write ports at the time, then go ahead 5702292SN/A // and write the instruction to that time. If there are not, 5712292SN/A // keep looking back to see where's the first time there's a 5722326SN/A // free slot. 5732292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5742292SN/A ++wbNumInst; 5752820Sktlim@umich.edu if (wbNumInst == wbWidth) { 5762292SN/A ++wbCycle; 5772292SN/A wbNumInst = 0; 5782292SN/A } 5792292SN/A 5802820Sktlim@umich.edu assert((wbCycle * wbWidth + wbNumInst) < wbMax); 5812292SN/A } 5822292SN/A 5832292SN/A // Add finished instruction to queue to commit. 5842292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5852292SN/A (*iewQueue)[wbCycle].size++; 5862292SN/A} 5872292SN/A 5882292SN/Atemplate <class Impl> 5892292SN/Aunsigned 5902292SN/ADefaultIEW<Impl>::validInstsFromRename() 5912292SN/A{ 5922292SN/A unsigned inst_count = 0; 5932292SN/A 5942292SN/A for (int i=0; i<fromRename->size; i++) { 5952731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 5962292SN/A inst_count++; 5972292SN/A } 5982292SN/A 5992292SN/A return inst_count; 6002292SN/A} 6012292SN/A 6022292SN/Atemplate<class Impl> 6032292SN/Avoid 6042292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6052292SN/A{ 6062292SN/A DynInstPtr inst = NULL; 6072292SN/A 6082292SN/A while (!insts[tid].empty()) { 6092292SN/A inst = insts[tid].front(); 6102292SN/A 6112292SN/A insts[tid].pop(); 6122292SN/A 6132292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6142292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6152292SN/A inst->readPC(),tid); 6162292SN/A 6172292SN/A skidBuffer[tid].push(inst); 6182292SN/A } 6192292SN/A 6202292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6212292SN/A "Skidbuffer Exceeded Max Size"); 6222292SN/A} 6232292SN/A 6242292SN/Atemplate<class Impl> 6252292SN/Aint 6262292SN/ADefaultIEW<Impl>::skidCount() 6272292SN/A{ 6282292SN/A int max=0; 6292292SN/A 6302292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6312292SN/A 6322292SN/A while (threads != (*activeThreads).end()) { 6332292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6342292SN/A if (max < thread_count) 6352292SN/A max = thread_count; 6362292SN/A } 6372292SN/A 6382292SN/A return max; 6392292SN/A} 6402292SN/A 6412292SN/Atemplate<class Impl> 6422292SN/Abool 6432292SN/ADefaultIEW<Impl>::skidsEmpty() 6442292SN/A{ 6452292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6462292SN/A 6472292SN/A while (threads != (*activeThreads).end()) { 6482292SN/A if (!skidBuffer[*threads++].empty()) 6492292SN/A return false; 6502292SN/A } 6512292SN/A 6522292SN/A return true; 6531062SN/A} 6541062SN/A 6551681SN/Atemplate <class Impl> 6561062SN/Avoid 6572292SN/ADefaultIEW<Impl>::updateStatus() 6581062SN/A{ 6592292SN/A bool any_unblocking = false; 6601062SN/A 6612292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6621062SN/A 6632292SN/A threads = (*activeThreads).begin(); 6641062SN/A 6652292SN/A while (threads != (*activeThreads).end()) { 6662292SN/A unsigned tid = *threads++; 6671062SN/A 6682292SN/A if (dispatchStatus[tid] == Unblocking) { 6692292SN/A any_unblocking = true; 6702292SN/A break; 6712292SN/A } 6722292SN/A } 6731062SN/A 6742292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6752292SN/A // and there's no stores waiting to write back, and dispatch is not 6762292SN/A // unblocking, then there is no internal activity for the IEW stage. 6772292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6782292SN/A !ldstQueue.willWB() && !any_unblocking) { 6792292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6801062SN/A 6812292SN/A deactivateStage(); 6821062SN/A 6832292SN/A _status = Inactive; 6842292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6852292SN/A ldstQueue.willWB() || 6862292SN/A any_unblocking)) { 6872292SN/A // Otherwise there is internal activity. Set to active. 6882292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6891062SN/A 6902292SN/A activateStage(); 6911062SN/A 6922292SN/A _status = Active; 6931062SN/A } 6941062SN/A} 6951062SN/A 6961681SN/Atemplate <class Impl> 6971062SN/Avoid 6982292SN/ADefaultIEW<Impl>::resetEntries() 6991062SN/A{ 7002292SN/A instQueue.resetEntries(); 7012292SN/A ldstQueue.resetEntries(); 7022292SN/A} 7031062SN/A 7042292SN/Atemplate <class Impl> 7052292SN/Avoid 7062292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7072292SN/A{ 7082292SN/A if (fromCommit->commitBlock[tid]) { 7092292SN/A stalls[tid].commit = true; 7102292SN/A } 7111062SN/A 7122292SN/A if (fromCommit->commitUnblock[tid]) { 7132292SN/A assert(stalls[tid].commit); 7142292SN/A stalls[tid].commit = false; 7152292SN/A } 7162292SN/A} 7172292SN/A 7182292SN/Atemplate <class Impl> 7192292SN/Abool 7202292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7212292SN/A{ 7222292SN/A bool ret_val(false); 7232292SN/A 7242292SN/A if (stalls[tid].commit) { 7252292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7262292SN/A ret_val = true; 7272292SN/A } else if (instQueue.isFull(tid)) { 7282292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7292292SN/A ret_val = true; 7302292SN/A } else if (ldstQueue.isFull(tid)) { 7312292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7322292SN/A 7332292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7342292SN/A 7352292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7362292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7372292SN/A } 7382292SN/A 7392292SN/A if (ldstQueue.numStores(tid) > 0) { 7402292SN/A 7412292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7422292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7432292SN/A } 7442292SN/A 7452292SN/A ret_val = true; 7462292SN/A } else if (ldstQueue.isStalled(tid)) { 7472292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7482292SN/A ret_val = true; 7492292SN/A } 7502292SN/A 7512292SN/A return ret_val; 7522292SN/A} 7532292SN/A 7542292SN/Atemplate <class Impl> 7552292SN/Avoid 7562292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7572292SN/A{ 7582292SN/A // Check if there's a squash signal, squash if there is 7592292SN/A // Check stall signals, block if there is. 7602292SN/A // If status was Blocked 7612292SN/A // if so then go to unblocking 7622292SN/A // If status was Squashing 7632292SN/A // check if squashing is not high. Switch to running this cycle. 7642292SN/A 7652292SN/A readStallSignals(tid); 7662292SN/A 7672292SN/A if (fromCommit->commitInfo[tid].squash) { 7682292SN/A squash(tid); 7692292SN/A 7702292SN/A if (dispatchStatus[tid] == Blocked || 7712292SN/A dispatchStatus[tid] == Unblocking) { 7722292SN/A toRename->iewUnblock[tid] = true; 7732292SN/A wroteToTimeBuffer = true; 7742292SN/A } 7752292SN/A 7762292SN/A dispatchStatus[tid] = Squashing; 7772292SN/A 7782292SN/A fetchRedirect[tid] = false; 7792292SN/A return; 7802292SN/A } 7812292SN/A 7822292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7832702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7842292SN/A 7852292SN/A dispatchStatus[tid] = Squashing; 7862292SN/A 7872702Sktlim@umich.edu emptyRenameInsts(tid); 7882702Sktlim@umich.edu wroteToTimeBuffer = true; 7892292SN/A return; 7902292SN/A } 7912292SN/A 7922292SN/A if (checkStall(tid)) { 7932292SN/A block(tid); 7942292SN/A dispatchStatus[tid] = Blocked; 7952292SN/A return; 7962292SN/A } 7972292SN/A 7982292SN/A if (dispatchStatus[tid] == Blocked) { 7992292SN/A // Status from previous cycle was blocked, but there are no more stall 8002292SN/A // conditions. Switch over to unblocking. 8012292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8022292SN/A tid); 8032292SN/A 8042292SN/A dispatchStatus[tid] = Unblocking; 8052292SN/A 8062292SN/A unblock(tid); 8072292SN/A 8082292SN/A return; 8092292SN/A } 8102292SN/A 8112292SN/A if (dispatchStatus[tid] == Squashing) { 8122292SN/A // Switch status to running if rename isn't being told to block or 8132292SN/A // squash this cycle. 8142292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8152292SN/A tid); 8162292SN/A 8172292SN/A dispatchStatus[tid] = Running; 8182292SN/A 8192292SN/A return; 8202292SN/A } 8212292SN/A} 8222292SN/A 8232292SN/Atemplate <class Impl> 8242292SN/Avoid 8252292SN/ADefaultIEW<Impl>::sortInsts() 8262292SN/A{ 8272292SN/A int insts_from_rename = fromRename->size; 8282326SN/A#ifdef DEBUG 8292292SN/A for (int i = 0; i < numThreads; i++) 8302292SN/A assert(insts[i].empty()); 8312326SN/A#endif 8322292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8332292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8342292SN/A } 8352292SN/A} 8362292SN/A 8372292SN/Atemplate <class Impl> 8382292SN/Avoid 8392702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8402702Sktlim@umich.edu{ 8412702Sktlim@umich.edu while (!insts[tid].empty()) { 8422702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8432702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8442702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8452702Sktlim@umich.edu } 8462702Sktlim@umich.edu 8472702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8482702Sktlim@umich.edu 8492702Sktlim@umich.edu insts[tid].pop(); 8502702Sktlim@umich.edu } 8512702Sktlim@umich.edu} 8522702Sktlim@umich.edu 8532702Sktlim@umich.edutemplate <class Impl> 8542702Sktlim@umich.eduvoid 8552292SN/ADefaultIEW<Impl>::wakeCPU() 8562292SN/A{ 8572292SN/A cpu->wakeCPU(); 8582292SN/A} 8592292SN/A 8602292SN/Atemplate <class Impl> 8612292SN/Avoid 8622292SN/ADefaultIEW<Impl>::activityThisCycle() 8632292SN/A{ 8642292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8652292SN/A cpu->activityThisCycle(); 8662292SN/A} 8672292SN/A 8682292SN/Atemplate <class Impl> 8692292SN/Ainline void 8702292SN/ADefaultIEW<Impl>::activateStage() 8712292SN/A{ 8722292SN/A DPRINTF(Activity, "Activating stage.\n"); 8732733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8742292SN/A} 8752292SN/A 8762292SN/Atemplate <class Impl> 8772292SN/Ainline void 8782292SN/ADefaultIEW<Impl>::deactivateStage() 8792292SN/A{ 8802292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8812733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8822292SN/A} 8832292SN/A 8842292SN/Atemplate<class Impl> 8852292SN/Avoid 8862292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8872292SN/A{ 8882292SN/A // If status is Running or idle, 8892292SN/A // call dispatchInsts() 8902292SN/A // If status is Unblocking, 8912292SN/A // buffer any instructions coming from rename 8922292SN/A // continue trying to empty skid buffer 8932292SN/A // check if stall conditions have passed 8942292SN/A 8952292SN/A if (dispatchStatus[tid] == Blocked) { 8962292SN/A ++iewBlockCycles; 8972292SN/A 8982292SN/A } else if (dispatchStatus[tid] == Squashing) { 8992292SN/A ++iewSquashCycles; 9002292SN/A } 9012292SN/A 9022292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9032292SN/A // will allow, as long as it is not currently blocked. 9042292SN/A if (dispatchStatus[tid] == Running || 9052292SN/A dispatchStatus[tid] == Idle) { 9062292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9072292SN/A "dispatch.\n", tid); 9082292SN/A 9092292SN/A dispatchInsts(tid); 9102292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9112292SN/A // Make sure that the skid buffer has something in it if the 9122292SN/A // status is unblocking. 9132292SN/A assert(!skidsEmpty()); 9142292SN/A 9152292SN/A // If the status was unblocking, then instructions from the skid 9162292SN/A // buffer were used. Remove those instructions and handle 9172292SN/A // the rest of unblocking. 9182292SN/A dispatchInsts(tid); 9192292SN/A 9202292SN/A ++iewUnblockCycles; 9212292SN/A 9222292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9232292SN/A // Add the current inputs to the skid buffer so they can be 9242292SN/A // reprocessed when this stage unblocks. 9252292SN/A skidInsert(tid); 9262292SN/A } 9272292SN/A 9282292SN/A unblock(tid); 9292292SN/A } 9302292SN/A} 9312292SN/A 9322292SN/Atemplate <class Impl> 9332292SN/Avoid 9342292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9352292SN/A{ 9362292SN/A dispatchedAllInsts = true; 9372292SN/A 9382292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9392292SN/A // otherwise. 9402292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9412292SN/A dispatchStatus[tid] == Unblocking ? 9422292SN/A skidBuffer[tid] : insts[tid]; 9432292SN/A 9442292SN/A int insts_to_add = insts_to_dispatch.size(); 9452292SN/A 9462292SN/A DynInstPtr inst; 9472292SN/A bool add_to_iq = false; 9482292SN/A int dis_num_inst = 0; 9492292SN/A 9502292SN/A // Loop through the instructions, putting them in the instruction 9512292SN/A // queue. 9522292SN/A for ( ; dis_num_inst < insts_to_add && 9532820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9542292SN/A ++dis_num_inst) 9552292SN/A { 9562292SN/A inst = insts_to_dispatch.front(); 9572292SN/A 9582292SN/A if (dispatchStatus[tid] == Unblocking) { 9592292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9602292SN/A "buffer\n", tid); 9612292SN/A } 9622292SN/A 9632292SN/A // Make sure there's a valid instruction there. 9642292SN/A assert(inst); 9652292SN/A 9662292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9672292SN/A "IQ.\n", 9682292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9692292SN/A 9702292SN/A // Be sure to mark these instructions as ready so that the 9712292SN/A // commit stage can go ahead and execute them, and mark 9722292SN/A // them as issued so the IQ doesn't reprocess them. 9732292SN/A 9742292SN/A // Check for squashed instructions. 9752292SN/A if (inst->isSquashed()) { 9762292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9772292SN/A "not adding to IQ.\n", tid); 9782292SN/A 9792292SN/A ++iewDispSquashedInsts; 9802292SN/A 9812292SN/A insts_to_dispatch.pop(); 9822292SN/A 9832292SN/A //Tell Rename That An Instruction has been processed 9842292SN/A if (inst->isLoad() || inst->isStore()) { 9852292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9862292SN/A } 9872292SN/A toRename->iewInfo[tid].dispatched++; 9882292SN/A 9892292SN/A continue; 9902292SN/A } 9912292SN/A 9922292SN/A // Check for full conditions. 9932292SN/A if (instQueue.isFull(tid)) { 9942292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 9952292SN/A 9962292SN/A // Call function to start blocking. 9972292SN/A block(tid); 9982292SN/A 9992292SN/A // Set unblock to false. Special case where we are using 10002292SN/A // skidbuffer (unblocking) instructions but then we still 10012292SN/A // get full in the IQ. 10022292SN/A toRename->iewUnblock[tid] = false; 10032292SN/A 10042292SN/A dispatchedAllInsts = false; 10052292SN/A 10062292SN/A ++iewIQFullEvents; 10072292SN/A break; 10082292SN/A } else if (ldstQueue.isFull(tid)) { 10092292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10102292SN/A 10112292SN/A // Call function to start blocking. 10122292SN/A block(tid); 10132292SN/A 10142292SN/A // Set unblock to false. Special case where we are using 10152292SN/A // skidbuffer (unblocking) instructions but then we still 10162292SN/A // get full in the IQ. 10172292SN/A toRename->iewUnblock[tid] = false; 10182292SN/A 10192292SN/A dispatchedAllInsts = false; 10202292SN/A 10212292SN/A ++iewLSQFullEvents; 10222292SN/A break; 10232292SN/A } 10242292SN/A 10252292SN/A // Otherwise issue the instruction just fine. 10262292SN/A if (inst->isLoad()) { 10272292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10282292SN/A "encountered, adding to LSQ.\n", tid); 10292292SN/A 10302292SN/A // Reserve a spot in the load store queue for this 10312292SN/A // memory access. 10322292SN/A ldstQueue.insertLoad(inst); 10332292SN/A 10342292SN/A ++iewDispLoadInsts; 10352292SN/A 10362292SN/A add_to_iq = true; 10372292SN/A 10382292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10392292SN/A } else if (inst->isStore()) { 10402292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10412292SN/A "encountered, adding to LSQ.\n", tid); 10422292SN/A 10432292SN/A ldstQueue.insertStore(inst); 10442292SN/A 10452292SN/A ++iewDispStoreInsts; 10462292SN/A 10472336SN/A if (inst->isStoreConditional()) { 10482336SN/A // Store conditionals need to be set as "canCommit()" 10492336SN/A // so that commit can process them when they reach the 10502336SN/A // head of commit. 10512348SN/A // @todo: This is somewhat specific to Alpha. 10522292SN/A inst->setCanCommit(); 10532292SN/A instQueue.insertNonSpec(inst); 10542292SN/A add_to_iq = false; 10552292SN/A 10562292SN/A ++iewDispNonSpecInsts; 10572292SN/A } else { 10582292SN/A add_to_iq = true; 10592292SN/A } 10602292SN/A 10612292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10622292SN/A#if FULL_SYSTEM 10632292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10642326SN/A // Same as non-speculative stores. 10652292SN/A inst->setCanCommit(); 10662292SN/A instQueue.insertBarrier(inst); 10672292SN/A add_to_iq = false; 10682292SN/A#endif 10692292SN/A } else if (inst->isNonSpeculative()) { 10702292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 10712292SN/A "encountered, skipping.\n", tid); 10722292SN/A 10732326SN/A // Same as non-speculative stores. 10742292SN/A inst->setCanCommit(); 10752292SN/A 10762292SN/A // Specifically insert it as nonspeculative. 10772292SN/A instQueue.insertNonSpec(inst); 10782292SN/A 10792292SN/A ++iewDispNonSpecInsts; 10802292SN/A 10812292SN/A add_to_iq = false; 10822292SN/A } else if (inst->isNop()) { 10832292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10842292SN/A "skipping.\n", tid); 10852292SN/A 10862292SN/A inst->setIssued(); 10872292SN/A inst->setExecuted(); 10882292SN/A inst->setCanCommit(); 10892292SN/A 10902326SN/A instQueue.recordProducer(inst); 10912292SN/A 10922727Sktlim@umich.edu iewExecutedNop[tid]++; 10932301SN/A 10942292SN/A add_to_iq = false; 10952292SN/A } else if (inst->isExecuted()) { 10962292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10972292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10982292SN/A "skipping.\n"); 10992292SN/A 11002292SN/A inst->setIssued(); 11012292SN/A inst->setCanCommit(); 11022292SN/A 11032326SN/A instQueue.recordProducer(inst); 11042292SN/A 11052292SN/A add_to_iq = false; 11062292SN/A } else { 11072292SN/A add_to_iq = true; 11082292SN/A } 11092292SN/A 11102292SN/A // If the instruction queue is not full, then add the 11112292SN/A // instruction. 11122292SN/A if (add_to_iq) { 11132292SN/A instQueue.insert(inst); 11142292SN/A } 11152292SN/A 11162292SN/A insts_to_dispatch.pop(); 11172292SN/A 11182292SN/A toRename->iewInfo[tid].dispatched++; 11192292SN/A 11202292SN/A ++iewDispatchedInsts; 11212292SN/A } 11222292SN/A 11232292SN/A if (!insts_to_dispatch.empty()) { 11242292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11252292SN/A block(tid); 11262292SN/A toRename->iewUnblock[tid] = false; 11272292SN/A } 11282292SN/A 11292292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11302292SN/A dispatchStatus[tid] = Running; 11312292SN/A 11322292SN/A updatedQueues = true; 11332292SN/A } 11342292SN/A 11352292SN/A dis_num_inst = 0; 11362292SN/A} 11372292SN/A 11382292SN/Atemplate <class Impl> 11392292SN/Avoid 11402292SN/ADefaultIEW<Impl>::printAvailableInsts() 11412292SN/A{ 11422292SN/A int inst = 0; 11432292SN/A 11442292SN/A cout << "Available Instructions: "; 11452292SN/A 11462292SN/A while (fromIssue->insts[inst]) { 11472292SN/A 11482292SN/A if (inst%3==0) cout << "\n\t"; 11492292SN/A 11502292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 11512292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11522292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11532292SN/A 11542292SN/A inst++; 11552292SN/A 11562292SN/A } 11572292SN/A 11582292SN/A cout << "\n"; 11592292SN/A} 11602292SN/A 11612292SN/Atemplate <class Impl> 11622292SN/Avoid 11632292SN/ADefaultIEW<Impl>::executeInsts() 11642292SN/A{ 11652292SN/A wbNumInst = 0; 11662292SN/A wbCycle = 0; 11672292SN/A 11682292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11692292SN/A 11702292SN/A while (threads != (*activeThreads).end()) { 11712292SN/A unsigned tid = *threads++; 11722292SN/A fetchRedirect[tid] = false; 11732292SN/A } 11742292SN/A 11752698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11762698Sktlim@umich.edu// printAvailableInsts(); 11771062SN/A 11781062SN/A // Execute/writeback any instructions that are available. 11792333SN/A int insts_to_execute = fromIssue->size; 11802292SN/A int inst_num = 0; 11812333SN/A for (; inst_num < insts_to_execute; 11822326SN/A ++inst_num) { 11831062SN/A 11842292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11851062SN/A 11862333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11871062SN/A 11882292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11892292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11901062SN/A 11911062SN/A // Check if the instruction is squashed; if so then skip it 11921062SN/A if (inst->isSquashed()) { 11932292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 11941062SN/A 11951062SN/A // Consider this instruction executed so that commit can go 11961062SN/A // ahead and retire the instruction. 11971062SN/A inst->setExecuted(); 11981062SN/A 11992292SN/A // Not sure if I should set this here or just let commit try to 12002292SN/A // commit any squashed instructions. I like the latter a bit more. 12012292SN/A inst->setCanCommit(); 12021062SN/A 12031062SN/A ++iewExecSquashedInsts; 12041062SN/A 12052820Sktlim@umich.edu decrWb(inst->seqNum); 12061062SN/A continue; 12071062SN/A } 12081062SN/A 12092292SN/A Fault fault = NoFault; 12101062SN/A 12111062SN/A // Execute instruction. 12121062SN/A // Note that if the instruction faults, it will be handled 12131062SN/A // at the commit stage. 12142292SN/A if (inst->isMemRef() && 12152292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12162292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12171062SN/A "reference.\n"); 12181062SN/A 12191062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12201062SN/A if (inst->isLoad()) { 12212292SN/A // Loads will mark themselves as executed, and their writeback 12222292SN/A // event adds the instruction to the queue to commit 12232292SN/A fault = ldstQueue.executeLoad(inst); 12241062SN/A } else if (inst->isStore()) { 12251681SN/A ldstQueue.executeStore(inst); 12261062SN/A 12272292SN/A // If the store had a fault then it may not have a mem req 12282669Sktlim@umich.edu if (inst->req && !(inst->req->getFlags() & LOCKED)) { 12292292SN/A inst->setExecuted(); 12302292SN/A 12312292SN/A instToCommit(inst); 12322292SN/A } 12332326SN/A 12342326SN/A // Store conditionals will mark themselves as 12352326SN/A // executed, and their writeback event will add the 12362326SN/A // instruction to the queue to commit. 12371062SN/A } else { 12382292SN/A panic("Unexpected memory type!\n"); 12391062SN/A } 12401062SN/A 12411062SN/A } else { 12421062SN/A inst->execute(); 12431062SN/A 12442292SN/A inst->setExecuted(); 12452292SN/A 12462292SN/A instToCommit(inst); 12471062SN/A } 12481062SN/A 12492301SN/A updateExeInstStats(inst); 12501681SN/A 12512326SN/A // Check if branch prediction was correct, if not then we need 12522326SN/A // to tell commit to squash in flight instructions. Only 12532326SN/A // handle this if there hasn't already been something that 12542107SN/A // redirects fetch in this group of instructions. 12551681SN/A 12562292SN/A // This probably needs to prioritize the redirects if a different 12572292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12582292SN/A // instruction first, so the branch resolution order will be correct. 12592292SN/A unsigned tid = inst->threadNumber; 12601062SN/A 12612292SN/A if (!fetchRedirect[tid]) { 12621062SN/A 12631062SN/A if (inst->mispredicted()) { 12642292SN/A fetchRedirect[tid] = true; 12651062SN/A 12662292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12672292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 12681062SN/A inst->nextPC); 12691062SN/A 12701062SN/A // If incorrect, then signal the ROB that it must be squashed. 12712292SN/A squashDueToBranch(inst, tid); 12721062SN/A 12731062SN/A if (inst->predTaken()) { 12741062SN/A predictedTakenIncorrect++; 12752292SN/A } else { 12762292SN/A predictedNotTakenIncorrect++; 12771062SN/A } 12782292SN/A } else if (ldstQueue.violation(tid)) { 12792292SN/A fetchRedirect[tid] = true; 12801062SN/A 12812326SN/A // If there was an ordering violation, then get the 12822326SN/A // DynInst that caused the violation. Note that this 12832292SN/A // clears the violation signal. 12842292SN/A DynInstPtr violator; 12852292SN/A violator = ldstQueue.getMemDepViolator(tid); 12861062SN/A 12872292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 12881062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 12891062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 12901062SN/A 12911062SN/A // Tell the instruction queue that a violation has occured. 12921062SN/A instQueue.violation(inst, violator); 12931062SN/A 12941062SN/A // Squash. 12952292SN/A squashDueToMemOrder(inst,tid); 12961062SN/A 12971062SN/A ++memOrderViolationEvents; 12982292SN/A } else if (ldstQueue.loadBlocked(tid) && 12992292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13002292SN/A fetchRedirect[tid] = true; 13012292SN/A 13022292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13032292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13042292SN/A inst->readPC(), inst->seqNum); 13052292SN/A 13062292SN/A squashDueToMemBlocked(inst, tid); 13071062SN/A } 13081062SN/A } 13091062SN/A } 13102292SN/A 13112348SN/A // Update and record activity if we processed any instructions. 13122292SN/A if (inst_num) { 13132292SN/A if (exeStatus == Idle) { 13142292SN/A exeStatus = Running; 13152292SN/A } 13162292SN/A 13172292SN/A updatedQueues = true; 13182292SN/A 13192292SN/A cpu->activityThisCycle(); 13202292SN/A } 13212292SN/A 13222292SN/A // Need to reset this in case a writeback event needs to write into the 13232292SN/A // iew queue. That way the writeback event will write into the correct 13242292SN/A // spot in the queue. 13252292SN/A wbNumInst = 0; 13262107SN/A} 13272107SN/A 13282292SN/Atemplate <class Impl> 13292107SN/Avoid 13302292SN/ADefaultIEW<Impl>::writebackInsts() 13312107SN/A{ 13322326SN/A // Loop through the head of the time buffer and wake any 13332326SN/A // dependents. These instructions are about to write back. Also 13342326SN/A // mark scoreboard that this instruction is finally complete. 13352326SN/A // Either have IEW have direct access to scoreboard, or have this 13362326SN/A // as part of backwards communication. 13372107SN/A for (int inst_num = 0; inst_num < issueWidth && 13382292SN/A toCommit->insts[inst_num]; inst_num++) { 13392107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13402301SN/A int tid = inst->threadNumber; 13412107SN/A 13422698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13432698Sktlim@umich.edu inst->seqNum, inst->readPC()); 13442107SN/A 13452301SN/A iewInstsToCommit[tid]++; 13462301SN/A 13472292SN/A // Some instructions will be sent to commit without having 13482292SN/A // executed because they need commit to handle them. 13492292SN/A // E.g. Uncached loads have not actually executed when they 13502292SN/A // are first sent to commit. Instead commit must tell the LSQ 13512292SN/A // when it's ready to execute the uncached load. 13522292SN/A if (!inst->isSquashed() && inst->isExecuted()) { 13532301SN/A int dependents = instQueue.wakeDependents(inst); 13542107SN/A 13552292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 13562292SN/A //mark as Ready 13572292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 13582292SN/A inst->renamedDestRegIdx(i)); 13592292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 13602107SN/A } 13612301SN/A 13622348SN/A if (dependents) { 13632348SN/A producerInst[tid]++; 13642348SN/A consumerInst[tid]+= dependents; 13652348SN/A } 13662326SN/A writebackCount[tid]++; 13672107SN/A } 13682820Sktlim@umich.edu 13692820Sktlim@umich.edu decrWb(inst->seqNum); 13702107SN/A } 13711060SN/A} 13721060SN/A 13731681SN/Atemplate<class Impl> 13741060SN/Avoid 13752292SN/ADefaultIEW<Impl>::tick() 13761060SN/A{ 13772292SN/A wbNumInst = 0; 13782292SN/A wbCycle = 0; 13791060SN/A 13802292SN/A wroteToTimeBuffer = false; 13812292SN/A updatedQueues = false; 13821060SN/A 13832292SN/A sortInsts(); 13841060SN/A 13852326SN/A // Free function units marked as being freed this cycle. 13862326SN/A fuPool->processFreeUnits(); 13871062SN/A 13882292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 13891060SN/A 13902326SN/A // Check stall and squash signals, dispatch any instructions. 13912292SN/A while (threads != (*activeThreads).end()) { 13922292SN/A unsigned tid = *threads++; 13931060SN/A 13942292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 13951060SN/A 13962292SN/A checkSignalsAndUpdate(tid); 13972292SN/A dispatch(tid); 13981060SN/A } 13991060SN/A 14002292SN/A if (exeStatus != Squashing) { 14012292SN/A executeInsts(); 14021060SN/A 14032292SN/A writebackInsts(); 14042292SN/A 14052292SN/A // Have the instruction queue try to schedule any ready instructions. 14062292SN/A // (In actuality, this scheduling is for instructions that will 14072292SN/A // be executed next cycle.) 14082292SN/A instQueue.scheduleReadyInsts(); 14092292SN/A 14102292SN/A // Also should advance its own time buffers if the stage ran. 14112292SN/A // Not the best place for it, but this works (hopefully). 14122292SN/A issueToExecQueue.advance(); 14132292SN/A } 14142292SN/A 14152292SN/A bool broadcast_free_entries = false; 14162292SN/A 14172292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14182292SN/A exeStatus = Idle; 14192292SN/A updateLSQNextCycle = false; 14202292SN/A 14212292SN/A broadcast_free_entries = true; 14222292SN/A } 14232292SN/A 14242292SN/A // Writeback any stores using any leftover bandwidth. 14251681SN/A ldstQueue.writebackStores(); 14261681SN/A 14271061SN/A // Check the committed load/store signals to see if there's a load 14281061SN/A // or store to commit. Also check if it's being told to execute a 14291061SN/A // nonspeculative instruction. 14301681SN/A // This is pretty inefficient... 14312292SN/A 14322292SN/A threads = (*activeThreads).begin(); 14332292SN/A while (threads != (*activeThreads).end()) { 14342292SN/A unsigned tid = (*threads++); 14352292SN/A 14362292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14372292SN/A 14382348SN/A // Update structures based on instructions committed. 14392292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14402292SN/A !fromCommit->commitInfo[tid].squash && 14412292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14422292SN/A 14432292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14442292SN/A 14452292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14462292SN/A 14472292SN/A updateLSQNextCycle = true; 14482292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14492292SN/A } 14502292SN/A 14512292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 14522292SN/A 14532292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 14542292SN/A if (fromCommit->commitInfo[tid].uncached) { 14552292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 14562292SN/A } else { 14572292SN/A instQueue.scheduleNonSpec( 14582292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 14592292SN/A } 14602292SN/A } 14612292SN/A 14622292SN/A if (broadcast_free_entries) { 14632292SN/A toFetch->iewInfo[tid].iqCount = 14642292SN/A instQueue.getCount(tid); 14652292SN/A toFetch->iewInfo[tid].ldstqCount = 14662292SN/A ldstQueue.getCount(tid); 14672292SN/A 14682292SN/A toRename->iewInfo[tid].usedIQ = true; 14692292SN/A toRename->iewInfo[tid].freeIQEntries = 14702292SN/A instQueue.numFreeEntries(); 14712292SN/A toRename->iewInfo[tid].usedLSQ = true; 14722292SN/A toRename->iewInfo[tid].freeLSQEntries = 14732292SN/A ldstQueue.numFreeEntries(tid); 14742292SN/A 14752292SN/A wroteToTimeBuffer = true; 14762292SN/A } 14772292SN/A 14782292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 14792292SN/A tid, toRename->iewInfo[tid].dispatched); 14801061SN/A } 14811061SN/A 14822292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 14832292SN/A "LSQ has %i free entries.\n", 14842292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 14852292SN/A ldstQueue.numFreeEntries()); 14862292SN/A 14872292SN/A updateStatus(); 14882292SN/A 14892292SN/A if (wroteToTimeBuffer) { 14902292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 14912292SN/A cpu->activityThisCycle(); 14921061SN/A } 14931060SN/A} 14941060SN/A 14952301SN/Atemplate <class Impl> 14961060SN/Avoid 14972301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 14981060SN/A{ 14992301SN/A int thread_number = inst->threadNumber; 15001060SN/A 15012301SN/A // 15022301SN/A // Pick off the software prefetches 15032301SN/A // 15042301SN/A#ifdef TARGET_ALPHA 15052301SN/A if (inst->isDataPrefetch()) 15062727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 15072301SN/A else 15082727Sktlim@umich.edu iewIewExecutedcutedInsts++; 15092301SN/A#else 15102669Sktlim@umich.edu iewExecutedInsts++; 15112301SN/A#endif 15121060SN/A 15132301SN/A // 15142301SN/A // Control operations 15152301SN/A // 15162301SN/A if (inst->isControl()) 15172727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 15181060SN/A 15192301SN/A // 15202301SN/A // Memory operations 15212301SN/A // 15222301SN/A if (inst->isMemRef()) { 15232727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 15241060SN/A 15252301SN/A if (inst->isLoad()) { 15262301SN/A iewExecLoadInsts[thread_number]++; 15271060SN/A } 15281060SN/A } 15291060SN/A} 1530