iew_impl.hh revision 2733
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 412292SN/Ausing namespace std; 421681SN/A 431681SN/Atemplate<class Impl> 442292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 452326SN/A : // @todo: Make this into a parameter. 461061SN/A issueToExecQueue(5, 5), 471060SN/A instQueue(params), 481061SN/A ldstQueue(params), 492292SN/A fuPool(params->fuPool), 502292SN/A commitToIEWDelay(params->commitToIEWDelay), 512292SN/A renameToIEWDelay(params->renameToIEWDelay), 522292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 532292SN/A issueReadWidth(params->issueWidth), 542292SN/A issueWidth(params->issueWidth), 552307SN/A numThreads(params->numberOfThreads), 562307SN/A switchedOut(false) 571060SN/A{ 582292SN/A _status = Active; 592292SN/A exeStatus = Running; 602292SN/A wbStatus = Idle; 611060SN/A 621060SN/A // Setup wire to read instructions coming from issue. 631060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 641060SN/A 651060SN/A // Instruction queue needs the queue between issue and execute. 661060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 671681SN/A 682292SN/A instQueue.setIEW(this); 691681SN/A ldstQueue.setIEW(this); 702292SN/A 712292SN/A for (int i=0; i < numThreads; i++) { 722292SN/A dispatchStatus[i] = Running; 732292SN/A stalls[i].commit = false; 742292SN/A fetchRedirect[i] = false; 752292SN/A } 762292SN/A 772292SN/A updateLSQNextCycle = false; 782292SN/A 792292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 802292SN/A} 812292SN/A 822292SN/Atemplate <class Impl> 832292SN/Astd::string 842292SN/ADefaultIEW<Impl>::name() const 852292SN/A{ 862292SN/A return cpu->name() + ".iew"; 871060SN/A} 881060SN/A 891681SN/Atemplate <class Impl> 901062SN/Avoid 912292SN/ADefaultIEW<Impl>::regStats() 921062SN/A{ 932301SN/A using namespace Stats; 942301SN/A 951062SN/A instQueue.regStats(); 962727Sktlim@umich.edu ldstQueue.regStats(); 971062SN/A 981062SN/A iewIdleCycles 991062SN/A .name(name() + ".iewIdleCycles") 1001062SN/A .desc("Number of cycles IEW is idle"); 1011062SN/A 1021062SN/A iewSquashCycles 1031062SN/A .name(name() + ".iewSquashCycles") 1041062SN/A .desc("Number of cycles IEW is squashing"); 1051062SN/A 1061062SN/A iewBlockCycles 1071062SN/A .name(name() + ".iewBlockCycles") 1081062SN/A .desc("Number of cycles IEW is blocking"); 1091062SN/A 1101062SN/A iewUnblockCycles 1111062SN/A .name(name() + ".iewUnblockCycles") 1121062SN/A .desc("Number of cycles IEW is unblocking"); 1131062SN/A 1141062SN/A iewDispatchedInsts 1151062SN/A .name(name() + ".iewDispatchedInsts") 1161062SN/A .desc("Number of instructions dispatched to IQ"); 1171062SN/A 1181062SN/A iewDispSquashedInsts 1191062SN/A .name(name() + ".iewDispSquashedInsts") 1201062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1211062SN/A 1221062SN/A iewDispLoadInsts 1231062SN/A .name(name() + ".iewDispLoadInsts") 1241062SN/A .desc("Number of dispatched load instructions"); 1251062SN/A 1261062SN/A iewDispStoreInsts 1271062SN/A .name(name() + ".iewDispStoreInsts") 1281062SN/A .desc("Number of dispatched store instructions"); 1291062SN/A 1301062SN/A iewDispNonSpecInsts 1311062SN/A .name(name() + ".iewDispNonSpecInsts") 1321062SN/A .desc("Number of dispatched non-speculative instructions"); 1331062SN/A 1341062SN/A iewIQFullEvents 1351062SN/A .name(name() + ".iewIQFullEvents") 1361062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1371062SN/A 1382292SN/A iewLSQFullEvents 1392292SN/A .name(name() + ".iewLSQFullEvents") 1402292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1412292SN/A 1421062SN/A memOrderViolationEvents 1431062SN/A .name(name() + ".memOrderViolationEvents") 1441062SN/A .desc("Number of memory order violations"); 1451062SN/A 1461062SN/A predictedTakenIncorrect 1471062SN/A .name(name() + ".predictedTakenIncorrect") 1481062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1492292SN/A 1502292SN/A predictedNotTakenIncorrect 1512292SN/A .name(name() + ".predictedNotTakenIncorrect") 1522292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1532292SN/A 1542292SN/A branchMispredicts 1552292SN/A .name(name() + ".branchMispredicts") 1562292SN/A .desc("Number of branch mispredicts detected at execute"); 1572292SN/A 1582292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1592301SN/A 1602727Sktlim@umich.edu iewExecutedInsts 1612727Sktlim@umich.edu .name(name() + ".EXEC:insts") 1622727Sktlim@umich.edu .desc("Number of executed instructions"); 1632727Sktlim@umich.edu 1642727Sktlim@umich.edu iewExecLoadInsts 1652727Sktlim@umich.edu .init(cpu->number_of_threads) 1662727Sktlim@umich.edu .name(name() + ".EXEC:loads") 1672727Sktlim@umich.edu .desc("Number of load instructions executed") 1682727Sktlim@umich.edu .flags(total); 1692727Sktlim@umich.edu 1702727Sktlim@umich.edu iewExecSquashedInsts 1712727Sktlim@umich.edu .name(name() + ".EXEC:squashedInsts") 1722727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1732727Sktlim@umich.edu 1742727Sktlim@umich.edu iewExecutedSwp 1752301SN/A .init(cpu->number_of_threads) 1762301SN/A .name(name() + ".EXEC:swp") 1772301SN/A .desc("number of swp insts executed") 1782727Sktlim@umich.edu .flags(total); 1792301SN/A 1802727Sktlim@umich.edu iewExecutedNop 1812301SN/A .init(cpu->number_of_threads) 1822301SN/A .name(name() + ".EXEC:nop") 1832301SN/A .desc("number of nop insts executed") 1842727Sktlim@umich.edu .flags(total); 1852301SN/A 1862727Sktlim@umich.edu iewExecutedRefs 1872301SN/A .init(cpu->number_of_threads) 1882301SN/A .name(name() + ".EXEC:refs") 1892301SN/A .desc("number of memory reference insts executed") 1902727Sktlim@umich.edu .flags(total); 1912301SN/A 1922727Sktlim@umich.edu iewExecutedBranches 1932301SN/A .init(cpu->number_of_threads) 1942301SN/A .name(name() + ".EXEC:branches") 1952301SN/A .desc("Number of branches executed") 1962727Sktlim@umich.edu .flags(total); 1972301SN/A 1982301SN/A iewExecStoreInsts 1992301SN/A .name(name() + ".EXEC:stores") 2002301SN/A .desc("Number of stores executed") 2012727Sktlim@umich.edu .flags(total); 2022727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2032727Sktlim@umich.edu 2042727Sktlim@umich.edu iewExecRate 2052727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2062727Sktlim@umich.edu .desc("Inst execution rate") 2072727Sktlim@umich.edu .flags(total); 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2102301SN/A 2112301SN/A iewInstsToCommit 2122301SN/A .init(cpu->number_of_threads) 2132301SN/A .name(name() + ".WB:sent") 2142301SN/A .desc("cumulative count of insts sent to commit") 2152727Sktlim@umich.edu .flags(total); 2162301SN/A 2172326SN/A writebackCount 2182301SN/A .init(cpu->number_of_threads) 2192301SN/A .name(name() + ".WB:count") 2202301SN/A .desc("cumulative count of insts written-back") 2212727Sktlim@umich.edu .flags(total); 2222301SN/A 2232326SN/A producerInst 2242301SN/A .init(cpu->number_of_threads) 2252301SN/A .name(name() + ".WB:producers") 2262301SN/A .desc("num instructions producing a value") 2272727Sktlim@umich.edu .flags(total); 2282301SN/A 2292326SN/A consumerInst 2302301SN/A .init(cpu->number_of_threads) 2312301SN/A .name(name() + ".WB:consumers") 2322301SN/A .desc("num instructions consuming a value") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352326SN/A wbPenalized 2362301SN/A .init(cpu->number_of_threads) 2372301SN/A .name(name() + ".WB:penalized") 2382301SN/A .desc("number of instrctions required to write to 'other' IQ") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412326SN/A wbPenalizedRate 2422301SN/A .name(name() + ".WB:penalized_rate") 2432301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2472301SN/A 2482326SN/A wbFanout 2492301SN/A .name(name() + ".WB:fanout") 2502301SN/A .desc("average fanout of values written-back") 2512727Sktlim@umich.edu .flags(total); 2522301SN/A 2532326SN/A wbFanout = producerInst / consumerInst; 2542301SN/A 2552326SN/A wbRate 2562301SN/A .name(name() + ".WB:rate") 2572301SN/A .desc("insts written-back per cycle") 2582727Sktlim@umich.edu .flags(total); 2592326SN/A wbRate = writebackCount / cpu->numCycles; 2601062SN/A} 2611062SN/A 2621681SN/Atemplate<class Impl> 2631060SN/Avoid 2642292SN/ADefaultIEW<Impl>::initStage() 2651060SN/A{ 2662292SN/A for (int tid=0; tid < numThreads; tid++) { 2672292SN/A toRename->iewInfo[tid].usedIQ = true; 2682292SN/A toRename->iewInfo[tid].freeIQEntries = 2692292SN/A instQueue.numFreeEntries(tid); 2702292SN/A 2712292SN/A toRename->iewInfo[tid].usedLSQ = true; 2722292SN/A toRename->iewInfo[tid].freeLSQEntries = 2732292SN/A ldstQueue.numFreeEntries(tid); 2742292SN/A } 2752292SN/A} 2762292SN/A 2772292SN/Atemplate<class Impl> 2782292SN/Avoid 2792733Sktlim@umich.eduDefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 2802292SN/A{ 2812292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 2821060SN/A cpu = cpu_ptr; 2831060SN/A 2841060SN/A instQueue.setCPU(cpu_ptr); 2851061SN/A ldstQueue.setCPU(cpu_ptr); 2862292SN/A 2872733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2881060SN/A} 2891060SN/A 2901681SN/Atemplate<class Impl> 2911060SN/Avoid 2922292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2931060SN/A{ 2942292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 2951060SN/A timeBuffer = tb_ptr; 2961060SN/A 2971060SN/A // Setup wire to read information from time buffer, from commit. 2981060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2991060SN/A 3001060SN/A // Setup wire to write information back to previous stages. 3011060SN/A toRename = timeBuffer->getWire(0); 3021060SN/A 3032292SN/A toFetch = timeBuffer->getWire(0); 3042292SN/A 3051060SN/A // Instruction queue also needs main time buffer. 3061060SN/A instQueue.setTimeBuffer(tb_ptr); 3071060SN/A} 3081060SN/A 3091681SN/Atemplate<class Impl> 3101060SN/Avoid 3112292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3121060SN/A{ 3132292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3141060SN/A renameQueue = rq_ptr; 3151060SN/A 3161060SN/A // Setup wire to read information from rename queue. 3171060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3181060SN/A} 3191060SN/A 3201681SN/Atemplate<class Impl> 3211060SN/Avoid 3222292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3231060SN/A{ 3242292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3251060SN/A iewQueue = iq_ptr; 3261060SN/A 3271060SN/A // Setup wire to write instructions to commit. 3281060SN/A toCommit = iewQueue->getWire(0); 3291060SN/A} 3301060SN/A 3311681SN/Atemplate<class Impl> 3321060SN/Avoid 3332292SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3341060SN/A{ 3352292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3362292SN/A activeThreads = at_ptr; 3372292SN/A 3382292SN/A ldstQueue.setActiveThreads(at_ptr); 3392292SN/A instQueue.setActiveThreads(at_ptr); 3401060SN/A} 3411060SN/A 3421681SN/Atemplate<class Impl> 3431060SN/Avoid 3442292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3451060SN/A{ 3462292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3472292SN/A scoreboard = sb_ptr; 3481060SN/A} 3491060SN/A 3502307SN/Atemplate <class Impl> 3512307SN/Avoid 3522307SN/ADefaultIEW<Impl>::switchOut() 3532307SN/A{ 3542348SN/A // IEW is ready to switch out at any time. 3552316SN/A cpu->signalSwitched(); 3561681SN/A} 3571681SN/A 3582316SN/Atemplate <class Impl> 3591681SN/Avoid 3602316SN/ADefaultIEW<Impl>::doSwitchOut() 3611681SN/A{ 3622348SN/A // Clear any state. 3632307SN/A switchedOut = true; 3641681SN/A 3652307SN/A instQueue.switchOut(); 3662307SN/A ldstQueue.switchOut(); 3672307SN/A fuPool->switchOut(); 3682307SN/A 3692307SN/A for (int i = 0; i < numThreads; i++) { 3702307SN/A while (!insts[i].empty()) 3712307SN/A insts[i].pop(); 3722307SN/A while (!skidBuffer[i].empty()) 3732307SN/A skidBuffer[i].pop(); 3742307SN/A } 3751681SN/A} 3761681SN/A 3772307SN/Atemplate <class Impl> 3781681SN/Avoid 3792307SN/ADefaultIEW<Impl>::takeOverFrom() 3801060SN/A{ 3812348SN/A // Reset all state. 3822307SN/A _status = Active; 3832307SN/A exeStatus = Running; 3842307SN/A wbStatus = Idle; 3852307SN/A switchedOut = false; 3861060SN/A 3872307SN/A instQueue.takeOverFrom(); 3882307SN/A ldstQueue.takeOverFrom(); 3892307SN/A fuPool->takeOverFrom(); 3901060SN/A 3912307SN/A initStage(); 3922307SN/A cpu->activityThisCycle(); 3931060SN/A 3942307SN/A for (int i=0; i < numThreads; i++) { 3952307SN/A dispatchStatus[i] = Running; 3962307SN/A stalls[i].commit = false; 3972307SN/A fetchRedirect[i] = false; 3982307SN/A } 3991060SN/A 4002307SN/A updateLSQNextCycle = false; 4012307SN/A 4022307SN/A // @todo: Fix hardcoded number 4032307SN/A for (int i = 0; i < 6; ++i) { 4042307SN/A issueToExecQueue.advance(); 4051060SN/A } 4061060SN/A} 4071060SN/A 4081681SN/Atemplate<class Impl> 4091060SN/Avoid 4102292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4112107SN/A{ 4122292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4132292SN/A tid); 4142107SN/A 4152292SN/A // Tell the IQ to start squashing. 4162292SN/A instQueue.squash(tid); 4172107SN/A 4182292SN/A // Tell the LDSTQ to start squashing. 4192326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4202107SN/A 4212292SN/A updatedQueues = true; 4222107SN/A 4232292SN/A // Clear the skid buffer in case it has any data in it. 4242292SN/A while (!skidBuffer[tid].empty()) { 4252107SN/A 4262292SN/A if (skidBuffer[tid].front()->isLoad() || 4272292SN/A skidBuffer[tid].front()->isStore() ) { 4282292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4292292SN/A } 4302107SN/A 4312292SN/A toRename->iewInfo[tid].dispatched++; 4322107SN/A 4332292SN/A skidBuffer[tid].pop(); 4342292SN/A } 4352107SN/A 4362702Sktlim@umich.edu emptyRenameInsts(tid); 4372107SN/A} 4382107SN/A 4392107SN/Atemplate<class Impl> 4402107SN/Avoid 4412292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4422292SN/A{ 4432292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4442292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4452292SN/A 4462292SN/A toCommit->squash[tid] = true; 4472292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4482292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4492292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4502292SN/A toCommit->branchMispredict[tid] = true; 4512292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4522292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4532292SN/A 4542292SN/A toCommit->includeSquashInst[tid] = false; 4552292SN/A 4562292SN/A wroteToTimeBuffer = true; 4572292SN/A} 4582292SN/A 4592292SN/Atemplate<class Impl> 4602292SN/Avoid 4612292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4622292SN/A{ 4632292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4642292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4652292SN/A 4662292SN/A toCommit->squash[tid] = true; 4672292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4682292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4692292SN/A 4702292SN/A toCommit->includeSquashInst[tid] = false; 4712292SN/A 4722292SN/A wroteToTimeBuffer = true; 4732292SN/A} 4742292SN/A 4752292SN/Atemplate<class Impl> 4762292SN/Avoid 4772292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 4782292SN/A{ 4792292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4802292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4812292SN/A 4822292SN/A toCommit->squash[tid] = true; 4832292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4842292SN/A toCommit->nextPC[tid] = inst->readPC(); 4852292SN/A 4862348SN/A // Must include the broadcasted SN in the squash. 4872292SN/A toCommit->includeSquashInst[tid] = true; 4882292SN/A 4892292SN/A ldstQueue.setLoadBlockedHandled(tid); 4902292SN/A 4912292SN/A wroteToTimeBuffer = true; 4922292SN/A} 4932292SN/A 4942292SN/Atemplate<class Impl> 4952292SN/Avoid 4962292SN/ADefaultIEW<Impl>::block(unsigned tid) 4972292SN/A{ 4982292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 4992292SN/A 5002292SN/A if (dispatchStatus[tid] != Blocked && 5012292SN/A dispatchStatus[tid] != Unblocking) { 5022292SN/A toRename->iewBlock[tid] = true; 5032292SN/A wroteToTimeBuffer = true; 5042292SN/A } 5052292SN/A 5062292SN/A // Add the current inputs to the skid buffer so they can be 5072292SN/A // reprocessed when this stage unblocks. 5082292SN/A skidInsert(tid); 5092292SN/A 5102292SN/A dispatchStatus[tid] = Blocked; 5112292SN/A} 5122292SN/A 5132292SN/Atemplate<class Impl> 5142292SN/Avoid 5152292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5162292SN/A{ 5172292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5182292SN/A "buffer %u.\n",tid, tid); 5192292SN/A 5202292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5212292SN/A // Also switch status to running. 5222292SN/A if (skidBuffer[tid].empty()) { 5232292SN/A toRename->iewUnblock[tid] = true; 5242292SN/A wroteToTimeBuffer = true; 5252292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5262292SN/A dispatchStatus[tid] = Running; 5272292SN/A } 5282292SN/A} 5292292SN/A 5302292SN/Atemplate<class Impl> 5312292SN/Avoid 5322292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5331060SN/A{ 5341681SN/A instQueue.wakeDependents(inst); 5351060SN/A} 5361060SN/A 5372292SN/Atemplate<class Impl> 5382292SN/Avoid 5392292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5402292SN/A{ 5412292SN/A instQueue.rescheduleMemInst(inst); 5422292SN/A} 5431681SN/A 5441681SN/Atemplate<class Impl> 5451060SN/Avoid 5462292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5471060SN/A{ 5482292SN/A instQueue.replayMemInst(inst); 5492292SN/A} 5501060SN/A 5512292SN/Atemplate<class Impl> 5522292SN/Avoid 5532292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5542292SN/A{ 5552292SN/A // First check the time slot that this instruction will write 5562292SN/A // to. If there are free write ports at the time, then go ahead 5572292SN/A // and write the instruction to that time. If there are not, 5582292SN/A // keep looking back to see where's the first time there's a 5592326SN/A // free slot. 5602292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5612292SN/A ++wbNumInst; 5622292SN/A if (wbNumInst == issueWidth) { 5632292SN/A ++wbCycle; 5642292SN/A wbNumInst = 0; 5652292SN/A } 5662292SN/A 5672292SN/A assert(wbCycle < 5); 5682292SN/A } 5692292SN/A 5702292SN/A // Add finished instruction to queue to commit. 5712292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5722292SN/A (*iewQueue)[wbCycle].size++; 5732292SN/A} 5742292SN/A 5752292SN/Atemplate <class Impl> 5762292SN/Aunsigned 5772292SN/ADefaultIEW<Impl>::validInstsFromRename() 5782292SN/A{ 5792292SN/A unsigned inst_count = 0; 5802292SN/A 5812292SN/A for (int i=0; i<fromRename->size; i++) { 5822731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 5832292SN/A inst_count++; 5842292SN/A } 5852292SN/A 5862292SN/A return inst_count; 5872292SN/A} 5882292SN/A 5892292SN/Atemplate<class Impl> 5902292SN/Avoid 5912292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 5922292SN/A{ 5932292SN/A DynInstPtr inst = NULL; 5942292SN/A 5952292SN/A while (!insts[tid].empty()) { 5962292SN/A inst = insts[tid].front(); 5972292SN/A 5982292SN/A insts[tid].pop(); 5992292SN/A 6002292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6012292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6022292SN/A inst->readPC(),tid); 6032292SN/A 6042292SN/A skidBuffer[tid].push(inst); 6052292SN/A } 6062292SN/A 6072292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6082292SN/A "Skidbuffer Exceeded Max Size"); 6092292SN/A} 6102292SN/A 6112292SN/Atemplate<class Impl> 6122292SN/Aint 6132292SN/ADefaultIEW<Impl>::skidCount() 6142292SN/A{ 6152292SN/A int max=0; 6162292SN/A 6172292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6182292SN/A 6192292SN/A while (threads != (*activeThreads).end()) { 6202292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6212292SN/A if (max < thread_count) 6222292SN/A max = thread_count; 6232292SN/A } 6242292SN/A 6252292SN/A return max; 6262292SN/A} 6272292SN/A 6282292SN/Atemplate<class Impl> 6292292SN/Abool 6302292SN/ADefaultIEW<Impl>::skidsEmpty() 6312292SN/A{ 6322292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6332292SN/A 6342292SN/A while (threads != (*activeThreads).end()) { 6352292SN/A if (!skidBuffer[*threads++].empty()) 6362292SN/A return false; 6372292SN/A } 6382292SN/A 6392292SN/A return true; 6401062SN/A} 6411062SN/A 6421681SN/Atemplate <class Impl> 6431062SN/Avoid 6442292SN/ADefaultIEW<Impl>::updateStatus() 6451062SN/A{ 6462292SN/A bool any_unblocking = false; 6471062SN/A 6482292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6491062SN/A 6502292SN/A threads = (*activeThreads).begin(); 6511062SN/A 6522292SN/A while (threads != (*activeThreads).end()) { 6532292SN/A unsigned tid = *threads++; 6541062SN/A 6552292SN/A if (dispatchStatus[tid] == Unblocking) { 6562292SN/A any_unblocking = true; 6572292SN/A break; 6582292SN/A } 6592292SN/A } 6601062SN/A 6612292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6622292SN/A // and there's no stores waiting to write back, and dispatch is not 6632292SN/A // unblocking, then there is no internal activity for the IEW stage. 6642292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6652292SN/A !ldstQueue.willWB() && !any_unblocking) { 6662292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6671062SN/A 6682292SN/A deactivateStage(); 6691062SN/A 6702292SN/A _status = Inactive; 6712292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6722292SN/A ldstQueue.willWB() || 6732292SN/A any_unblocking)) { 6742292SN/A // Otherwise there is internal activity. Set to active. 6752292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6761062SN/A 6772292SN/A activateStage(); 6781062SN/A 6792292SN/A _status = Active; 6801062SN/A } 6811062SN/A} 6821062SN/A 6831681SN/Atemplate <class Impl> 6841062SN/Avoid 6852292SN/ADefaultIEW<Impl>::resetEntries() 6861062SN/A{ 6872292SN/A instQueue.resetEntries(); 6882292SN/A ldstQueue.resetEntries(); 6892292SN/A} 6901062SN/A 6912292SN/Atemplate <class Impl> 6922292SN/Avoid 6932292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 6942292SN/A{ 6952292SN/A if (fromCommit->commitBlock[tid]) { 6962292SN/A stalls[tid].commit = true; 6972292SN/A } 6981062SN/A 6992292SN/A if (fromCommit->commitUnblock[tid]) { 7002292SN/A assert(stalls[tid].commit); 7012292SN/A stalls[tid].commit = false; 7022292SN/A } 7032292SN/A} 7042292SN/A 7052292SN/Atemplate <class Impl> 7062292SN/Abool 7072292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7082292SN/A{ 7092292SN/A bool ret_val(false); 7102292SN/A 7112292SN/A if (stalls[tid].commit) { 7122292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7132292SN/A ret_val = true; 7142292SN/A } else if (instQueue.isFull(tid)) { 7152292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7162292SN/A ret_val = true; 7172292SN/A } else if (ldstQueue.isFull(tid)) { 7182292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7192292SN/A 7202292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7212292SN/A 7222292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7232292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7242292SN/A } 7252292SN/A 7262292SN/A if (ldstQueue.numStores(tid) > 0) { 7272292SN/A 7282292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7292292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7302292SN/A } 7312292SN/A 7322292SN/A ret_val = true; 7332292SN/A } else if (ldstQueue.isStalled(tid)) { 7342292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7352292SN/A ret_val = true; 7362292SN/A } 7372292SN/A 7382292SN/A return ret_val; 7392292SN/A} 7402292SN/A 7412292SN/Atemplate <class Impl> 7422292SN/Avoid 7432292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7442292SN/A{ 7452292SN/A // Check if there's a squash signal, squash if there is 7462292SN/A // Check stall signals, block if there is. 7472292SN/A // If status was Blocked 7482292SN/A // if so then go to unblocking 7492292SN/A // If status was Squashing 7502292SN/A // check if squashing is not high. Switch to running this cycle. 7512292SN/A 7522292SN/A readStallSignals(tid); 7532292SN/A 7542292SN/A if (fromCommit->commitInfo[tid].squash) { 7552292SN/A squash(tid); 7562292SN/A 7572292SN/A if (dispatchStatus[tid] == Blocked || 7582292SN/A dispatchStatus[tid] == Unblocking) { 7592292SN/A toRename->iewUnblock[tid] = true; 7602292SN/A wroteToTimeBuffer = true; 7612292SN/A } 7622292SN/A 7632292SN/A dispatchStatus[tid] = Squashing; 7642292SN/A 7652292SN/A fetchRedirect[tid] = false; 7662292SN/A return; 7672292SN/A } 7682292SN/A 7692292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7702702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7712292SN/A 7722292SN/A dispatchStatus[tid] = Squashing; 7732292SN/A 7742702Sktlim@umich.edu emptyRenameInsts(tid); 7752702Sktlim@umich.edu wroteToTimeBuffer = true; 7762292SN/A return; 7772292SN/A } 7782292SN/A 7792292SN/A if (checkStall(tid)) { 7802292SN/A block(tid); 7812292SN/A dispatchStatus[tid] = Blocked; 7822292SN/A return; 7832292SN/A } 7842292SN/A 7852292SN/A if (dispatchStatus[tid] == Blocked) { 7862292SN/A // Status from previous cycle was blocked, but there are no more stall 7872292SN/A // conditions. Switch over to unblocking. 7882292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 7892292SN/A tid); 7902292SN/A 7912292SN/A dispatchStatus[tid] = Unblocking; 7922292SN/A 7932292SN/A unblock(tid); 7942292SN/A 7952292SN/A return; 7962292SN/A } 7972292SN/A 7982292SN/A if (dispatchStatus[tid] == Squashing) { 7992292SN/A // Switch status to running if rename isn't being told to block or 8002292SN/A // squash this cycle. 8012292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8022292SN/A tid); 8032292SN/A 8042292SN/A dispatchStatus[tid] = Running; 8052292SN/A 8062292SN/A return; 8072292SN/A } 8082292SN/A} 8092292SN/A 8102292SN/Atemplate <class Impl> 8112292SN/Avoid 8122292SN/ADefaultIEW<Impl>::sortInsts() 8132292SN/A{ 8142292SN/A int insts_from_rename = fromRename->size; 8152326SN/A#ifdef DEBUG 8162292SN/A for (int i = 0; i < numThreads; i++) 8172292SN/A assert(insts[i].empty()); 8182326SN/A#endif 8192292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8202292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8212292SN/A } 8222292SN/A} 8232292SN/A 8242292SN/Atemplate <class Impl> 8252292SN/Avoid 8262702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8272702Sktlim@umich.edu{ 8282702Sktlim@umich.edu while (!insts[tid].empty()) { 8292702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8302702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8312702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8322702Sktlim@umich.edu } 8332702Sktlim@umich.edu 8342702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8352702Sktlim@umich.edu 8362702Sktlim@umich.edu insts[tid].pop(); 8372702Sktlim@umich.edu } 8382702Sktlim@umich.edu} 8392702Sktlim@umich.edu 8402702Sktlim@umich.edutemplate <class Impl> 8412702Sktlim@umich.eduvoid 8422292SN/ADefaultIEW<Impl>::wakeCPU() 8432292SN/A{ 8442292SN/A cpu->wakeCPU(); 8452292SN/A} 8462292SN/A 8472292SN/Atemplate <class Impl> 8482292SN/Avoid 8492292SN/ADefaultIEW<Impl>::activityThisCycle() 8502292SN/A{ 8512292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8522292SN/A cpu->activityThisCycle(); 8532292SN/A} 8542292SN/A 8552292SN/Atemplate <class Impl> 8562292SN/Ainline void 8572292SN/ADefaultIEW<Impl>::activateStage() 8582292SN/A{ 8592292SN/A DPRINTF(Activity, "Activating stage.\n"); 8602733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8612292SN/A} 8622292SN/A 8632292SN/Atemplate <class Impl> 8642292SN/Ainline void 8652292SN/ADefaultIEW<Impl>::deactivateStage() 8662292SN/A{ 8672292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8682733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8692292SN/A} 8702292SN/A 8712292SN/Atemplate<class Impl> 8722292SN/Avoid 8732292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8742292SN/A{ 8752292SN/A // If status is Running or idle, 8762292SN/A // call dispatchInsts() 8772292SN/A // If status is Unblocking, 8782292SN/A // buffer any instructions coming from rename 8792292SN/A // continue trying to empty skid buffer 8802292SN/A // check if stall conditions have passed 8812292SN/A 8822292SN/A if (dispatchStatus[tid] == Blocked) { 8832292SN/A ++iewBlockCycles; 8842292SN/A 8852292SN/A } else if (dispatchStatus[tid] == Squashing) { 8862292SN/A ++iewSquashCycles; 8872292SN/A } 8882292SN/A 8892292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 8902292SN/A // will allow, as long as it is not currently blocked. 8912292SN/A if (dispatchStatus[tid] == Running || 8922292SN/A dispatchStatus[tid] == Idle) { 8932292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 8942292SN/A "dispatch.\n", tid); 8952292SN/A 8962292SN/A dispatchInsts(tid); 8972292SN/A } else if (dispatchStatus[tid] == Unblocking) { 8982292SN/A // Make sure that the skid buffer has something in it if the 8992292SN/A // status is unblocking. 9002292SN/A assert(!skidsEmpty()); 9012292SN/A 9022292SN/A // If the status was unblocking, then instructions from the skid 9032292SN/A // buffer were used. Remove those instructions and handle 9042292SN/A // the rest of unblocking. 9052292SN/A dispatchInsts(tid); 9062292SN/A 9072292SN/A ++iewUnblockCycles; 9082292SN/A 9092292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9102292SN/A // Add the current inputs to the skid buffer so they can be 9112292SN/A // reprocessed when this stage unblocks. 9122292SN/A skidInsert(tid); 9132292SN/A } 9142292SN/A 9152292SN/A unblock(tid); 9162292SN/A } 9172292SN/A} 9182292SN/A 9192292SN/Atemplate <class Impl> 9202292SN/Avoid 9212292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9222292SN/A{ 9232292SN/A dispatchedAllInsts = true; 9242292SN/A 9252292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9262292SN/A // otherwise. 9272292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9282292SN/A dispatchStatus[tid] == Unblocking ? 9292292SN/A skidBuffer[tid] : insts[tid]; 9302292SN/A 9312292SN/A int insts_to_add = insts_to_dispatch.size(); 9322292SN/A 9332292SN/A DynInstPtr inst; 9342292SN/A bool add_to_iq = false; 9352292SN/A int dis_num_inst = 0; 9362292SN/A 9372292SN/A // Loop through the instructions, putting them in the instruction 9382292SN/A // queue. 9392292SN/A for ( ; dis_num_inst < insts_to_add && 9402292SN/A dis_num_inst < issueReadWidth; 9412292SN/A ++dis_num_inst) 9422292SN/A { 9432292SN/A inst = insts_to_dispatch.front(); 9442292SN/A 9452292SN/A if (dispatchStatus[tid] == Unblocking) { 9462292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9472292SN/A "buffer\n", tid); 9482292SN/A } 9492292SN/A 9502292SN/A // Make sure there's a valid instruction there. 9512292SN/A assert(inst); 9522292SN/A 9532292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9542292SN/A "IQ.\n", 9552292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9562292SN/A 9572292SN/A // Be sure to mark these instructions as ready so that the 9582292SN/A // commit stage can go ahead and execute them, and mark 9592292SN/A // them as issued so the IQ doesn't reprocess them. 9602292SN/A 9612292SN/A // Check for squashed instructions. 9622292SN/A if (inst->isSquashed()) { 9632292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9642292SN/A "not adding to IQ.\n", tid); 9652292SN/A 9662292SN/A ++iewDispSquashedInsts; 9672292SN/A 9682292SN/A insts_to_dispatch.pop(); 9692292SN/A 9702292SN/A //Tell Rename That An Instruction has been processed 9712292SN/A if (inst->isLoad() || inst->isStore()) { 9722292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9732292SN/A } 9742292SN/A toRename->iewInfo[tid].dispatched++; 9752292SN/A 9762292SN/A continue; 9772292SN/A } 9782292SN/A 9792292SN/A // Check for full conditions. 9802292SN/A if (instQueue.isFull(tid)) { 9812292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 9822292SN/A 9832292SN/A // Call function to start blocking. 9842292SN/A block(tid); 9852292SN/A 9862292SN/A // Set unblock to false. Special case where we are using 9872292SN/A // skidbuffer (unblocking) instructions but then we still 9882292SN/A // get full in the IQ. 9892292SN/A toRename->iewUnblock[tid] = false; 9902292SN/A 9912292SN/A dispatchedAllInsts = false; 9922292SN/A 9932292SN/A ++iewIQFullEvents; 9942292SN/A break; 9952292SN/A } else if (ldstQueue.isFull(tid)) { 9962292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 9972292SN/A 9982292SN/A // Call function to start blocking. 9992292SN/A block(tid); 10002292SN/A 10012292SN/A // Set unblock to false. Special case where we are using 10022292SN/A // skidbuffer (unblocking) instructions but then we still 10032292SN/A // get full in the IQ. 10042292SN/A toRename->iewUnblock[tid] = false; 10052292SN/A 10062292SN/A dispatchedAllInsts = false; 10072292SN/A 10082292SN/A ++iewLSQFullEvents; 10092292SN/A break; 10102292SN/A } 10112292SN/A 10122292SN/A // Otherwise issue the instruction just fine. 10132292SN/A if (inst->isLoad()) { 10142292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10152292SN/A "encountered, adding to LSQ.\n", tid); 10162292SN/A 10172292SN/A // Reserve a spot in the load store queue for this 10182292SN/A // memory access. 10192292SN/A ldstQueue.insertLoad(inst); 10202292SN/A 10212292SN/A ++iewDispLoadInsts; 10222292SN/A 10232292SN/A add_to_iq = true; 10242292SN/A 10252292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10262292SN/A } else if (inst->isStore()) { 10272292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10282292SN/A "encountered, adding to LSQ.\n", tid); 10292292SN/A 10302292SN/A ldstQueue.insertStore(inst); 10312292SN/A 10322292SN/A ++iewDispStoreInsts; 10332292SN/A 10342336SN/A if (inst->isStoreConditional()) { 10352336SN/A // Store conditionals need to be set as "canCommit()" 10362336SN/A // so that commit can process them when they reach the 10372336SN/A // head of commit. 10382348SN/A // @todo: This is somewhat specific to Alpha. 10392292SN/A inst->setCanCommit(); 10402292SN/A instQueue.insertNonSpec(inst); 10412292SN/A add_to_iq = false; 10422292SN/A 10432292SN/A ++iewDispNonSpecInsts; 10442292SN/A } else { 10452292SN/A add_to_iq = true; 10462292SN/A } 10472292SN/A 10482292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10492292SN/A#if FULL_SYSTEM 10502292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10512326SN/A // Same as non-speculative stores. 10522292SN/A inst->setCanCommit(); 10532292SN/A instQueue.insertBarrier(inst); 10542292SN/A add_to_iq = false; 10552292SN/A#endif 10562292SN/A } else if (inst->isNonSpeculative()) { 10572292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 10582292SN/A "encountered, skipping.\n", tid); 10592292SN/A 10602326SN/A // Same as non-speculative stores. 10612292SN/A inst->setCanCommit(); 10622292SN/A 10632292SN/A // Specifically insert it as nonspeculative. 10642292SN/A instQueue.insertNonSpec(inst); 10652292SN/A 10662292SN/A ++iewDispNonSpecInsts; 10672292SN/A 10682292SN/A add_to_iq = false; 10692292SN/A } else if (inst->isNop()) { 10702292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10712292SN/A "skipping.\n", tid); 10722292SN/A 10732292SN/A inst->setIssued(); 10742292SN/A inst->setExecuted(); 10752292SN/A inst->setCanCommit(); 10762292SN/A 10772326SN/A instQueue.recordProducer(inst); 10782292SN/A 10792727Sktlim@umich.edu iewExecutedNop[tid]++; 10802301SN/A 10812292SN/A add_to_iq = false; 10822292SN/A } else if (inst->isExecuted()) { 10832292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10842292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10852292SN/A "skipping.\n"); 10862292SN/A 10872292SN/A inst->setIssued(); 10882292SN/A inst->setCanCommit(); 10892292SN/A 10902326SN/A instQueue.recordProducer(inst); 10912292SN/A 10922292SN/A add_to_iq = false; 10932292SN/A } else { 10942292SN/A add_to_iq = true; 10952292SN/A } 10962292SN/A 10972292SN/A // If the instruction queue is not full, then add the 10982292SN/A // instruction. 10992292SN/A if (add_to_iq) { 11002292SN/A instQueue.insert(inst); 11012292SN/A } 11022292SN/A 11032292SN/A insts_to_dispatch.pop(); 11042292SN/A 11052292SN/A toRename->iewInfo[tid].dispatched++; 11062292SN/A 11072292SN/A ++iewDispatchedInsts; 11082292SN/A } 11092292SN/A 11102292SN/A if (!insts_to_dispatch.empty()) { 11112292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11122292SN/A block(tid); 11132292SN/A toRename->iewUnblock[tid] = false; 11142292SN/A } 11152292SN/A 11162292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11172292SN/A dispatchStatus[tid] = Running; 11182292SN/A 11192292SN/A updatedQueues = true; 11202292SN/A } 11212292SN/A 11222292SN/A dis_num_inst = 0; 11232292SN/A} 11242292SN/A 11252292SN/Atemplate <class Impl> 11262292SN/Avoid 11272292SN/ADefaultIEW<Impl>::printAvailableInsts() 11282292SN/A{ 11292292SN/A int inst = 0; 11302292SN/A 11312292SN/A cout << "Available Instructions: "; 11322292SN/A 11332292SN/A while (fromIssue->insts[inst]) { 11342292SN/A 11352292SN/A if (inst%3==0) cout << "\n\t"; 11362292SN/A 11372292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 11382292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11392292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11402292SN/A 11412292SN/A inst++; 11422292SN/A 11432292SN/A } 11442292SN/A 11452292SN/A cout << "\n"; 11462292SN/A} 11472292SN/A 11482292SN/Atemplate <class Impl> 11492292SN/Avoid 11502292SN/ADefaultIEW<Impl>::executeInsts() 11512292SN/A{ 11522292SN/A wbNumInst = 0; 11532292SN/A wbCycle = 0; 11542292SN/A 11552292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11562292SN/A 11572292SN/A while (threads != (*activeThreads).end()) { 11582292SN/A unsigned tid = *threads++; 11592292SN/A fetchRedirect[tid] = false; 11602292SN/A } 11612292SN/A 11622698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11632698Sktlim@umich.edu// printAvailableInsts(); 11641062SN/A 11651062SN/A // Execute/writeback any instructions that are available. 11662333SN/A int insts_to_execute = fromIssue->size; 11672292SN/A int inst_num = 0; 11682333SN/A for (; inst_num < insts_to_execute; 11692326SN/A ++inst_num) { 11701062SN/A 11712292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11721062SN/A 11732333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11741062SN/A 11752292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11762292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11771062SN/A 11781062SN/A // Check if the instruction is squashed; if so then skip it 11791062SN/A if (inst->isSquashed()) { 11802292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 11811062SN/A 11821062SN/A // Consider this instruction executed so that commit can go 11831062SN/A // ahead and retire the instruction. 11841062SN/A inst->setExecuted(); 11851062SN/A 11862292SN/A // Not sure if I should set this here or just let commit try to 11872292SN/A // commit any squashed instructions. I like the latter a bit more. 11882292SN/A inst->setCanCommit(); 11891062SN/A 11901062SN/A ++iewExecSquashedInsts; 11911062SN/A 11921062SN/A continue; 11931062SN/A } 11941062SN/A 11952292SN/A Fault fault = NoFault; 11961062SN/A 11971062SN/A // Execute instruction. 11981062SN/A // Note that if the instruction faults, it will be handled 11991062SN/A // at the commit stage. 12002292SN/A if (inst->isMemRef() && 12012292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12022292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12031062SN/A "reference.\n"); 12041062SN/A 12051062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12061062SN/A if (inst->isLoad()) { 12072292SN/A // Loads will mark themselves as executed, and their writeback 12082292SN/A // event adds the instruction to the queue to commit 12092292SN/A fault = ldstQueue.executeLoad(inst); 12101062SN/A } else if (inst->isStore()) { 12111681SN/A ldstQueue.executeStore(inst); 12121062SN/A 12132292SN/A // If the store had a fault then it may not have a mem req 12142669Sktlim@umich.edu if (inst->req && !(inst->req->getFlags() & LOCKED)) { 12152292SN/A inst->setExecuted(); 12162292SN/A 12172292SN/A instToCommit(inst); 12182292SN/A } 12192326SN/A 12202326SN/A // Store conditionals will mark themselves as 12212326SN/A // executed, and their writeback event will add the 12222326SN/A // instruction to the queue to commit. 12231062SN/A } else { 12242292SN/A panic("Unexpected memory type!\n"); 12251062SN/A } 12261062SN/A 12271062SN/A } else { 12281062SN/A inst->execute(); 12291062SN/A 12302292SN/A inst->setExecuted(); 12312292SN/A 12322292SN/A instToCommit(inst); 12331062SN/A } 12341062SN/A 12352301SN/A updateExeInstStats(inst); 12361681SN/A 12372326SN/A // Check if branch prediction was correct, if not then we need 12382326SN/A // to tell commit to squash in flight instructions. Only 12392326SN/A // handle this if there hasn't already been something that 12402107SN/A // redirects fetch in this group of instructions. 12411681SN/A 12422292SN/A // This probably needs to prioritize the redirects if a different 12432292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12442292SN/A // instruction first, so the branch resolution order will be correct. 12452292SN/A unsigned tid = inst->threadNumber; 12461062SN/A 12472292SN/A if (!fetchRedirect[tid]) { 12481062SN/A 12491062SN/A if (inst->mispredicted()) { 12502292SN/A fetchRedirect[tid] = true; 12511062SN/A 12522292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12532292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 12541062SN/A inst->nextPC); 12551062SN/A 12561062SN/A // If incorrect, then signal the ROB that it must be squashed. 12572292SN/A squashDueToBranch(inst, tid); 12581062SN/A 12591062SN/A if (inst->predTaken()) { 12601062SN/A predictedTakenIncorrect++; 12612292SN/A } else { 12622292SN/A predictedNotTakenIncorrect++; 12631062SN/A } 12642292SN/A } else if (ldstQueue.violation(tid)) { 12652292SN/A fetchRedirect[tid] = true; 12661062SN/A 12672326SN/A // If there was an ordering violation, then get the 12682326SN/A // DynInst that caused the violation. Note that this 12692292SN/A // clears the violation signal. 12702292SN/A DynInstPtr violator; 12712292SN/A violator = ldstQueue.getMemDepViolator(tid); 12721062SN/A 12732292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 12741062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 12751062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 12761062SN/A 12771062SN/A // Tell the instruction queue that a violation has occured. 12781062SN/A instQueue.violation(inst, violator); 12791062SN/A 12801062SN/A // Squash. 12812292SN/A squashDueToMemOrder(inst,tid); 12821062SN/A 12831062SN/A ++memOrderViolationEvents; 12842292SN/A } else if (ldstQueue.loadBlocked(tid) && 12852292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 12862292SN/A fetchRedirect[tid] = true; 12872292SN/A 12882292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 12892292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 12902292SN/A inst->readPC(), inst->seqNum); 12912292SN/A 12922292SN/A squashDueToMemBlocked(inst, tid); 12931062SN/A } 12941062SN/A } 12951062SN/A } 12962292SN/A 12972348SN/A // Update and record activity if we processed any instructions. 12982292SN/A if (inst_num) { 12992292SN/A if (exeStatus == Idle) { 13002292SN/A exeStatus = Running; 13012292SN/A } 13022292SN/A 13032292SN/A updatedQueues = true; 13042292SN/A 13052292SN/A cpu->activityThisCycle(); 13062292SN/A } 13072292SN/A 13082292SN/A // Need to reset this in case a writeback event needs to write into the 13092292SN/A // iew queue. That way the writeback event will write into the correct 13102292SN/A // spot in the queue. 13112292SN/A wbNumInst = 0; 13122107SN/A} 13132107SN/A 13142292SN/Atemplate <class Impl> 13152107SN/Avoid 13162292SN/ADefaultIEW<Impl>::writebackInsts() 13172107SN/A{ 13182326SN/A // Loop through the head of the time buffer and wake any 13192326SN/A // dependents. These instructions are about to write back. Also 13202326SN/A // mark scoreboard that this instruction is finally complete. 13212326SN/A // Either have IEW have direct access to scoreboard, or have this 13222326SN/A // as part of backwards communication. 13232107SN/A for (int inst_num = 0; inst_num < issueWidth && 13242292SN/A toCommit->insts[inst_num]; inst_num++) { 13252107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13262301SN/A int tid = inst->threadNumber; 13272107SN/A 13282698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13292698Sktlim@umich.edu inst->seqNum, inst->readPC()); 13302107SN/A 13312301SN/A iewInstsToCommit[tid]++; 13322301SN/A 13332292SN/A // Some instructions will be sent to commit without having 13342292SN/A // executed because they need commit to handle them. 13352292SN/A // E.g. Uncached loads have not actually executed when they 13362292SN/A // are first sent to commit. Instead commit must tell the LSQ 13372292SN/A // when it's ready to execute the uncached load. 13382292SN/A if (!inst->isSquashed() && inst->isExecuted()) { 13392301SN/A int dependents = instQueue.wakeDependents(inst); 13402107SN/A 13412292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 13422292SN/A //mark as Ready 13432292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 13442292SN/A inst->renamedDestRegIdx(i)); 13452292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 13462107SN/A } 13472301SN/A 13482348SN/A if (dependents) { 13492348SN/A producerInst[tid]++; 13502348SN/A consumerInst[tid]+= dependents; 13512348SN/A } 13522326SN/A writebackCount[tid]++; 13532107SN/A } 13542107SN/A } 13551060SN/A} 13561060SN/A 13571681SN/Atemplate<class Impl> 13581060SN/Avoid 13592292SN/ADefaultIEW<Impl>::tick() 13601060SN/A{ 13612292SN/A wbNumInst = 0; 13622292SN/A wbCycle = 0; 13631060SN/A 13642292SN/A wroteToTimeBuffer = false; 13652292SN/A updatedQueues = false; 13661060SN/A 13672292SN/A sortInsts(); 13681060SN/A 13692326SN/A // Free function units marked as being freed this cycle. 13702326SN/A fuPool->processFreeUnits(); 13711062SN/A 13722292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 13731060SN/A 13742326SN/A // Check stall and squash signals, dispatch any instructions. 13752292SN/A while (threads != (*activeThreads).end()) { 13762292SN/A unsigned tid = *threads++; 13771060SN/A 13782292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 13791060SN/A 13802292SN/A checkSignalsAndUpdate(tid); 13812292SN/A dispatch(tid); 13821060SN/A } 13831060SN/A 13842292SN/A if (exeStatus != Squashing) { 13852292SN/A executeInsts(); 13861060SN/A 13872292SN/A writebackInsts(); 13882292SN/A 13892292SN/A // Have the instruction queue try to schedule any ready instructions. 13902292SN/A // (In actuality, this scheduling is for instructions that will 13912292SN/A // be executed next cycle.) 13922292SN/A instQueue.scheduleReadyInsts(); 13932292SN/A 13942292SN/A // Also should advance its own time buffers if the stage ran. 13952292SN/A // Not the best place for it, but this works (hopefully). 13962292SN/A issueToExecQueue.advance(); 13972292SN/A } 13982292SN/A 13992292SN/A bool broadcast_free_entries = false; 14002292SN/A 14012292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14022292SN/A exeStatus = Idle; 14032292SN/A updateLSQNextCycle = false; 14042292SN/A 14052292SN/A broadcast_free_entries = true; 14062292SN/A } 14072292SN/A 14082292SN/A // Writeback any stores using any leftover bandwidth. 14091681SN/A ldstQueue.writebackStores(); 14101681SN/A 14111061SN/A // Check the committed load/store signals to see if there's a load 14121061SN/A // or store to commit. Also check if it's being told to execute a 14131061SN/A // nonspeculative instruction. 14141681SN/A // This is pretty inefficient... 14152292SN/A 14162292SN/A threads = (*activeThreads).begin(); 14172292SN/A while (threads != (*activeThreads).end()) { 14182292SN/A unsigned tid = (*threads++); 14192292SN/A 14202292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14212292SN/A 14222348SN/A // Update structures based on instructions committed. 14232292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14242292SN/A !fromCommit->commitInfo[tid].squash && 14252292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14262292SN/A 14272292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14282292SN/A 14292292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14302292SN/A 14312292SN/A updateLSQNextCycle = true; 14322292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14332292SN/A } 14342292SN/A 14352292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 14362292SN/A 14372292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 14382292SN/A if (fromCommit->commitInfo[tid].uncached) { 14392292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 14402292SN/A } else { 14412292SN/A instQueue.scheduleNonSpec( 14422292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 14432292SN/A } 14442292SN/A } 14452292SN/A 14462292SN/A if (broadcast_free_entries) { 14472292SN/A toFetch->iewInfo[tid].iqCount = 14482292SN/A instQueue.getCount(tid); 14492292SN/A toFetch->iewInfo[tid].ldstqCount = 14502292SN/A ldstQueue.getCount(tid); 14512292SN/A 14522292SN/A toRename->iewInfo[tid].usedIQ = true; 14532292SN/A toRename->iewInfo[tid].freeIQEntries = 14542292SN/A instQueue.numFreeEntries(); 14552292SN/A toRename->iewInfo[tid].usedLSQ = true; 14562292SN/A toRename->iewInfo[tid].freeLSQEntries = 14572292SN/A ldstQueue.numFreeEntries(tid); 14582292SN/A 14592292SN/A wroteToTimeBuffer = true; 14602292SN/A } 14612292SN/A 14622292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 14632292SN/A tid, toRename->iewInfo[tid].dispatched); 14641061SN/A } 14651061SN/A 14662292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 14672292SN/A "LSQ has %i free entries.\n", 14682292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 14692292SN/A ldstQueue.numFreeEntries()); 14702292SN/A 14712292SN/A updateStatus(); 14722292SN/A 14732292SN/A if (wroteToTimeBuffer) { 14742292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 14752292SN/A cpu->activityThisCycle(); 14761061SN/A } 14771060SN/A} 14781060SN/A 14792301SN/Atemplate <class Impl> 14801060SN/Avoid 14812301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 14821060SN/A{ 14832301SN/A int thread_number = inst->threadNumber; 14841060SN/A 14852301SN/A // 14862301SN/A // Pick off the software prefetches 14872301SN/A // 14882301SN/A#ifdef TARGET_ALPHA 14892301SN/A if (inst->isDataPrefetch()) 14902727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 14912301SN/A else 14922727Sktlim@umich.edu iewIewExecutedcutedInsts++; 14932301SN/A#else 14942669Sktlim@umich.edu iewExecutedInsts++; 14952301SN/A#endif 14961060SN/A 14972301SN/A // 14982301SN/A // Control operations 14992301SN/A // 15002301SN/A if (inst->isControl()) 15012727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 15021060SN/A 15032301SN/A // 15042301SN/A // Memory operations 15052301SN/A // 15062301SN/A if (inst->isMemRef()) { 15072727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 15081060SN/A 15092301SN/A if (inst->isLoad()) { 15102301SN/A iewExecLoadInsts[thread_number]++; 15111060SN/A } 15121060SN/A } 15131060SN/A} 1514