iew_impl.hh revision 2702
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 412292SN/Ausing namespace std; 421681SN/A 431681SN/Atemplate<class Impl> 442292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 452326SN/A : // @todo: Make this into a parameter. 461061SN/A issueToExecQueue(5, 5), 471060SN/A instQueue(params), 481061SN/A ldstQueue(params), 492292SN/A fuPool(params->fuPool), 502292SN/A commitToIEWDelay(params->commitToIEWDelay), 512292SN/A renameToIEWDelay(params->renameToIEWDelay), 522292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 532292SN/A issueReadWidth(params->issueWidth), 542292SN/A issueWidth(params->issueWidth), 552307SN/A numThreads(params->numberOfThreads), 562307SN/A switchedOut(false) 571060SN/A{ 582292SN/A _status = Active; 592292SN/A exeStatus = Running; 602292SN/A wbStatus = Idle; 611060SN/A 621060SN/A // Setup wire to read instructions coming from issue. 631060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 641060SN/A 651060SN/A // Instruction queue needs the queue between issue and execute. 661060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 671681SN/A 682292SN/A instQueue.setIEW(this); 691681SN/A ldstQueue.setIEW(this); 702292SN/A 712292SN/A for (int i=0; i < numThreads; i++) { 722292SN/A dispatchStatus[i] = Running; 732292SN/A stalls[i].commit = false; 742292SN/A fetchRedirect[i] = false; 752292SN/A } 762292SN/A 772292SN/A updateLSQNextCycle = false; 782292SN/A 792292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 802292SN/A} 812292SN/A 822292SN/Atemplate <class Impl> 832292SN/Astd::string 842292SN/ADefaultIEW<Impl>::name() const 852292SN/A{ 862292SN/A return cpu->name() + ".iew"; 871060SN/A} 881060SN/A 891681SN/Atemplate <class Impl> 901062SN/Avoid 912292SN/ADefaultIEW<Impl>::regStats() 921062SN/A{ 932301SN/A using namespace Stats; 942301SN/A 951062SN/A instQueue.regStats(); 961062SN/A 971062SN/A iewIdleCycles 981062SN/A .name(name() + ".iewIdleCycles") 991062SN/A .desc("Number of cycles IEW is idle"); 1001062SN/A 1011062SN/A iewSquashCycles 1021062SN/A .name(name() + ".iewSquashCycles") 1031062SN/A .desc("Number of cycles IEW is squashing"); 1041062SN/A 1051062SN/A iewBlockCycles 1061062SN/A .name(name() + ".iewBlockCycles") 1071062SN/A .desc("Number of cycles IEW is blocking"); 1081062SN/A 1091062SN/A iewUnblockCycles 1101062SN/A .name(name() + ".iewUnblockCycles") 1111062SN/A .desc("Number of cycles IEW is unblocking"); 1121062SN/A 1131062SN/A iewDispatchedInsts 1141062SN/A .name(name() + ".iewDispatchedInsts") 1151062SN/A .desc("Number of instructions dispatched to IQ"); 1161062SN/A 1171062SN/A iewDispSquashedInsts 1181062SN/A .name(name() + ".iewDispSquashedInsts") 1191062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1201062SN/A 1211062SN/A iewDispLoadInsts 1221062SN/A .name(name() + ".iewDispLoadInsts") 1231062SN/A .desc("Number of dispatched load instructions"); 1241062SN/A 1251062SN/A iewDispStoreInsts 1261062SN/A .name(name() + ".iewDispStoreInsts") 1271062SN/A .desc("Number of dispatched store instructions"); 1281062SN/A 1291062SN/A iewDispNonSpecInsts 1301062SN/A .name(name() + ".iewDispNonSpecInsts") 1311062SN/A .desc("Number of dispatched non-speculative instructions"); 1321062SN/A 1331062SN/A iewIQFullEvents 1341062SN/A .name(name() + ".iewIQFullEvents") 1351062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1361062SN/A 1372292SN/A iewLSQFullEvents 1382292SN/A .name(name() + ".iewLSQFullEvents") 1392292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1402292SN/A 1411062SN/A iewExecutedInsts 1421062SN/A .name(name() + ".iewExecutedInsts") 1431062SN/A .desc("Number of executed instructions"); 1441062SN/A 1451062SN/A iewExecLoadInsts 1462301SN/A .init(cpu->number_of_threads) 1471062SN/A .name(name() + ".iewExecLoadInsts") 1482301SN/A .desc("Number of load instructions executed") 1492301SN/A .flags(total); 1501062SN/A 1511062SN/A iewExecSquashedInsts 1521062SN/A .name(name() + ".iewExecSquashedInsts") 1531062SN/A .desc("Number of squashed instructions skipped in execute"); 1541062SN/A 1551062SN/A memOrderViolationEvents 1561062SN/A .name(name() + ".memOrderViolationEvents") 1571062SN/A .desc("Number of memory order violations"); 1581062SN/A 1591062SN/A predictedTakenIncorrect 1601062SN/A .name(name() + ".predictedTakenIncorrect") 1611062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1622292SN/A 1632292SN/A predictedNotTakenIncorrect 1642292SN/A .name(name() + ".predictedNotTakenIncorrect") 1652292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1662292SN/A 1672292SN/A branchMispredicts 1682292SN/A .name(name() + ".branchMispredicts") 1692292SN/A .desc("Number of branch mispredicts detected at execute"); 1702292SN/A 1712292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1722301SN/A 1732326SN/A exeSwp 1742301SN/A .init(cpu->number_of_threads) 1752301SN/A .name(name() + ".EXEC:swp") 1762301SN/A .desc("number of swp insts executed") 1772301SN/A .flags(total) 1782301SN/A ; 1792301SN/A 1802326SN/A exeNop 1812301SN/A .init(cpu->number_of_threads) 1822301SN/A .name(name() + ".EXEC:nop") 1832301SN/A .desc("number of nop insts executed") 1842301SN/A .flags(total) 1852301SN/A ; 1862301SN/A 1872326SN/A exeRefs 1882301SN/A .init(cpu->number_of_threads) 1892301SN/A .name(name() + ".EXEC:refs") 1902301SN/A .desc("number of memory reference insts executed") 1912301SN/A .flags(total) 1922301SN/A ; 1932301SN/A 1942326SN/A exeBranches 1952301SN/A .init(cpu->number_of_threads) 1962301SN/A .name(name() + ".EXEC:branches") 1972301SN/A .desc("Number of branches executed") 1982301SN/A .flags(total) 1992301SN/A ; 2002301SN/A 2012326SN/A issueRate 2022301SN/A .name(name() + ".EXEC:rate") 2032301SN/A .desc("Inst execution rate") 2042301SN/A .flags(total) 2052301SN/A ; 2062326SN/A issueRate = iewExecutedInsts / cpu->numCycles; 2072301SN/A 2082301SN/A iewExecStoreInsts 2092301SN/A .name(name() + ".EXEC:stores") 2102301SN/A .desc("Number of stores executed") 2112301SN/A .flags(total) 2122301SN/A ; 2132326SN/A iewExecStoreInsts = exeRefs - iewExecLoadInsts; 2142301SN/A/* 2152301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2162301SN/A stringstream subname; 2172301SN/A subname << opClassStrings[i] << "_delay"; 2182301SN/A issue_delay_dist.subname(i, subname.str()); 2192301SN/A } 2202301SN/A*/ 2212301SN/A // 2222301SN/A // Other stats 2232301SN/A // 2242301SN/A 2252301SN/A iewInstsToCommit 2262301SN/A .init(cpu->number_of_threads) 2272301SN/A .name(name() + ".WB:sent") 2282301SN/A .desc("cumulative count of insts sent to commit") 2292301SN/A .flags(total) 2302301SN/A ; 2312301SN/A 2322326SN/A writebackCount 2332301SN/A .init(cpu->number_of_threads) 2342301SN/A .name(name() + ".WB:count") 2352301SN/A .desc("cumulative count of insts written-back") 2362301SN/A .flags(total) 2372301SN/A ; 2382301SN/A 2392326SN/A producerInst 2402301SN/A .init(cpu->number_of_threads) 2412301SN/A .name(name() + ".WB:producers") 2422301SN/A .desc("num instructions producing a value") 2432301SN/A .flags(total) 2442301SN/A ; 2452301SN/A 2462326SN/A consumerInst 2472301SN/A .init(cpu->number_of_threads) 2482301SN/A .name(name() + ".WB:consumers") 2492301SN/A .desc("num instructions consuming a value") 2502301SN/A .flags(total) 2512301SN/A ; 2522301SN/A 2532326SN/A wbPenalized 2542301SN/A .init(cpu->number_of_threads) 2552301SN/A .name(name() + ".WB:penalized") 2562301SN/A .desc("number of instrctions required to write to 'other' IQ") 2572301SN/A .flags(total) 2582301SN/A ; 2592301SN/A 2602326SN/A wbPenalizedRate 2612301SN/A .name(name() + ".WB:penalized_rate") 2622301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2632301SN/A .flags(total) 2642301SN/A ; 2652301SN/A 2662326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2672301SN/A 2682326SN/A wbFanout 2692301SN/A .name(name() + ".WB:fanout") 2702301SN/A .desc("average fanout of values written-back") 2712301SN/A .flags(total) 2722301SN/A ; 2732301SN/A 2742326SN/A wbFanout = producerInst / consumerInst; 2752301SN/A 2762326SN/A wbRate 2772301SN/A .name(name() + ".WB:rate") 2782301SN/A .desc("insts written-back per cycle") 2792301SN/A .flags(total) 2802301SN/A ; 2812326SN/A wbRate = writebackCount / cpu->numCycles; 2821062SN/A} 2831062SN/A 2841681SN/Atemplate<class Impl> 2851060SN/Avoid 2862292SN/ADefaultIEW<Impl>::initStage() 2871060SN/A{ 2882292SN/A for (int tid=0; tid < numThreads; tid++) { 2892292SN/A toRename->iewInfo[tid].usedIQ = true; 2902292SN/A toRename->iewInfo[tid].freeIQEntries = 2912292SN/A instQueue.numFreeEntries(tid); 2922292SN/A 2932292SN/A toRename->iewInfo[tid].usedLSQ = true; 2942292SN/A toRename->iewInfo[tid].freeLSQEntries = 2952292SN/A ldstQueue.numFreeEntries(tid); 2962292SN/A } 2972292SN/A} 2982292SN/A 2992292SN/Atemplate<class Impl> 3002292SN/Avoid 3012292SN/ADefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) 3022292SN/A{ 3032292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 3041060SN/A cpu = cpu_ptr; 3051060SN/A 3061060SN/A instQueue.setCPU(cpu_ptr); 3071061SN/A ldstQueue.setCPU(cpu_ptr); 3082292SN/A 3092292SN/A cpu->activateStage(FullCPU::IEWIdx); 3101060SN/A} 3111060SN/A 3121681SN/Atemplate<class Impl> 3131060SN/Avoid 3142292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3151060SN/A{ 3162292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 3171060SN/A timeBuffer = tb_ptr; 3181060SN/A 3191060SN/A // Setup wire to read information from time buffer, from commit. 3201060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3211060SN/A 3221060SN/A // Setup wire to write information back to previous stages. 3231060SN/A toRename = timeBuffer->getWire(0); 3241060SN/A 3252292SN/A toFetch = timeBuffer->getWire(0); 3262292SN/A 3271060SN/A // Instruction queue also needs main time buffer. 3281060SN/A instQueue.setTimeBuffer(tb_ptr); 3291060SN/A} 3301060SN/A 3311681SN/Atemplate<class Impl> 3321060SN/Avoid 3332292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3341060SN/A{ 3352292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3361060SN/A renameQueue = rq_ptr; 3371060SN/A 3381060SN/A // Setup wire to read information from rename queue. 3391060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3401060SN/A} 3411060SN/A 3421681SN/Atemplate<class Impl> 3431060SN/Avoid 3442292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3451060SN/A{ 3462292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3471060SN/A iewQueue = iq_ptr; 3481060SN/A 3491060SN/A // Setup wire to write instructions to commit. 3501060SN/A toCommit = iewQueue->getWire(0); 3511060SN/A} 3521060SN/A 3531681SN/Atemplate<class Impl> 3541060SN/Avoid 3552292SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3561060SN/A{ 3572292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3582292SN/A activeThreads = at_ptr; 3592292SN/A 3602292SN/A ldstQueue.setActiveThreads(at_ptr); 3612292SN/A instQueue.setActiveThreads(at_ptr); 3621060SN/A} 3631060SN/A 3641681SN/Atemplate<class Impl> 3651060SN/Avoid 3662292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3671060SN/A{ 3682292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3692292SN/A scoreboard = sb_ptr; 3701060SN/A} 3711060SN/A 3722307SN/Atemplate <class Impl> 3732307SN/Avoid 3742307SN/ADefaultIEW<Impl>::switchOut() 3752307SN/A{ 3762348SN/A // IEW is ready to switch out at any time. 3772316SN/A cpu->signalSwitched(); 3781681SN/A} 3791681SN/A 3802316SN/Atemplate <class Impl> 3811681SN/Avoid 3822316SN/ADefaultIEW<Impl>::doSwitchOut() 3831681SN/A{ 3842348SN/A // Clear any state. 3852307SN/A switchedOut = true; 3861681SN/A 3872307SN/A instQueue.switchOut(); 3882307SN/A ldstQueue.switchOut(); 3892307SN/A fuPool->switchOut(); 3902307SN/A 3912307SN/A for (int i = 0; i < numThreads; i++) { 3922307SN/A while (!insts[i].empty()) 3932307SN/A insts[i].pop(); 3942307SN/A while (!skidBuffer[i].empty()) 3952307SN/A skidBuffer[i].pop(); 3962307SN/A } 3971681SN/A} 3981681SN/A 3992307SN/Atemplate <class Impl> 4001681SN/Avoid 4012307SN/ADefaultIEW<Impl>::takeOverFrom() 4021060SN/A{ 4032348SN/A // Reset all state. 4042307SN/A _status = Active; 4052307SN/A exeStatus = Running; 4062307SN/A wbStatus = Idle; 4072307SN/A switchedOut = false; 4081060SN/A 4092307SN/A instQueue.takeOverFrom(); 4102307SN/A ldstQueue.takeOverFrom(); 4112307SN/A fuPool->takeOverFrom(); 4121060SN/A 4132307SN/A initStage(); 4142307SN/A cpu->activityThisCycle(); 4151060SN/A 4162307SN/A for (int i=0; i < numThreads; i++) { 4172307SN/A dispatchStatus[i] = Running; 4182307SN/A stalls[i].commit = false; 4192307SN/A fetchRedirect[i] = false; 4202307SN/A } 4211060SN/A 4222307SN/A updateLSQNextCycle = false; 4232307SN/A 4242307SN/A // @todo: Fix hardcoded number 4252307SN/A for (int i = 0; i < 6; ++i) { 4262307SN/A issueToExecQueue.advance(); 4271060SN/A } 4281060SN/A} 4291060SN/A 4301681SN/Atemplate<class Impl> 4311060SN/Avoid 4322292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4332107SN/A{ 4342292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4352292SN/A tid); 4362107SN/A 4372292SN/A // Tell the IQ to start squashing. 4382292SN/A instQueue.squash(tid); 4392107SN/A 4402292SN/A // Tell the LDSTQ to start squashing. 4412326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4422107SN/A 4432292SN/A updatedQueues = true; 4442107SN/A 4452292SN/A // Clear the skid buffer in case it has any data in it. 4462292SN/A while (!skidBuffer[tid].empty()) { 4472107SN/A 4482292SN/A if (skidBuffer[tid].front()->isLoad() || 4492292SN/A skidBuffer[tid].front()->isStore() ) { 4502292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4512292SN/A } 4522107SN/A 4532292SN/A toRename->iewInfo[tid].dispatched++; 4542107SN/A 4552292SN/A skidBuffer[tid].pop(); 4562292SN/A } 4572107SN/A 4582702Sktlim@umich.edu emptyRenameInsts(tid); 4592107SN/A} 4602107SN/A 4612107SN/Atemplate<class Impl> 4622107SN/Avoid 4632292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4642292SN/A{ 4652292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4662292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4672292SN/A 4682292SN/A toCommit->squash[tid] = true; 4692292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4702292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4712292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4722292SN/A toCommit->branchMispredict[tid] = true; 4732292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4742292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4752292SN/A 4762292SN/A toCommit->includeSquashInst[tid] = false; 4772292SN/A 4782292SN/A wroteToTimeBuffer = true; 4792292SN/A} 4802292SN/A 4812292SN/Atemplate<class Impl> 4822292SN/Avoid 4832292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4842292SN/A{ 4852292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4862292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4872292SN/A 4882292SN/A toCommit->squash[tid] = true; 4892292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4902292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4912292SN/A 4922292SN/A toCommit->includeSquashInst[tid] = false; 4932292SN/A 4942292SN/A wroteToTimeBuffer = true; 4952292SN/A} 4962292SN/A 4972292SN/Atemplate<class Impl> 4982292SN/Avoid 4992292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5002292SN/A{ 5012292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5022292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5032292SN/A 5042292SN/A toCommit->squash[tid] = true; 5052292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5062292SN/A toCommit->nextPC[tid] = inst->readPC(); 5072292SN/A 5082348SN/A // Must include the broadcasted SN in the squash. 5092292SN/A toCommit->includeSquashInst[tid] = true; 5102292SN/A 5112292SN/A ldstQueue.setLoadBlockedHandled(tid); 5122292SN/A 5132292SN/A wroteToTimeBuffer = true; 5142292SN/A} 5152292SN/A 5162292SN/Atemplate<class Impl> 5172292SN/Avoid 5182292SN/ADefaultIEW<Impl>::block(unsigned tid) 5192292SN/A{ 5202292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5212292SN/A 5222292SN/A if (dispatchStatus[tid] != Blocked && 5232292SN/A dispatchStatus[tid] != Unblocking) { 5242292SN/A toRename->iewBlock[tid] = true; 5252292SN/A wroteToTimeBuffer = true; 5262292SN/A } 5272292SN/A 5282292SN/A // Add the current inputs to the skid buffer so they can be 5292292SN/A // reprocessed when this stage unblocks. 5302292SN/A skidInsert(tid); 5312292SN/A 5322292SN/A dispatchStatus[tid] = Blocked; 5332292SN/A} 5342292SN/A 5352292SN/Atemplate<class Impl> 5362292SN/Avoid 5372292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5382292SN/A{ 5392292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5402292SN/A "buffer %u.\n",tid, tid); 5412292SN/A 5422292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5432292SN/A // Also switch status to running. 5442292SN/A if (skidBuffer[tid].empty()) { 5452292SN/A toRename->iewUnblock[tid] = true; 5462292SN/A wroteToTimeBuffer = true; 5472292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5482292SN/A dispatchStatus[tid] = Running; 5492292SN/A } 5502292SN/A} 5512292SN/A 5522292SN/Atemplate<class Impl> 5532292SN/Avoid 5542292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5551060SN/A{ 5561681SN/A instQueue.wakeDependents(inst); 5571060SN/A} 5581060SN/A 5592292SN/Atemplate<class Impl> 5602292SN/Avoid 5612292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5622292SN/A{ 5632292SN/A instQueue.rescheduleMemInst(inst); 5642292SN/A} 5651681SN/A 5661681SN/Atemplate<class Impl> 5671060SN/Avoid 5682292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5691060SN/A{ 5702292SN/A instQueue.replayMemInst(inst); 5712292SN/A} 5721060SN/A 5732292SN/Atemplate<class Impl> 5742292SN/Avoid 5752292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5762292SN/A{ 5772292SN/A // First check the time slot that this instruction will write 5782292SN/A // to. If there are free write ports at the time, then go ahead 5792292SN/A // and write the instruction to that time. If there are not, 5802292SN/A // keep looking back to see where's the first time there's a 5812326SN/A // free slot. 5822292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5832292SN/A ++wbNumInst; 5842292SN/A if (wbNumInst == issueWidth) { 5852292SN/A ++wbCycle; 5862292SN/A wbNumInst = 0; 5872292SN/A } 5882292SN/A 5892292SN/A assert(wbCycle < 5); 5902292SN/A } 5912292SN/A 5922292SN/A // Add finished instruction to queue to commit. 5932292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5942292SN/A (*iewQueue)[wbCycle].size++; 5952292SN/A} 5962292SN/A 5972292SN/Atemplate <class Impl> 5982292SN/Aunsigned 5992292SN/ADefaultIEW<Impl>::validInstsFromRename() 6002292SN/A{ 6012292SN/A unsigned inst_count = 0; 6022292SN/A 6032292SN/A for (int i=0; i<fromRename->size; i++) { 6042292SN/A if (!fromRename->insts[i]->squashed) 6052292SN/A inst_count++; 6062292SN/A } 6072292SN/A 6082292SN/A return inst_count; 6092292SN/A} 6102292SN/A 6112292SN/Atemplate<class Impl> 6122292SN/Avoid 6132292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6142292SN/A{ 6152292SN/A DynInstPtr inst = NULL; 6162292SN/A 6172292SN/A while (!insts[tid].empty()) { 6182292SN/A inst = insts[tid].front(); 6192292SN/A 6202292SN/A insts[tid].pop(); 6212292SN/A 6222292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6232292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6242292SN/A inst->readPC(),tid); 6252292SN/A 6262292SN/A skidBuffer[tid].push(inst); 6272292SN/A } 6282292SN/A 6292292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6302292SN/A "Skidbuffer Exceeded Max Size"); 6312292SN/A} 6322292SN/A 6332292SN/Atemplate<class Impl> 6342292SN/Aint 6352292SN/ADefaultIEW<Impl>::skidCount() 6362292SN/A{ 6372292SN/A int max=0; 6382292SN/A 6392292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6402292SN/A 6412292SN/A while (threads != (*activeThreads).end()) { 6422292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6432292SN/A if (max < thread_count) 6442292SN/A max = thread_count; 6452292SN/A } 6462292SN/A 6472292SN/A return max; 6482292SN/A} 6492292SN/A 6502292SN/Atemplate<class Impl> 6512292SN/Abool 6522292SN/ADefaultIEW<Impl>::skidsEmpty() 6532292SN/A{ 6542292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6552292SN/A 6562292SN/A while (threads != (*activeThreads).end()) { 6572292SN/A if (!skidBuffer[*threads++].empty()) 6582292SN/A return false; 6592292SN/A } 6602292SN/A 6612292SN/A return true; 6621062SN/A} 6631062SN/A 6641681SN/Atemplate <class Impl> 6651062SN/Avoid 6662292SN/ADefaultIEW<Impl>::updateStatus() 6671062SN/A{ 6682292SN/A bool any_unblocking = false; 6691062SN/A 6702292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6711062SN/A 6722292SN/A threads = (*activeThreads).begin(); 6731062SN/A 6742292SN/A while (threads != (*activeThreads).end()) { 6752292SN/A unsigned tid = *threads++; 6761062SN/A 6772292SN/A if (dispatchStatus[tid] == Unblocking) { 6782292SN/A any_unblocking = true; 6792292SN/A break; 6802292SN/A } 6812292SN/A } 6821062SN/A 6832292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6842292SN/A // and there's no stores waiting to write back, and dispatch is not 6852292SN/A // unblocking, then there is no internal activity for the IEW stage. 6862292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6872292SN/A !ldstQueue.willWB() && !any_unblocking) { 6882292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6891062SN/A 6902292SN/A deactivateStage(); 6911062SN/A 6922292SN/A _status = Inactive; 6932292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6942292SN/A ldstQueue.willWB() || 6952292SN/A any_unblocking)) { 6962292SN/A // Otherwise there is internal activity. Set to active. 6972292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6981062SN/A 6992292SN/A activateStage(); 7001062SN/A 7012292SN/A _status = Active; 7021062SN/A } 7031062SN/A} 7041062SN/A 7051681SN/Atemplate <class Impl> 7061062SN/Avoid 7072292SN/ADefaultIEW<Impl>::resetEntries() 7081062SN/A{ 7092292SN/A instQueue.resetEntries(); 7102292SN/A ldstQueue.resetEntries(); 7112292SN/A} 7121062SN/A 7132292SN/Atemplate <class Impl> 7142292SN/Avoid 7152292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7162292SN/A{ 7172292SN/A if (fromCommit->commitBlock[tid]) { 7182292SN/A stalls[tid].commit = true; 7192292SN/A } 7201062SN/A 7212292SN/A if (fromCommit->commitUnblock[tid]) { 7222292SN/A assert(stalls[tid].commit); 7232292SN/A stalls[tid].commit = false; 7242292SN/A } 7252292SN/A} 7262292SN/A 7272292SN/Atemplate <class Impl> 7282292SN/Abool 7292292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7302292SN/A{ 7312292SN/A bool ret_val(false); 7322292SN/A 7332292SN/A if (stalls[tid].commit) { 7342292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7352292SN/A ret_val = true; 7362292SN/A } else if (instQueue.isFull(tid)) { 7372292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7382292SN/A ret_val = true; 7392292SN/A } else if (ldstQueue.isFull(tid)) { 7402292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7412292SN/A 7422292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7432292SN/A 7442292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7452292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7462292SN/A } 7472292SN/A 7482292SN/A if (ldstQueue.numStores(tid) > 0) { 7492292SN/A 7502292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7512292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7522292SN/A } 7532292SN/A 7542292SN/A ret_val = true; 7552292SN/A } else if (ldstQueue.isStalled(tid)) { 7562292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7572292SN/A ret_val = true; 7582292SN/A } 7592292SN/A 7602292SN/A return ret_val; 7612292SN/A} 7622292SN/A 7632292SN/Atemplate <class Impl> 7642292SN/Avoid 7652292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7662292SN/A{ 7672292SN/A // Check if there's a squash signal, squash if there is 7682292SN/A // Check stall signals, block if there is. 7692292SN/A // If status was Blocked 7702292SN/A // if so then go to unblocking 7712292SN/A // If status was Squashing 7722292SN/A // check if squashing is not high. Switch to running this cycle. 7732292SN/A 7742292SN/A readStallSignals(tid); 7752292SN/A 7762292SN/A if (fromCommit->commitInfo[tid].squash) { 7772292SN/A squash(tid); 7782292SN/A 7792292SN/A if (dispatchStatus[tid] == Blocked || 7802292SN/A dispatchStatus[tid] == Unblocking) { 7812292SN/A toRename->iewUnblock[tid] = true; 7822292SN/A wroteToTimeBuffer = true; 7832292SN/A } 7842292SN/A 7852292SN/A dispatchStatus[tid] = Squashing; 7862292SN/A 7872292SN/A fetchRedirect[tid] = false; 7882292SN/A return; 7892292SN/A } 7902292SN/A 7912292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7922702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7932292SN/A 7942292SN/A dispatchStatus[tid] = Squashing; 7952292SN/A 7962702Sktlim@umich.edu emptyRenameInsts(tid); 7972702Sktlim@umich.edu wroteToTimeBuffer = true; 7982292SN/A return; 7992292SN/A } 8002292SN/A 8012292SN/A if (checkStall(tid)) { 8022292SN/A block(tid); 8032292SN/A dispatchStatus[tid] = Blocked; 8042292SN/A return; 8052292SN/A } 8062292SN/A 8072292SN/A if (dispatchStatus[tid] == Blocked) { 8082292SN/A // Status from previous cycle was blocked, but there are no more stall 8092292SN/A // conditions. Switch over to unblocking. 8102292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8112292SN/A tid); 8122292SN/A 8132292SN/A dispatchStatus[tid] = Unblocking; 8142292SN/A 8152292SN/A unblock(tid); 8162292SN/A 8172292SN/A return; 8182292SN/A } 8192292SN/A 8202292SN/A if (dispatchStatus[tid] == Squashing) { 8212292SN/A // Switch status to running if rename isn't being told to block or 8222292SN/A // squash this cycle. 8232292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8242292SN/A tid); 8252292SN/A 8262292SN/A dispatchStatus[tid] = Running; 8272292SN/A 8282292SN/A return; 8292292SN/A } 8302292SN/A} 8312292SN/A 8322292SN/Atemplate <class Impl> 8332292SN/Avoid 8342292SN/ADefaultIEW<Impl>::sortInsts() 8352292SN/A{ 8362292SN/A int insts_from_rename = fromRename->size; 8372326SN/A#ifdef DEBUG 8382292SN/A for (int i = 0; i < numThreads; i++) 8392292SN/A assert(insts[i].empty()); 8402326SN/A#endif 8412292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8422292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8432292SN/A } 8442292SN/A} 8452292SN/A 8462292SN/Atemplate <class Impl> 8472292SN/Avoid 8482702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8492702Sktlim@umich.edu{ 8502702Sktlim@umich.edu while (!insts[tid].empty()) { 8512702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8522702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8532702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8542702Sktlim@umich.edu } 8552702Sktlim@umich.edu 8562702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8572702Sktlim@umich.edu 8582702Sktlim@umich.edu insts[tid].pop(); 8592702Sktlim@umich.edu } 8602702Sktlim@umich.edu} 8612702Sktlim@umich.edu 8622702Sktlim@umich.edutemplate <class Impl> 8632702Sktlim@umich.eduvoid 8642292SN/ADefaultIEW<Impl>::wakeCPU() 8652292SN/A{ 8662292SN/A cpu->wakeCPU(); 8672292SN/A} 8682292SN/A 8692292SN/Atemplate <class Impl> 8702292SN/Avoid 8712292SN/ADefaultIEW<Impl>::activityThisCycle() 8722292SN/A{ 8732292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8742292SN/A cpu->activityThisCycle(); 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Ainline void 8792292SN/ADefaultIEW<Impl>::activateStage() 8802292SN/A{ 8812292SN/A DPRINTF(Activity, "Activating stage.\n"); 8822292SN/A cpu->activateStage(FullCPU::IEWIdx); 8832292SN/A} 8842292SN/A 8852292SN/Atemplate <class Impl> 8862292SN/Ainline void 8872292SN/ADefaultIEW<Impl>::deactivateStage() 8882292SN/A{ 8892292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8902292SN/A cpu->deactivateStage(FullCPU::IEWIdx); 8912292SN/A} 8922292SN/A 8932292SN/Atemplate<class Impl> 8942292SN/Avoid 8952292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8962292SN/A{ 8972292SN/A // If status is Running or idle, 8982292SN/A // call dispatchInsts() 8992292SN/A // If status is Unblocking, 9002292SN/A // buffer any instructions coming from rename 9012292SN/A // continue trying to empty skid buffer 9022292SN/A // check if stall conditions have passed 9032292SN/A 9042292SN/A if (dispatchStatus[tid] == Blocked) { 9052292SN/A ++iewBlockCycles; 9062292SN/A 9072292SN/A } else if (dispatchStatus[tid] == Squashing) { 9082292SN/A ++iewSquashCycles; 9092292SN/A } 9102292SN/A 9112292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9122292SN/A // will allow, as long as it is not currently blocked. 9132292SN/A if (dispatchStatus[tid] == Running || 9142292SN/A dispatchStatus[tid] == Idle) { 9152292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9162292SN/A "dispatch.\n", tid); 9172292SN/A 9182292SN/A dispatchInsts(tid); 9192292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9202292SN/A // Make sure that the skid buffer has something in it if the 9212292SN/A // status is unblocking. 9222292SN/A assert(!skidsEmpty()); 9232292SN/A 9242292SN/A // If the status was unblocking, then instructions from the skid 9252292SN/A // buffer were used. Remove those instructions and handle 9262292SN/A // the rest of unblocking. 9272292SN/A dispatchInsts(tid); 9282292SN/A 9292292SN/A ++iewUnblockCycles; 9302292SN/A 9312292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9322292SN/A // Add the current inputs to the skid buffer so they can be 9332292SN/A // reprocessed when this stage unblocks. 9342292SN/A skidInsert(tid); 9352292SN/A } 9362292SN/A 9372292SN/A unblock(tid); 9382292SN/A } 9392292SN/A} 9402292SN/A 9412292SN/Atemplate <class Impl> 9422292SN/Avoid 9432292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9442292SN/A{ 9452292SN/A dispatchedAllInsts = true; 9462292SN/A 9472292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9482292SN/A // otherwise. 9492292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9502292SN/A dispatchStatus[tid] == Unblocking ? 9512292SN/A skidBuffer[tid] : insts[tid]; 9522292SN/A 9532292SN/A int insts_to_add = insts_to_dispatch.size(); 9542292SN/A 9552292SN/A DynInstPtr inst; 9562292SN/A bool add_to_iq = false; 9572292SN/A int dis_num_inst = 0; 9582292SN/A 9592292SN/A // Loop through the instructions, putting them in the instruction 9602292SN/A // queue. 9612292SN/A for ( ; dis_num_inst < insts_to_add && 9622292SN/A dis_num_inst < issueReadWidth; 9632292SN/A ++dis_num_inst) 9642292SN/A { 9652292SN/A inst = insts_to_dispatch.front(); 9662292SN/A 9672292SN/A if (dispatchStatus[tid] == Unblocking) { 9682292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9692292SN/A "buffer\n", tid); 9702292SN/A } 9712292SN/A 9722292SN/A // Make sure there's a valid instruction there. 9732292SN/A assert(inst); 9742292SN/A 9752292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9762292SN/A "IQ.\n", 9772292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9782292SN/A 9792292SN/A // Be sure to mark these instructions as ready so that the 9802292SN/A // commit stage can go ahead and execute them, and mark 9812292SN/A // them as issued so the IQ doesn't reprocess them. 9822292SN/A 9832292SN/A // Check for squashed instructions. 9842292SN/A if (inst->isSquashed()) { 9852292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9862292SN/A "not adding to IQ.\n", tid); 9872292SN/A 9882292SN/A ++iewDispSquashedInsts; 9892292SN/A 9902292SN/A insts_to_dispatch.pop(); 9912292SN/A 9922292SN/A //Tell Rename That An Instruction has been processed 9932292SN/A if (inst->isLoad() || inst->isStore()) { 9942292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9952292SN/A } 9962292SN/A toRename->iewInfo[tid].dispatched++; 9972292SN/A 9982292SN/A continue; 9992292SN/A } 10002292SN/A 10012292SN/A // Check for full conditions. 10022292SN/A if (instQueue.isFull(tid)) { 10032292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10042292SN/A 10052292SN/A // Call function to start blocking. 10062292SN/A block(tid); 10072292SN/A 10082292SN/A // Set unblock to false. Special case where we are using 10092292SN/A // skidbuffer (unblocking) instructions but then we still 10102292SN/A // get full in the IQ. 10112292SN/A toRename->iewUnblock[tid] = false; 10122292SN/A 10132292SN/A dispatchedAllInsts = false; 10142292SN/A 10152292SN/A ++iewIQFullEvents; 10162292SN/A break; 10172292SN/A } else if (ldstQueue.isFull(tid)) { 10182292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10192292SN/A 10202292SN/A // Call function to start blocking. 10212292SN/A block(tid); 10222292SN/A 10232292SN/A // Set unblock to false. Special case where we are using 10242292SN/A // skidbuffer (unblocking) instructions but then we still 10252292SN/A // get full in the IQ. 10262292SN/A toRename->iewUnblock[tid] = false; 10272292SN/A 10282292SN/A dispatchedAllInsts = false; 10292292SN/A 10302292SN/A ++iewLSQFullEvents; 10312292SN/A break; 10322292SN/A } 10332292SN/A 10342292SN/A // Otherwise issue the instruction just fine. 10352292SN/A if (inst->isLoad()) { 10362292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10372292SN/A "encountered, adding to LSQ.\n", tid); 10382292SN/A 10392292SN/A // Reserve a spot in the load store queue for this 10402292SN/A // memory access. 10412292SN/A ldstQueue.insertLoad(inst); 10422292SN/A 10432292SN/A ++iewDispLoadInsts; 10442292SN/A 10452292SN/A add_to_iq = true; 10462292SN/A 10472292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10482292SN/A } else if (inst->isStore()) { 10492292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10502292SN/A "encountered, adding to LSQ.\n", tid); 10512292SN/A 10522292SN/A ldstQueue.insertStore(inst); 10532292SN/A 10542292SN/A ++iewDispStoreInsts; 10552292SN/A 10562336SN/A if (inst->isStoreConditional()) { 10572336SN/A // Store conditionals need to be set as "canCommit()" 10582336SN/A // so that commit can process them when they reach the 10592336SN/A // head of commit. 10602348SN/A // @todo: This is somewhat specific to Alpha. 10612292SN/A inst->setCanCommit(); 10622292SN/A instQueue.insertNonSpec(inst); 10632292SN/A add_to_iq = false; 10642292SN/A 10652292SN/A ++iewDispNonSpecInsts; 10662292SN/A } else { 10672292SN/A add_to_iq = true; 10682292SN/A } 10692292SN/A 10702292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10712292SN/A#if FULL_SYSTEM 10722292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10732326SN/A // Same as non-speculative stores. 10742292SN/A inst->setCanCommit(); 10752292SN/A instQueue.insertBarrier(inst); 10762292SN/A add_to_iq = false; 10772292SN/A#endif 10782292SN/A } else if (inst->isNonSpeculative()) { 10792292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 10802292SN/A "encountered, skipping.\n", tid); 10812292SN/A 10822326SN/A // Same as non-speculative stores. 10832292SN/A inst->setCanCommit(); 10842292SN/A 10852292SN/A // Specifically insert it as nonspeculative. 10862292SN/A instQueue.insertNonSpec(inst); 10872292SN/A 10882292SN/A ++iewDispNonSpecInsts; 10892292SN/A 10902292SN/A add_to_iq = false; 10912292SN/A } else if (inst->isNop()) { 10922292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10932292SN/A "skipping.\n", tid); 10942292SN/A 10952292SN/A inst->setIssued(); 10962292SN/A inst->setExecuted(); 10972292SN/A inst->setCanCommit(); 10982292SN/A 10992326SN/A instQueue.recordProducer(inst); 11002292SN/A 11012326SN/A exeNop[tid]++; 11022301SN/A 11032292SN/A add_to_iq = false; 11042292SN/A } else if (inst->isExecuted()) { 11052292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11062292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11072292SN/A "skipping.\n"); 11082292SN/A 11092292SN/A inst->setIssued(); 11102292SN/A inst->setCanCommit(); 11112292SN/A 11122326SN/A instQueue.recordProducer(inst); 11132292SN/A 11142292SN/A add_to_iq = false; 11152292SN/A } else { 11162292SN/A add_to_iq = true; 11172292SN/A } 11182292SN/A 11192292SN/A // If the instruction queue is not full, then add the 11202292SN/A // instruction. 11212292SN/A if (add_to_iq) { 11222292SN/A instQueue.insert(inst); 11232292SN/A } 11242292SN/A 11252292SN/A insts_to_dispatch.pop(); 11262292SN/A 11272292SN/A toRename->iewInfo[tid].dispatched++; 11282292SN/A 11292292SN/A ++iewDispatchedInsts; 11302292SN/A } 11312292SN/A 11322292SN/A if (!insts_to_dispatch.empty()) { 11332292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11342292SN/A block(tid); 11352292SN/A toRename->iewUnblock[tid] = false; 11362292SN/A } 11372292SN/A 11382292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11392292SN/A dispatchStatus[tid] = Running; 11402292SN/A 11412292SN/A updatedQueues = true; 11422292SN/A } 11432292SN/A 11442292SN/A dis_num_inst = 0; 11452292SN/A} 11462292SN/A 11472292SN/Atemplate <class Impl> 11482292SN/Avoid 11492292SN/ADefaultIEW<Impl>::printAvailableInsts() 11502292SN/A{ 11512292SN/A int inst = 0; 11522292SN/A 11532292SN/A cout << "Available Instructions: "; 11542292SN/A 11552292SN/A while (fromIssue->insts[inst]) { 11562292SN/A 11572292SN/A if (inst%3==0) cout << "\n\t"; 11582292SN/A 11592292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 11602292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11612292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11622292SN/A 11632292SN/A inst++; 11642292SN/A 11652292SN/A } 11662292SN/A 11672292SN/A cout << "\n"; 11682292SN/A} 11692292SN/A 11702292SN/Atemplate <class Impl> 11712292SN/Avoid 11722292SN/ADefaultIEW<Impl>::executeInsts() 11732292SN/A{ 11742292SN/A wbNumInst = 0; 11752292SN/A wbCycle = 0; 11762292SN/A 11772292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11782292SN/A 11792292SN/A while (threads != (*activeThreads).end()) { 11802292SN/A unsigned tid = *threads++; 11812292SN/A fetchRedirect[tid] = false; 11822292SN/A } 11832292SN/A 11842698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11852698Sktlim@umich.edu// printAvailableInsts(); 11861062SN/A 11871062SN/A // Execute/writeback any instructions that are available. 11882333SN/A int insts_to_execute = fromIssue->size; 11892292SN/A int inst_num = 0; 11902333SN/A for (; inst_num < insts_to_execute; 11912326SN/A ++inst_num) { 11921062SN/A 11932292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11941062SN/A 11952333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11961062SN/A 11972292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11982292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11991062SN/A 12001062SN/A // Check if the instruction is squashed; if so then skip it 12011062SN/A if (inst->isSquashed()) { 12022292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12031062SN/A 12041062SN/A // Consider this instruction executed so that commit can go 12051062SN/A // ahead and retire the instruction. 12061062SN/A inst->setExecuted(); 12071062SN/A 12082292SN/A // Not sure if I should set this here or just let commit try to 12092292SN/A // commit any squashed instructions. I like the latter a bit more. 12102292SN/A inst->setCanCommit(); 12111062SN/A 12121062SN/A ++iewExecSquashedInsts; 12131062SN/A 12141062SN/A continue; 12151062SN/A } 12161062SN/A 12172292SN/A Fault fault = NoFault; 12181062SN/A 12191062SN/A // Execute instruction. 12201062SN/A // Note that if the instruction faults, it will be handled 12211062SN/A // at the commit stage. 12222292SN/A if (inst->isMemRef() && 12232292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12242292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12251062SN/A "reference.\n"); 12261062SN/A 12271062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12281062SN/A if (inst->isLoad()) { 12292292SN/A // Loads will mark themselves as executed, and their writeback 12302292SN/A // event adds the instruction to the queue to commit 12312292SN/A fault = ldstQueue.executeLoad(inst); 12321062SN/A } else if (inst->isStore()) { 12331681SN/A ldstQueue.executeStore(inst); 12341062SN/A 12352292SN/A // If the store had a fault then it may not have a mem req 12362669Sktlim@umich.edu if (inst->req && !(inst->req->getFlags() & LOCKED)) { 12372292SN/A inst->setExecuted(); 12382292SN/A 12392292SN/A instToCommit(inst); 12402292SN/A } 12412326SN/A 12422326SN/A // Store conditionals will mark themselves as 12432326SN/A // executed, and their writeback event will add the 12442326SN/A // instruction to the queue to commit. 12451062SN/A } else { 12462292SN/A panic("Unexpected memory type!\n"); 12471062SN/A } 12481062SN/A 12491062SN/A } else { 12501062SN/A inst->execute(); 12511062SN/A 12522292SN/A inst->setExecuted(); 12532292SN/A 12542292SN/A instToCommit(inst); 12551062SN/A } 12561062SN/A 12572301SN/A updateExeInstStats(inst); 12581681SN/A 12592326SN/A // Check if branch prediction was correct, if not then we need 12602326SN/A // to tell commit to squash in flight instructions. Only 12612326SN/A // handle this if there hasn't already been something that 12622107SN/A // redirects fetch in this group of instructions. 12631681SN/A 12642292SN/A // This probably needs to prioritize the redirects if a different 12652292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12662292SN/A // instruction first, so the branch resolution order will be correct. 12672292SN/A unsigned tid = inst->threadNumber; 12681062SN/A 12692292SN/A if (!fetchRedirect[tid]) { 12701062SN/A 12711062SN/A if (inst->mispredicted()) { 12722292SN/A fetchRedirect[tid] = true; 12731062SN/A 12742292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12752292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 12761062SN/A inst->nextPC); 12771062SN/A 12781062SN/A // If incorrect, then signal the ROB that it must be squashed. 12792292SN/A squashDueToBranch(inst, tid); 12801062SN/A 12811062SN/A if (inst->predTaken()) { 12821062SN/A predictedTakenIncorrect++; 12832292SN/A } else { 12842292SN/A predictedNotTakenIncorrect++; 12851062SN/A } 12862292SN/A } else if (ldstQueue.violation(tid)) { 12872292SN/A fetchRedirect[tid] = true; 12881062SN/A 12892326SN/A // If there was an ordering violation, then get the 12902326SN/A // DynInst that caused the violation. Note that this 12912292SN/A // clears the violation signal. 12922292SN/A DynInstPtr violator; 12932292SN/A violator = ldstQueue.getMemDepViolator(tid); 12941062SN/A 12952292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 12961062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 12971062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 12981062SN/A 12991062SN/A // Tell the instruction queue that a violation has occured. 13001062SN/A instQueue.violation(inst, violator); 13011062SN/A 13021062SN/A // Squash. 13032292SN/A squashDueToMemOrder(inst,tid); 13041062SN/A 13051062SN/A ++memOrderViolationEvents; 13062292SN/A } else if (ldstQueue.loadBlocked(tid) && 13072292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13082292SN/A fetchRedirect[tid] = true; 13092292SN/A 13102292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13112292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13122292SN/A inst->readPC(), inst->seqNum); 13132292SN/A 13142292SN/A squashDueToMemBlocked(inst, tid); 13151062SN/A } 13161062SN/A } 13171062SN/A } 13182292SN/A 13192348SN/A // Update and record activity if we processed any instructions. 13202292SN/A if (inst_num) { 13212292SN/A if (exeStatus == Idle) { 13222292SN/A exeStatus = Running; 13232292SN/A } 13242292SN/A 13252292SN/A updatedQueues = true; 13262292SN/A 13272292SN/A cpu->activityThisCycle(); 13282292SN/A } 13292292SN/A 13302292SN/A // Need to reset this in case a writeback event needs to write into the 13312292SN/A // iew queue. That way the writeback event will write into the correct 13322292SN/A // spot in the queue. 13332292SN/A wbNumInst = 0; 13342107SN/A} 13352107SN/A 13362292SN/Atemplate <class Impl> 13372107SN/Avoid 13382292SN/ADefaultIEW<Impl>::writebackInsts() 13392107SN/A{ 13402326SN/A // Loop through the head of the time buffer and wake any 13412326SN/A // dependents. These instructions are about to write back. Also 13422326SN/A // mark scoreboard that this instruction is finally complete. 13432326SN/A // Either have IEW have direct access to scoreboard, or have this 13442326SN/A // as part of backwards communication. 13452107SN/A for (int inst_num = 0; inst_num < issueWidth && 13462292SN/A toCommit->insts[inst_num]; inst_num++) { 13472107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13482301SN/A int tid = inst->threadNumber; 13492107SN/A 13502698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13512698Sktlim@umich.edu inst->seqNum, inst->readPC()); 13522107SN/A 13532301SN/A iewInstsToCommit[tid]++; 13542301SN/A 13552292SN/A // Some instructions will be sent to commit without having 13562292SN/A // executed because they need commit to handle them. 13572292SN/A // E.g. Uncached loads have not actually executed when they 13582292SN/A // are first sent to commit. Instead commit must tell the LSQ 13592292SN/A // when it's ready to execute the uncached load. 13602292SN/A if (!inst->isSquashed() && inst->isExecuted()) { 13612301SN/A int dependents = instQueue.wakeDependents(inst); 13622107SN/A 13632292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 13642292SN/A //mark as Ready 13652292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 13662292SN/A inst->renamedDestRegIdx(i)); 13672292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 13682107SN/A } 13692301SN/A 13702348SN/A if (dependents) { 13712348SN/A producerInst[tid]++; 13722348SN/A consumerInst[tid]+= dependents; 13732348SN/A } 13742326SN/A writebackCount[tid]++; 13752107SN/A } 13762107SN/A } 13771060SN/A} 13781060SN/A 13791681SN/Atemplate<class Impl> 13801060SN/Avoid 13812292SN/ADefaultIEW<Impl>::tick() 13821060SN/A{ 13832292SN/A wbNumInst = 0; 13842292SN/A wbCycle = 0; 13851060SN/A 13862292SN/A wroteToTimeBuffer = false; 13872292SN/A updatedQueues = false; 13881060SN/A 13892292SN/A sortInsts(); 13901060SN/A 13912326SN/A // Free function units marked as being freed this cycle. 13922326SN/A fuPool->processFreeUnits(); 13931062SN/A 13942292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 13951060SN/A 13962326SN/A // Check stall and squash signals, dispatch any instructions. 13972292SN/A while (threads != (*activeThreads).end()) { 13982292SN/A unsigned tid = *threads++; 13991060SN/A 14002292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14011060SN/A 14022292SN/A checkSignalsAndUpdate(tid); 14032292SN/A dispatch(tid); 14041060SN/A } 14051060SN/A 14062292SN/A if (exeStatus != Squashing) { 14072292SN/A executeInsts(); 14081060SN/A 14092292SN/A writebackInsts(); 14102292SN/A 14112292SN/A // Have the instruction queue try to schedule any ready instructions. 14122292SN/A // (In actuality, this scheduling is for instructions that will 14132292SN/A // be executed next cycle.) 14142292SN/A instQueue.scheduleReadyInsts(); 14152292SN/A 14162292SN/A // Also should advance its own time buffers if the stage ran. 14172292SN/A // Not the best place for it, but this works (hopefully). 14182292SN/A issueToExecQueue.advance(); 14192292SN/A } 14202292SN/A 14212292SN/A bool broadcast_free_entries = false; 14222292SN/A 14232292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14242292SN/A exeStatus = Idle; 14252292SN/A updateLSQNextCycle = false; 14262292SN/A 14272292SN/A broadcast_free_entries = true; 14282292SN/A } 14292292SN/A 14302292SN/A // Writeback any stores using any leftover bandwidth. 14311681SN/A ldstQueue.writebackStores(); 14321681SN/A 14331061SN/A // Check the committed load/store signals to see if there's a load 14341061SN/A // or store to commit. Also check if it's being told to execute a 14351061SN/A // nonspeculative instruction. 14361681SN/A // This is pretty inefficient... 14372292SN/A 14382292SN/A threads = (*activeThreads).begin(); 14392292SN/A while (threads != (*activeThreads).end()) { 14402292SN/A unsigned tid = (*threads++); 14412292SN/A 14422292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14432292SN/A 14442348SN/A // Update structures based on instructions committed. 14452292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14462292SN/A !fromCommit->commitInfo[tid].squash && 14472292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14482292SN/A 14492292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14502292SN/A 14512292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14522292SN/A 14532292SN/A updateLSQNextCycle = true; 14542292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14552292SN/A } 14562292SN/A 14572292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 14582292SN/A 14592292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 14602292SN/A if (fromCommit->commitInfo[tid].uncached) { 14612292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 14622292SN/A } else { 14632292SN/A instQueue.scheduleNonSpec( 14642292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 14652292SN/A } 14662292SN/A } 14672292SN/A 14682292SN/A if (broadcast_free_entries) { 14692292SN/A toFetch->iewInfo[tid].iqCount = 14702292SN/A instQueue.getCount(tid); 14712292SN/A toFetch->iewInfo[tid].ldstqCount = 14722292SN/A ldstQueue.getCount(tid); 14732292SN/A 14742292SN/A toRename->iewInfo[tid].usedIQ = true; 14752292SN/A toRename->iewInfo[tid].freeIQEntries = 14762292SN/A instQueue.numFreeEntries(); 14772292SN/A toRename->iewInfo[tid].usedLSQ = true; 14782292SN/A toRename->iewInfo[tid].freeLSQEntries = 14792292SN/A ldstQueue.numFreeEntries(tid); 14802292SN/A 14812292SN/A wroteToTimeBuffer = true; 14822292SN/A } 14832292SN/A 14842292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 14852292SN/A tid, toRename->iewInfo[tid].dispatched); 14861061SN/A } 14871061SN/A 14882292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 14892292SN/A "LSQ has %i free entries.\n", 14902292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 14912292SN/A ldstQueue.numFreeEntries()); 14922292SN/A 14932292SN/A updateStatus(); 14942292SN/A 14952292SN/A if (wroteToTimeBuffer) { 14962292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 14972292SN/A cpu->activityThisCycle(); 14981061SN/A } 14991060SN/A} 15001060SN/A 15012301SN/Atemplate <class Impl> 15021060SN/Avoid 15032301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15041060SN/A{ 15052301SN/A int thread_number = inst->threadNumber; 15061060SN/A 15072301SN/A // 15082301SN/A // Pick off the software prefetches 15092301SN/A // 15102301SN/A#ifdef TARGET_ALPHA 15112301SN/A if (inst->isDataPrefetch()) 15122326SN/A exeSwp[thread_number]++; 15132301SN/A else 15142301SN/A iewExecutedInsts++; 15152301SN/A#else 15162669Sktlim@umich.edu iewExecutedInsts++; 15172301SN/A#endif 15181060SN/A 15192301SN/A // 15202301SN/A // Control operations 15212301SN/A // 15222301SN/A if (inst->isControl()) 15232326SN/A exeBranches[thread_number]++; 15241060SN/A 15252301SN/A // 15262301SN/A // Memory operations 15272301SN/A // 15282301SN/A if (inst->isMemRef()) { 15292326SN/A exeRefs[thread_number]++; 15301060SN/A 15312301SN/A if (inst->isLoad()) { 15322301SN/A iewExecLoadInsts[thread_number]++; 15331060SN/A } 15341060SN/A } 15351060SN/A} 1536