iew_impl.hh revision 14194
11689SN/A/* 22326SN/A * Copyright (c) 2010-2013, 2018 ARM Limited 31689SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * The license below extends only to copyright in the software and shall 71689SN/A * not be construed as granting a license to any other intellectual 81689SN/A * property including but not limited to intellectual property relating 91689SN/A * to a hardware implementation of the functionality of the software 101689SN/A * licensed hereunder. You may use the software subject to the license 111689SN/A * terms below provided that you ensure that this notice is replicated 121689SN/A * unmodified and in its entirety in all distributions of the software, 131689SN/A * modified or unmodified, in source code or in binary form. 141689SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292831Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322064SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354167Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381717SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 401061SN/A * 412292SN/A * Authors: Kevin Lim 422292SN/A */ 432292SN/A 442292SN/A#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 452326SN/A#define __CPU_O3_IEW_IMPL_IMPL_HH__ 461060SN/A 472292SN/A// @todo: Fix the instantaneous communication among all the stages within 482292SN/A// iew. There's a clear delay between issue and execute, yet backwards 492292SN/A// communication happens simultaneously. 502292SN/A 512292SN/A#include <queue> 522292SN/A 532292SN/A#include "arch/utility.hh" 542326SN/A#include "config/the_isa.hh" 552292SN/A#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 572292SN/A#include "cpu/o3/iew.hh" 582292SN/A#include "cpu/timebuf.hh" 592292SN/A#include "debug/Activity.hh" 602292SN/A#include "debug/Drain.hh" 612292SN/A#include "debug/IEW.hh" 622292SN/A#include "debug/O3PipeView.hh" 632292SN/A#include "params/DerivO3CPU.hh" 642292SN/A 652292SN/Ausing namespace std; 662292SN/A 672292SN/Atemplate<class Impl> 682669Sktlim@umich.eduDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692292SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 702292SN/A cpu(_cpu), 712292SN/A instQueue(_cpu, this, params), 722292SN/A ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772307SN/A dispatchWidth(params->dispatchWidth), 782307SN/A issueWidth(params->issueWidth), 792292SN/A wbNumInst(0), 801060SN/A wbCycle(0), 811060SN/A wbWidth(params->wbWidth), 821060SN/A numThreads(params->numThreads) 831060SN/A{ 841060SN/A if (dispatchWidth > Impl::MaxWidth) 851060SN/A fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 862326SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 871060SN/A dispatchWidth, static_cast<int>(Impl::MaxWidth)); 881060SN/A if (issueWidth > Impl::MaxWidth) 891060SN/A fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 901060SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 912292SN/A issueWidth, static_cast<int>(Impl::MaxWidth)); 922292SN/A if (wbWidth > Impl::MaxWidth) 932292SN/A fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 942292SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 951060SN/A wbWidth, static_cast<int>(Impl::MaxWidth)); 961060SN/A 972307SN/A _status = Active; 982292SN/A exeStatus = Running; 992980Sgblack@eecs.umich.edu wbStatus = Idle; 1002292SN/A 1012292SN/A // Setup wire to read instructions coming from issue. 1022292SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1032292SN/A 1042292SN/A // Instruction queue needs the queue between issue and execute. 1052292SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1062292SN/A 1072292SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1082292SN/A dispatchStatus[tid] = Running; 1092292SN/A fetchRedirect[tid] = false; 1102292SN/A } 1112292SN/A 1122292SN/A updateLSQNextCycle = false; 1132292SN/A 1142292SN/A skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1152292SN/A} 1162292SN/A 1172292SN/Atemplate <class Impl> 1182292SN/Astd::string 1192292SN/ADefaultIEW<Impl>::name() const 1202292SN/A{ 1212292SN/A return cpu->name() + ".iew"; 1222292SN/A} 1232292SN/A 1242292SN/Atemplate <class Impl> 1254318Sktlim@umich.eduvoid 1262831Sksewell@umich.eduDefaultIEW<Impl>::regProbePoints() 1272292SN/A{ 1284318Sktlim@umich.edu ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1292292SN/A ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1302292SN/A /** 1312292SN/A * Probe point with dynamic instruction as the argument used to probe when 1322292SN/A * an instruction starts to execute. 1332292SN/A */ 1342292SN/A ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 1352292SN/A "Execute"); 1362292SN/A /** 1372292SN/A * Probe point with dynamic instruction as the argument used to probe when 1382292SN/A * an instruction execution completes and it is marked ready to commit. 1392292SN/A */ 1402292SN/A ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 1412292SN/A "ToCommit"); 1424318Sktlim@umich.edu} 1432831Sksewell@umich.edu 1442292SN/Atemplate <class Impl> 1454318Sktlim@umich.eduvoid 1462292SN/ADefaultIEW<Impl>::regStats() 1472292SN/A{ 1482292SN/A using namespace Stats; 1492292SN/A 1502292SN/A instQueue.regStats(); 1512292SN/A ldstQueue.regStats(); 1522292SN/A 1532292SN/A iewIdleCycles 1542292SN/A .name(name() + ".iewIdleCycles") 1552326SN/A .desc("Number of cycles IEW is idle"); 1562348SN/A 1572326SN/A iewSquashCycles 1582326SN/A .name(name() + ".iewSquashCycles") 1592348SN/A .desc("Number of cycles IEW is squashing"); 1602292SN/A 1612292SN/A iewBlockCycles 1622292SN/A .name(name() + ".iewBlockCycles") 1632292SN/A .desc("Number of cycles IEW is blocking"); 1642292SN/A 1652292SN/A iewUnblockCycles 1662292SN/A .name(name() + ".iewUnblockCycles") 1671060SN/A .desc("Number of cycles IEW is unblocking"); 1681060SN/A 1691061SN/A iewDispatchedInsts 1701060SN/A .name(name() + ".iewDispatchedInsts") 1711062SN/A .desc("Number of instructions dispatched to IQ"); 1721062SN/A 1732301SN/A iewDispSquashedInsts 1741062SN/A .name(name() + ".iewDispSquashedInsts") 1751062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1761062SN/A 1771062SN/A iewDispLoadInsts 1781062SN/A .name(name() + ".iewDispLoadInsts") 1791062SN/A .desc("Number of dispatched load instructions"); 1801062SN/A 1811062SN/A iewDispStoreInsts 1821062SN/A .name(name() + ".iewDispStoreInsts") 1831062SN/A .desc("Number of dispatched store instructions"); 1842301SN/A 1852301SN/A iewDispNonSpecInsts 1862301SN/A .name(name() + ".iewDispNonSpecInsts") 1872301SN/A .desc("Number of dispatched non-speculative instructions"); 1881062SN/A 1891062SN/A iewIQFullEvents 1901062SN/A .name(name() + ".iewIQFullEvents") 1911062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1921062SN/A 1931062SN/A iewLSQFullEvents 1941062SN/A .name(name() + ".iewLSQFullEvents") 1951062SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1961062SN/A 1971062SN/A memOrderViolationEvents 1981062SN/A .name(name() + ".memOrderViolationEvents") 1991062SN/A .desc("Number of memory order violations"); 2001062SN/A 2011062SN/A predictedTakenIncorrect 2021062SN/A .name(name() + ".predictedTakenIncorrect") 2031062SN/A .desc("Number of branches that were predicted taken incorrectly"); 2041062SN/A 2051062SN/A predictedNotTakenIncorrect 2061062SN/A .name(name() + ".predictedNotTakenIncorrect") 2071062SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2081062SN/A 2091062SN/A branchMispredicts 2101062SN/A .name(name() + ".branchMispredicts") 2111062SN/A .desc("Number of branch mispredicts detected at execute"); 2121062SN/A 2131062SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2141062SN/A 2151062SN/A iewExecutedInsts 2161062SN/A .name(name() + ".iewExecutedInsts") 2171062SN/A .desc("Number of executed instructions"); 2181062SN/A 2191062SN/A iewExecLoadInsts 2201062SN/A .init(cpu->numThreads) 2211062SN/A .name(name() + ".iewExecLoadInsts") 2221062SN/A .desc("Number of load instructions executed") 2231062SN/A .flags(total); 2241062SN/A 2251062SN/A iewExecSquashedInsts 2261062SN/A .name(name() + ".iewExecSquashedInsts") 2271062SN/A .desc("Number of squashed instructions skipped in execute"); 2281062SN/A 2291062SN/A iewExecutedSwp 2301062SN/A .init(cpu->numThreads) 2311062SN/A .name(name() + ".exec_swp") 2321062SN/A .desc("number of swp insts executed") 2331062SN/A .flags(total); 2341062SN/A 2352361SN/A iewExecutedNop 2362326SN/A .init(cpu->numThreads) 2372301SN/A .name(name() + ".exec_nop") 2382301SN/A .desc("number of nop insts executed") 2392301SN/A .flags(total); 2402301SN/A 2412301SN/A iewExecutedRefs 2422301SN/A .init(cpu->numThreads) 2432326SN/A .name(name() + ".exec_refs") 2442301SN/A .desc("number of memory reference insts executed") 2452361SN/A .flags(total); 2462326SN/A 2472307SN/A iewExecutedBranches 2482301SN/A .init(cpu->numThreads) 2492301SN/A .name(name() + ".exec_branches") 2502307SN/A .desc("Number of branches executed") 2512301SN/A .flags(total); 2522301SN/A 2532301SN/A iewExecStoreInsts 2542301SN/A .name(name() + ".exec_stores") 2552301SN/A .desc("Number of stores executed") 2562301SN/A .flags(total); 2572301SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2582301SN/A 2592301SN/A iewExecRate 2602301SN/A .name(name() + ".exec_rate") 2612301SN/A .desc("Inst execution rate") 2622301SN/A .flags(total); 2632326SN/A 2642301SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2652301SN/A 2662301SN/A iewInstsToCommit 2672301SN/A .init(cpu->numThreads) 2682301SN/A .name(name() + ".wb_sent") 2692326SN/A .desc("cumulative count of insts sent to commit") 2702301SN/A .flags(total); 2712301SN/A 2722301SN/A writebackCount 2732301SN/A .init(cpu->numThreads) 2742361SN/A .name(name() + ".wb_count") 2752326SN/A .desc("cumulative count of insts written-back") 2762301SN/A .flags(total); 2772301SN/A 2782301SN/A producerInst 2792301SN/A .init(cpu->numThreads) 2802301SN/A .name(name() + ".wb_producers") 2812301SN/A .desc("num instructions producing a value") 2822301SN/A .flags(total); 2832980Sgblack@eecs.umich.edu 2842301SN/A consumerInst 2852326SN/A .init(cpu->numThreads) 2862301SN/A .name(name() + ".wb_consumers") 2872361SN/A .desc("num instructions consuming a value") 2882326SN/A .flags(total); 2892301SN/A 2902301SN/A wbFanout 2912301SN/A .name(name() + ".wb_fanout") 2922301SN/A .desc("average fanout of values written-back") 2932326SN/A .flags(total); 2942727Sktlim@umich.edu 2952326SN/A wbFanout = producerInst / consumerInst; 2962301SN/A 2972301SN/A wbRate 2982301SN/A .name(name() + ".wb_rate") 2992301SN/A .desc("insts written-back per cycle") 3002301SN/A .flags(total); 3012301SN/A wbRate = writebackCount / cpu->numCycles; 3022326SN/A} 3032301SN/A 3042301SN/Atemplate<class Impl> 3052326SN/Avoid 3062301SN/ADefaultIEW<Impl>::startupStage() 3072301SN/A{ 3082301SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3092301SN/A toRename->iewInfo[tid].usedIQ = true; 3102301SN/A toRename->iewInfo[tid].freeIQEntries = 3112301SN/A instQueue.numFreeEntries(tid); 3122326SN/A 3132301SN/A toRename->iewInfo[tid].usedLSQ = true; 3142301SN/A toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3152301SN/A toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3162301SN/A } 3172326SN/A 3182301SN/A // Initialize the checker's dcache port here 3192292SN/A if (cpu->checker) { 3202292SN/A cpu->checker->setDcachePort(&ldstQueue.getDataPort()); 3212292SN/A } 3222292SN/A 3231062SN/A cpu->activateStage(O3CPU::IEWIdx); 3241062SN/A} 3251062SN/A 3261062SN/Atemplate<class Impl> 3272307SN/Avoid 3281060SN/ADefaultIEW<Impl>::clearStates(ThreadID tid) 3292307SN/A{ 3302307SN/A toRename->iewInfo[tid].usedIQ = true; 3312307SN/A toRename->iewInfo[tid].freeIQEntries = 3322307SN/A instQueue.numFreeEntries(tid); 3332307SN/A 3341060SN/A toRename->iewInfo[tid].usedLSQ = true; 3352307SN/A toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3362307SN/A toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3372307SN/A} 3382307SN/A 3392307SN/Atemplate<class Impl> 3402307SN/Avoid 3412307SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3422307SN/A{ 3432307SN/A timeBuffer = tb_ptr; 3442307SN/A 3452307SN/A // Setup wire to read information from time buffer, from commit. 3462307SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3472307SN/A 3482307SN/A // Setup wire to write information back to previous stages. 3492307SN/A toRename = timeBuffer->getWire(0); 3502307SN/A 3512307SN/A toFetch = timeBuffer->getWire(0); 3522307SN/A 3532307SN/A // Instruction queue also needs main time buffer. 3542307SN/A instQueue.setTimeBuffer(tb_ptr); 3552307SN/A} 3562307SN/A 3572307SN/Atemplate<class Impl> 3582307SN/Avoid 3591060SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3601060SN/A{ 3611061SN/A renameQueue = rq_ptr; 3621060SN/A 3632980Sgblack@eecs.umich.edu // Setup wire to read information from rename queue. 3641060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3652292SN/A} 3662064SN/A 3672064SN/Atemplate<class Impl> 3682064SN/Avoid 3692064SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3702292SN/A{ 3712064SN/A iewQueue = iq_ptr; 3724318Sktlim@umich.edu 3731060SN/A // Setup wire to write instructions to commit. 3741060SN/A toCommit = iewQueue->getWire(0); 3751061SN/A} 3761060SN/A 3771060SN/Atemplate<class Impl> 3781060SN/Avoid 3791060SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3801060SN/A{ 3811060SN/A activeThreads = at_ptr; 3821060SN/A 3831060SN/A ldstQueue.setActiveThreads(at_ptr); 3841684SN/A instQueue.setActiveThreads(at_ptr); 3852307SN/A} 3862307SN/A 3872307SN/Atemplate<class Impl> 3882367SN/Avoid 3892367SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3902367SN/A{ 3912367SN/A scoreboard = sb_ptr; 3922367SN/A} 3932367SN/A 3942367SN/Atemplate <class Impl> 3952307SN/Abool 3962326SN/ADefaultIEW<Impl>::isDrained() const 3972367SN/A{ 3982307SN/A bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3992307SN/A 4002307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4012307SN/A if (!insts[tid].empty()) { 4022307SN/A DPRINTF(Drain, "%i: Insts not empty.\n", tid); 4032307SN/A drained = false; 4042307SN/A } 4052307SN/A if (!skidBuffer[tid].empty()) { 4062307SN/A DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 4072307SN/A drained = false; 4082307SN/A } 4092307SN/A drained = drained && dispatchStatus[tid] == Running; 4102307SN/A } 4112307SN/A 4122292SN/A // Also check the FU pool as instructions are "stored" in FU 4132292SN/A // completion events until they are done and not accounted for 4142292SN/A // above 4152292SN/A if (drained && !fuPool->isDrained()) { 4162292SN/A DPRINTF(Drain, "FU pool still busy.\n"); 4172292SN/A drained = false; 4182292SN/A } 4192292SN/A 4202292SN/A return drained; 4212292SN/A} 4222292SN/A 4232292SN/Atemplate <class Impl> 4242292SN/Avoid 4252292SN/ADefaultIEW<Impl>::drainSanityCheck() const 4262292SN/A{ 4272292SN/A assert(isDrained()); 4283867Sbinkertn@umich.edu 4292292SN/A instQueue.drainSanityCheck(); 4303867Sbinkertn@umich.edu ldstQueue.drainSanityCheck(); 4313867Sbinkertn@umich.edu} 4322292SN/A 4333867Sbinkertn@umich.edutemplate <class Impl> 4343867Sbinkertn@umich.eduvoid 4353867Sbinkertn@umich.eduDefaultIEW<Impl>::takeOverFrom() 4362292SN/A{ 4373867Sbinkertn@umich.edu // Reset all state. 4382292SN/A _status = Active; 4393867Sbinkertn@umich.edu exeStatus = Running; 4402292SN/A wbStatus = Idle; 4412292SN/A 4422292SN/A instQueue.takeOverFrom(); 4432292SN/A ldstQueue.takeOverFrom(); 4442292SN/A fuPool->takeOverFrom(); 4452292SN/A 4461684SN/A startupStage(); 4471684SN/A cpu->activityThisCycle(); 4481684SN/A 4491684SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4501684SN/A dispatchStatus[tid] = Running; 4511684SN/A fetchRedirect[tid] = false; 4522292SN/A } 4532292SN/A 4542292SN/A updateLSQNextCycle = false; 4552292SN/A 4562292SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4572292SN/A issueToExecQueue.advance(); 4582292SN/A } 4591060SN/A} 4601060SN/A 4611061SN/Atemplate<class Impl> 4621060SN/Avoid 4631060SN/ADefaultIEW<Impl>::squash(ThreadID tid) 4641060SN/A{ 4651060SN/A DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid); 4661060SN/A 4671060SN/A // Tell the IQ to start squashing. 4681060SN/A instQueue.squash(tid); 4691060SN/A 4701060SN/A // Tell the LDSTQ to start squashing. 4711060SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4721061SN/A updatedQueues = true; 4732292SN/A 4742292SN/A // Clear the skid buffer in case it has any data in it. 4752292SN/A DPRINTF(IEW, 4762292SN/A "Removing skidbuffer instructions until " 4772292SN/A "[sn:%llu] [tid:%i]\n", 4782292SN/A fromCommit->commitInfo[tid].doneSeqNum, tid); 4792292SN/A 4802292SN/A while (!skidBuffer[tid].empty()) { 4812292SN/A if (skidBuffer[tid].front()->isLoad()) { 4822292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 4832292SN/A } 4842292SN/A if (skidBuffer[tid].front()->isStore() || 4852292SN/A skidBuffer[tid].front()->isAtomic()) { 4862292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 4872292SN/A } 4882292SN/A 4892292SN/A toRename->iewInfo[tid].dispatched++; 4902292SN/A 4912292SN/A skidBuffer[tid].pop(); 4922292SN/A } 4932292SN/A 4942292SN/A emptyRenameInsts(tid); 4952292SN/A} 4962292SN/A 4972292SN/Atemplate<class Impl> 4982292SN/Avoid 4992292SN/ADefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 5002292SN/A{ 5011060SN/A DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction," 5021061SN/A " PC: %s " 5031060SN/A "\n", tid, inst->seqNum, inst->pcState() ); 5041060SN/A 5051060SN/A if (!toCommit->squash[tid] || 5061060SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 5072326SN/A toCommit->squash[tid] = true; 5082326SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5091060SN/A toCommit->branchTaken[tid] = inst->pcState().branching(); 5101060SN/A 5111060SN/A TheISA::PCState pc = inst->pcState(); 5122292SN/A TheISA::advancePC(pc, inst->staticInst); 5131060SN/A 5142064SN/A toCommit->pc[tid] = pc; 5151060SN/A toCommit->mispredictInst[tid] = inst; 5162292SN/A toCommit->includeSquashInst[tid] = false; 5171060SN/A 5181060SN/A wroteToTimeBuffer = true; 5191060SN/A } 5201060SN/A 5211060SN/A} 5221060SN/A 5231060SN/Atemplate<class Impl> 5242326SN/Avoid 5251060SN/ADefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 5261061SN/A{ 5272292SN/A DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger " 5281062SN/A "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum); 5291062SN/A // Need to include inst->seqNum in the following comparison to cover the 5301061SN/A // corner case when a branch misprediction and a memory violation for the 5311061SN/A // same instruction (e.g. load PC) are detected in the same cycle. In this 5321062SN/A // case the memory violator should take precedence over the branch 5331060SN/A // misprediction because it requires the violator itself to be included in 5342292SN/A // the squash. 5352292SN/A if (!toCommit->squash[tid] || 5361060SN/A inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5371060SN/A toCommit->squash[tid] = true; 5381060SN/A 5391061SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5401061SN/A toCommit->pc[tid] = inst->pcState(); 5412292SN/A toCommit->mispredictInst[tid] = NULL; 5421061SN/A 5431061SN/A // Must include the memory violator in the squash. 5441061SN/A toCommit->includeSquashInst[tid] = true; 5451061SN/A 5462292SN/A wroteToTimeBuffer = true; 5471061SN/A } 5482292SN/A} 5491061SN/A 5502326SN/Atemplate<class Impl> 5512326SN/Avoid 5522326SN/ADefaultIEW<Impl>::block(ThreadID tid) 5532064SN/A{ 5541061SN/A DPRINTF(IEW, "[tid:%i] Blocking.\n", tid); 5551061SN/A 5562292SN/A if (dispatchStatus[tid] != Blocked && 5571061SN/A dispatchStatus[tid] != Unblocking) { 5582064SN/A toRename->iewBlock[tid] = true; 5591061SN/A wroteToTimeBuffer = true; 5602292SN/A } 5611061SN/A 5621061SN/A // Add the current inputs to the skid buffer so they can be 5631061SN/A // reprocessed when this stage unblocks. 5642326SN/A skidInsert(tid); 5651061SN/A 5661061SN/A dispatchStatus[tid] = Blocked; 5671061SN/A} 5682292SN/A 5692292SN/Atemplate<class Impl> 5701061SN/Avoid 5711062SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5721062SN/A{ 5732292SN/A DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid " 5742292SN/A "buffer %u.\n",tid, tid); 5752292SN/A 5762292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5771061SN/A // Also switch status to running. 5781061SN/A if (skidBuffer[tid].empty()) { 5791061SN/A toRename->iewUnblock[tid] = true; 5801060SN/A wroteToTimeBuffer = true; 5812292SN/A DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid); 5821060SN/A dispatchStatus[tid] = Running; 5832292SN/A } 5841060SN/A} 5852292SN/A 5862292SN/Atemplate<class Impl> 5871060SN/Avoid 5882064SN/ADefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 5892333SN/A{ 5902333SN/A instQueue.wakeDependents(inst); 5912333SN/A} 5922333SN/A 5932333SN/Atemplate<class Impl> 5942333SN/Avoid 5952333SN/ADefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 5962333SN/A{ 5971060SN/A instQueue.rescheduleMemInst(inst); 5982333SN/A} 5992064SN/A 6002292SN/Atemplate<class Impl> 6012292SN/Avoid 6022292SN/ADefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 6032292SN/A{ 6042292SN/A instQueue.replayMemInst(inst); 6052292SN/A} 6062292SN/A 6072292SN/Atemplate<class Impl> 6082292SN/Avoid 6092292SN/ADefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 6102292SN/A{ 6112292SN/A instQueue.blockMemInst(inst); 6122292SN/A} 6132292SN/A 6142292SN/Atemplate<class Impl> 6152292SN/Avoid 6162292SN/ADefaultIEW<Impl>::cacheUnblocked() 6172292SN/A{ 6182292SN/A instQueue.cacheUnblocked(); 6191060SN/A} 6201060SN/A 6212292SN/Atemplate<class Impl> 6222292SN/Avoid 6232292SN/ADefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 6241060SN/A{ 6252292SN/A // This function should not be called after writebackInsts in a 6262292SN/A // single cycle. That will cause problems with an instruction 6272292SN/A // being added to the queue to commit without being processed by 6282292SN/A // writebackInsts prior to being sent to commit. 6292292SN/A 6302292SN/A // First check the time slot that this instruction will write 6312292SN/A // to. If there are free write ports at the time, then go ahead 6322292SN/A // and write the instruction to that time. If there are not, 6332292SN/A // keep looking back to see where's the first time there's a 6342292SN/A // free slot. 6352292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6362292SN/A ++wbNumInst; 6372292SN/A if (wbNumInst == wbWidth) { 6382292SN/A ++wbCycle; 6392292SN/A wbNumInst = 0; 6402292SN/A } 6412292SN/A } 6422292SN/A 6432292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6442292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6452292SN/A // Add finished instruction to queue to commit. 6461060SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6471060SN/A (*iewQueue)[wbCycle].size++; 6482292SN/A} 6491060SN/A 6501060SN/Atemplate <class Impl> 6512292SN/Aunsigned 6522292SN/ADefaultIEW<Impl>::validInstsFromRename() 6532292SN/A{ 6542292SN/A unsigned inst_count = 0; 6552367SN/A 6562292SN/A for (int i=0; i<fromRename->size; i++) { 6572292SN/A if (!fromRename->insts[i]->isSquashed()) 6582307SN/A inst_count++; 6592367SN/A } 6602367SN/A 6612307SN/A return inst_count; 6622307SN/A} 6632307SN/A 6642292SN/Atemplate<class Impl> 6652292SN/Avoid 6662326SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6672326SN/A{ 6682292SN/A DynInstPtr inst = NULL; 6692326SN/A 6702326SN/A while (!insts[tid].empty()) { 6712326SN/A inst = insts[tid].front(); 6722333SN/A 6732333SN/A insts[tid].pop(); 6742292SN/A 6752292SN/A DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into " 6761061SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6771061SN/A inst->pcState(),tid); 6781061SN/A 6791061SN/A skidBuffer[tid].push(inst); 6801060SN/A } 6811060SN/A 6821060SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6832292SN/A "Skidbuffer Exceeded Max Size"); 6842292SN/A} 6851060SN/A 6861060SN/Atemplate<class Impl> 6871060SN/Aint 6882292SN/ADefaultIEW<Impl>::skidCount() 6892292SN/A{ 6902292SN/A int max=0; 6912292SN/A 6922292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6932292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6942292SN/A 6952292SN/A while (threads != end) { 6962292SN/A ThreadID tid = *threads++; 6972292SN/A unsigned thread_count = skidBuffer[tid].size(); 6982292SN/A if (max < thread_count) 6991060SN/A max = thread_count; 7002333SN/A } 7012820Sktlim@umich.edu 7022326SN/A return max; 7032292SN/A} 7041060SN/A 7052292SN/Atemplate<class Impl> 7061060SN/Abool 7072292SN/ADefaultIEW<Impl>::skidsEmpty() 7081060SN/A{ 7092292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7101060SN/A list<ThreadID>::iterator end = activeThreads->end(); 7112292SN/A 7122292SN/A while (threads != end) { 7131060SN/A ThreadID tid = *threads++; 7142292SN/A 7152292SN/A if (!skidBuffer[tid].empty()) 7162292SN/A return false; 7172292SN/A } 7182292SN/A 7191060SN/A return true; 7201060SN/A} 7212292SN/A 7221060SN/Atemplate <class Impl> 7232292SN/Avoid 7242292SN/ADefaultIEW<Impl>::updateStatus() 7252292SN/A{ 7261060SN/A bool any_unblocking = false; 7271060SN/A 7282326SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7292326SN/A list<ThreadID>::iterator end = activeThreads->end(); 7302301SN/A 7311060SN/A while (threads != end) { 7322326SN/A ThreadID tid = *threads++; 7332326SN/A 7341060SN/A if (dispatchStatus[tid] == Unblocking) { 7352326SN/A any_unblocking = true; 7362326SN/A break; 7371060SN/A } 7381060SN/A } 7391060SN/A 7402348SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7412348SN/A // and there's no stores waiting to write back, and dispatch is not 7422326SN/A // unblocking, then there is no internal activity for the IEW stage. 7432292SN/A instQueue.intInstQueueReads++; 7442292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7452333SN/A !ldstQueue.willWB() && !any_unblocking) { 7461060SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7472326SN/A 7482326SN/A deactivateStage(); 7492326SN/A 7502326SN/A _status = Inactive; 7512292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7522292SN/A ldstQueue.willWB() || 7532326SN/A any_unblocking)) { 7542326SN/A // Otherwise there is internal activity. Set to active. 7552326SN/A DPRINTF(IEW, "IEW switching to active\n"); 7561060SN/A 7572326SN/A activateStage(); 7581060SN/A 7592326SN/A _status = Active; 7602292SN/A } 7612348SN/A} 7622348SN/A 7632326SN/Atemplate <class Impl> 7642292SN/Abool 7652292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7662326SN/A{ 7672292SN/A bool ret_val(false); 7681060SN/A 7691060SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7702292SN/A DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid); 7712292SN/A ret_val = true; 7722301SN/A } else if (instQueue.isFull(tid)) { 7732292SN/A DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid); 7741060SN/A ret_val = true; 7752292SN/A } 7761061SN/A 7772292SN/A return ret_val; 7782292SN/A} 7792292SN/A 7802292SN/Atemplate <class Impl> 7812292SN/Avoid 7821060SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7831060SN/A{ 7842064SN/A // Check if there's a squash signal, squash if there is 7852292SN/A // Check stall signals, block if there is. 7862064SN/A // If status was Blocked 7872292SN/A // if so then go to unblocking 7882292SN/A // If status was Squashing 7892292SN/A // check if squashing is not high. Switch to running this cycle. 7902292SN/A 7912301SN/A if (fromCommit->commitInfo[tid].squash) { 7922731Sktlim@umich.edu squash(tid); 7932292SN/A 7942301SN/A if (dispatchStatus[tid] == Blocked || 7952292SN/A dispatchStatus[tid] == Unblocking) { 7962292SN/A toRename->iewUnblock[tid] = true; 7972292SN/A wroteToTimeBuffer = true; 7982326SN/A } 7992820Sktlim@umich.edu 8002292SN/A dispatchStatus[tid] = Squashing; 8012326SN/A fetchRedirect[tid] = false; 8022326SN/A return; 8032292SN/A } 8041060SN/A 8051060SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8061062SN/A DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid); 8072326SN/A 8082326SN/A dispatchStatus[tid] = Squashing; 8092307SN/A emptyRenameInsts(tid); 8102348SN/A wroteToTimeBuffer = true; 8112292SN/A } 8122292SN/A 8132292SN/A if (checkStall(tid)) { 8142292SN/A block(tid); 8152292SN/A dispatchStatus[tid] = Blocked; 8161060SN/A return; 8171060SN/A } 8181061SN/A 8191060SN/A if (dispatchStatus[tid] == Blocked) { 8201061SN/A // Status from previous cycle was blocked, but there are no more stall 8211060SN/A // conditions. Switch over to unblocking. 8222292SN/A DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n", 8232292SN/A tid); 8241062SN/A 8252292SN/A dispatchStatus[tid] = Unblocking; 8261060SN/A 8271061SN/A unblock(tid); 8281060SN/A 8292292SN/A return; 8302292SN/A } 8314033Sktlim@umich.edu 8324033Sktlim@umich.edu if (dispatchStatus[tid] == Squashing) { 8331061SN/A // Switch status to running if rename isn't being told to block or 8341060SN/A // squash this cycle. 8351062SN/A DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n", 8361062SN/A tid); 8371062SN/A 8382292SN/A dispatchStatus[tid] = Running; 8391062SN/A 8401060SN/A return; 8412292SN/A } 8422292SN/A} 8431061SN/A 8441060SN/Atemplate <class Impl> 8451060SN/Avoid 8461061SN/ADefaultIEW<Impl>::sortInsts() 8471061SN/A{ 8482292SN/A int insts_from_rename = fromRename->size; 8492292SN/A#ifdef DEBUG 8502292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8512292SN/A assert(insts[tid].empty()); 8522292SN/A#endif 8532292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8542292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8552292SN/A } 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Avoid 8602292SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8612292SN/A{ 8622292SN/A DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid); 8632292SN/A 8642292SN/A while (!insts[tid].empty()) { 8652301SN/A 8661684SN/A if (insts[tid].front()->isLoad()) { 8671684SN/A toRename->iewInfo[tid].dispatchedToLQ++; 8682301SN/A } 8692301SN/A if (insts[tid].front()->isStore() || 8702292SN/A insts[tid].front()->isAtomic()) { 8712292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 8722292SN/A } 8731684SN/A 8741684SN/A toRename->iewInfo[tid].dispatched++; 8752292SN/A 8762326SN/A insts[tid].pop(); 8772326SN/A } 8782326SN/A} 8792326SN/A 8801684SN/Atemplate <class Impl> 8812292SN/Avoid 8822292SN/ADefaultIEW<Impl>::wakeCPU() 8832292SN/A{ 8842292SN/A cpu->wakeCPU(); 8852292SN/A} 8861684SN/A 8871684SN/Atemplate <class Impl> 8881684SN/Avoid 8891684SN/ADefaultIEW<Impl>::activityThisCycle() 8901684SN/A{ 8911684SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8921684SN/A cpu->activityThisCycle(); 8931684SN/A} 8941684SN/A 8951684SN/Atemplate <class Impl> 8961684SN/Ainline void 8971684SN/ADefaultIEW<Impl>::activateStage() 8981684SN/A{ 8991684SN/A DPRINTF(Activity, "Activating stage.\n"); 9001684SN/A cpu->activateStage(O3CPU::IEWIdx); 9011684SN/A} 9022292SN/A 9031684SN/Atemplate <class Impl> 9041684SN/Ainline void 9052326SN/ADefaultIEW<Impl>::deactivateStage() 9062326SN/A{ 9072326SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9081684SN/A cpu->deactivateStage(O3CPU::IEWIdx); 9092326SN/A} 9102292SN/A 9112326SN/Atemplate<class Impl> 9121684SN/Avoid 9131684SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9142326SN/A{ 9152326SN/A // If status is Running or idle, 9162326SN/A // call dispatchInsts() 9172326SN/A // If status is Unblocking, 9181684SN/A // buffer any instructions coming from rename 9192326SN/A // continue trying to empty skid buffer 9201684SN/A // check if stall conditions have passed 9212326SN/A 9221684SN/A if (dispatchStatus[tid] == Blocked) { 9232301SN/A ++iewBlockCycles; 9241684SN/A 9251684SN/A } else if (dispatchStatus[tid] == Squashing) { 9262326SN/A ++iewSquashCycles; 9272326SN/A } 9282326SN/A 9292326SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9301684SN/A // will allow, as long as it is not currently blocked. 9311684SN/A if (dispatchStatus[tid] == Running || 9321684SN/A dispatchStatus[tid] == Idle) { 9331684SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9342301SN/A "dispatch.\n", tid); 9352064SN/A 9362064SN/A dispatchInsts(tid); 9372064SN/A } else if (dispatchStatus[tid] == Unblocking) { 9382064SN/A // Make sure that the skid buffer has something in it if the 9392292SN/A // status is unblocking. 9402064SN/A assert(!skidsEmpty()); 9412292SN/A 9422292SN/A // If the status was unblocking, then instructions from the skid 9432292SN/A // buffer were used. Remove those instructions and handle 9442292SN/A // the rest of unblocking. 9452326SN/A dispatchInsts(tid); 9462326SN/A 9472326SN/A ++iewUnblockCycles; 9482326SN/A 9492326SN/A if (validInstsFromRename()) { 9502326SN/A // Add the current inputs to the skid buffer so they can be 9512326SN/A // reprocessed when this stage unblocks. 9522326SN/A skidInsert(tid); 9532326SN/A } 9542326SN/A 9552292SN/A unblock(tid); 9562292SN/A } 9572292SN/A} 9582064SN/A 9592064SN/Atemplate <class Impl> 9602064SN/Avoid 9612064SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9622292SN/A{ 9632064SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9644033Sktlim@umich.edu // otherwise. 9654033Sktlim@umich.edu std::queue<DynInstPtr> &insts_to_dispatch = 9662292SN/A dispatchStatus[tid] == Unblocking ? 9672064SN/A skidBuffer[tid] : insts[tid]; 9682064SN/A 9692064SN/A int insts_to_add = insts_to_dispatch.size(); 9702064SN/A 9712292SN/A DynInstPtr inst; 9722064SN/A bool add_to_iq = false; 9732292SN/A int dis_num_inst = 0; 9742292SN/A 9752292SN/A // Loop through the instructions, putting them in the instruction 9762292SN/A // queue. 9772292SN/A for ( ; dis_num_inst < insts_to_add && 9782292SN/A dis_num_inst < dispatchWidth; 9792292SN/A ++dis_num_inst) 9802292SN/A { 9812292SN/A inst = insts_to_dispatch.front(); 9822292SN/A 9832292SN/A if (dispatchStatus[tid] == Unblocking) { 9842292SN/A DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid " 9852292SN/A "buffer\n", tid); 9862292SN/A } 9872292SN/A 9882292SN/A // Make sure there's a valid instruction there. 9892292SN/A assert(inst); 9902292SN/A 9911684SN/A DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9921684SN/A "IQ.\n", 9931684SN/A tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9941684SN/A 9951061SN/A // Be sure to mark these instructions as ready so that the 9961061SN/A // commit stage can go ahead and execute them, and mark 9971061SN/A // them as issued so the IQ doesn't reprocess them. 9982292SN/A 9991061SN/A // Check for squashed instructions. 10001061SN/A if (inst->isSquashed()) { 10011061SN/A DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, " 10021060SN/A "not adding to IQ.\n", tid); 10032292SN/A 10041060SN/A ++iewDispSquashedInsts; 10052292SN/A 10062292SN/A insts_to_dispatch.pop(); 10071060SN/A 10081060SN/A //Tell Rename That An Instruction has been processed 10091060SN/A if (inst->isLoad()) { 10103093Sksewell@umich.edu toRename->iewInfo[tid].dispatchedToLQ++; 10113093Sksewell@umich.edu } 10123093Sksewell@umich.edu if (inst->isStore() || inst->isAtomic()) { 10132292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10142935Sksewell@umich.edu } 10151060SN/A 10161681SN/A toRename->iewInfo[tid].dispatched++; 10172292SN/A 10182292SN/A continue; 10191681SN/A } 10201061SN/A 10211061SN/A // Check for full conditions. 10222292SN/A if (instQueue.isFull(tid)) { 10231060SN/A DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid); 10241060SN/A 10251061SN/A // Call function to start blocking. 10261061SN/A block(tid); 10272292SN/A 10281061SN/A // Set unblock to false. Special case where we are using 10292326SN/A // skidbuffer (unblocking) instructions but then we still 10302326SN/A // get full in the IQ. 10312326SN/A toRename->iewUnblock[tid] = false; 10321061SN/A 10332292SN/A ++iewIQFullEvents; 10342292SN/A break; 10351061SN/A } 10361061SN/A 10371061SN/A // Check LSQ if inst is LD/ST 10382326SN/A if ((inst->isAtomic() && ldstQueue.sqFull(tid)) || 10392326SN/A (inst->isLoad() && ldstQueue.lqFull(tid)) || 10402292SN/A (inst->isStore() && ldstQueue.sqFull(tid))) { 10412326SN/A DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid, 10421061SN/A inst->isLoad() ? "LQ" : "SQ"); 10431061SN/A 10441061SN/A // Call function to start blocking. 10452292SN/A block(tid); 10462292SN/A 10472326SN/A // Set unblock to false. Special case where we are using 10482292SN/A // skidbuffer (unblocking) instructions but then we still 10492292SN/A // get full in the IQ. 10502292SN/A toRename->iewUnblock[tid] = false; 10512292SN/A 10522292SN/A ++iewLSQFullEvents; 10532292SN/A break; 10541062SN/A } 10552367SN/A 10562367SN/A // Otherwise issue the instruction just fine. 10572367SN/A if (inst->isAtomic()) { 10582367SN/A DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " 10591061SN/A "encountered, adding to LSQ.\n", tid); 10602292SN/A 10612336SN/A ldstQueue.insertStore(inst); 10622292SN/A 10632292SN/A ++iewDispStoreInsts; 10641061SN/A 10651061SN/A // AMOs need to be set as "canCommit()" 10661681SN/A // so that commit can process them when they reach the 10671061SN/A // head of commit. 10681061SN/A inst->setCanCommit(); 10691061SN/A instQueue.insertNonSpec(inst); 10701061SN/A add_to_iq = false; 10711061SN/A 10722326SN/A ++iewDispNonSpecInsts; 10732326SN/A 10742326SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10752326SN/A } else if (inst->isLoad()) { 10762326SN/A DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " 10772326SN/A "encountered, adding to LSQ.\n", tid); 10782326SN/A 10792326SN/A // Reserve a spot in the load store queue for this 10802292SN/A // memory access. 10811061SN/A ldstQueue.insertLoad(inst); 10821061SN/A 10832326SN/A ++iewDispLoadInsts; 10841061SN/A 10851062SN/A add_to_iq = true; 10862292SN/A 10871062SN/A toRename->iewInfo[tid].dispatchedToLQ++; 10881061SN/A } else if (inst->isStore()) { 10894033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " 10904033Sktlim@umich.edu "encountered, adding to LSQ.\n", tid); 10912292SN/A 10922292SN/A ldstQueue.insertStore(inst); 10932292SN/A 10944033Sktlim@umich.edu ++iewDispStoreInsts; 10954033Sktlim@umich.edu 10964033Sktlim@umich.edu if (inst->isStoreConditional()) { 10971062SN/A // Store conditionals need to be set as "canCommit()" 10984033Sktlim@umich.edu // so that commit can process them when they reach the 10991681SN/A // head of commit. 11004033Sktlim@umich.edu // @todo: This is somewhat specific to Alpha. 11011062SN/A inst->setCanCommit(); 11024033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11034033Sktlim@umich.edu add_to_iq = false; 11041061SN/A 11051061SN/A ++iewDispNonSpecInsts; 11061061SN/A } else { 11071061SN/A add_to_iq = true; 11081061SN/A } 11091061SN/A 11101061SN/A toRename->iewInfo[tid].dispatchedToSQ++; 11112292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11122292SN/A // Same as non-speculative stores. 11131681SN/A inst->setCanCommit(); 11141681SN/A instQueue.insertBarrier(inst); 11152731Sktlim@umich.edu add_to_iq = false; 11162292SN/A } else if (inst->isNop()) { 11172292SN/A DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, " 11182292SN/A "skipping.\n", tid); 11191681SN/A 11201681SN/A inst->setIssued(); 11211061SN/A inst->setExecuted(); 11221061SN/A inst->setCanCommit(); 11232326SN/A 11241062SN/A instQueue.recordProducer(inst); 11251061SN/A 11261060SN/A iewExecutedNop[tid]++; 11271060SN/A 11281061SN/A add_to_iq = false; 11291060SN/A } else { 11301061SN/A assert(!inst->isExecuted()); 11311060SN/A add_to_iq = true; 11321060SN/A } 11331060SN/A 11341060SN/A if (add_to_iq && inst->isNonSpeculative()) { 11351060SN/A DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction " 11361060SN/A "encountered, skipping.\n", tid); 11371060SN/A 11381060SN/A // Same as non-speculative stores. 11391060SN/A inst->setCanCommit(); 11401060SN/A 11411060SN/A // Specifically insert it as nonspeculative. 11421060SN/A instQueue.insertNonSpec(inst); 11431060SN/A 11441060SN/A ++iewDispNonSpecInsts; 11451060SN/A 11461060SN/A add_to_iq = false; 11471060SN/A } 11481060SN/A 11491061SN/A // If the instruction queue is not full, then add the 11501061SN/A // instruction. 11511061SN/A if (add_to_iq) { 11522292SN/A instQueue.insert(inst); 11531060SN/A } 11541060SN/A 11551060SN/A insts_to_dispatch.pop(); 11562326SN/A 11571060SN/A toRename->iewInfo[tid].dispatched++; 11581060SN/A 11591060SN/A ++iewDispatchedInsts; 11601060SN/A 11611060SN/A#if TRACING_ON 11622292SN/A inst->dispatchTick = curTick() - inst->fetchTick; 11631060SN/A#endif 11641060SN/A ppDispatch->notify(inst); 11651060SN/A } 11662326SN/A 11671060SN/A if (!insts_to_dispatch.empty()) { 11681060SN/A DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid); 11691060SN/A block(tid); 11701060SN/A toRename->iewUnblock[tid] = false; 11711060SN/A } 11721060SN/A 11731060SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11741061SN/A dispatchStatus[tid] = Running; 11751060SN/A 11762326SN/A updatedQueues = true; 11771060SN/A } 11782326SN/A 11792326SN/A dis_num_inst = 0; 11802326SN/A} 11812326SN/A 11821060SN/Atemplate <class Impl> 11831060SN/Avoid 11841060SN/ADefaultIEW<Impl>::printAvailableInsts() 11851060SN/A{ 11861060SN/A int inst = 0; 11871060SN/A 11881061SN/A std::cout << "Available Instructions: "; 11891061SN/A 11901061SN/A while (fromIssue->insts[inst]) { 11911061SN/A 11921061SN/A if (inst%3==0) std::cout << "\n\t"; 11931061SN/A 11941061SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11951061SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11961060SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11971060SN/A 11982326SN/A inst++; 11992326SN/A 12002292SN/A } 12012064SN/A 12021062SN/A std::cout << "\n"; 12032326SN/A} 12041062SN/A 12051060SN/Atemplate <class Impl> 12061060SN/Avoid 12071060SN/ADefaultIEW<Impl>::executeInsts() 12081060SN/A{ 12091060SN/A wbNumInst = 0; 12101061SN/A wbCycle = 0; 12111060SN/A 12121061SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 12131060SN/A list<ThreadID>::iterator end = activeThreads->end(); 12142326SN/A 12151060SN/A while (threads != end) { 12161060SN/A ThreadID tid = *threads++; 12171061SN/A fetchRedirect[tid] = false; 12181060SN/A } 12192292SN/A 12201061SN/A // Uncomment this if you want to see all available instructions. 12212292SN/A // @todo This doesn't actually work anymore, we should fix it. 12221061SN/A// printAvailableInsts(); 12231062SN/A 12241062SN/A // Execute/writeback any instructions that are available. 12252292SN/A int insts_to_execute = fromIssue->size; 12261062SN/A int inst_num = 0; 12272292SN/A for (; inst_num < insts_to_execute; 12282292SN/A ++inst_num) { 12291062SN/A 12302292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12311061SN/A 12322292SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12332292SN/A 12342292SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n", 12351061SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12362292SN/A 12371061SN/A // Notify potential listeners that this instruction has started 12382326SN/A // executing 12392326SN/A ppExecute->notify(inst); 12402326SN/A 12412326SN/A // Check if the instruction is squashed; if so then skip it 12422326SN/A if (inst->isSquashed()) { 12432326SN/A DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12442326SN/A " [sn:%llu]\n", inst->pcState(), inst->threadNumber, 12452326SN/A inst->seqNum); 12461060SN/A 12471060SN/A // Consider this instruction executed so that commit can go 12481060SN/A // ahead and retire the instruction. 12491060SN/A inst->setExecuted(); 12501061SN/A 12511061SN/A // Not sure if I should set this here or just let commit try to 12521061SN/A // commit any squashed instructions. I like the latter a bit more. 12531061SN/A inst->setCanCommit(); 12542698Sktlim@umich.edu 12552292SN/A ++iewExecSquashedInsts; 12562292SN/A 12572292SN/A continue; 12582698Sktlim@umich.edu } 12591061SN/A 12601061SN/A Fault fault = NoFault; 12612292SN/A 12622292SN/A // Execute instruction. 12631681SN/A // Note that if the instruction faults, it will be handled 12642292SN/A // at the commit stage. 12652292SN/A if (inst->isMemRef()) { 12662292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12672292SN/A "reference.\n"); 12682292SN/A 12692292SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12702292SN/A if (inst->isAtomic()) { 12712292SN/A // AMOs are treated like store requests 12722292SN/A fault = ldstQueue.executeStore(inst); 12732292SN/A 12742292SN/A if (inst->isTranslationDelayed() && 12752292SN/A fault == NoFault) { 12762292SN/A // A hw page table walk is currently going on; the 12771061SN/A // instruction must be deferred. 12781061SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12791061SN/A "store.\n"); 12801061SN/A instQueue.deferMemInst(inst); 12812292SN/A continue; 12822292SN/A } 12832292SN/A } else if (inst->isLoad()) { 12841681SN/A // Loads will mark themselves as executed, and their writeback 12851681SN/A // event adds the instruction to the queue to commit 12861681SN/A fault = ldstQueue.executeLoad(inst); 12871681SN/A 12881061SN/A if (inst->isTranslationDelayed() && 12891061SN/A fault == NoFault) { 12902292SN/A // A hw page table walk is currently going on; the 12912292SN/A // instruction must be deferred. 12921061SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12932292SN/A "load.\n"); 12942292SN/A instQueue.deferMemInst(inst); 12951061SN/A continue; 12961061SN/A } 12971061SN/A 12982292SN/A if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12992292SN/A inst->fault = NoFault; 13001061SN/A } 13011061SN/A } else if (inst->isStore()) { 13021061SN/A fault = ldstQueue.executeStore(inst); 13032292SN/A 13042292SN/A if (inst->isTranslationDelayed() && 13052292SN/A fault == NoFault) { 13061061SN/A // A hw page table walk is currently going on; the 13071061SN/A // instruction must be deferred. 13081061SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 13091061SN/A "store.\n"); 13101061SN/A instQueue.deferMemInst(inst); 13112292SN/A continue; 13122292SN/A } 13132292SN/A 13142292SN/A // If the store had a fault then it may not have a mem req 13152292SN/A if (fault != NoFault || !inst->readPredicate() || 13162292SN/A !inst->isStoreConditional()) { 13172292SN/A // If the instruction faulted, then we need to send it along 13182292SN/A // to commit without the instruction completing. 13192292SN/A // Send this instruction to commit, also make sure iew stage 13202292SN/A // realizes there is activity. 13212292SN/A inst->setExecuted(); 13222292SN/A instToCommit(inst); 13232292SN/A activityThisCycle(); 13242292SN/A } 13252292SN/A 13261061SN/A // Store conditionals will mark themselves as 13272292SN/A // executed, and their writeback event will add the 13282292SN/A // instruction to the queue to commit. 13292292SN/A } else { 13302292SN/A panic("Unexpected memory type!\n"); 13312292SN/A } 13322292SN/A 13332292SN/A } else { 13342292SN/A // If the instruction has already faulted, then skip executing it. 13352292SN/A // Such case can happen when it faulted during ITLB translation. 13362292SN/A // If we execute the instruction (even if it's a nop) the fault 13372292SN/A // will be replaced and we will lose it. 13382292SN/A if (inst->getFault() == NoFault) { 13392292SN/A inst->execute(); 13402292SN/A if (!inst->readPredicate()) 13412292SN/A inst->forwardOldRegs(); 13422292SN/A } 13432292SN/A 13442292SN/A inst->setExecuted(); 13452292SN/A 13462292SN/A instToCommit(inst); 13472292SN/A } 13482326SN/A 13492326SN/A updateExeInstStats(inst); 13502292SN/A 13512292SN/A // Check if branch prediction was correct, if not then we need 13522292SN/A // to tell commit to squash in flight instructions. Only 13532292SN/A // handle this if there hasn't already been something that 13542292SN/A // redirects fetch in this group of instructions. 13552292SN/A 13562292SN/A // This probably needs to prioritize the redirects if a different 13572292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13582292SN/A // instruction first, so the branch resolution order will be correct. 13592292SN/A ThreadID tid = inst->threadNumber; 13602292SN/A 13612292SN/A if (!fetchRedirect[tid] || 13622292SN/A !toCommit->squash[tid] || 13632292SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 13642292SN/A 13652292SN/A // Prevent testing for misprediction on load instructions, 13662292SN/A // that have not been executed. 13672292SN/A bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13682292SN/A 13692292SN/A if (inst->mispredicted() && !loadNotExecuted) { 13702292SN/A fetchRedirect[tid] = true; 13712292SN/A 13722292SN/A DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 13732348SN/A "Branch mispredict detected.\n", 13742348SN/A tid,inst->seqNum); 13752348SN/A DPRINTF(IEW, "[tid:%i] [sn:%llu] " 13762348SN/A "Predicted target was PC: %s\n", 13772348SN/A tid,inst->seqNum,inst->readPredTarg()); 13782348SN/A DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 13792348SN/A "Redirecting fetch to PC: %s\n", 13802348SN/A tid,inst->seqNum,inst->pcState()); 13812348SN/A // If incorrect, then signal the ROB that it must be squashed. 13822348SN/A squashDueToBranch(inst, tid); 13832348SN/A 13842348SN/A ppMispredict->notify(inst); 13852348SN/A 13862348SN/A if (inst->readPredTaken()) { 13872348SN/A predictedTakenIncorrect++; 13882348SN/A } else { 13892348SN/A predictedNotTakenIncorrect++; 13902348SN/A } 13912348SN/A } else if (ldstQueue.violation(tid)) { 13922348SN/A assert(inst->isMemRef()); 13932348SN/A // If there was an ordering violation, then get the 13942348SN/A // DynInst that caused the violation. Note that this 13952348SN/A // clears the violation signal. 13962348SN/A DynInstPtr violator; 13972348SN/A violator = ldstQueue.getMemDepViolator(tid); 13982348SN/A 13992348SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 14002348SN/A "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 14012348SN/A violator->pcState(), violator->seqNum, 14022348SN/A inst->pcState(), inst->seqNum, inst->physEffAddr); 14032348SN/A 14042348SN/A fetchRedirect[tid] = true; 14052348SN/A 14062348SN/A // Tell the instruction queue that a violation has occured. 14072348SN/A instQueue.violation(inst, violator); 14082348SN/A 14092348SN/A // Squash. 14102348SN/A squashDueToMemOrder(violator, tid); 14112348SN/A 14122348SN/A ++memOrderViolationEvents; 14132348SN/A } 14142292SN/A } else { 1415 // Reset any state associated with redirects that will not 1416 // be used. 1417 if (ldstQueue.violation(tid)) { 1418 assert(inst->isMemRef()); 1419 1420 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1421 1422 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1423 "%s, inst PC: %s. Addr is: %#x.\n", 1424 violator->pcState(), inst->pcState(), 1425 inst->physEffAddr); 1426 DPRINTF(IEW, "Violation will not be handled because " 1427 "already squashing\n"); 1428 1429 ++memOrderViolationEvents; 1430 } 1431 } 1432 } 1433 1434 // Update and record activity if we processed any instructions. 1435 if (inst_num) { 1436 if (exeStatus == Idle) { 1437 exeStatus = Running; 1438 } 1439 1440 updatedQueues = true; 1441 1442 cpu->activityThisCycle(); 1443 } 1444 1445 // Need to reset this in case a writeback event needs to write into the 1446 // iew queue. That way the writeback event will write into the correct 1447 // spot in the queue. 1448 wbNumInst = 0; 1449 1450} 1451 1452template <class Impl> 1453void 1454DefaultIEW<Impl>::writebackInsts() 1455{ 1456 // Loop through the head of the time buffer and wake any 1457 // dependents. These instructions are about to write back. Also 1458 // mark scoreboard that this instruction is finally complete. 1459 // Either have IEW have direct access to scoreboard, or have this 1460 // as part of backwards communication. 1461 for (int inst_num = 0; inst_num < wbWidth && 1462 toCommit->insts[inst_num]; inst_num++) { 1463 DynInstPtr inst = toCommit->insts[inst_num]; 1464 ThreadID tid = inst->threadNumber; 1465 1466 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1467 inst->seqNum, inst->pcState()); 1468 1469 iewInstsToCommit[tid]++; 1470 // Notify potential listeners that execution is complete for this 1471 // instruction. 1472 ppToCommit->notify(inst); 1473 1474 // Some instructions will be sent to commit without having 1475 // executed because they need commit to handle them. 1476 // E.g. Strictly ordered loads have not actually executed when they 1477 // are first sent to commit. Instead commit must tell the LSQ 1478 // when it's ready to execute the strictly ordered load. 1479 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1480 int dependents = instQueue.wakeDependents(inst); 1481 1482 for (int i = 0; i < inst->numDestRegs(); i++) { 1483 // Mark register as ready if not pinned 1484 if (inst->renamedDestRegIdx(i)-> 1485 getNumPinnedWritesToComplete() == 0) { 1486 DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 1487 inst->renamedDestRegIdx(i)->index(), 1488 inst->renamedDestRegIdx(i)->className()); 1489 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1490 } 1491 } 1492 1493 if (dependents) { 1494 producerInst[tid]++; 1495 consumerInst[tid]+= dependents; 1496 } 1497 writebackCount[tid]++; 1498 } 1499 } 1500} 1501 1502template<class Impl> 1503void 1504DefaultIEW<Impl>::tick() 1505{ 1506 wbNumInst = 0; 1507 wbCycle = 0; 1508 1509 wroteToTimeBuffer = false; 1510 updatedQueues = false; 1511 1512 ldstQueue.tick(); 1513 1514 sortInsts(); 1515 1516 // Free function units marked as being freed this cycle. 1517 fuPool->processFreeUnits(); 1518 1519 list<ThreadID>::iterator threads = activeThreads->begin(); 1520 list<ThreadID>::iterator end = activeThreads->end(); 1521 1522 // Check stall and squash signals, dispatch any instructions. 1523 while (threads != end) { 1524 ThreadID tid = *threads++; 1525 1526 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1527 1528 checkSignalsAndUpdate(tid); 1529 dispatch(tid); 1530 } 1531 1532 if (exeStatus != Squashing) { 1533 executeInsts(); 1534 1535 writebackInsts(); 1536 1537 // Have the instruction queue try to schedule any ready instructions. 1538 // (In actuality, this scheduling is for instructions that will 1539 // be executed next cycle.) 1540 instQueue.scheduleReadyInsts(); 1541 1542 // Also should advance its own time buffers if the stage ran. 1543 // Not the best place for it, but this works (hopefully). 1544 issueToExecQueue.advance(); 1545 } 1546 1547 bool broadcast_free_entries = false; 1548 1549 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1550 exeStatus = Idle; 1551 updateLSQNextCycle = false; 1552 1553 broadcast_free_entries = true; 1554 } 1555 1556 // Writeback any stores using any leftover bandwidth. 1557 ldstQueue.writebackStores(); 1558 1559 // Check the committed load/store signals to see if there's a load 1560 // or store to commit. Also check if it's being told to execute a 1561 // nonspeculative instruction. 1562 // This is pretty inefficient... 1563 1564 threads = activeThreads->begin(); 1565 while (threads != end) { 1566 ThreadID tid = (*threads++); 1567 1568 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1569 1570 // Update structures based on instructions committed. 1571 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1572 !fromCommit->commitInfo[tid].squash && 1573 !fromCommit->commitInfo[tid].robSquashing) { 1574 1575 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1576 1577 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1578 1579 updateLSQNextCycle = true; 1580 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1581 } 1582 1583 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1584 1585 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1586 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1587 instQueue.replayMemInst( 1588 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1589 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1590 } else { 1591 instQueue.scheduleNonSpec( 1592 fromCommit->commitInfo[tid].nonSpecSeqNum); 1593 } 1594 } 1595 1596 if (broadcast_free_entries) { 1597 toFetch->iewInfo[tid].iqCount = 1598 instQueue.getCount(tid); 1599 toFetch->iewInfo[tid].ldstqCount = 1600 ldstQueue.getCount(tid); 1601 1602 toRename->iewInfo[tid].usedIQ = true; 1603 toRename->iewInfo[tid].freeIQEntries = 1604 instQueue.numFreeEntries(tid); 1605 toRename->iewInfo[tid].usedLSQ = true; 1606 1607 toRename->iewInfo[tid].freeLQEntries = 1608 ldstQueue.numFreeLoadEntries(tid); 1609 toRename->iewInfo[tid].freeSQEntries = 1610 ldstQueue.numFreeStoreEntries(tid); 1611 1612 wroteToTimeBuffer = true; 1613 } 1614 1615 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1616 tid, toRename->iewInfo[tid].dispatched); 1617 } 1618 1619 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1620 "LQ has %i free entries. SQ has %i free entries.\n", 1621 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1622 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1623 1624 updateStatus(); 1625 1626 if (wroteToTimeBuffer) { 1627 DPRINTF(Activity, "Activity this cycle.\n"); 1628 cpu->activityThisCycle(); 1629 } 1630} 1631 1632template <class Impl> 1633void 1634DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 1635{ 1636 ThreadID tid = inst->threadNumber; 1637 1638 iewExecutedInsts++; 1639 1640#if TRACING_ON 1641 if (DTRACE(O3PipeView)) { 1642 inst->completeTick = curTick() - inst->fetchTick; 1643 } 1644#endif 1645 1646 // 1647 // Control operations 1648 // 1649 if (inst->isControl()) 1650 iewExecutedBranches[tid]++; 1651 1652 // 1653 // Memory operations 1654 // 1655 if (inst->isMemRef()) { 1656 iewExecutedRefs[tid]++; 1657 1658 if (inst->isLoad()) { 1659 iewExecLoadInsts[tid]++; 1660 } 1661 } 1662} 1663 1664template <class Impl> 1665void 1666DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 1667{ 1668 ThreadID tid = inst->threadNumber; 1669 1670 if (!fetchRedirect[tid] || 1671 !toCommit->squash[tid] || 1672 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1673 1674 if (inst->mispredicted()) { 1675 fetchRedirect[tid] = true; 1676 1677 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 1678 "Branch mispredict detected.\n", 1679 tid,inst->seqNum); 1680 DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target " 1681 "was PC:%#x, NPC:%#x\n", 1682 tid,inst->seqNum, 1683 inst->predInstAddr(), inst->predNextInstAddr()); 1684 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 1685 "Redirecting fetch to PC: %#x, " 1686 "NPC: %#x.\n", 1687 tid,inst->seqNum, 1688 inst->nextInstAddr(), 1689 inst->nextInstAddr()); 1690 // If incorrect, then signal the ROB that it must be squashed. 1691 squashDueToBranch(inst, tid); 1692 1693 if (inst->readPredTaken()) { 1694 predictedTakenIncorrect++; 1695 } else { 1696 predictedNotTakenIncorrect++; 1697 } 1698 } 1699 } 1700} 1701 1702#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1703