iew_impl.hh revision 14025
11689SN/A/* 213590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2010-2013, 2018 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147598Sminkyu.jeong@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469944Smatt.horsnell@ARM.com 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 491689SN/A// communication happens simultaneously. 501060SN/A 511060SN/A#include <queue> 521060SN/A 538230Snate@binkert.org#include "arch/utility.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 571717SN/A#include "cpu/o3/iew.hh" 588229Snate@binkert.org#include "cpu/timebuf.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/IEW.hh" 629527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 635529Snate@binkert.org#include "params/DerivO3CPU.hh" 641060SN/A 656221Snate@binkert.orgusing namespace std; 666221Snate@binkert.org 671681SN/Atemplate<class Impl> 685529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 704329Sktlim@umich.edu cpu(_cpu), 714329Sktlim@umich.edu instQueue(_cpu, this, params), 724329Sktlim@umich.edu ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 7913453Srekai.gonzalezalberquilla@arm.com wbNumInst(0), 8013453Srekai.gonzalezalberquilla@arm.com wbCycle(0), 812820Sktlim@umich.edu wbWidth(params->wbWidth), 829444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 831060SN/A{ 8410172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8510172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8610172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8710172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8810172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8910172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 9010172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9110172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9210172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9310172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9510172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9610172Sdam.sunwoo@arm.com 972292SN/A _status = Active; 982292SN/A exeStatus = Running; 992292SN/A wbStatus = Idle; 1001060SN/A 1011060SN/A // Setup wire to read instructions coming from issue. 1021060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1031060SN/A 1041060SN/A // Instruction queue needs the queue between issue and execute. 1051060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1061681SN/A 10713453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1086221Snate@binkert.org dispatchStatus[tid] = Running; 1096221Snate@binkert.org fetchRedirect[tid] = false; 1102292SN/A } 1112292SN/A 1122292SN/A updateLSQNextCycle = false; 1132292SN/A 11410328Smitch.hayenga@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1152292SN/A} 1162292SN/A 1172292SN/Atemplate <class Impl> 1182292SN/Astd::string 1192292SN/ADefaultIEW<Impl>::name() const 1202292SN/A{ 1212292SN/A return cpu->name() + ".iew"; 1221060SN/A} 1231060SN/A 1241681SN/Atemplate <class Impl> 1251062SN/Avoid 12610023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 12710023Smatt.horsnell@ARM.com{ 12810023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12910023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13011246Sradhika.jagtap@ARM.com /** 13111246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13211246Sradhika.jagtap@ARM.com * an instruction starts to execute. 13311246Sradhika.jagtap@ARM.com */ 13411246Sradhika.jagtap@ARM.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13511246Sradhika.jagtap@ARM.com "Execute"); 13611246Sradhika.jagtap@ARM.com /** 13711246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13811246Sradhika.jagtap@ARM.com * an instruction execution completes and it is marked ready to commit. 13911246Sradhika.jagtap@ARM.com */ 14011246Sradhika.jagtap@ARM.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 14111246Sradhika.jagtap@ARM.com "ToCommit"); 14210023Smatt.horsnell@ARM.com} 14310023Smatt.horsnell@ARM.com 14410023Smatt.horsnell@ARM.comtemplate <class Impl> 14510023Smatt.horsnell@ARM.comvoid 1462292SN/ADefaultIEW<Impl>::regStats() 1471062SN/A{ 1482301SN/A using namespace Stats; 1492301SN/A 1501062SN/A instQueue.regStats(); 1512727Sktlim@umich.edu ldstQueue.regStats(); 1521062SN/A 1531062SN/A iewIdleCycles 1541062SN/A .name(name() + ".iewIdleCycles") 1551062SN/A .desc("Number of cycles IEW is idle"); 1561062SN/A 1571062SN/A iewSquashCycles 1581062SN/A .name(name() + ".iewSquashCycles") 1591062SN/A .desc("Number of cycles IEW is squashing"); 1601062SN/A 1611062SN/A iewBlockCycles 1621062SN/A .name(name() + ".iewBlockCycles") 1631062SN/A .desc("Number of cycles IEW is blocking"); 1641062SN/A 1651062SN/A iewUnblockCycles 1661062SN/A .name(name() + ".iewUnblockCycles") 1671062SN/A .desc("Number of cycles IEW is unblocking"); 1681062SN/A 1691062SN/A iewDispatchedInsts 1701062SN/A .name(name() + ".iewDispatchedInsts") 1711062SN/A .desc("Number of instructions dispatched to IQ"); 1721062SN/A 1731062SN/A iewDispSquashedInsts 1741062SN/A .name(name() + ".iewDispSquashedInsts") 1751062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1761062SN/A 1771062SN/A iewDispLoadInsts 1781062SN/A .name(name() + ".iewDispLoadInsts") 1791062SN/A .desc("Number of dispatched load instructions"); 1801062SN/A 1811062SN/A iewDispStoreInsts 1821062SN/A .name(name() + ".iewDispStoreInsts") 1831062SN/A .desc("Number of dispatched store instructions"); 1841062SN/A 1851062SN/A iewDispNonSpecInsts 1861062SN/A .name(name() + ".iewDispNonSpecInsts") 1871062SN/A .desc("Number of dispatched non-speculative instructions"); 1881062SN/A 1891062SN/A iewIQFullEvents 1901062SN/A .name(name() + ".iewIQFullEvents") 1911062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1921062SN/A 1932292SN/A iewLSQFullEvents 1942292SN/A .name(name() + ".iewLSQFullEvents") 1952292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1962292SN/A 1971062SN/A memOrderViolationEvents 1981062SN/A .name(name() + ".memOrderViolationEvents") 1991062SN/A .desc("Number of memory order violations"); 2001062SN/A 2011062SN/A predictedTakenIncorrect 2021062SN/A .name(name() + ".predictedTakenIncorrect") 2031062SN/A .desc("Number of branches that were predicted taken incorrectly"); 2042292SN/A 2052292SN/A predictedNotTakenIncorrect 2062292SN/A .name(name() + ".predictedNotTakenIncorrect") 2072292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2082292SN/A 2092292SN/A branchMispredicts 2102292SN/A .name(name() + ".branchMispredicts") 2112292SN/A .desc("Number of branch mispredicts detected at execute"); 2122292SN/A 2132292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2142301SN/A 2152727Sktlim@umich.edu iewExecutedInsts 2162353SN/A .name(name() + ".iewExecutedInsts") 2172727Sktlim@umich.edu .desc("Number of executed instructions"); 2182727Sktlim@umich.edu 2192727Sktlim@umich.edu iewExecLoadInsts 2206221Snate@binkert.org .init(cpu->numThreads) 2212353SN/A .name(name() + ".iewExecLoadInsts") 2222727Sktlim@umich.edu .desc("Number of load instructions executed") 2232727Sktlim@umich.edu .flags(total); 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu iewExecSquashedInsts 2262353SN/A .name(name() + ".iewExecSquashedInsts") 2272727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu iewExecutedSwp 2306221Snate@binkert.org .init(cpu->numThreads) 2318240Snate@binkert.org .name(name() + ".exec_swp") 2322301SN/A .desc("number of swp insts executed") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352727Sktlim@umich.edu iewExecutedNop 2366221Snate@binkert.org .init(cpu->numThreads) 2378240Snate@binkert.org .name(name() + ".exec_nop") 2382301SN/A .desc("number of nop insts executed") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412727Sktlim@umich.edu iewExecutedRefs 2426221Snate@binkert.org .init(cpu->numThreads) 2438240Snate@binkert.org .name(name() + ".exec_refs") 2442301SN/A .desc("number of memory reference insts executed") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472727Sktlim@umich.edu iewExecutedBranches 2486221Snate@binkert.org .init(cpu->numThreads) 2498240Snate@binkert.org .name(name() + ".exec_branches") 2502301SN/A .desc("Number of branches executed") 2512727Sktlim@umich.edu .flags(total); 2522301SN/A 2532301SN/A iewExecStoreInsts 2548240Snate@binkert.org .name(name() + ".exec_stores") 2552301SN/A .desc("Number of stores executed") 2562727Sktlim@umich.edu .flags(total); 2572727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2582727Sktlim@umich.edu 2592727Sktlim@umich.edu iewExecRate 2608240Snate@binkert.org .name(name() + ".exec_rate") 2612727Sktlim@umich.edu .desc("Inst execution rate") 2622727Sktlim@umich.edu .flags(total); 2632727Sktlim@umich.edu 2642727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2652301SN/A 2662301SN/A iewInstsToCommit 2676221Snate@binkert.org .init(cpu->numThreads) 2688240Snate@binkert.org .name(name() + ".wb_sent") 2692301SN/A .desc("cumulative count of insts sent to commit") 2702727Sktlim@umich.edu .flags(total); 2712301SN/A 2722326SN/A writebackCount 2736221Snate@binkert.org .init(cpu->numThreads) 2748240Snate@binkert.org .name(name() + ".wb_count") 2752301SN/A .desc("cumulative count of insts written-back") 2762727Sktlim@umich.edu .flags(total); 2772301SN/A 2782326SN/A producerInst 2796221Snate@binkert.org .init(cpu->numThreads) 2808240Snate@binkert.org .name(name() + ".wb_producers") 2812301SN/A .desc("num instructions producing a value") 2822727Sktlim@umich.edu .flags(total); 2832301SN/A 2842326SN/A consumerInst 2856221Snate@binkert.org .init(cpu->numThreads) 2868240Snate@binkert.org .name(name() + ".wb_consumers") 2872301SN/A .desc("num instructions consuming a value") 2882727Sktlim@umich.edu .flags(total); 2892301SN/A 2902326SN/A wbFanout 2918240Snate@binkert.org .name(name() + ".wb_fanout") 2922301SN/A .desc("average fanout of values written-back") 2932727Sktlim@umich.edu .flags(total); 2942301SN/A 2952326SN/A wbFanout = producerInst / consumerInst; 2962301SN/A 2972326SN/A wbRate 2988240Snate@binkert.org .name(name() + ".wb_rate") 2992301SN/A .desc("insts written-back per cycle") 3002727Sktlim@umich.edu .flags(total); 3012326SN/A wbRate = writebackCount / cpu->numCycles; 3021062SN/A} 3031062SN/A 3041681SN/Atemplate<class Impl> 3051060SN/Avoid 3069427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3071060SN/A{ 3086221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3092292SN/A toRename->iewInfo[tid].usedIQ = true; 3102292SN/A toRename->iewInfo[tid].freeIQEntries = 3112292SN/A instQueue.numFreeEntries(tid); 3122292SN/A 3132292SN/A toRename->iewInfo[tid].usedLSQ = true; 31410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 31510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3162292SN/A } 3172292SN/A 3188887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3198733Sgeoffrey.blake@arm.com if (cpu->checker) { 3208850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3218887Sgeoffrey.blake@arm.com } 3228733Sgeoffrey.blake@arm.com 3232733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3241060SN/A} 3251060SN/A 3261681SN/Atemplate<class Impl> 3271060SN/Avoid 32813641Sqtt2@cornell.eduDefaultIEW<Impl>::clearStates(ThreadID tid) 32913641Sqtt2@cornell.edu{ 33013641Sqtt2@cornell.edu toRename->iewInfo[tid].usedIQ = true; 33113641Sqtt2@cornell.edu toRename->iewInfo[tid].freeIQEntries = 33213641Sqtt2@cornell.edu instQueue.numFreeEntries(tid); 33313641Sqtt2@cornell.edu 33413641Sqtt2@cornell.edu toRename->iewInfo[tid].usedLSQ = true; 33513641Sqtt2@cornell.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 33613641Sqtt2@cornell.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 33713641Sqtt2@cornell.edu} 33813641Sqtt2@cornell.edu 33913641Sqtt2@cornell.edutemplate<class Impl> 34013641Sqtt2@cornell.eduvoid 3412292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3421060SN/A{ 3431060SN/A timeBuffer = tb_ptr; 3441060SN/A 3451060SN/A // Setup wire to read information from time buffer, from commit. 3461060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3471060SN/A 3481060SN/A // Setup wire to write information back to previous stages. 3491060SN/A toRename = timeBuffer->getWire(0); 3501060SN/A 3512292SN/A toFetch = timeBuffer->getWire(0); 3522292SN/A 3531060SN/A // Instruction queue also needs main time buffer. 3541060SN/A instQueue.setTimeBuffer(tb_ptr); 3551060SN/A} 3561060SN/A 3571681SN/Atemplate<class Impl> 3581060SN/Avoid 3592292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3601060SN/A{ 3611060SN/A renameQueue = rq_ptr; 3621060SN/A 3631060SN/A // Setup wire to read information from rename queue. 3641060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3651060SN/A} 3661060SN/A 3671681SN/Atemplate<class Impl> 3681060SN/Avoid 3692292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3701060SN/A{ 3711060SN/A iewQueue = iq_ptr; 3721060SN/A 3731060SN/A // Setup wire to write instructions to commit. 3741060SN/A toCommit = iewQueue->getWire(0); 3751060SN/A} 3761060SN/A 3771681SN/Atemplate<class Impl> 3781060SN/Avoid 3796221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3801060SN/A{ 3812292SN/A activeThreads = at_ptr; 3822292SN/A 3832292SN/A ldstQueue.setActiveThreads(at_ptr); 3842292SN/A instQueue.setActiveThreads(at_ptr); 3851060SN/A} 3861060SN/A 3871681SN/Atemplate<class Impl> 3881060SN/Avoid 3892292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3901060SN/A{ 3912292SN/A scoreboard = sb_ptr; 3921060SN/A} 3931060SN/A 3942307SN/Atemplate <class Impl> 3952863Sktlim@umich.edubool 3969444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3972307SN/A{ 39810510Smitch.hayenga@arm.com bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3999444SAndreas.Sandberg@ARM.com 4009444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4019444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 4029444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 4039444SAndreas.Sandberg@ARM.com drained = false; 4049444SAndreas.Sandberg@ARM.com } 4059444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 4069444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 4079444SAndreas.Sandberg@ARM.com drained = false; 4089444SAndreas.Sandberg@ARM.com } 40911650Srekai.gonzalezalberquilla@arm.com drained = drained && dispatchStatus[tid] == Running; 4109444SAndreas.Sandberg@ARM.com } 4119444SAndreas.Sandberg@ARM.com 4129783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 4139783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 4149783Sandreas.hansson@arm.com // above 4159783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4169783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4179783Sandreas.hansson@arm.com drained = false; 4189783Sandreas.hansson@arm.com } 4199783Sandreas.hansson@arm.com 4209444SAndreas.Sandberg@ARM.com return drained; 4211681SN/A} 4221681SN/A 4232316SN/Atemplate <class Impl> 4241681SN/Avoid 4259444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4262843Sktlim@umich.edu{ 4279444SAndreas.Sandberg@ARM.com assert(isDrained()); 4282843Sktlim@umich.edu 4299444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4309444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4311681SN/A} 4321681SN/A 4332307SN/Atemplate <class Impl> 4341681SN/Avoid 4352307SN/ADefaultIEW<Impl>::takeOverFrom() 4361060SN/A{ 4372348SN/A // Reset all state. 4382307SN/A _status = Active; 4392307SN/A exeStatus = Running; 4402307SN/A wbStatus = Idle; 4411060SN/A 4422307SN/A instQueue.takeOverFrom(); 4432307SN/A ldstQueue.takeOverFrom(); 4449444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4451060SN/A 4469427SAndreas.Sandberg@ARM.com startupStage(); 4472307SN/A cpu->activityThisCycle(); 4481060SN/A 4496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4506221Snate@binkert.org dispatchStatus[tid] = Running; 4516221Snate@binkert.org fetchRedirect[tid] = false; 4522307SN/A } 4531060SN/A 4542307SN/A updateLSQNextCycle = false; 4552307SN/A 4562873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4572307SN/A issueToExecQueue.advance(); 4581060SN/A } 4591060SN/A} 4601060SN/A 4611681SN/Atemplate<class Impl> 4621060SN/Avoid 4636221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4642107SN/A{ 46513831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid); 4662107SN/A 4672292SN/A // Tell the IQ to start squashing. 4682292SN/A instQueue.squash(tid); 4692107SN/A 4702292SN/A // Tell the LDSTQ to start squashing. 4712326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4722292SN/A updatedQueues = true; 4732107SN/A 4742292SN/A // Clear the skid buffer in case it has any data in it. 47513831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, 47613831SAndrea.Mondelli@ucf.edu "Removing skidbuffer instructions until " 47713831SAndrea.Mondelli@ucf.edu "[sn:%llu] [tid:%i]\n", 47813831SAndrea.Mondelli@ucf.edu fromCommit->commitInfo[tid].doneSeqNum, tid); 4792935Sksewell@umich.edu 4802292SN/A while (!skidBuffer[tid].empty()) { 48110239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isLoad()) { 48210239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 48310239Sbinhpham@cs.rutgers.edu } 48413652Sqtt2@cornell.edu if (skidBuffer[tid].front()->isStore() || 48513652Sqtt2@cornell.edu skidBuffer[tid].front()->isAtomic()) { 48610239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 4872292SN/A } 4882107SN/A 4892292SN/A toRename->iewInfo[tid].dispatched++; 4902107SN/A 4912292SN/A skidBuffer[tid].pop(); 4922292SN/A } 4932107SN/A 4942702Sktlim@umich.edu emptyRenameInsts(tid); 4952107SN/A} 4962107SN/A 4972107SN/Atemplate<class Impl> 4982107SN/Avoid 49913429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 5002292SN/A{ 50113831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction," 50213831SAndrea.Mondelli@ucf.edu " PC: %s " 50313831SAndrea.Mondelli@ucf.edu "\n", tid, inst->seqNum, inst->pcState() ); 5042292SN/A 50510231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5067852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5077852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5087852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5097852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 5102935Sksewell@umich.edu 5117852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 5127852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 5132292SN/A 5147852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 5157852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 5167852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5172292SN/A 5187852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5197852SMatt.Horsnell@arm.com } 5207852SMatt.Horsnell@arm.com 5212292SN/A} 5222292SN/A 5232292SN/Atemplate<class Impl> 5242292SN/Avoid 52513429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 5262292SN/A{ 52713831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger " 52813831SAndrea.Mondelli@ucf.edu "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum); 5298513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5308513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5318513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5328513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5338513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5348513SGiacomo.Gabrielli@arm.com // the squash. 53510231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5368513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5378513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5382292SN/A 5397852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5408513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5418137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5422292SN/A 5438513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5448513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5452292SN/A 5467852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5477852SMatt.Horsnell@arm.com } 5482292SN/A} 5492292SN/A 5502292SN/Atemplate<class Impl> 5512292SN/Avoid 5526221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5532292SN/A{ 55413831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Blocking.\n", tid); 5552292SN/A 5562292SN/A if (dispatchStatus[tid] != Blocked && 5572292SN/A dispatchStatus[tid] != Unblocking) { 5582292SN/A toRename->iewBlock[tid] = true; 5592292SN/A wroteToTimeBuffer = true; 5602292SN/A } 5612292SN/A 5622292SN/A // Add the current inputs to the skid buffer so they can be 5632292SN/A // reprocessed when this stage unblocks. 5642292SN/A skidInsert(tid); 5652292SN/A 5662292SN/A dispatchStatus[tid] = Blocked; 5672292SN/A} 5682292SN/A 5692292SN/Atemplate<class Impl> 5702292SN/Avoid 5716221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5722292SN/A{ 57313831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid " 5742292SN/A "buffer %u.\n",tid, tid); 5752292SN/A 5762292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5772292SN/A // Also switch status to running. 5782292SN/A if (skidBuffer[tid].empty()) { 5792292SN/A toRename->iewUnblock[tid] = true; 5802292SN/A wroteToTimeBuffer = true; 58113831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid); 5822292SN/A dispatchStatus[tid] = Running; 5832292SN/A } 5842292SN/A} 5852292SN/A 5862292SN/Atemplate<class Impl> 5872292SN/Avoid 58813429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 5891060SN/A{ 5901681SN/A instQueue.wakeDependents(inst); 5911060SN/A} 5921060SN/A 5932292SN/Atemplate<class Impl> 5942292SN/Avoid 59513429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 5962292SN/A{ 5972292SN/A instQueue.rescheduleMemInst(inst); 5982292SN/A} 5991681SN/A 6001681SN/Atemplate<class Impl> 6011060SN/Avoid 60213429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 6031060SN/A{ 6042292SN/A instQueue.replayMemInst(inst); 6052292SN/A} 6061060SN/A 6072292SN/Atemplate<class Impl> 6082292SN/Avoid 60913429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 61010333Smitch.hayenga@arm.com{ 61110333Smitch.hayenga@arm.com instQueue.blockMemInst(inst); 61210333Smitch.hayenga@arm.com} 61310333Smitch.hayenga@arm.com 61410333Smitch.hayenga@arm.comtemplate<class Impl> 61510333Smitch.hayenga@arm.comvoid 61610333Smitch.hayenga@arm.comDefaultIEW<Impl>::cacheUnblocked() 61710333Smitch.hayenga@arm.com{ 61810333Smitch.hayenga@arm.com instQueue.cacheUnblocked(); 61910333Smitch.hayenga@arm.com} 62010333Smitch.hayenga@arm.com 62110333Smitch.hayenga@arm.comtemplate<class Impl> 62210333Smitch.hayenga@arm.comvoid 62313429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 6242292SN/A{ 6253221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6263221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6273221Sktlim@umich.edu // being added to the queue to commit without being processed by 6283221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6293221Sktlim@umich.edu 6302292SN/A // First check the time slot that this instruction will write 6312292SN/A // to. If there are free write ports at the time, then go ahead 6322292SN/A // and write the instruction to that time. If there are not, 6332292SN/A // keep looking back to see where's the first time there's a 6342326SN/A // free slot. 6352292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6362292SN/A ++wbNumInst; 6372820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6382292SN/A ++wbCycle; 6392292SN/A wbNumInst = 0; 6402292SN/A } 6412292SN/A } 6422292SN/A 6432353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6442353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6452292SN/A // Add finished instruction to queue to commit. 6462292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6472292SN/A (*iewQueue)[wbCycle].size++; 6482292SN/A} 6492292SN/A 6502292SN/Atemplate <class Impl> 6512292SN/Aunsigned 6522292SN/ADefaultIEW<Impl>::validInstsFromRename() 6532292SN/A{ 6542292SN/A unsigned inst_count = 0; 6552292SN/A 6562292SN/A for (int i=0; i<fromRename->size; i++) { 6572731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6582292SN/A inst_count++; 6592292SN/A } 6602292SN/A 6612292SN/A return inst_count; 6622292SN/A} 6632292SN/A 6642292SN/Atemplate<class Impl> 6652292SN/Avoid 6666221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6672292SN/A{ 6682292SN/A DynInstPtr inst = NULL; 6692292SN/A 6702292SN/A while (!insts[tid].empty()) { 6712292SN/A inst = insts[tid].front(); 6722292SN/A 6732292SN/A insts[tid].pop(); 6742292SN/A 67513831SAndrea.Mondelli@ucf.edu DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into " 6762292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6777720Sgblack@eecs.umich.edu inst->pcState(),tid); 6782292SN/A 6792292SN/A skidBuffer[tid].push(inst); 6802292SN/A } 6812292SN/A 6822292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6832292SN/A "Skidbuffer Exceeded Max Size"); 6842292SN/A} 6852292SN/A 6862292SN/Atemplate<class Impl> 6872292SN/Aint 6882292SN/ADefaultIEW<Impl>::skidCount() 6892292SN/A{ 6902292SN/A int max=0; 6912292SN/A 6926221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6936221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6942292SN/A 6953867Sbinkertn@umich.edu while (threads != end) { 6966221Snate@binkert.org ThreadID tid = *threads++; 6973867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6982292SN/A if (max < thread_count) 6992292SN/A max = thread_count; 7002292SN/A } 7012292SN/A 7022292SN/A return max; 7032292SN/A} 7042292SN/A 7052292SN/Atemplate<class Impl> 7062292SN/Abool 7072292SN/ADefaultIEW<Impl>::skidsEmpty() 7082292SN/A{ 7096221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7106221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7112292SN/A 7123867Sbinkertn@umich.edu while (threads != end) { 7136221Snate@binkert.org ThreadID tid = *threads++; 7143867Sbinkertn@umich.edu 7153867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7162292SN/A return false; 7172292SN/A } 7182292SN/A 7192292SN/A return true; 7201062SN/A} 7211062SN/A 7221681SN/Atemplate <class Impl> 7231062SN/Avoid 7242292SN/ADefaultIEW<Impl>::updateStatus() 7251062SN/A{ 7262292SN/A bool any_unblocking = false; 7271062SN/A 7286221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7296221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7301062SN/A 7313867Sbinkertn@umich.edu while (threads != end) { 7326221Snate@binkert.org ThreadID tid = *threads++; 7331062SN/A 7342292SN/A if (dispatchStatus[tid] == Unblocking) { 7352292SN/A any_unblocking = true; 7362292SN/A break; 7372292SN/A } 7382292SN/A } 7391062SN/A 7402292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7412292SN/A // and there's no stores waiting to write back, and dispatch is not 7422292SN/A // unblocking, then there is no internal activity for the IEW stage. 7437897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7442292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7452292SN/A !ldstQueue.willWB() && !any_unblocking) { 7462292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7471062SN/A 7482292SN/A deactivateStage(); 7491062SN/A 7502292SN/A _status = Inactive; 7512292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7522292SN/A ldstQueue.willWB() || 7532292SN/A any_unblocking)) { 7542292SN/A // Otherwise there is internal activity. Set to active. 7552292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7561062SN/A 7572292SN/A activateStage(); 7581062SN/A 7592292SN/A _status = Active; 7601062SN/A } 7611062SN/A} 7621062SN/A 7631681SN/Atemplate <class Impl> 7642292SN/Abool 7656221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7662292SN/A{ 7672292SN/A bool ret_val(false); 7682292SN/A 76910328Smitch.hayenga@arm.com if (fromCommit->commitInfo[tid].robSquashing) { 77013831SAndrea.Mondelli@ucf.edu DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid); 7712292SN/A ret_val = true; 7722292SN/A } else if (instQueue.isFull(tid)) { 77313831SAndrea.Mondelli@ucf.edu DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid); 7742292SN/A ret_val = true; 7752292SN/A } 7762292SN/A 7772292SN/A return ret_val; 7782292SN/A} 7792292SN/A 7802292SN/Atemplate <class Impl> 7812292SN/Avoid 7826221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7832292SN/A{ 7842292SN/A // Check if there's a squash signal, squash if there is 7852292SN/A // Check stall signals, block if there is. 7862292SN/A // If status was Blocked 7872292SN/A // if so then go to unblocking 7882292SN/A // If status was Squashing 7892292SN/A // check if squashing is not high. Switch to running this cycle. 7902292SN/A 7912292SN/A if (fromCommit->commitInfo[tid].squash) { 7922292SN/A squash(tid); 7932292SN/A 7942292SN/A if (dispatchStatus[tid] == Blocked || 7952292SN/A dispatchStatus[tid] == Unblocking) { 7962292SN/A toRename->iewUnblock[tid] = true; 7972292SN/A wroteToTimeBuffer = true; 7982292SN/A } 7992292SN/A 8002292SN/A dispatchStatus[tid] = Squashing; 8012292SN/A fetchRedirect[tid] = false; 8022292SN/A return; 8032292SN/A } 8042292SN/A 8052292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 80613831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid); 8072292SN/A 8082292SN/A dispatchStatus[tid] = Squashing; 8092702Sktlim@umich.edu emptyRenameInsts(tid); 8102702Sktlim@umich.edu wroteToTimeBuffer = true; 8112292SN/A } 8122292SN/A 8132292SN/A if (checkStall(tid)) { 8142292SN/A block(tid); 8152292SN/A dispatchStatus[tid] = Blocked; 8162292SN/A return; 8172292SN/A } 8182292SN/A 8192292SN/A if (dispatchStatus[tid] == Blocked) { 8202292SN/A // Status from previous cycle was blocked, but there are no more stall 8212292SN/A // conditions. Switch over to unblocking. 82213831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n", 8232292SN/A tid); 8242292SN/A 8252292SN/A dispatchStatus[tid] = Unblocking; 8262292SN/A 8272292SN/A unblock(tid); 8282292SN/A 8292292SN/A return; 8302292SN/A } 8312292SN/A 8322292SN/A if (dispatchStatus[tid] == Squashing) { 8332292SN/A // Switch status to running if rename isn't being told to block or 8342292SN/A // squash this cycle. 83513831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n", 8362292SN/A tid); 8372292SN/A 8382292SN/A dispatchStatus[tid] = Running; 8392292SN/A 8402292SN/A return; 8412292SN/A } 8422292SN/A} 8432292SN/A 8442292SN/Atemplate <class Impl> 8452292SN/Avoid 8462292SN/ADefaultIEW<Impl>::sortInsts() 8472292SN/A{ 8482292SN/A int insts_from_rename = fromRename->size; 8492326SN/A#ifdef DEBUG 8506221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8516221Snate@binkert.org assert(insts[tid].empty()); 8522326SN/A#endif 8532292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8542292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8552292SN/A } 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Avoid 8606221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8612702Sktlim@umich.edu{ 86213831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid); 8632935Sksewell@umich.edu 8642702Sktlim@umich.edu while (!insts[tid].empty()) { 8652935Sksewell@umich.edu 86610239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isLoad()) { 86710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 86810239Sbinhpham@cs.rutgers.edu } 86913652Sqtt2@cornell.edu if (insts[tid].front()->isStore() || 87013652Sqtt2@cornell.edu insts[tid].front()->isAtomic()) { 87110239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 8722702Sktlim@umich.edu } 8732702Sktlim@umich.edu 8742702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8752702Sktlim@umich.edu 8762702Sktlim@umich.edu insts[tid].pop(); 8772702Sktlim@umich.edu } 8782702Sktlim@umich.edu} 8792702Sktlim@umich.edu 8802702Sktlim@umich.edutemplate <class Impl> 8812702Sktlim@umich.eduvoid 8822292SN/ADefaultIEW<Impl>::wakeCPU() 8832292SN/A{ 8842292SN/A cpu->wakeCPU(); 8852292SN/A} 8862292SN/A 8872292SN/Atemplate <class Impl> 8882292SN/Avoid 8892292SN/ADefaultIEW<Impl>::activityThisCycle() 8902292SN/A{ 8912292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8922292SN/A cpu->activityThisCycle(); 8932292SN/A} 8942292SN/A 8952292SN/Atemplate <class Impl> 8962292SN/Ainline void 8972292SN/ADefaultIEW<Impl>::activateStage() 8982292SN/A{ 8992292SN/A DPRINTF(Activity, "Activating stage.\n"); 9002733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9012292SN/A} 9022292SN/A 9032292SN/Atemplate <class Impl> 9042292SN/Ainline void 9052292SN/ADefaultIEW<Impl>::deactivateStage() 9062292SN/A{ 9072292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9082733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9092292SN/A} 9102292SN/A 9112292SN/Atemplate<class Impl> 9122292SN/Avoid 9136221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9142292SN/A{ 9152292SN/A // If status is Running or idle, 9162292SN/A // call dispatchInsts() 9172292SN/A // If status is Unblocking, 9182292SN/A // buffer any instructions coming from rename 9192292SN/A // continue trying to empty skid buffer 9202292SN/A // check if stall conditions have passed 9212292SN/A 9222292SN/A if (dispatchStatus[tid] == Blocked) { 9232292SN/A ++iewBlockCycles; 9242292SN/A 9252292SN/A } else if (dispatchStatus[tid] == Squashing) { 9262292SN/A ++iewSquashCycles; 9272292SN/A } 9282292SN/A 9292292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9302292SN/A // will allow, as long as it is not currently blocked. 9312292SN/A if (dispatchStatus[tid] == Running || 9322292SN/A dispatchStatus[tid] == Idle) { 9332292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9342292SN/A "dispatch.\n", tid); 9352292SN/A 9362292SN/A dispatchInsts(tid); 9372292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9382292SN/A // Make sure that the skid buffer has something in it if the 9392292SN/A // status is unblocking. 9402292SN/A assert(!skidsEmpty()); 9412292SN/A 9422292SN/A // If the status was unblocking, then instructions from the skid 9432292SN/A // buffer were used. Remove those instructions and handle 9442292SN/A // the rest of unblocking. 9452292SN/A dispatchInsts(tid); 9462292SN/A 9472292SN/A ++iewUnblockCycles; 9482292SN/A 9495215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9502292SN/A // Add the current inputs to the skid buffer so they can be 9512292SN/A // reprocessed when this stage unblocks. 9522292SN/A skidInsert(tid); 9532292SN/A } 9542292SN/A 9552292SN/A unblock(tid); 9562292SN/A } 9572292SN/A} 9582292SN/A 9592292SN/Atemplate <class Impl> 9602292SN/Avoid 9616221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9622292SN/A{ 9632292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9642292SN/A // otherwise. 9652292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9662292SN/A dispatchStatus[tid] == Unblocking ? 9672292SN/A skidBuffer[tid] : insts[tid]; 9682292SN/A 9692292SN/A int insts_to_add = insts_to_dispatch.size(); 9702292SN/A 9712292SN/A DynInstPtr inst; 9722292SN/A bool add_to_iq = false; 9732292SN/A int dis_num_inst = 0; 9742292SN/A 9752292SN/A // Loop through the instructions, putting them in the instruction 9762292SN/A // queue. 9772292SN/A for ( ; dis_num_inst < insts_to_add && 9782820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9792292SN/A ++dis_num_inst) 9802292SN/A { 9812292SN/A inst = insts_to_dispatch.front(); 9822292SN/A 9832292SN/A if (dispatchStatus[tid] == Unblocking) { 98413831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid " 9852292SN/A "buffer\n", tid); 9862292SN/A } 9872292SN/A 9882292SN/A // Make sure there's a valid instruction there. 9892292SN/A assert(inst); 9902292SN/A 99113831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9922292SN/A "IQ.\n", 9937720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9942292SN/A 9952292SN/A // Be sure to mark these instructions as ready so that the 9962292SN/A // commit stage can go ahead and execute them, and mark 9972292SN/A // them as issued so the IQ doesn't reprocess them. 9982292SN/A 9992292SN/A // Check for squashed instructions. 10002292SN/A if (inst->isSquashed()) { 100113831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, " 10022292SN/A "not adding to IQ.\n", tid); 10032292SN/A 10042292SN/A ++iewDispSquashedInsts; 10052292SN/A 10062292SN/A insts_to_dispatch.pop(); 10072292SN/A 10082292SN/A //Tell Rename That An Instruction has been processed 100910239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 101010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10112292SN/A } 101213652Sqtt2@cornell.edu if (inst->isStore() || inst->isAtomic()) { 101310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 101410239Sbinhpham@cs.rutgers.edu } 101510239Sbinhpham@cs.rutgers.edu 10162292SN/A toRename->iewInfo[tid].dispatched++; 10172292SN/A 10182292SN/A continue; 10192292SN/A } 10202292SN/A 10212292SN/A // Check for full conditions. 10222292SN/A if (instQueue.isFull(tid)) { 102313831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid); 10242292SN/A 10252292SN/A // Call function to start blocking. 10262292SN/A block(tid); 10272292SN/A 10282292SN/A // Set unblock to false. Special case where we are using 10292292SN/A // skidbuffer (unblocking) instructions but then we still 10302292SN/A // get full in the IQ. 10312292SN/A toRename->iewUnblock[tid] = false; 10322292SN/A 10332292SN/A ++iewIQFullEvents; 10342292SN/A break; 103510240Sbinhpham@cs.rutgers.edu } 103610240Sbinhpham@cs.rutgers.edu 103710240Sbinhpham@cs.rutgers.edu // Check LSQ if inst is LD/ST 103813652Sqtt2@cornell.edu if ((inst->isAtomic() && ldstQueue.sqFull(tid)) || 103913652Sqtt2@cornell.edu (inst->isLoad() && ldstQueue.lqFull(tid)) || 104010240Sbinhpham@cs.rutgers.edu (inst->isStore() && ldstQueue.sqFull(tid))) { 104113831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid, 104210240Sbinhpham@cs.rutgers.edu inst->isLoad() ? "LQ" : "SQ"); 10432292SN/A 10442292SN/A // Call function to start blocking. 10452292SN/A block(tid); 10462292SN/A 10472292SN/A // Set unblock to false. Special case where we are using 10482292SN/A // skidbuffer (unblocking) instructions but then we still 10492292SN/A // get full in the IQ. 10502292SN/A toRename->iewUnblock[tid] = false; 10512292SN/A 10522292SN/A ++iewLSQFullEvents; 10532292SN/A break; 10542292SN/A } 10552292SN/A 10562292SN/A // Otherwise issue the instruction just fine. 105713652Sqtt2@cornell.edu if (inst->isAtomic()) { 105813831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " 105913652Sqtt2@cornell.edu "encountered, adding to LSQ.\n", tid); 106013652Sqtt2@cornell.edu 106113652Sqtt2@cornell.edu ldstQueue.insertStore(inst); 106213652Sqtt2@cornell.edu 106313652Sqtt2@cornell.edu ++iewDispStoreInsts; 106413652Sqtt2@cornell.edu 106513652Sqtt2@cornell.edu // AMOs need to be set as "canCommit()" 106613652Sqtt2@cornell.edu // so that commit can process them when they reach the 106713652Sqtt2@cornell.edu // head of commit. 106813652Sqtt2@cornell.edu inst->setCanCommit(); 106913652Sqtt2@cornell.edu instQueue.insertNonSpec(inst); 107013652Sqtt2@cornell.edu add_to_iq = false; 107113652Sqtt2@cornell.edu 107213652Sqtt2@cornell.edu ++iewDispNonSpecInsts; 107313652Sqtt2@cornell.edu 107413652Sqtt2@cornell.edu toRename->iewInfo[tid].dispatchedToSQ++; 107513652Sqtt2@cornell.edu } else if (inst->isLoad()) { 107613831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " 10772292SN/A "encountered, adding to LSQ.\n", tid); 10782292SN/A 10792292SN/A // Reserve a spot in the load store queue for this 10802292SN/A // memory access. 10812292SN/A ldstQueue.insertLoad(inst); 10822292SN/A 10832292SN/A ++iewDispLoadInsts; 10842292SN/A 10852292SN/A add_to_iq = true; 10862292SN/A 108710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10882292SN/A } else if (inst->isStore()) { 108913831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Memory instruction " 10902292SN/A "encountered, adding to LSQ.\n", tid); 10912292SN/A 10922292SN/A ldstQueue.insertStore(inst); 10932292SN/A 10942292SN/A ++iewDispStoreInsts; 10952292SN/A 10962336SN/A if (inst->isStoreConditional()) { 10972336SN/A // Store conditionals need to be set as "canCommit()" 10982336SN/A // so that commit can process them when they reach the 10992336SN/A // head of commit. 11002348SN/A // @todo: This is somewhat specific to Alpha. 11012292SN/A inst->setCanCommit(); 11022292SN/A instQueue.insertNonSpec(inst); 11032292SN/A add_to_iq = false; 11042292SN/A 11052292SN/A ++iewDispNonSpecInsts; 11062292SN/A } else { 11072292SN/A add_to_iq = true; 11082292SN/A } 11092292SN/A 111010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 11112292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11122326SN/A // Same as non-speculative stores. 11132292SN/A inst->setCanCommit(); 11142292SN/A instQueue.insertBarrier(inst); 11152292SN/A add_to_iq = false; 11162292SN/A } else if (inst->isNop()) { 111713831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, " 11182292SN/A "skipping.\n", tid); 11192292SN/A 11202292SN/A inst->setIssued(); 11212292SN/A inst->setExecuted(); 11222292SN/A inst->setCanCommit(); 11232292SN/A 11242326SN/A instQueue.recordProducer(inst); 11252292SN/A 11262727Sktlim@umich.edu iewExecutedNop[tid]++; 11272301SN/A 11282292SN/A add_to_iq = false; 11292292SN/A } else { 113010733Snilay@cs.wisc.edu assert(!inst->isExecuted()); 11312292SN/A add_to_iq = true; 11322292SN/A } 113310733Snilay@cs.wisc.edu 113412537Sandreas.sandberg@arm.com if (add_to_iq && inst->isNonSpeculative()) { 113513831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction " 11364033Sktlim@umich.edu "encountered, skipping.\n", tid); 11374033Sktlim@umich.edu 11384033Sktlim@umich.edu // Same as non-speculative stores. 11394033Sktlim@umich.edu inst->setCanCommit(); 11404033Sktlim@umich.edu 11414033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11424033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11434033Sktlim@umich.edu 11444033Sktlim@umich.edu ++iewDispNonSpecInsts; 11454033Sktlim@umich.edu 11464033Sktlim@umich.edu add_to_iq = false; 11474033Sktlim@umich.edu } 11482292SN/A 11492292SN/A // If the instruction queue is not full, then add the 11502292SN/A // instruction. 11512292SN/A if (add_to_iq) { 11522292SN/A instQueue.insert(inst); 11532292SN/A } 11542292SN/A 11552292SN/A insts_to_dispatch.pop(); 11562292SN/A 11572292SN/A toRename->iewInfo[tid].dispatched++; 11582292SN/A 11592292SN/A ++iewDispatchedInsts; 11608471SGiacomo.Gabrielli@arm.com 11618471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11629046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11638471SGiacomo.Gabrielli@arm.com#endif 116410023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11652292SN/A } 11662292SN/A 11672292SN/A if (!insts_to_dispatch.empty()) { 116813831SAndrea.Mondelli@ucf.edu DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid); 11692292SN/A block(tid); 11702292SN/A toRename->iewUnblock[tid] = false; 11712292SN/A } 11722292SN/A 11732292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11742292SN/A dispatchStatus[tid] = Running; 11752292SN/A 11762292SN/A updatedQueues = true; 11772292SN/A } 11782292SN/A 11792292SN/A dis_num_inst = 0; 11802292SN/A} 11812292SN/A 11822292SN/Atemplate <class Impl> 11832292SN/Avoid 11842292SN/ADefaultIEW<Impl>::printAvailableInsts() 11852292SN/A{ 11862292SN/A int inst = 0; 11872292SN/A 11882980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11892292SN/A 11902292SN/A while (fromIssue->insts[inst]) { 11912292SN/A 11922980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11932292SN/A 11947720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11952292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11962292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11972292SN/A 11982292SN/A inst++; 11992292SN/A 12002292SN/A } 12012292SN/A 12022980Sgblack@eecs.umich.edu std::cout << "\n"; 12032292SN/A} 12042292SN/A 12052292SN/Atemplate <class Impl> 12062292SN/Avoid 12072292SN/ADefaultIEW<Impl>::executeInsts() 12082292SN/A{ 12092292SN/A wbNumInst = 0; 12102292SN/A wbCycle = 0; 12112292SN/A 12126221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12136221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12142292SN/A 12153867Sbinkertn@umich.edu while (threads != end) { 12166221Snate@binkert.org ThreadID tid = *threads++; 12172292SN/A fetchRedirect[tid] = false; 12182292SN/A } 12192292SN/A 12202698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12217599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12222698Sktlim@umich.edu// printAvailableInsts(); 12231062SN/A 12241062SN/A // Execute/writeback any instructions that are available. 12252333SN/A int insts_to_execute = fromIssue->size; 12262292SN/A int inst_num = 0; 12272333SN/A for (; inst_num < insts_to_execute; 12282326SN/A ++inst_num) { 12291062SN/A 12302292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12311062SN/A 12322333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12331062SN/A 123413831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n", 12357720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12361062SN/A 123711246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction has started 123811246Sradhika.jagtap@ARM.com // executing 123911246Sradhika.jagtap@ARM.com ppExecute->notify(inst); 124011246Sradhika.jagtap@ARM.com 12411062SN/A // Check if the instruction is squashed; if so then skip it 12421062SN/A if (inst->isSquashed()) { 12438315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 124413831SAndrea.Mondelli@ucf.edu " [sn:%llu]\n", inst->pcState(), inst->threadNumber, 12458315Sgeoffrey.blake@arm.com inst->seqNum); 12461062SN/A 12471062SN/A // Consider this instruction executed so that commit can go 12481062SN/A // ahead and retire the instruction. 12491062SN/A inst->setExecuted(); 12501062SN/A 12512292SN/A // Not sure if I should set this here or just let commit try to 12522292SN/A // commit any squashed instructions. I like the latter a bit more. 12532292SN/A inst->setCanCommit(); 12541062SN/A 12551062SN/A ++iewExecSquashedInsts; 12561062SN/A 12571062SN/A continue; 12581062SN/A } 12591062SN/A 12602292SN/A Fault fault = NoFault; 12611062SN/A 12621062SN/A // Execute instruction. 12631062SN/A // Note that if the instruction faults, it will be handled 12641062SN/A // at the commit stage. 12657850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12662292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12671062SN/A "reference.\n"); 12681062SN/A 12691062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 127013652Sqtt2@cornell.edu if (inst->isAtomic()) { 127113652Sqtt2@cornell.edu // AMOs are treated like store requests 127213652Sqtt2@cornell.edu fault = ldstQueue.executeStore(inst); 127313652Sqtt2@cornell.edu 127413652Sqtt2@cornell.edu if (inst->isTranslationDelayed() && 127513652Sqtt2@cornell.edu fault == NoFault) { 127613652Sqtt2@cornell.edu // A hw page table walk is currently going on; the 127713652Sqtt2@cornell.edu // instruction must be deferred. 127813652Sqtt2@cornell.edu DPRINTF(IEW, "Execute: Delayed translation, deferring " 127913652Sqtt2@cornell.edu "store.\n"); 128013652Sqtt2@cornell.edu instQueue.deferMemInst(inst); 128113652Sqtt2@cornell.edu continue; 128213652Sqtt2@cornell.edu } 128313652Sqtt2@cornell.edu } else if (inst->isLoad()) { 12842292SN/A // Loads will mark themselves as executed, and their writeback 12852292SN/A // event adds the instruction to the queue to commit 12862292SN/A fault = ldstQueue.executeLoad(inst); 12877944SGiacomo.Gabrielli@arm.com 12887944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12897944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12907944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12917944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12927944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12937944SGiacomo.Gabrielli@arm.com "load.\n"); 12947944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12957944SGiacomo.Gabrielli@arm.com continue; 12967944SGiacomo.Gabrielli@arm.com } 12977944SGiacomo.Gabrielli@arm.com 12987850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12998073SAli.Saidi@ARM.com inst->fault = NoFault; 13007850SMatt.Horsnell@arm.com } 13011062SN/A } else if (inst->isStore()) { 13022367SN/A fault = ldstQueue.executeStore(inst); 13031062SN/A 13047944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 13057944SGiacomo.Gabrielli@arm.com fault == NoFault) { 13067944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 13077944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 13087944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 13097944SGiacomo.Gabrielli@arm.com "store.\n"); 13107944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 13117944SGiacomo.Gabrielli@arm.com continue; 13127944SGiacomo.Gabrielli@arm.com } 13137944SGiacomo.Gabrielli@arm.com 13142292SN/A // If the store had a fault then it may not have a mem req 131510231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 13167782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 13177782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 13187782Sminkyu.jeong@arm.com // to commit without the instruction completing. 13192367SN/A // Send this instruction to commit, also make sure iew stage 13202367SN/A // realizes there is activity. 13212367SN/A inst->setExecuted(); 13222367SN/A instToCommit(inst); 13232367SN/A activityThisCycle(); 13242292SN/A } 13252326SN/A 13262326SN/A // Store conditionals will mark themselves as 13272326SN/A // executed, and their writeback event will add the 13282326SN/A // instruction to the queue to commit. 13291062SN/A } else { 13302292SN/A panic("Unexpected memory type!\n"); 13311062SN/A } 13321062SN/A 13331062SN/A } else { 13347847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13357847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13367847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13377847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13387847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13397847Sminkyu.jeong@arm.com inst->execute(); 134010231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 13417848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13427847Sminkyu.jeong@arm.com } 13431062SN/A 13442292SN/A inst->setExecuted(); 13452292SN/A 13462292SN/A instToCommit(inst); 13471062SN/A } 13481062SN/A 13492301SN/A updateExeInstStats(inst); 13501681SN/A 13512326SN/A // Check if branch prediction was correct, if not then we need 13522326SN/A // to tell commit to squash in flight instructions. Only 13532326SN/A // handle this if there hasn't already been something that 13542107SN/A // redirects fetch in this group of instructions. 13551681SN/A 13562292SN/A // This probably needs to prioritize the redirects if a different 13572292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13582292SN/A // instruction first, so the branch resolution order will be correct. 13596221Snate@binkert.org ThreadID tid = inst->threadNumber; 13601062SN/A 13613732Sktlim@umich.edu if (!fetchRedirect[tid] || 13627852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13633732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13641062SN/A 13657856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13667856SMatt.Horsnell@arm.com // that have not been executed. 13677856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13687856SMatt.Horsnell@arm.com 13697856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13702292SN/A fetchRedirect[tid] = true; 13711062SN/A 137213831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 137313831SAndrea.Mondelli@ucf.edu "Branch mispredict detected.\n", 137413831SAndrea.Mondelli@ucf.edu tid,inst->seqNum); 137513831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] " 137613831SAndrea.Mondelli@ucf.edu "Predicted target was PC: %s\n", 137713831SAndrea.Mondelli@ucf.edu tid,inst->seqNum,inst->readPredTarg()); 137813831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 137913831SAndrea.Mondelli@ucf.edu "Redirecting fetch to PC: %s\n", 138013831SAndrea.Mondelli@ucf.edu tid,inst->seqNum,inst->pcState()); 13811062SN/A // If incorrect, then signal the ROB that it must be squashed. 13822292SN/A squashDueToBranch(inst, tid); 13831062SN/A 138410023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 138510023Smatt.horsnell@ARM.com 13863795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13871062SN/A predictedTakenIncorrect++; 13882292SN/A } else { 13892292SN/A predictedNotTakenIncorrect++; 13901062SN/A } 13912292SN/A } else if (ldstQueue.violation(tid)) { 13924033Sktlim@umich.edu assert(inst->isMemRef()); 13932326SN/A // If there was an ordering violation, then get the 13942326SN/A // DynInst that caused the violation. Note that this 13952292SN/A // clears the violation signal. 13962292SN/A DynInstPtr violator; 13972292SN/A violator = ldstQueue.getMemDepViolator(tid); 13981062SN/A 13997720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 14007720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 14017720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 140213590Srekai.gonzalezalberquilla@arm.com inst->pcState(), inst->seqNum, inst->physEffAddr); 14037720Sgblack@eecs.umich.edu 14043732Sktlim@umich.edu fetchRedirect[tid] = true; 14053732Sktlim@umich.edu 14061062SN/A // Tell the instruction queue that a violation has occured. 14071062SN/A instQueue.violation(inst, violator); 14081062SN/A 14091062SN/A // Squash. 14108513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 14111062SN/A 14121062SN/A ++memOrderViolationEvents; 14131062SN/A } 14144033Sktlim@umich.edu } else { 14154033Sktlim@umich.edu // Reset any state associated with redirects that will not 14164033Sktlim@umich.edu // be used. 14174033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14184033Sktlim@umich.edu assert(inst->isMemRef()); 14194033Sktlim@umich.edu 14204033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14214033Sktlim@umich.edu 14224033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14237720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14247720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 142513590Srekai.gonzalezalberquilla@arm.com inst->physEffAddr); 14264033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14274033Sktlim@umich.edu "already squashing\n"); 14284033Sktlim@umich.edu 14294033Sktlim@umich.edu ++memOrderViolationEvents; 14304033Sktlim@umich.edu } 14311062SN/A } 14321062SN/A } 14332292SN/A 14342348SN/A // Update and record activity if we processed any instructions. 14352292SN/A if (inst_num) { 14362292SN/A if (exeStatus == Idle) { 14372292SN/A exeStatus = Running; 14382292SN/A } 14392292SN/A 14402292SN/A updatedQueues = true; 14412292SN/A 14422292SN/A cpu->activityThisCycle(); 14432292SN/A } 14442292SN/A 14452292SN/A // Need to reset this in case a writeback event needs to write into the 14462292SN/A // iew queue. That way the writeback event will write into the correct 14472292SN/A // spot in the queue. 14482292SN/A wbNumInst = 0; 14497852SMatt.Horsnell@arm.com 14502107SN/A} 14512107SN/A 14522292SN/Atemplate <class Impl> 14532107SN/Avoid 14542292SN/ADefaultIEW<Impl>::writebackInsts() 14552107SN/A{ 14562326SN/A // Loop through the head of the time buffer and wake any 14572326SN/A // dependents. These instructions are about to write back. Also 14582326SN/A // mark scoreboard that this instruction is finally complete. 14592326SN/A // Either have IEW have direct access to scoreboard, or have this 14602326SN/A // as part of backwards communication. 14613958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14622292SN/A toCommit->insts[inst_num]; inst_num++) { 14632107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14646221Snate@binkert.org ThreadID tid = inst->threadNumber; 14652107SN/A 14667720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14677720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14682107SN/A 14692301SN/A iewInstsToCommit[tid]++; 147011246Sradhika.jagtap@ARM.com // Notify potential listeners that execution is complete for this 147111246Sradhika.jagtap@ARM.com // instruction. 147211246Sradhika.jagtap@ARM.com ppToCommit->notify(inst); 14732301SN/A 14742292SN/A // Some instructions will be sent to commit without having 14752292SN/A // executed because they need commit to handle them. 147610824SAndreas.Sandberg@ARM.com // E.g. Strictly ordered loads have not actually executed when they 14772292SN/A // are first sent to commit. Instead commit must tell the LSQ 147810824SAndreas.Sandberg@ARM.com // when it's ready to execute the strictly ordered load. 14792367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14802301SN/A int dependents = instQueue.wakeDependents(inst); 14812107SN/A 14822292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 148314025Sgiacomo.gabrielli@arm.com // Mark register as ready if not pinned 148414025Sgiacomo.gabrielli@arm.com if (inst->renamedDestRegIdx(i)-> 148514025Sgiacomo.gabrielli@arm.com getNumPinnedWritesToComplete() == 0) { 148614025Sgiacomo.gabrielli@arm.com DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 148714025Sgiacomo.gabrielli@arm.com inst->renamedDestRegIdx(i)->index(), 148814025Sgiacomo.gabrielli@arm.com inst->renamedDestRegIdx(i)->className()); 148914025Sgiacomo.gabrielli@arm.com scoreboard->setReg(inst->renamedDestRegIdx(i)); 149014025Sgiacomo.gabrielli@arm.com } 14912107SN/A } 14922301SN/A 14932348SN/A if (dependents) { 14942348SN/A producerInst[tid]++; 14952348SN/A consumerInst[tid]+= dependents; 14962348SN/A } 14972326SN/A writebackCount[tid]++; 14982107SN/A } 14992107SN/A } 15001060SN/A} 15011060SN/A 15021681SN/Atemplate<class Impl> 15031060SN/Avoid 15042292SN/ADefaultIEW<Impl>::tick() 15051060SN/A{ 15062292SN/A wbNumInst = 0; 15072292SN/A wbCycle = 0; 15081060SN/A 15092292SN/A wroteToTimeBuffer = false; 15102292SN/A updatedQueues = false; 15111060SN/A 151213590Srekai.gonzalezalberquilla@arm.com ldstQueue.tick(); 151313590Srekai.gonzalezalberquilla@arm.com 15142292SN/A sortInsts(); 15151060SN/A 15162326SN/A // Free function units marked as being freed this cycle. 15172326SN/A fuPool->processFreeUnits(); 15181062SN/A 15196221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15206221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15211060SN/A 15222326SN/A // Check stall and squash signals, dispatch any instructions. 15233867Sbinkertn@umich.edu while (threads != end) { 15246221Snate@binkert.org ThreadID tid = *threads++; 15251060SN/A 15262292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15271060SN/A 15282292SN/A checkSignalsAndUpdate(tid); 15292292SN/A dispatch(tid); 15301060SN/A } 15311060SN/A 15322292SN/A if (exeStatus != Squashing) { 15332292SN/A executeInsts(); 15341060SN/A 15352292SN/A writebackInsts(); 15362292SN/A 15372292SN/A // Have the instruction queue try to schedule any ready instructions. 15382292SN/A // (In actuality, this scheduling is for instructions that will 15392292SN/A // be executed next cycle.) 15402292SN/A instQueue.scheduleReadyInsts(); 15412292SN/A 15422292SN/A // Also should advance its own time buffers if the stage ran. 15432292SN/A // Not the best place for it, but this works (hopefully). 15442292SN/A issueToExecQueue.advance(); 15452292SN/A } 15462292SN/A 15472292SN/A bool broadcast_free_entries = false; 15482292SN/A 15492292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15502292SN/A exeStatus = Idle; 15512292SN/A updateLSQNextCycle = false; 15522292SN/A 15532292SN/A broadcast_free_entries = true; 15542292SN/A } 15552292SN/A 15562292SN/A // Writeback any stores using any leftover bandwidth. 15571681SN/A ldstQueue.writebackStores(); 15581681SN/A 15591061SN/A // Check the committed load/store signals to see if there's a load 15601061SN/A // or store to commit. Also check if it's being told to execute a 15611061SN/A // nonspeculative instruction. 15621681SN/A // This is pretty inefficient... 15632292SN/A 15643867Sbinkertn@umich.edu threads = activeThreads->begin(); 15653867Sbinkertn@umich.edu while (threads != end) { 15666221Snate@binkert.org ThreadID tid = (*threads++); 15672292SN/A 15682292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15692292SN/A 15702348SN/A // Update structures based on instructions committed. 15712292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15722292SN/A !fromCommit->commitInfo[tid].squash && 15732292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15742292SN/A 15752292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15762292SN/A 15772292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15782292SN/A 15792292SN/A updateLSQNextCycle = true; 15802292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15812292SN/A } 15822292SN/A 15832292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15842292SN/A 15852292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 158610824SAndreas.Sandberg@ARM.com if (fromCommit->commitInfo[tid].strictlyOrdered) { 158710824SAndreas.Sandberg@ARM.com instQueue.replayMemInst( 158810824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad); 158910824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 15902292SN/A } else { 15912292SN/A instQueue.scheduleNonSpec( 15922292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15932292SN/A } 15942292SN/A } 15952292SN/A 15962292SN/A if (broadcast_free_entries) { 15972292SN/A toFetch->iewInfo[tid].iqCount = 15982292SN/A instQueue.getCount(tid); 15992292SN/A toFetch->iewInfo[tid].ldstqCount = 16002292SN/A ldstQueue.getCount(tid); 16012292SN/A 16022292SN/A toRename->iewInfo[tid].usedIQ = true; 16032292SN/A toRename->iewInfo[tid].freeIQEntries = 160410164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 16052292SN/A toRename->iewInfo[tid].usedLSQ = true; 160610239Sbinhpham@cs.rutgers.edu 160710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = 160810239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(tid); 160910239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = 161010239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeStoreEntries(tid); 16112292SN/A 16122292SN/A wroteToTimeBuffer = true; 16132292SN/A } 16142292SN/A 16152292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 16162292SN/A tid, toRename->iewInfo[tid].dispatched); 16171061SN/A } 16181061SN/A 16192292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 162010239Sbinhpham@cs.rutgers.edu "LQ has %i free entries. SQ has %i free entries.\n", 16212292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 162210239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 16232292SN/A 16242292SN/A updateStatus(); 16252292SN/A 16262292SN/A if (wroteToTimeBuffer) { 16272292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16282292SN/A cpu->activityThisCycle(); 16291061SN/A } 16301060SN/A} 16311060SN/A 16322301SN/Atemplate <class Impl> 16331060SN/Avoid 163413429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 16351060SN/A{ 16366221Snate@binkert.org ThreadID tid = inst->threadNumber; 16371060SN/A 16382669Sktlim@umich.edu iewExecutedInsts++; 16391060SN/A 16408471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16419527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16429527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16439527SMatt.Horsnell@arm.com } 16448471SGiacomo.Gabrielli@arm.com#endif 16458471SGiacomo.Gabrielli@arm.com 16462301SN/A // 16472301SN/A // Control operations 16482301SN/A // 16492301SN/A if (inst->isControl()) 16506221Snate@binkert.org iewExecutedBranches[tid]++; 16511060SN/A 16522301SN/A // 16532301SN/A // Memory operations 16542301SN/A // 16552301SN/A if (inst->isMemRef()) { 16566221Snate@binkert.org iewExecutedRefs[tid]++; 16571060SN/A 16582301SN/A if (inst->isLoad()) { 16596221Snate@binkert.org iewExecLoadInsts[tid]++; 16601060SN/A } 16611060SN/A } 16621060SN/A} 16637598Sminkyu.jeong@arm.com 16647598Sminkyu.jeong@arm.comtemplate <class Impl> 16657598Sminkyu.jeong@arm.comvoid 166613429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 16677598Sminkyu.jeong@arm.com{ 16687598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16697598Sminkyu.jeong@arm.com 16707598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16717852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16727598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16737598Sminkyu.jeong@arm.com 16747598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16757598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16767598Sminkyu.jeong@arm.com 167713831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 167813831SAndrea.Mondelli@ucf.edu "Branch mispredict detected.\n", 167913831SAndrea.Mondelli@ucf.edu tid,inst->seqNum); 168013831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target " 168113831SAndrea.Mondelli@ucf.edu "was PC:%#x, NPC:%#x\n", 168213831SAndrea.Mondelli@ucf.edu tid,inst->seqNum, 16837720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 168413831SAndrea.Mondelli@ucf.edu DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: " 168513831SAndrea.Mondelli@ucf.edu "Redirecting fetch to PC: %#x, " 168613831SAndrea.Mondelli@ucf.edu "NPC: %#x.\n", 168713831SAndrea.Mondelli@ucf.edu tid,inst->seqNum, 168813831SAndrea.Mondelli@ucf.edu inst->nextInstAddr(), 16897720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16907598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16917598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16927598Sminkyu.jeong@arm.com 16937598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16947598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16957598Sminkyu.jeong@arm.com } else { 16967598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16977598Sminkyu.jeong@arm.com } 16987598Sminkyu.jeong@arm.com } 16997598Sminkyu.jeong@arm.com } 17007598Sminkyu.jeong@arm.com} 17019944Smatt.horsnell@ARM.com 17029944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1703