iew_impl.hh revision 13641
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2010-2013, 2018 ARM Limited 311308Santhony.gutierrez@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 411308Santhony.gutierrez@amd.com * All rights reserved. 511308Santhony.gutierrez@amd.com * 611308Santhony.gutierrez@amd.com * The license below extends only to copyright in the software and shall 711308Santhony.gutierrez@amd.com * not be construed as granting a license to any other intellectual 811308Santhony.gutierrez@amd.com * property including but not limited to intellectual property relating 911308Santhony.gutierrez@amd.com * to a hardware implementation of the functionality of the software 1011308Santhony.gutierrez@amd.com * licensed hereunder. You may use the software subject to the license 1111308Santhony.gutierrez@amd.com * terms below provided that you ensure that this notice is replicated 1211308Santhony.gutierrez@amd.com * unmodified and in its entirety in all distributions of the software, 1311308Santhony.gutierrez@amd.com * modified or unmodified, in source code or in binary form. 1411308Santhony.gutierrez@amd.com * 1511308Santhony.gutierrez@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1611308Santhony.gutierrez@amd.com * All rights reserved. 1711308Santhony.gutierrez@amd.com * 1811308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 1911308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 2011308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 2111308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 2211308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 2311308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 2411308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 2511308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 2611308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 2711308Santhony.gutierrez@amd.com * this software without specific prior written permission. 2811308Santhony.gutierrez@amd.com * 2911308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011308Santhony.gutierrez@amd.com * 4111308Santhony.gutierrez@amd.com * Authors: Kevin Lim 4211308Santhony.gutierrez@amd.com */ 4311308Santhony.gutierrez@amd.com 4411308Santhony.gutierrez@amd.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 4511308Santhony.gutierrez@amd.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.com// @todo: Fix the instantaneous communication among all the stages within 4811308Santhony.gutierrez@amd.com// iew. There's a clear delay between issue and execute, yet backwards 4911308Santhony.gutierrez@amd.com// communication happens simultaneously. 5011308Santhony.gutierrez@amd.com 5111308Santhony.gutierrez@amd.com#include <queue> 5211308Santhony.gutierrez@amd.com 5311308Santhony.gutierrez@amd.com#include "arch/utility.hh" 5411308Santhony.gutierrez@amd.com#include "config/the_isa.hh" 5511308Santhony.gutierrez@amd.com#include "cpu/checker/cpu.hh" 5611308Santhony.gutierrez@amd.com#include "cpu/o3/fu_pool.hh" 5711308Santhony.gutierrez@amd.com#include "cpu/o3/iew.hh" 5811308Santhony.gutierrez@amd.com#include "cpu/timebuf.hh" 5911308Santhony.gutierrez@amd.com#include "debug/Activity.hh" 6011308Santhony.gutierrez@amd.com#include "debug/Drain.hh" 6111308Santhony.gutierrez@amd.com#include "debug/IEW.hh" 6211308Santhony.gutierrez@amd.com#include "debug/O3PipeView.hh" 6311308Santhony.gutierrez@amd.com#include "params/DerivO3CPU.hh" 6411308Santhony.gutierrez@amd.com 6511308Santhony.gutierrez@amd.comusing namespace std; 6611308Santhony.gutierrez@amd.com 6711308Santhony.gutierrez@amd.comtemplate<class Impl> 6811308Santhony.gutierrez@amd.comDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 6911308Santhony.gutierrez@amd.com : issueToExecQueue(params->backComSize, params->forwardComSize), 7011308Santhony.gutierrez@amd.com cpu(_cpu), 7111308Santhony.gutierrez@amd.com instQueue(_cpu, this, params), 7211308Santhony.gutierrez@amd.com ldstQueue(_cpu, this, params), 7311308Santhony.gutierrez@amd.com fuPool(params->fuPool), 7411308Santhony.gutierrez@amd.com commitToIEWDelay(params->commitToIEWDelay), 7511308Santhony.gutierrez@amd.com renameToIEWDelay(params->renameToIEWDelay), 7611308Santhony.gutierrez@amd.com issueToExecuteDelay(params->issueToExecuteDelay), 7711308Santhony.gutierrez@amd.com dispatchWidth(params->dispatchWidth), 7811308Santhony.gutierrez@amd.com issueWidth(params->issueWidth), 7911308Santhony.gutierrez@amd.com wbNumInst(0), 8011308Santhony.gutierrez@amd.com wbCycle(0), 8111308Santhony.gutierrez@amd.com wbWidth(params->wbWidth), 8211308Santhony.gutierrez@amd.com numThreads(params->numThreads) 8311308Santhony.gutierrez@amd.com{ 8411308Santhony.gutierrez@amd.com if (dispatchWidth > Impl::MaxWidth) 8511308Santhony.gutierrez@amd.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8611308Santhony.gutierrez@amd.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8711308Santhony.gutierrez@amd.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8811308Santhony.gutierrez@amd.com if (issueWidth > Impl::MaxWidth) 8911308Santhony.gutierrez@amd.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 9011308Santhony.gutierrez@amd.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9111308Santhony.gutierrez@amd.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9211308Santhony.gutierrez@amd.com if (wbWidth > Impl::MaxWidth) 9311308Santhony.gutierrez@amd.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9411308Santhony.gutierrez@amd.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9511308Santhony.gutierrez@amd.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9611308Santhony.gutierrez@amd.com 9711308Santhony.gutierrez@amd.com _status = Active; 9811308Santhony.gutierrez@amd.com exeStatus = Running; 9911308Santhony.gutierrez@amd.com wbStatus = Idle; 10011308Santhony.gutierrez@amd.com 10111308Santhony.gutierrez@amd.com // Setup wire to read instructions coming from issue. 10211308Santhony.gutierrez@amd.com fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 10311308Santhony.gutierrez@amd.com 10411308Santhony.gutierrez@amd.com // Instruction queue needs the queue between issue and execute. 10511308Santhony.gutierrez@amd.com instQueue.setIssueToExecuteQueue(&issueToExecQueue); 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 10811308Santhony.gutierrez@amd.com dispatchStatus[tid] = Running; 10911308Santhony.gutierrez@amd.com fetchRedirect[tid] = false; 11011308Santhony.gutierrez@amd.com } 11111308Santhony.gutierrez@amd.com 11211308Santhony.gutierrez@amd.com updateLSQNextCycle = false; 11311308Santhony.gutierrez@amd.com 11411308Santhony.gutierrez@amd.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 11511308Santhony.gutierrez@amd.com} 11611308Santhony.gutierrez@amd.com 11711308Santhony.gutierrez@amd.comtemplate <class Impl> 11811308Santhony.gutierrez@amd.comstd::string 11911308Santhony.gutierrez@amd.comDefaultIEW<Impl>::name() const 12011308Santhony.gutierrez@amd.com{ 12111308Santhony.gutierrez@amd.com return cpu->name() + ".iew"; 12211308Santhony.gutierrez@amd.com} 12311308Santhony.gutierrez@amd.com 12411308Santhony.gutierrez@amd.comtemplate <class Impl> 12511308Santhony.gutierrez@amd.comvoid 12611308Santhony.gutierrez@amd.comDefaultIEW<Impl>::regProbePoints() 12711308Santhony.gutierrez@amd.com{ 12811308Santhony.gutierrez@amd.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12911308Santhony.gutierrez@amd.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13011308Santhony.gutierrez@amd.com /** 13111308Santhony.gutierrez@amd.com * Probe point with dynamic instruction as the argument used to probe when 13211308Santhony.gutierrez@amd.com * an instruction starts to execute. 13311308Santhony.gutierrez@amd.com */ 13411308Santhony.gutierrez@amd.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13511308Santhony.gutierrez@amd.com "Execute"); 13611308Santhony.gutierrez@amd.com /** 13711308Santhony.gutierrez@amd.com * Probe point with dynamic instruction as the argument used to probe when 13811308Santhony.gutierrez@amd.com * an instruction execution completes and it is marked ready to commit. 13911308Santhony.gutierrez@amd.com */ 14011308Santhony.gutierrez@amd.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 14111308Santhony.gutierrez@amd.com "ToCommit"); 14211308Santhony.gutierrez@amd.com} 14311308Santhony.gutierrez@amd.com 14411308Santhony.gutierrez@amd.comtemplate <class Impl> 14511308Santhony.gutierrez@amd.comvoid 14611308Santhony.gutierrez@amd.comDefaultIEW<Impl>::regStats() 14711308Santhony.gutierrez@amd.com{ 14811308Santhony.gutierrez@amd.com using namespace Stats; 14911308Santhony.gutierrez@amd.com 15011308Santhony.gutierrez@amd.com instQueue.regStats(); 15111308Santhony.gutierrez@amd.com ldstQueue.regStats(); 15211308Santhony.gutierrez@amd.com 15311308Santhony.gutierrez@amd.com iewIdleCycles 15411308Santhony.gutierrez@amd.com .name(name() + ".iewIdleCycles") 15511308Santhony.gutierrez@amd.com .desc("Number of cycles IEW is idle"); 15611308Santhony.gutierrez@amd.com 15711308Santhony.gutierrez@amd.com iewSquashCycles 15811308Santhony.gutierrez@amd.com .name(name() + ".iewSquashCycles") 15911308Santhony.gutierrez@amd.com .desc("Number of cycles IEW is squashing"); 16011308Santhony.gutierrez@amd.com 16111308Santhony.gutierrez@amd.com iewBlockCycles 16211308Santhony.gutierrez@amd.com .name(name() + ".iewBlockCycles") 16311308Santhony.gutierrez@amd.com .desc("Number of cycles IEW is blocking"); 16411308Santhony.gutierrez@amd.com 16511308Santhony.gutierrez@amd.com iewUnblockCycles 16611308Santhony.gutierrez@amd.com .name(name() + ".iewUnblockCycles") 16711308Santhony.gutierrez@amd.com .desc("Number of cycles IEW is unblocking"); 16811308Santhony.gutierrez@amd.com 16911308Santhony.gutierrez@amd.com iewDispatchedInsts 17011308Santhony.gutierrez@amd.com .name(name() + ".iewDispatchedInsts") 17111308Santhony.gutierrez@amd.com .desc("Number of instructions dispatched to IQ"); 17211308Santhony.gutierrez@amd.com 17311308Santhony.gutierrez@amd.com iewDispSquashedInsts 17411308Santhony.gutierrez@amd.com .name(name() + ".iewDispSquashedInsts") 17511308Santhony.gutierrez@amd.com .desc("Number of squashed instructions skipped by dispatch"); 17611308Santhony.gutierrez@amd.com 17711308Santhony.gutierrez@amd.com iewDispLoadInsts 17811308Santhony.gutierrez@amd.com .name(name() + ".iewDispLoadInsts") 17911308Santhony.gutierrez@amd.com .desc("Number of dispatched load instructions"); 18011308Santhony.gutierrez@amd.com 18111308Santhony.gutierrez@amd.com iewDispStoreInsts 18211308Santhony.gutierrez@amd.com .name(name() + ".iewDispStoreInsts") 18311308Santhony.gutierrez@amd.com .desc("Number of dispatched store instructions"); 18411308Santhony.gutierrez@amd.com 18511308Santhony.gutierrez@amd.com iewDispNonSpecInsts 18611308Santhony.gutierrez@amd.com .name(name() + ".iewDispNonSpecInsts") 18711308Santhony.gutierrez@amd.com .desc("Number of dispatched non-speculative instructions"); 18811308Santhony.gutierrez@amd.com 18911308Santhony.gutierrez@amd.com iewIQFullEvents 19011308Santhony.gutierrez@amd.com .name(name() + ".iewIQFullEvents") 19111308Santhony.gutierrez@amd.com .desc("Number of times the IQ has become full, causing a stall"); 19211308Santhony.gutierrez@amd.com 19311308Santhony.gutierrez@amd.com iewLSQFullEvents 19411308Santhony.gutierrez@amd.com .name(name() + ".iewLSQFullEvents") 19511308Santhony.gutierrez@amd.com .desc("Number of times the LSQ has become full, causing a stall"); 19611308Santhony.gutierrez@amd.com 19711308Santhony.gutierrez@amd.com memOrderViolationEvents 19811308Santhony.gutierrez@amd.com .name(name() + ".memOrderViolationEvents") 19911308Santhony.gutierrez@amd.com .desc("Number of memory order violations"); 20011308Santhony.gutierrez@amd.com 20111308Santhony.gutierrez@amd.com predictedTakenIncorrect 20211308Santhony.gutierrez@amd.com .name(name() + ".predictedTakenIncorrect") 20311308Santhony.gutierrez@amd.com .desc("Number of branches that were predicted taken incorrectly"); 20411308Santhony.gutierrez@amd.com 20511308Santhony.gutierrez@amd.com predictedNotTakenIncorrect 20611308Santhony.gutierrez@amd.com .name(name() + ".predictedNotTakenIncorrect") 20711308Santhony.gutierrez@amd.com .desc("Number of branches that were predicted not taken incorrectly"); 20811308Santhony.gutierrez@amd.com 20911308Santhony.gutierrez@amd.com branchMispredicts 21011308Santhony.gutierrez@amd.com .name(name() + ".branchMispredicts") 21111308Santhony.gutierrez@amd.com .desc("Number of branch mispredicts detected at execute"); 21211308Santhony.gutierrez@amd.com 21311308Santhony.gutierrez@amd.com branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 21411308Santhony.gutierrez@amd.com 21511308Santhony.gutierrez@amd.com iewExecutedInsts 21611308Santhony.gutierrez@amd.com .name(name() + ".iewExecutedInsts") 21711308Santhony.gutierrez@amd.com .desc("Number of executed instructions"); 21811308Santhony.gutierrez@amd.com 21911308Santhony.gutierrez@amd.com iewExecLoadInsts 22011308Santhony.gutierrez@amd.com .init(cpu->numThreads) 22111308Santhony.gutierrez@amd.com .name(name() + ".iewExecLoadInsts") 22211308Santhony.gutierrez@amd.com .desc("Number of load instructions executed") 22311308Santhony.gutierrez@amd.com .flags(total); 22411308Santhony.gutierrez@amd.com 22511308Santhony.gutierrez@amd.com iewExecSquashedInsts 22611308Santhony.gutierrez@amd.com .name(name() + ".iewExecSquashedInsts") 22711308Santhony.gutierrez@amd.com .desc("Number of squashed instructions skipped in execute"); 22811308Santhony.gutierrez@amd.com 22911308Santhony.gutierrez@amd.com iewExecutedSwp 23011308Santhony.gutierrez@amd.com .init(cpu->numThreads) 23111308Santhony.gutierrez@amd.com .name(name() + ".exec_swp") 23211308Santhony.gutierrez@amd.com .desc("number of swp insts executed") 23311308Santhony.gutierrez@amd.com .flags(total); 23411308Santhony.gutierrez@amd.com 23511308Santhony.gutierrez@amd.com iewExecutedNop 23611308Santhony.gutierrez@amd.com .init(cpu->numThreads) 23711308Santhony.gutierrez@amd.com .name(name() + ".exec_nop") 23811308Santhony.gutierrez@amd.com .desc("number of nop insts executed") 23911308Santhony.gutierrez@amd.com .flags(total); 24011308Santhony.gutierrez@amd.com 24111308Santhony.gutierrez@amd.com iewExecutedRefs 24211308Santhony.gutierrez@amd.com .init(cpu->numThreads) 24311308Santhony.gutierrez@amd.com .name(name() + ".exec_refs") 24411308Santhony.gutierrez@amd.com .desc("number of memory reference insts executed") 24511308Santhony.gutierrez@amd.com .flags(total); 24611308Santhony.gutierrez@amd.com 24711308Santhony.gutierrez@amd.com iewExecutedBranches 24811308Santhony.gutierrez@amd.com .init(cpu->numThreads) 24911308Santhony.gutierrez@amd.com .name(name() + ".exec_branches") 25011308Santhony.gutierrez@amd.com .desc("Number of branches executed") 25111308Santhony.gutierrez@amd.com .flags(total); 25211308Santhony.gutierrez@amd.com 25311308Santhony.gutierrez@amd.com iewExecStoreInsts 25411308Santhony.gutierrez@amd.com .name(name() + ".exec_stores") 25511308Santhony.gutierrez@amd.com .desc("Number of stores executed") 25611308Santhony.gutierrez@amd.com .flags(total); 25711308Santhony.gutierrez@amd.com iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 25811308Santhony.gutierrez@amd.com 25911308Santhony.gutierrez@amd.com iewExecRate 26011308Santhony.gutierrez@amd.com .name(name() + ".exec_rate") 26111308Santhony.gutierrez@amd.com .desc("Inst execution rate") 26211308Santhony.gutierrez@amd.com .flags(total); 26311308Santhony.gutierrez@amd.com 26411308Santhony.gutierrez@amd.com iewExecRate = iewExecutedInsts / cpu->numCycles; 26511308Santhony.gutierrez@amd.com 26611308Santhony.gutierrez@amd.com iewInstsToCommit 26711308Santhony.gutierrez@amd.com .init(cpu->numThreads) 26811308Santhony.gutierrez@amd.com .name(name() + ".wb_sent") 26911308Santhony.gutierrez@amd.com .desc("cumulative count of insts sent to commit") 27011308Santhony.gutierrez@amd.com .flags(total); 27111308Santhony.gutierrez@amd.com 27211308Santhony.gutierrez@amd.com writebackCount 27311308Santhony.gutierrez@amd.com .init(cpu->numThreads) 27411308Santhony.gutierrez@amd.com .name(name() + ".wb_count") 27511308Santhony.gutierrez@amd.com .desc("cumulative count of insts written-back") 27611308Santhony.gutierrez@amd.com .flags(total); 27711308Santhony.gutierrez@amd.com 27811308Santhony.gutierrez@amd.com producerInst 27911308Santhony.gutierrez@amd.com .init(cpu->numThreads) 28011308Santhony.gutierrez@amd.com .name(name() + ".wb_producers") 28111308Santhony.gutierrez@amd.com .desc("num instructions producing a value") 28211308Santhony.gutierrez@amd.com .flags(total); 28311308Santhony.gutierrez@amd.com 28411308Santhony.gutierrez@amd.com consumerInst 28511308Santhony.gutierrez@amd.com .init(cpu->numThreads) 28611308Santhony.gutierrez@amd.com .name(name() + ".wb_consumers") 28711308Santhony.gutierrez@amd.com .desc("num instructions consuming a value") 28811308Santhony.gutierrez@amd.com .flags(total); 28911308Santhony.gutierrez@amd.com 29011308Santhony.gutierrez@amd.com wbFanout 29111308Santhony.gutierrez@amd.com .name(name() + ".wb_fanout") 29211308Santhony.gutierrez@amd.com .desc("average fanout of values written-back") 29311308Santhony.gutierrez@amd.com .flags(total); 29411308Santhony.gutierrez@amd.com 29511308Santhony.gutierrez@amd.com wbFanout = producerInst / consumerInst; 29611308Santhony.gutierrez@amd.com 29711308Santhony.gutierrez@amd.com wbRate 29811308Santhony.gutierrez@amd.com .name(name() + ".wb_rate") 29911308Santhony.gutierrez@amd.com .desc("insts written-back per cycle") 30011308Santhony.gutierrez@amd.com .flags(total); 30111308Santhony.gutierrez@amd.com wbRate = writebackCount / cpu->numCycles; 30211308Santhony.gutierrez@amd.com} 30311308Santhony.gutierrez@amd.com 30411308Santhony.gutierrez@amd.comtemplate<class Impl> 30511308Santhony.gutierrez@amd.comvoid 30611308Santhony.gutierrez@amd.comDefaultIEW<Impl>::startupStage() 30711308Santhony.gutierrez@amd.com{ 30811308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 30911308Santhony.gutierrez@amd.com toRename->iewInfo[tid].usedIQ = true; 31011308Santhony.gutierrez@amd.com toRename->iewInfo[tid].freeIQEntries = 31111308Santhony.gutierrez@amd.com instQueue.numFreeEntries(tid); 31211308Santhony.gutierrez@amd.com 31311308Santhony.gutierrez@amd.com toRename->iewInfo[tid].usedLSQ = true; 31411308Santhony.gutierrez@amd.com toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 31511308Santhony.gutierrez@amd.com toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 31611308Santhony.gutierrez@amd.com } 31711308Santhony.gutierrez@amd.com 31811308Santhony.gutierrez@amd.com // Initialize the checker's dcache port here 31911308Santhony.gutierrez@amd.com if (cpu->checker) { 32011308Santhony.gutierrez@amd.com cpu->checker->setDcachePort(&cpu->getDataPort()); 32111308Santhony.gutierrez@amd.com } 32211308Santhony.gutierrez@amd.com 32311308Santhony.gutierrez@amd.com cpu->activateStage(O3CPU::IEWIdx); 32411308Santhony.gutierrez@amd.com} 32511308Santhony.gutierrez@amd.com 32611308Santhony.gutierrez@amd.comtemplate<class Impl> 327void 328DefaultIEW<Impl>::clearStates(ThreadID tid) 329{ 330 toRename->iewInfo[tid].usedIQ = true; 331 toRename->iewInfo[tid].freeIQEntries = 332 instQueue.numFreeEntries(tid); 333 334 toRename->iewInfo[tid].usedLSQ = true; 335 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 336 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 337} 338 339template<class Impl> 340void 341DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 342{ 343 timeBuffer = tb_ptr; 344 345 // Setup wire to read information from time buffer, from commit. 346 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 347 348 // Setup wire to write information back to previous stages. 349 toRename = timeBuffer->getWire(0); 350 351 toFetch = timeBuffer->getWire(0); 352 353 // Instruction queue also needs main time buffer. 354 instQueue.setTimeBuffer(tb_ptr); 355} 356 357template<class Impl> 358void 359DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 360{ 361 renameQueue = rq_ptr; 362 363 // Setup wire to read information from rename queue. 364 fromRename = renameQueue->getWire(-renameToIEWDelay); 365} 366 367template<class Impl> 368void 369DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 370{ 371 iewQueue = iq_ptr; 372 373 // Setup wire to write instructions to commit. 374 toCommit = iewQueue->getWire(0); 375} 376 377template<class Impl> 378void 379DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 380{ 381 activeThreads = at_ptr; 382 383 ldstQueue.setActiveThreads(at_ptr); 384 instQueue.setActiveThreads(at_ptr); 385} 386 387template<class Impl> 388void 389DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 390{ 391 scoreboard = sb_ptr; 392} 393 394template <class Impl> 395bool 396DefaultIEW<Impl>::isDrained() const 397{ 398 bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 399 400 for (ThreadID tid = 0; tid < numThreads; tid++) { 401 if (!insts[tid].empty()) { 402 DPRINTF(Drain, "%i: Insts not empty.\n", tid); 403 drained = false; 404 } 405 if (!skidBuffer[tid].empty()) { 406 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 407 drained = false; 408 } 409 drained = drained && dispatchStatus[tid] == Running; 410 } 411 412 // Also check the FU pool as instructions are "stored" in FU 413 // completion events until they are done and not accounted for 414 // above 415 if (drained && !fuPool->isDrained()) { 416 DPRINTF(Drain, "FU pool still busy.\n"); 417 drained = false; 418 } 419 420 return drained; 421} 422 423template <class Impl> 424void 425DefaultIEW<Impl>::drainSanityCheck() const 426{ 427 assert(isDrained()); 428 429 instQueue.drainSanityCheck(); 430 ldstQueue.drainSanityCheck(); 431} 432 433template <class Impl> 434void 435DefaultIEW<Impl>::takeOverFrom() 436{ 437 // Reset all state. 438 _status = Active; 439 exeStatus = Running; 440 wbStatus = Idle; 441 442 instQueue.takeOverFrom(); 443 ldstQueue.takeOverFrom(); 444 fuPool->takeOverFrom(); 445 446 startupStage(); 447 cpu->activityThisCycle(); 448 449 for (ThreadID tid = 0; tid < numThreads; tid++) { 450 dispatchStatus[tid] = Running; 451 fetchRedirect[tid] = false; 452 } 453 454 updateLSQNextCycle = false; 455 456 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 457 issueToExecQueue.advance(); 458 } 459} 460 461template<class Impl> 462void 463DefaultIEW<Impl>::squash(ThreadID tid) 464{ 465 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 466 467 // Tell the IQ to start squashing. 468 instQueue.squash(tid); 469 470 // Tell the LDSTQ to start squashing. 471 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 472 updatedQueues = true; 473 474 // Clear the skid buffer in case it has any data in it. 475 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 476 tid, fromCommit->commitInfo[tid].doneSeqNum); 477 478 while (!skidBuffer[tid].empty()) { 479 if (skidBuffer[tid].front()->isLoad()) { 480 toRename->iewInfo[tid].dispatchedToLQ++; 481 } 482 if (skidBuffer[tid].front()->isStore()) { 483 toRename->iewInfo[tid].dispatchedToSQ++; 484 } 485 486 toRename->iewInfo[tid].dispatched++; 487 488 skidBuffer[tid].pop(); 489 } 490 491 emptyRenameInsts(tid); 492} 493 494template<class Impl> 495void 496DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 497{ 498 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 499 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 500 501 if (!toCommit->squash[tid] || 502 inst->seqNum < toCommit->squashedSeqNum[tid]) { 503 toCommit->squash[tid] = true; 504 toCommit->squashedSeqNum[tid] = inst->seqNum; 505 toCommit->branchTaken[tid] = inst->pcState().branching(); 506 507 TheISA::PCState pc = inst->pcState(); 508 TheISA::advancePC(pc, inst->staticInst); 509 510 toCommit->pc[tid] = pc; 511 toCommit->mispredictInst[tid] = inst; 512 toCommit->includeSquashInst[tid] = false; 513 514 wroteToTimeBuffer = true; 515 } 516 517} 518 519template<class Impl> 520void 521DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 522{ 523 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 524 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 525 // Need to include inst->seqNum in the following comparison to cover the 526 // corner case when a branch misprediction and a memory violation for the 527 // same instruction (e.g. load PC) are detected in the same cycle. In this 528 // case the memory violator should take precedence over the branch 529 // misprediction because it requires the violator itself to be included in 530 // the squash. 531 if (!toCommit->squash[tid] || 532 inst->seqNum <= toCommit->squashedSeqNum[tid]) { 533 toCommit->squash[tid] = true; 534 535 toCommit->squashedSeqNum[tid] = inst->seqNum; 536 toCommit->pc[tid] = inst->pcState(); 537 toCommit->mispredictInst[tid] = NULL; 538 539 // Must include the memory violator in the squash. 540 toCommit->includeSquashInst[tid] = true; 541 542 wroteToTimeBuffer = true; 543 } 544} 545 546template<class Impl> 547void 548DefaultIEW<Impl>::block(ThreadID tid) 549{ 550 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 551 552 if (dispatchStatus[tid] != Blocked && 553 dispatchStatus[tid] != Unblocking) { 554 toRename->iewBlock[tid] = true; 555 wroteToTimeBuffer = true; 556 } 557 558 // Add the current inputs to the skid buffer so they can be 559 // reprocessed when this stage unblocks. 560 skidInsert(tid); 561 562 dispatchStatus[tid] = Blocked; 563} 564 565template<class Impl> 566void 567DefaultIEW<Impl>::unblock(ThreadID tid) 568{ 569 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 570 "buffer %u.\n",tid, tid); 571 572 // If the skid bufffer is empty, signal back to previous stages to unblock. 573 // Also switch status to running. 574 if (skidBuffer[tid].empty()) { 575 toRename->iewUnblock[tid] = true; 576 wroteToTimeBuffer = true; 577 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 578 dispatchStatus[tid] = Running; 579 } 580} 581 582template<class Impl> 583void 584DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 585{ 586 instQueue.wakeDependents(inst); 587} 588 589template<class Impl> 590void 591DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 592{ 593 instQueue.rescheduleMemInst(inst); 594} 595 596template<class Impl> 597void 598DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 599{ 600 instQueue.replayMemInst(inst); 601} 602 603template<class Impl> 604void 605DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 606{ 607 instQueue.blockMemInst(inst); 608} 609 610template<class Impl> 611void 612DefaultIEW<Impl>::cacheUnblocked() 613{ 614 instQueue.cacheUnblocked(); 615} 616 617template<class Impl> 618void 619DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 620{ 621 // This function should not be called after writebackInsts in a 622 // single cycle. That will cause problems with an instruction 623 // being added to the queue to commit without being processed by 624 // writebackInsts prior to being sent to commit. 625 626 // First check the time slot that this instruction will write 627 // to. If there are free write ports at the time, then go ahead 628 // and write the instruction to that time. If there are not, 629 // keep looking back to see where's the first time there's a 630 // free slot. 631 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 632 ++wbNumInst; 633 if (wbNumInst == wbWidth) { 634 ++wbCycle; 635 wbNumInst = 0; 636 } 637 } 638 639 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 640 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 641 // Add finished instruction to queue to commit. 642 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 643 (*iewQueue)[wbCycle].size++; 644} 645 646template <class Impl> 647unsigned 648DefaultIEW<Impl>::validInstsFromRename() 649{ 650 unsigned inst_count = 0; 651 652 for (int i=0; i<fromRename->size; i++) { 653 if (!fromRename->insts[i]->isSquashed()) 654 inst_count++; 655 } 656 657 return inst_count; 658} 659 660template<class Impl> 661void 662DefaultIEW<Impl>::skidInsert(ThreadID tid) 663{ 664 DynInstPtr inst = NULL; 665 666 while (!insts[tid].empty()) { 667 inst = insts[tid].front(); 668 669 insts[tid].pop(); 670 671 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 672 "dispatch skidBuffer %i\n",tid, inst->seqNum, 673 inst->pcState(),tid); 674 675 skidBuffer[tid].push(inst); 676 } 677 678 assert(skidBuffer[tid].size() <= skidBufferMax && 679 "Skidbuffer Exceeded Max Size"); 680} 681 682template<class Impl> 683int 684DefaultIEW<Impl>::skidCount() 685{ 686 int max=0; 687 688 list<ThreadID>::iterator threads = activeThreads->begin(); 689 list<ThreadID>::iterator end = activeThreads->end(); 690 691 while (threads != end) { 692 ThreadID tid = *threads++; 693 unsigned thread_count = skidBuffer[tid].size(); 694 if (max < thread_count) 695 max = thread_count; 696 } 697 698 return max; 699} 700 701template<class Impl> 702bool 703DefaultIEW<Impl>::skidsEmpty() 704{ 705 list<ThreadID>::iterator threads = activeThreads->begin(); 706 list<ThreadID>::iterator end = activeThreads->end(); 707 708 while (threads != end) { 709 ThreadID tid = *threads++; 710 711 if (!skidBuffer[tid].empty()) 712 return false; 713 } 714 715 return true; 716} 717 718template <class Impl> 719void 720DefaultIEW<Impl>::updateStatus() 721{ 722 bool any_unblocking = false; 723 724 list<ThreadID>::iterator threads = activeThreads->begin(); 725 list<ThreadID>::iterator end = activeThreads->end(); 726 727 while (threads != end) { 728 ThreadID tid = *threads++; 729 730 if (dispatchStatus[tid] == Unblocking) { 731 any_unblocking = true; 732 break; 733 } 734 } 735 736 // If there are no ready instructions waiting to be scheduled by the IQ, 737 // and there's no stores waiting to write back, and dispatch is not 738 // unblocking, then there is no internal activity for the IEW stage. 739 instQueue.intInstQueueReads++; 740 if (_status == Active && !instQueue.hasReadyInsts() && 741 !ldstQueue.willWB() && !any_unblocking) { 742 DPRINTF(IEW, "IEW switching to idle\n"); 743 744 deactivateStage(); 745 746 _status = Inactive; 747 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 748 ldstQueue.willWB() || 749 any_unblocking)) { 750 // Otherwise there is internal activity. Set to active. 751 DPRINTF(IEW, "IEW switching to active\n"); 752 753 activateStage(); 754 755 _status = Active; 756 } 757} 758 759template <class Impl> 760bool 761DefaultIEW<Impl>::checkStall(ThreadID tid) 762{ 763 bool ret_val(false); 764 765 if (fromCommit->commitInfo[tid].robSquashing) { 766 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 767 ret_val = true; 768 } else if (instQueue.isFull(tid)) { 769 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 770 ret_val = true; 771 } 772 773 return ret_val; 774} 775 776template <class Impl> 777void 778DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 779{ 780 // Check if there's a squash signal, squash if there is 781 // Check stall signals, block if there is. 782 // If status was Blocked 783 // if so then go to unblocking 784 // If status was Squashing 785 // check if squashing is not high. Switch to running this cycle. 786 787 if (fromCommit->commitInfo[tid].squash) { 788 squash(tid); 789 790 if (dispatchStatus[tid] == Blocked || 791 dispatchStatus[tid] == Unblocking) { 792 toRename->iewUnblock[tid] = true; 793 wroteToTimeBuffer = true; 794 } 795 796 dispatchStatus[tid] = Squashing; 797 fetchRedirect[tid] = false; 798 return; 799 } 800 801 if (fromCommit->commitInfo[tid].robSquashing) { 802 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 803 804 dispatchStatus[tid] = Squashing; 805 emptyRenameInsts(tid); 806 wroteToTimeBuffer = true; 807 } 808 809 if (checkStall(tid)) { 810 block(tid); 811 dispatchStatus[tid] = Blocked; 812 return; 813 } 814 815 if (dispatchStatus[tid] == Blocked) { 816 // Status from previous cycle was blocked, but there are no more stall 817 // conditions. Switch over to unblocking. 818 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 819 tid); 820 821 dispatchStatus[tid] = Unblocking; 822 823 unblock(tid); 824 825 return; 826 } 827 828 if (dispatchStatus[tid] == Squashing) { 829 // Switch status to running if rename isn't being told to block or 830 // squash this cycle. 831 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 832 tid); 833 834 dispatchStatus[tid] = Running; 835 836 return; 837 } 838} 839 840template <class Impl> 841void 842DefaultIEW<Impl>::sortInsts() 843{ 844 int insts_from_rename = fromRename->size; 845#ifdef DEBUG 846 for (ThreadID tid = 0; tid < numThreads; tid++) 847 assert(insts[tid].empty()); 848#endif 849 for (int i = 0; i < insts_from_rename; ++i) { 850 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 851 } 852} 853 854template <class Impl> 855void 856DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 857{ 858 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 859 860 while (!insts[tid].empty()) { 861 862 if (insts[tid].front()->isLoad()) { 863 toRename->iewInfo[tid].dispatchedToLQ++; 864 } 865 if (insts[tid].front()->isStore()) { 866 toRename->iewInfo[tid].dispatchedToSQ++; 867 } 868 869 toRename->iewInfo[tid].dispatched++; 870 871 insts[tid].pop(); 872 } 873} 874 875template <class Impl> 876void 877DefaultIEW<Impl>::wakeCPU() 878{ 879 cpu->wakeCPU(); 880} 881 882template <class Impl> 883void 884DefaultIEW<Impl>::activityThisCycle() 885{ 886 DPRINTF(Activity, "Activity this cycle.\n"); 887 cpu->activityThisCycle(); 888} 889 890template <class Impl> 891inline void 892DefaultIEW<Impl>::activateStage() 893{ 894 DPRINTF(Activity, "Activating stage.\n"); 895 cpu->activateStage(O3CPU::IEWIdx); 896} 897 898template <class Impl> 899inline void 900DefaultIEW<Impl>::deactivateStage() 901{ 902 DPRINTF(Activity, "Deactivating stage.\n"); 903 cpu->deactivateStage(O3CPU::IEWIdx); 904} 905 906template<class Impl> 907void 908DefaultIEW<Impl>::dispatch(ThreadID tid) 909{ 910 // If status is Running or idle, 911 // call dispatchInsts() 912 // If status is Unblocking, 913 // buffer any instructions coming from rename 914 // continue trying to empty skid buffer 915 // check if stall conditions have passed 916 917 if (dispatchStatus[tid] == Blocked) { 918 ++iewBlockCycles; 919 920 } else if (dispatchStatus[tid] == Squashing) { 921 ++iewSquashCycles; 922 } 923 924 // Dispatch should try to dispatch as many instructions as its bandwidth 925 // will allow, as long as it is not currently blocked. 926 if (dispatchStatus[tid] == Running || 927 dispatchStatus[tid] == Idle) { 928 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 929 "dispatch.\n", tid); 930 931 dispatchInsts(tid); 932 } else if (dispatchStatus[tid] == Unblocking) { 933 // Make sure that the skid buffer has something in it if the 934 // status is unblocking. 935 assert(!skidsEmpty()); 936 937 // If the status was unblocking, then instructions from the skid 938 // buffer were used. Remove those instructions and handle 939 // the rest of unblocking. 940 dispatchInsts(tid); 941 942 ++iewUnblockCycles; 943 944 if (validInstsFromRename()) { 945 // Add the current inputs to the skid buffer so they can be 946 // reprocessed when this stage unblocks. 947 skidInsert(tid); 948 } 949 950 unblock(tid); 951 } 952} 953 954template <class Impl> 955void 956DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 957{ 958 // Obtain instructions from skid buffer if unblocking, or queue from rename 959 // otherwise. 960 std::queue<DynInstPtr> &insts_to_dispatch = 961 dispatchStatus[tid] == Unblocking ? 962 skidBuffer[tid] : insts[tid]; 963 964 int insts_to_add = insts_to_dispatch.size(); 965 966 DynInstPtr inst; 967 bool add_to_iq = false; 968 int dis_num_inst = 0; 969 970 // Loop through the instructions, putting them in the instruction 971 // queue. 972 for ( ; dis_num_inst < insts_to_add && 973 dis_num_inst < dispatchWidth; 974 ++dis_num_inst) 975 { 976 inst = insts_to_dispatch.front(); 977 978 if (dispatchStatus[tid] == Unblocking) { 979 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 980 "buffer\n", tid); 981 } 982 983 // Make sure there's a valid instruction there. 984 assert(inst); 985 986 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 987 "IQ.\n", 988 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 989 990 // Be sure to mark these instructions as ready so that the 991 // commit stage can go ahead and execute them, and mark 992 // them as issued so the IQ doesn't reprocess them. 993 994 // Check for squashed instructions. 995 if (inst->isSquashed()) { 996 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 997 "not adding to IQ.\n", tid); 998 999 ++iewDispSquashedInsts; 1000 1001 insts_to_dispatch.pop(); 1002 1003 //Tell Rename That An Instruction has been processed 1004 if (inst->isLoad()) { 1005 toRename->iewInfo[tid].dispatchedToLQ++; 1006 } 1007 if (inst->isStore()) { 1008 toRename->iewInfo[tid].dispatchedToSQ++; 1009 } 1010 1011 toRename->iewInfo[tid].dispatched++; 1012 1013 continue; 1014 } 1015 1016 // Check for full conditions. 1017 if (instQueue.isFull(tid)) { 1018 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1019 1020 // Call function to start blocking. 1021 block(tid); 1022 1023 // Set unblock to false. Special case where we are using 1024 // skidbuffer (unblocking) instructions but then we still 1025 // get full in the IQ. 1026 toRename->iewUnblock[tid] = false; 1027 1028 ++iewIQFullEvents; 1029 break; 1030 } 1031 1032 // Check LSQ if inst is LD/ST 1033 if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 1034 (inst->isStore() && ldstQueue.sqFull(tid))) { 1035 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1036 inst->isLoad() ? "LQ" : "SQ"); 1037 1038 // Call function to start blocking. 1039 block(tid); 1040 1041 // Set unblock to false. Special case where we are using 1042 // skidbuffer (unblocking) instructions but then we still 1043 // get full in the IQ. 1044 toRename->iewUnblock[tid] = false; 1045 1046 ++iewLSQFullEvents; 1047 break; 1048 } 1049 1050 // Otherwise issue the instruction just fine. 1051 if (inst->isLoad()) { 1052 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1053 "encountered, adding to LSQ.\n", tid); 1054 1055 // Reserve a spot in the load store queue for this 1056 // memory access. 1057 ldstQueue.insertLoad(inst); 1058 1059 ++iewDispLoadInsts; 1060 1061 add_to_iq = true; 1062 1063 toRename->iewInfo[tid].dispatchedToLQ++; 1064 } else if (inst->isStore()) { 1065 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1066 "encountered, adding to LSQ.\n", tid); 1067 1068 ldstQueue.insertStore(inst); 1069 1070 ++iewDispStoreInsts; 1071 1072 if (inst->isStoreConditional()) { 1073 // Store conditionals need to be set as "canCommit()" 1074 // so that commit can process them when they reach the 1075 // head of commit. 1076 // @todo: This is somewhat specific to Alpha. 1077 inst->setCanCommit(); 1078 instQueue.insertNonSpec(inst); 1079 add_to_iq = false; 1080 1081 ++iewDispNonSpecInsts; 1082 } else { 1083 add_to_iq = true; 1084 } 1085 1086 toRename->iewInfo[tid].dispatchedToSQ++; 1087 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1088 // Same as non-speculative stores. 1089 inst->setCanCommit(); 1090 instQueue.insertBarrier(inst); 1091 add_to_iq = false; 1092 } else if (inst->isNop()) { 1093 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1094 "skipping.\n", tid); 1095 1096 inst->setIssued(); 1097 inst->setExecuted(); 1098 inst->setCanCommit(); 1099 1100 instQueue.recordProducer(inst); 1101 1102 iewExecutedNop[tid]++; 1103 1104 add_to_iq = false; 1105 } else { 1106 assert(!inst->isExecuted()); 1107 add_to_iq = true; 1108 } 1109 1110 if (add_to_iq && inst->isNonSpeculative()) { 1111 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1112 "encountered, skipping.\n", tid); 1113 1114 // Same as non-speculative stores. 1115 inst->setCanCommit(); 1116 1117 // Specifically insert it as nonspeculative. 1118 instQueue.insertNonSpec(inst); 1119 1120 ++iewDispNonSpecInsts; 1121 1122 add_to_iq = false; 1123 } 1124 1125 // If the instruction queue is not full, then add the 1126 // instruction. 1127 if (add_to_iq) { 1128 instQueue.insert(inst); 1129 } 1130 1131 insts_to_dispatch.pop(); 1132 1133 toRename->iewInfo[tid].dispatched++; 1134 1135 ++iewDispatchedInsts; 1136 1137#if TRACING_ON 1138 inst->dispatchTick = curTick() - inst->fetchTick; 1139#endif 1140 ppDispatch->notify(inst); 1141 } 1142 1143 if (!insts_to_dispatch.empty()) { 1144 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1145 block(tid); 1146 toRename->iewUnblock[tid] = false; 1147 } 1148 1149 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1150 dispatchStatus[tid] = Running; 1151 1152 updatedQueues = true; 1153 } 1154 1155 dis_num_inst = 0; 1156} 1157 1158template <class Impl> 1159void 1160DefaultIEW<Impl>::printAvailableInsts() 1161{ 1162 int inst = 0; 1163 1164 std::cout << "Available Instructions: "; 1165 1166 while (fromIssue->insts[inst]) { 1167 1168 if (inst%3==0) std::cout << "\n\t"; 1169 1170 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1171 << " TN: " << fromIssue->insts[inst]->threadNumber 1172 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1173 1174 inst++; 1175 1176 } 1177 1178 std::cout << "\n"; 1179} 1180 1181template <class Impl> 1182void 1183DefaultIEW<Impl>::executeInsts() 1184{ 1185 wbNumInst = 0; 1186 wbCycle = 0; 1187 1188 list<ThreadID>::iterator threads = activeThreads->begin(); 1189 list<ThreadID>::iterator end = activeThreads->end(); 1190 1191 while (threads != end) { 1192 ThreadID tid = *threads++; 1193 fetchRedirect[tid] = false; 1194 } 1195 1196 // Uncomment this if you want to see all available instructions. 1197 // @todo This doesn't actually work anymore, we should fix it. 1198// printAvailableInsts(); 1199 1200 // Execute/writeback any instructions that are available. 1201 int insts_to_execute = fromIssue->size; 1202 int inst_num = 0; 1203 for (; inst_num < insts_to_execute; 1204 ++inst_num) { 1205 1206 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1207 1208 DynInstPtr inst = instQueue.getInstToExecute(); 1209 1210 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1211 inst->pcState(), inst->threadNumber,inst->seqNum); 1212 1213 // Notify potential listeners that this instruction has started 1214 // executing 1215 ppExecute->notify(inst); 1216 1217 // Check if the instruction is squashed; if so then skip it 1218 if (inst->isSquashed()) { 1219 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 1220 " [sn:%i]\n", inst->pcState(), inst->threadNumber, 1221 inst->seqNum); 1222 1223 // Consider this instruction executed so that commit can go 1224 // ahead and retire the instruction. 1225 inst->setExecuted(); 1226 1227 // Not sure if I should set this here or just let commit try to 1228 // commit any squashed instructions. I like the latter a bit more. 1229 inst->setCanCommit(); 1230 1231 ++iewExecSquashedInsts; 1232 1233 continue; 1234 } 1235 1236 Fault fault = NoFault; 1237 1238 // Execute instruction. 1239 // Note that if the instruction faults, it will be handled 1240 // at the commit stage. 1241 if (inst->isMemRef()) { 1242 DPRINTF(IEW, "Execute: Calculating address for memory " 1243 "reference.\n"); 1244 1245 // Tell the LDSTQ to execute this instruction (if it is a load). 1246 if (inst->isLoad()) { 1247 // Loads will mark themselves as executed, and their writeback 1248 // event adds the instruction to the queue to commit 1249 fault = ldstQueue.executeLoad(inst); 1250 1251 if (inst->isTranslationDelayed() && 1252 fault == NoFault) { 1253 // A hw page table walk is currently going on; the 1254 // instruction must be deferred. 1255 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1256 "load.\n"); 1257 instQueue.deferMemInst(inst); 1258 continue; 1259 } 1260 1261 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1262 inst->fault = NoFault; 1263 } 1264 } else if (inst->isStore()) { 1265 fault = ldstQueue.executeStore(inst); 1266 1267 if (inst->isTranslationDelayed() && 1268 fault == NoFault) { 1269 // A hw page table walk is currently going on; the 1270 // instruction must be deferred. 1271 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1272 "store.\n"); 1273 instQueue.deferMemInst(inst); 1274 continue; 1275 } 1276 1277 // If the store had a fault then it may not have a mem req 1278 if (fault != NoFault || !inst->readPredicate() || 1279 !inst->isStoreConditional()) { 1280 // If the instruction faulted, then we need to send it along 1281 // to commit without the instruction completing. 1282 // Send this instruction to commit, also make sure iew stage 1283 // realizes there is activity. 1284 inst->setExecuted(); 1285 instToCommit(inst); 1286 activityThisCycle(); 1287 } 1288 1289 // Store conditionals will mark themselves as 1290 // executed, and their writeback event will add the 1291 // instruction to the queue to commit. 1292 } else { 1293 panic("Unexpected memory type!\n"); 1294 } 1295 1296 } else { 1297 // If the instruction has already faulted, then skip executing it. 1298 // Such case can happen when it faulted during ITLB translation. 1299 // If we execute the instruction (even if it's a nop) the fault 1300 // will be replaced and we will lose it. 1301 if (inst->getFault() == NoFault) { 1302 inst->execute(); 1303 if (!inst->readPredicate()) 1304 inst->forwardOldRegs(); 1305 } 1306 1307 inst->setExecuted(); 1308 1309 instToCommit(inst); 1310 } 1311 1312 updateExeInstStats(inst); 1313 1314 // Check if branch prediction was correct, if not then we need 1315 // to tell commit to squash in flight instructions. Only 1316 // handle this if there hasn't already been something that 1317 // redirects fetch in this group of instructions. 1318 1319 // This probably needs to prioritize the redirects if a different 1320 // scheduler is used. Currently the scheduler schedules the oldest 1321 // instruction first, so the branch resolution order will be correct. 1322 ThreadID tid = inst->threadNumber; 1323 1324 if (!fetchRedirect[tid] || 1325 !toCommit->squash[tid] || 1326 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1327 1328 // Prevent testing for misprediction on load instructions, 1329 // that have not been executed. 1330 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1331 1332 if (inst->mispredicted() && !loadNotExecuted) { 1333 fetchRedirect[tid] = true; 1334 1335 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1336 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1337 inst->readPredTarg()); 1338 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1339 inst->pcState()); 1340 // If incorrect, then signal the ROB that it must be squashed. 1341 squashDueToBranch(inst, tid); 1342 1343 ppMispredict->notify(inst); 1344 1345 if (inst->readPredTaken()) { 1346 predictedTakenIncorrect++; 1347 } else { 1348 predictedNotTakenIncorrect++; 1349 } 1350 } else if (ldstQueue.violation(tid)) { 1351 assert(inst->isMemRef()); 1352 // If there was an ordering violation, then get the 1353 // DynInst that caused the violation. Note that this 1354 // clears the violation signal. 1355 DynInstPtr violator; 1356 violator = ldstQueue.getMemDepViolator(tid); 1357 1358 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1359 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1360 violator->pcState(), violator->seqNum, 1361 inst->pcState(), inst->seqNum, inst->physEffAddr); 1362 1363 fetchRedirect[tid] = true; 1364 1365 // Tell the instruction queue that a violation has occured. 1366 instQueue.violation(inst, violator); 1367 1368 // Squash. 1369 squashDueToMemOrder(violator, tid); 1370 1371 ++memOrderViolationEvents; 1372 } 1373 } else { 1374 // Reset any state associated with redirects that will not 1375 // be used. 1376 if (ldstQueue.violation(tid)) { 1377 assert(inst->isMemRef()); 1378 1379 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1380 1381 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1382 "%s, inst PC: %s. Addr is: %#x.\n", 1383 violator->pcState(), inst->pcState(), 1384 inst->physEffAddr); 1385 DPRINTF(IEW, "Violation will not be handled because " 1386 "already squashing\n"); 1387 1388 ++memOrderViolationEvents; 1389 } 1390 } 1391 } 1392 1393 // Update and record activity if we processed any instructions. 1394 if (inst_num) { 1395 if (exeStatus == Idle) { 1396 exeStatus = Running; 1397 } 1398 1399 updatedQueues = true; 1400 1401 cpu->activityThisCycle(); 1402 } 1403 1404 // Need to reset this in case a writeback event needs to write into the 1405 // iew queue. That way the writeback event will write into the correct 1406 // spot in the queue. 1407 wbNumInst = 0; 1408 1409} 1410 1411template <class Impl> 1412void 1413DefaultIEW<Impl>::writebackInsts() 1414{ 1415 // Loop through the head of the time buffer and wake any 1416 // dependents. These instructions are about to write back. Also 1417 // mark scoreboard that this instruction is finally complete. 1418 // Either have IEW have direct access to scoreboard, or have this 1419 // as part of backwards communication. 1420 for (int inst_num = 0; inst_num < wbWidth && 1421 toCommit->insts[inst_num]; inst_num++) { 1422 DynInstPtr inst = toCommit->insts[inst_num]; 1423 ThreadID tid = inst->threadNumber; 1424 1425 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1426 inst->seqNum, inst->pcState()); 1427 1428 iewInstsToCommit[tid]++; 1429 // Notify potential listeners that execution is complete for this 1430 // instruction. 1431 ppToCommit->notify(inst); 1432 1433 // Some instructions will be sent to commit without having 1434 // executed because they need commit to handle them. 1435 // E.g. Strictly ordered loads have not actually executed when they 1436 // are first sent to commit. Instead commit must tell the LSQ 1437 // when it's ready to execute the strictly ordered load. 1438 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1439 int dependents = instQueue.wakeDependents(inst); 1440 1441 for (int i = 0; i < inst->numDestRegs(); i++) { 1442 //mark as Ready 1443 DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 1444 inst->renamedDestRegIdx(i)->index(), 1445 inst->renamedDestRegIdx(i)->className()); 1446 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1447 } 1448 1449 if (dependents) { 1450 producerInst[tid]++; 1451 consumerInst[tid]+= dependents; 1452 } 1453 writebackCount[tid]++; 1454 } 1455 } 1456} 1457 1458template<class Impl> 1459void 1460DefaultIEW<Impl>::tick() 1461{ 1462 wbNumInst = 0; 1463 wbCycle = 0; 1464 1465 wroteToTimeBuffer = false; 1466 updatedQueues = false; 1467 1468 ldstQueue.tick(); 1469 1470 sortInsts(); 1471 1472 // Free function units marked as being freed this cycle. 1473 fuPool->processFreeUnits(); 1474 1475 list<ThreadID>::iterator threads = activeThreads->begin(); 1476 list<ThreadID>::iterator end = activeThreads->end(); 1477 1478 // Check stall and squash signals, dispatch any instructions. 1479 while (threads != end) { 1480 ThreadID tid = *threads++; 1481 1482 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1483 1484 checkSignalsAndUpdate(tid); 1485 dispatch(tid); 1486 } 1487 1488 if (exeStatus != Squashing) { 1489 executeInsts(); 1490 1491 writebackInsts(); 1492 1493 // Have the instruction queue try to schedule any ready instructions. 1494 // (In actuality, this scheduling is for instructions that will 1495 // be executed next cycle.) 1496 instQueue.scheduleReadyInsts(); 1497 1498 // Also should advance its own time buffers if the stage ran. 1499 // Not the best place for it, but this works (hopefully). 1500 issueToExecQueue.advance(); 1501 } 1502 1503 bool broadcast_free_entries = false; 1504 1505 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1506 exeStatus = Idle; 1507 updateLSQNextCycle = false; 1508 1509 broadcast_free_entries = true; 1510 } 1511 1512 // Writeback any stores using any leftover bandwidth. 1513 ldstQueue.writebackStores(); 1514 1515 // Check the committed load/store signals to see if there's a load 1516 // or store to commit. Also check if it's being told to execute a 1517 // nonspeculative instruction. 1518 // This is pretty inefficient... 1519 1520 threads = activeThreads->begin(); 1521 while (threads != end) { 1522 ThreadID tid = (*threads++); 1523 1524 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1525 1526 // Update structures based on instructions committed. 1527 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1528 !fromCommit->commitInfo[tid].squash && 1529 !fromCommit->commitInfo[tid].robSquashing) { 1530 1531 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1532 1533 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1534 1535 updateLSQNextCycle = true; 1536 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1537 } 1538 1539 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1540 1541 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1542 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1543 instQueue.replayMemInst( 1544 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1545 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1546 } else { 1547 instQueue.scheduleNonSpec( 1548 fromCommit->commitInfo[tid].nonSpecSeqNum); 1549 } 1550 } 1551 1552 if (broadcast_free_entries) { 1553 toFetch->iewInfo[tid].iqCount = 1554 instQueue.getCount(tid); 1555 toFetch->iewInfo[tid].ldstqCount = 1556 ldstQueue.getCount(tid); 1557 1558 toRename->iewInfo[tid].usedIQ = true; 1559 toRename->iewInfo[tid].freeIQEntries = 1560 instQueue.numFreeEntries(tid); 1561 toRename->iewInfo[tid].usedLSQ = true; 1562 1563 toRename->iewInfo[tid].freeLQEntries = 1564 ldstQueue.numFreeLoadEntries(tid); 1565 toRename->iewInfo[tid].freeSQEntries = 1566 ldstQueue.numFreeStoreEntries(tid); 1567 1568 wroteToTimeBuffer = true; 1569 } 1570 1571 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1572 tid, toRename->iewInfo[tid].dispatched); 1573 } 1574 1575 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1576 "LQ has %i free entries. SQ has %i free entries.\n", 1577 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1578 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1579 1580 updateStatus(); 1581 1582 if (wroteToTimeBuffer) { 1583 DPRINTF(Activity, "Activity this cycle.\n"); 1584 cpu->activityThisCycle(); 1585 } 1586} 1587 1588template <class Impl> 1589void 1590DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 1591{ 1592 ThreadID tid = inst->threadNumber; 1593 1594 iewExecutedInsts++; 1595 1596#if TRACING_ON 1597 if (DTRACE(O3PipeView)) { 1598 inst->completeTick = curTick() - inst->fetchTick; 1599 } 1600#endif 1601 1602 // 1603 // Control operations 1604 // 1605 if (inst->isControl()) 1606 iewExecutedBranches[tid]++; 1607 1608 // 1609 // Memory operations 1610 // 1611 if (inst->isMemRef()) { 1612 iewExecutedRefs[tid]++; 1613 1614 if (inst->isLoad()) { 1615 iewExecLoadInsts[tid]++; 1616 } 1617 } 1618} 1619 1620template <class Impl> 1621void 1622DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 1623{ 1624 ThreadID tid = inst->threadNumber; 1625 1626 if (!fetchRedirect[tid] || 1627 !toCommit->squash[tid] || 1628 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1629 1630 if (inst->mispredicted()) { 1631 fetchRedirect[tid] = true; 1632 1633 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1634 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1635 inst->predInstAddr(), inst->predNextInstAddr()); 1636 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1637 " NPC: %#x.\n", inst->nextInstAddr(), 1638 inst->nextInstAddr()); 1639 // If incorrect, then signal the ROB that it must be squashed. 1640 squashDueToBranch(inst, tid); 1641 1642 if (inst->readPredTaken()) { 1643 predictedTakenIncorrect++; 1644 } else { 1645 predictedNotTakenIncorrect++; 1646 } 1647 } 1648 } 1649} 1650 1651#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1652