iew_impl.hh revision 13590
111828Sjason@lowepower.com/* 211482Sandreas.sandberg@arm.com * Copyright (c) 2010-2013, 2018 ARM Limited 311482Sandreas.sandberg@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 411482Sandreas.sandberg@arm.com * All rights reserved. 511482Sandreas.sandberg@arm.com * 611482Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 711482Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 811482Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 911482Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 1011482Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1111482Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1211482Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1311482Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1411482Sandreas.sandberg@arm.com * 1511482Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1611482Sandreas.sandberg@arm.com * All rights reserved. 1711482Sandreas.sandberg@arm.com * 1811482Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1911482Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 2011482Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2111482Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2211482Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2311482Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2411482Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2511482Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2611482Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2711482Sandreas.sandberg@arm.com * this software without specific prior written permission. 2811482Sandreas.sandberg@arm.com * 2911482Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011482Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111482Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211482Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311482Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411482Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511482Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611482Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711482Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811482Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911482Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011482Sandreas.sandberg@arm.com * 4111482Sandreas.sandberg@arm.com * Authors: Kevin Lim 4211482Sandreas.sandberg@arm.com */ 4311482Sandreas.sandberg@arm.com 4411482Sandreas.sandberg@arm.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 4511482Sandreas.sandberg@arm.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 4611482Sandreas.sandberg@arm.com 4711482Sandreas.sandberg@arm.com// @todo: Fix the instantaneous communication among all the stages within 4811482Sandreas.sandberg@arm.com// iew. There's a clear delay between issue and execute, yet backwards 4911482Sandreas.sandberg@arm.com// communication happens simultaneously. 5011482Sandreas.sandberg@arm.com 5111482Sandreas.sandberg@arm.com#include <queue> 5211482Sandreas.sandberg@arm.com 5311482Sandreas.sandberg@arm.com#include "arch/utility.hh" 5411482Sandreas.sandberg@arm.com#include "config/the_isa.hh" 5511482Sandreas.sandberg@arm.com#include "cpu/checker/cpu.hh" 5611482Sandreas.sandberg@arm.com#include "cpu/o3/fu_pool.hh" 5711482Sandreas.sandberg@arm.com#include "cpu/o3/iew.hh" 5811482Sandreas.sandberg@arm.com#include "cpu/timebuf.hh" 5911482Sandreas.sandberg@arm.com#include "debug/Activity.hh" 6011482Sandreas.sandberg@arm.com#include "debug/Drain.hh" 6111482Sandreas.sandberg@arm.com#include "debug/IEW.hh" 6211482Sandreas.sandberg@arm.com#include "debug/O3PipeView.hh" 6311482Sandreas.sandberg@arm.com#include "params/DerivO3CPU.hh" 6411482Sandreas.sandberg@arm.com 6511482Sandreas.sandberg@arm.comusing namespace std; 6611482Sandreas.sandberg@arm.com 6711482Sandreas.sandberg@arm.comtemplate<class Impl> 6811482Sandreas.sandberg@arm.comDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 6911482Sandreas.sandberg@arm.com : issueToExecQueue(params->backComSize, params->forwardComSize), 7011482Sandreas.sandberg@arm.com cpu(_cpu), 7111482Sandreas.sandberg@arm.com instQueue(_cpu, this, params), 7211482Sandreas.sandberg@arm.com ldstQueue(_cpu, this, params), 7311482Sandreas.sandberg@arm.com fuPool(params->fuPool), 7411482Sandreas.sandberg@arm.com commitToIEWDelay(params->commitToIEWDelay), 7511482Sandreas.sandberg@arm.com renameToIEWDelay(params->renameToIEWDelay), 7611482Sandreas.sandberg@arm.com issueToExecuteDelay(params->issueToExecuteDelay), 7711482Sandreas.sandberg@arm.com dispatchWidth(params->dispatchWidth), 7811482Sandreas.sandberg@arm.com issueWidth(params->issueWidth), 7911482Sandreas.sandberg@arm.com wbNumInst(0), 8011482Sandreas.sandberg@arm.com wbCycle(0), 8111482Sandreas.sandberg@arm.com wbWidth(params->wbWidth), 8211482Sandreas.sandberg@arm.com numThreads(params->numThreads) 8311482Sandreas.sandberg@arm.com{ 8411482Sandreas.sandberg@arm.com if (dispatchWidth > Impl::MaxWidth) 8511482Sandreas.sandberg@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8611482Sandreas.sandberg@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8711482Sandreas.sandberg@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8811482Sandreas.sandberg@arm.com if (issueWidth > Impl::MaxWidth) 8911482Sandreas.sandberg@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 9011482Sandreas.sandberg@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9111482Sandreas.sandberg@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9211482Sandreas.sandberg@arm.com if (wbWidth > Impl::MaxWidth) 9311482Sandreas.sandberg@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9411482Sandreas.sandberg@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9511482Sandreas.sandberg@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9611482Sandreas.sandberg@arm.com 9711482Sandreas.sandberg@arm.com _status = Active; 9811482Sandreas.sandberg@arm.com exeStatus = Running; 9911482Sandreas.sandberg@arm.com wbStatus = Idle; 10011482Sandreas.sandberg@arm.com 10111482Sandreas.sandberg@arm.com // Setup wire to read instructions coming from issue. 10211482Sandreas.sandberg@arm.com fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 10311482Sandreas.sandberg@arm.com 10411482Sandreas.sandberg@arm.com // Instruction queue needs the queue between issue and execute. 10511482Sandreas.sandberg@arm.com instQueue.setIssueToExecuteQueue(&issueToExecQueue); 10611482Sandreas.sandberg@arm.com 10711482Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 10811482Sandreas.sandberg@arm.com dispatchStatus[tid] = Running; 10911482Sandreas.sandberg@arm.com fetchRedirect[tid] = false; 11011482Sandreas.sandberg@arm.com } 11111482Sandreas.sandberg@arm.com 11211482Sandreas.sandberg@arm.com updateLSQNextCycle = false; 11311482Sandreas.sandberg@arm.com 11411482Sandreas.sandberg@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 11511482Sandreas.sandberg@arm.com} 11611482Sandreas.sandberg@arm.com 11711482Sandreas.sandberg@arm.comtemplate <class Impl> 11811482Sandreas.sandberg@arm.comstd::string 11911482Sandreas.sandberg@arm.comDefaultIEW<Impl>::name() const 12011482Sandreas.sandberg@arm.com{ 12111482Sandreas.sandberg@arm.com return cpu->name() + ".iew"; 12211482Sandreas.sandberg@arm.com} 12311482Sandreas.sandberg@arm.com 12411482Sandreas.sandberg@arm.comtemplate <class Impl> 12511482Sandreas.sandberg@arm.comvoid 12611482Sandreas.sandberg@arm.comDefaultIEW<Impl>::regProbePoints() 12711482Sandreas.sandberg@arm.com{ 12811482Sandreas.sandberg@arm.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12911482Sandreas.sandberg@arm.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13011482Sandreas.sandberg@arm.com /** 13111482Sandreas.sandberg@arm.com * Probe point with dynamic instruction as the argument used to probe when 13211482Sandreas.sandberg@arm.com * an instruction starts to execute. 13311482Sandreas.sandberg@arm.com */ 13411482Sandreas.sandberg@arm.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13511482Sandreas.sandberg@arm.com "Execute"); 13611482Sandreas.sandberg@arm.com /** 13711482Sandreas.sandberg@arm.com * Probe point with dynamic instruction as the argument used to probe when 13811482Sandreas.sandberg@arm.com * an instruction execution completes and it is marked ready to commit. 13911482Sandreas.sandberg@arm.com */ 14011482Sandreas.sandberg@arm.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 14111482Sandreas.sandberg@arm.com "ToCommit"); 14211482Sandreas.sandberg@arm.com} 14311482Sandreas.sandberg@arm.com 14411482Sandreas.sandberg@arm.comtemplate <class Impl> 14511482Sandreas.sandberg@arm.comvoid 14611482Sandreas.sandberg@arm.comDefaultIEW<Impl>::regStats() 14711482Sandreas.sandberg@arm.com{ 14811482Sandreas.sandberg@arm.com using namespace Stats; 14911879Sandreas.sandberg@arm.com 15011482Sandreas.sandberg@arm.com instQueue.regStats(); 15111482Sandreas.sandberg@arm.com ldstQueue.regStats(); 15211482Sandreas.sandberg@arm.com 15311482Sandreas.sandberg@arm.com iewIdleCycles 15411482Sandreas.sandberg@arm.com .name(name() + ".iewIdleCycles") 15511482Sandreas.sandberg@arm.com .desc("Number of cycles IEW is idle"); 15611482Sandreas.sandberg@arm.com 15711482Sandreas.sandberg@arm.com iewSquashCycles 15811482Sandreas.sandberg@arm.com .name(name() + ".iewSquashCycles") 15911482Sandreas.sandberg@arm.com .desc("Number of cycles IEW is squashing"); 16011482Sandreas.sandberg@arm.com 16111482Sandreas.sandberg@arm.com iewBlockCycles 16211482Sandreas.sandberg@arm.com .name(name() + ".iewBlockCycles") 16311482Sandreas.sandberg@arm.com .desc("Number of cycles IEW is blocking"); 16411482Sandreas.sandberg@arm.com 16511482Sandreas.sandberg@arm.com iewUnblockCycles 16611482Sandreas.sandberg@arm.com .name(name() + ".iewUnblockCycles") 16711482Sandreas.sandberg@arm.com .desc("Number of cycles IEW is unblocking"); 16811482Sandreas.sandberg@arm.com 16911482Sandreas.sandberg@arm.com iewDispatchedInsts 17011482Sandreas.sandberg@arm.com .name(name() + ".iewDispatchedInsts") 17111482Sandreas.sandberg@arm.com .desc("Number of instructions dispatched to IQ"); 17211482Sandreas.sandberg@arm.com 17311482Sandreas.sandberg@arm.com iewDispSquashedInsts 17411482Sandreas.sandberg@arm.com .name(name() + ".iewDispSquashedInsts") 17511482Sandreas.sandberg@arm.com .desc("Number of squashed instructions skipped by dispatch"); 17611482Sandreas.sandberg@arm.com 17711482Sandreas.sandberg@arm.com iewDispLoadInsts 17811482Sandreas.sandberg@arm.com .name(name() + ".iewDispLoadInsts") 17911482Sandreas.sandberg@arm.com .desc("Number of dispatched load instructions"); 18011482Sandreas.sandberg@arm.com 18111482Sandreas.sandberg@arm.com iewDispStoreInsts 18211482Sandreas.sandberg@arm.com .name(name() + ".iewDispStoreInsts") 18311482Sandreas.sandberg@arm.com .desc("Number of dispatched store instructions"); 18411482Sandreas.sandberg@arm.com 18511482Sandreas.sandberg@arm.com iewDispNonSpecInsts 18611482Sandreas.sandberg@arm.com .name(name() + ".iewDispNonSpecInsts") 18711482Sandreas.sandberg@arm.com .desc("Number of dispatched non-speculative instructions"); 18811482Sandreas.sandberg@arm.com 18911482Sandreas.sandberg@arm.com iewIQFullEvents 19011482Sandreas.sandberg@arm.com .name(name() + ".iewIQFullEvents") 19111482Sandreas.sandberg@arm.com .desc("Number of times the IQ has become full, causing a stall"); 19211482Sandreas.sandberg@arm.com 19311482Sandreas.sandberg@arm.com iewLSQFullEvents 19411482Sandreas.sandberg@arm.com .name(name() + ".iewLSQFullEvents") 19511482Sandreas.sandberg@arm.com .desc("Number of times the LSQ has become full, causing a stall"); 19611482Sandreas.sandberg@arm.com 19711482Sandreas.sandberg@arm.com memOrderViolationEvents 19811482Sandreas.sandberg@arm.com .name(name() + ".memOrderViolationEvents") 19911482Sandreas.sandberg@arm.com .desc("Number of memory order violations"); 20011482Sandreas.sandberg@arm.com 20111482Sandreas.sandberg@arm.com predictedTakenIncorrect 20211482Sandreas.sandberg@arm.com .name(name() + ".predictedTakenIncorrect") 20311482Sandreas.sandberg@arm.com .desc("Number of branches that were predicted taken incorrectly"); 20411482Sandreas.sandberg@arm.com 20511482Sandreas.sandberg@arm.com predictedNotTakenIncorrect 20611482Sandreas.sandberg@arm.com .name(name() + ".predictedNotTakenIncorrect") 20711482Sandreas.sandberg@arm.com .desc("Number of branches that were predicted not taken incorrectly"); 20811482Sandreas.sandberg@arm.com 20911482Sandreas.sandberg@arm.com branchMispredicts 21011482Sandreas.sandberg@arm.com .name(name() + ".branchMispredicts") 21111482Sandreas.sandberg@arm.com .desc("Number of branch mispredicts detected at execute"); 21211482Sandreas.sandberg@arm.com 21311482Sandreas.sandberg@arm.com branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 21411482Sandreas.sandberg@arm.com 21511482Sandreas.sandberg@arm.com iewExecutedInsts 21611482Sandreas.sandberg@arm.com .name(name() + ".iewExecutedInsts") 21711482Sandreas.sandberg@arm.com .desc("Number of executed instructions"); 21811482Sandreas.sandberg@arm.com 21911482Sandreas.sandberg@arm.com iewExecLoadInsts 22011482Sandreas.sandberg@arm.com .init(cpu->numThreads) 22111482Sandreas.sandberg@arm.com .name(name() + ".iewExecLoadInsts") 22211482Sandreas.sandberg@arm.com .desc("Number of load instructions executed") 22311482Sandreas.sandberg@arm.com .flags(total); 22411482Sandreas.sandberg@arm.com 22511482Sandreas.sandberg@arm.com iewExecSquashedInsts 22611482Sandreas.sandberg@arm.com .name(name() + ".iewExecSquashedInsts") 22711482Sandreas.sandberg@arm.com .desc("Number of squashed instructions skipped in execute"); 22811482Sandreas.sandberg@arm.com 22911482Sandreas.sandberg@arm.com iewExecutedSwp 23011482Sandreas.sandberg@arm.com .init(cpu->numThreads) 23111482Sandreas.sandberg@arm.com .name(name() + ".exec_swp") 23211482Sandreas.sandberg@arm.com .desc("number of swp insts executed") 23311482Sandreas.sandberg@arm.com .flags(total); 23411482Sandreas.sandberg@arm.com 23511482Sandreas.sandberg@arm.com iewExecutedNop 23611482Sandreas.sandberg@arm.com .init(cpu->numThreads) 23711482Sandreas.sandberg@arm.com .name(name() + ".exec_nop") 23811482Sandreas.sandberg@arm.com .desc("number of nop insts executed") 23911482Sandreas.sandberg@arm.com .flags(total); 24011482Sandreas.sandberg@arm.com 24111482Sandreas.sandberg@arm.com iewExecutedRefs 24211482Sandreas.sandberg@arm.com .init(cpu->numThreads) 24311482Sandreas.sandberg@arm.com .name(name() + ".exec_refs") 24411482Sandreas.sandberg@arm.com .desc("number of memory reference insts executed") 24511482Sandreas.sandberg@arm.com .flags(total); 24611482Sandreas.sandberg@arm.com 24711482Sandreas.sandberg@arm.com iewExecutedBranches 24811482Sandreas.sandberg@arm.com .init(cpu->numThreads) 24911482Sandreas.sandberg@arm.com .name(name() + ".exec_branches") 25011482Sandreas.sandberg@arm.com .desc("Number of branches executed") 25111482Sandreas.sandberg@arm.com .flags(total); 25211482Sandreas.sandberg@arm.com 25311482Sandreas.sandberg@arm.com iewExecStoreInsts 25411482Sandreas.sandberg@arm.com .name(name() + ".exec_stores") 25511482Sandreas.sandberg@arm.com .desc("Number of stores executed") 25611482Sandreas.sandberg@arm.com .flags(total); 25711482Sandreas.sandberg@arm.com iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 25811482Sandreas.sandberg@arm.com 25911482Sandreas.sandberg@arm.com iewExecRate 26011482Sandreas.sandberg@arm.com .name(name() + ".exec_rate") 26111482Sandreas.sandberg@arm.com .desc("Inst execution rate") 26211482Sandreas.sandberg@arm.com .flags(total); 26311482Sandreas.sandberg@arm.com 26411482Sandreas.sandberg@arm.com iewExecRate = iewExecutedInsts / cpu->numCycles; 26511482Sandreas.sandberg@arm.com 26611482Sandreas.sandberg@arm.com iewInstsToCommit 26711482Sandreas.sandberg@arm.com .init(cpu->numThreads) 26811482Sandreas.sandberg@arm.com .name(name() + ".wb_sent") 26911482Sandreas.sandberg@arm.com .desc("cumulative count of insts sent to commit") 27011482Sandreas.sandberg@arm.com .flags(total); 27111482Sandreas.sandberg@arm.com 27211482Sandreas.sandberg@arm.com writebackCount 27311482Sandreas.sandberg@arm.com .init(cpu->numThreads) 27411482Sandreas.sandberg@arm.com .name(name() + ".wb_count") 27511482Sandreas.sandberg@arm.com .desc("cumulative count of insts written-back") 27611482Sandreas.sandberg@arm.com .flags(total); 27711482Sandreas.sandberg@arm.com 27811482Sandreas.sandberg@arm.com producerInst 27911482Sandreas.sandberg@arm.com .init(cpu->numThreads) 28011482Sandreas.sandberg@arm.com .name(name() + ".wb_producers") 28111482Sandreas.sandberg@arm.com .desc("num instructions producing a value") 28211482Sandreas.sandberg@arm.com .flags(total); 28311482Sandreas.sandberg@arm.com 28411482Sandreas.sandberg@arm.com consumerInst 28511482Sandreas.sandberg@arm.com .init(cpu->numThreads) 28611482Sandreas.sandberg@arm.com .name(name() + ".wb_consumers") 28711482Sandreas.sandberg@arm.com .desc("num instructions consuming a value") 28811482Sandreas.sandberg@arm.com .flags(total); 28911482Sandreas.sandberg@arm.com 29011482Sandreas.sandberg@arm.com wbFanout 29111482Sandreas.sandberg@arm.com .name(name() + ".wb_fanout") 292 .desc("average fanout of values written-back") 293 .flags(total); 294 295 wbFanout = producerInst / consumerInst; 296 297 wbRate 298 .name(name() + ".wb_rate") 299 .desc("insts written-back per cycle") 300 .flags(total); 301 wbRate = writebackCount / cpu->numCycles; 302} 303 304template<class Impl> 305void 306DefaultIEW<Impl>::startupStage() 307{ 308 for (ThreadID tid = 0; tid < numThreads; tid++) { 309 toRename->iewInfo[tid].usedIQ = true; 310 toRename->iewInfo[tid].freeIQEntries = 311 instQueue.numFreeEntries(tid); 312 313 toRename->iewInfo[tid].usedLSQ = true; 314 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 315 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 316 } 317 318 // Initialize the checker's dcache port here 319 if (cpu->checker) { 320 cpu->checker->setDcachePort(&cpu->getDataPort()); 321 } 322 323 cpu->activateStage(O3CPU::IEWIdx); 324} 325 326template<class Impl> 327void 328DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 329{ 330 timeBuffer = tb_ptr; 331 332 // Setup wire to read information from time buffer, from commit. 333 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 334 335 // Setup wire to write information back to previous stages. 336 toRename = timeBuffer->getWire(0); 337 338 toFetch = timeBuffer->getWire(0); 339 340 // Instruction queue also needs main time buffer. 341 instQueue.setTimeBuffer(tb_ptr); 342} 343 344template<class Impl> 345void 346DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 347{ 348 renameQueue = rq_ptr; 349 350 // Setup wire to read information from rename queue. 351 fromRename = renameQueue->getWire(-renameToIEWDelay); 352} 353 354template<class Impl> 355void 356DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 357{ 358 iewQueue = iq_ptr; 359 360 // Setup wire to write instructions to commit. 361 toCommit = iewQueue->getWire(0); 362} 363 364template<class Impl> 365void 366DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 367{ 368 activeThreads = at_ptr; 369 370 ldstQueue.setActiveThreads(at_ptr); 371 instQueue.setActiveThreads(at_ptr); 372} 373 374template<class Impl> 375void 376DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 377{ 378 scoreboard = sb_ptr; 379} 380 381template <class Impl> 382bool 383DefaultIEW<Impl>::isDrained() const 384{ 385 bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 386 387 for (ThreadID tid = 0; tid < numThreads; tid++) { 388 if (!insts[tid].empty()) { 389 DPRINTF(Drain, "%i: Insts not empty.\n", tid); 390 drained = false; 391 } 392 if (!skidBuffer[tid].empty()) { 393 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 394 drained = false; 395 } 396 drained = drained && dispatchStatus[tid] == Running; 397 } 398 399 // Also check the FU pool as instructions are "stored" in FU 400 // completion events until they are done and not accounted for 401 // above 402 if (drained && !fuPool->isDrained()) { 403 DPRINTF(Drain, "FU pool still busy.\n"); 404 drained = false; 405 } 406 407 return drained; 408} 409 410template <class Impl> 411void 412DefaultIEW<Impl>::drainSanityCheck() const 413{ 414 assert(isDrained()); 415 416 instQueue.drainSanityCheck(); 417 ldstQueue.drainSanityCheck(); 418} 419 420template <class Impl> 421void 422DefaultIEW<Impl>::takeOverFrom() 423{ 424 // Reset all state. 425 _status = Active; 426 exeStatus = Running; 427 wbStatus = Idle; 428 429 instQueue.takeOverFrom(); 430 ldstQueue.takeOverFrom(); 431 fuPool->takeOverFrom(); 432 433 startupStage(); 434 cpu->activityThisCycle(); 435 436 for (ThreadID tid = 0; tid < numThreads; tid++) { 437 dispatchStatus[tid] = Running; 438 fetchRedirect[tid] = false; 439 } 440 441 updateLSQNextCycle = false; 442 443 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 444 issueToExecQueue.advance(); 445 } 446} 447 448template<class Impl> 449void 450DefaultIEW<Impl>::squash(ThreadID tid) 451{ 452 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 453 454 // Tell the IQ to start squashing. 455 instQueue.squash(tid); 456 457 // Tell the LDSTQ to start squashing. 458 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 459 updatedQueues = true; 460 461 // Clear the skid buffer in case it has any data in it. 462 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 463 tid, fromCommit->commitInfo[tid].doneSeqNum); 464 465 while (!skidBuffer[tid].empty()) { 466 if (skidBuffer[tid].front()->isLoad()) { 467 toRename->iewInfo[tid].dispatchedToLQ++; 468 } 469 if (skidBuffer[tid].front()->isStore()) { 470 toRename->iewInfo[tid].dispatchedToSQ++; 471 } 472 473 toRename->iewInfo[tid].dispatched++; 474 475 skidBuffer[tid].pop(); 476 } 477 478 emptyRenameInsts(tid); 479} 480 481template<class Impl> 482void 483DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 484{ 485 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 486 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 487 488 if (!toCommit->squash[tid] || 489 inst->seqNum < toCommit->squashedSeqNum[tid]) { 490 toCommit->squash[tid] = true; 491 toCommit->squashedSeqNum[tid] = inst->seqNum; 492 toCommit->branchTaken[tid] = inst->pcState().branching(); 493 494 TheISA::PCState pc = inst->pcState(); 495 TheISA::advancePC(pc, inst->staticInst); 496 497 toCommit->pc[tid] = pc; 498 toCommit->mispredictInst[tid] = inst; 499 toCommit->includeSquashInst[tid] = false; 500 501 wroteToTimeBuffer = true; 502 } 503 504} 505 506template<class Impl> 507void 508DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 509{ 510 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 511 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 512 // Need to include inst->seqNum in the following comparison to cover the 513 // corner case when a branch misprediction and a memory violation for the 514 // same instruction (e.g. load PC) are detected in the same cycle. In this 515 // case the memory violator should take precedence over the branch 516 // misprediction because it requires the violator itself to be included in 517 // the squash. 518 if (!toCommit->squash[tid] || 519 inst->seqNum <= toCommit->squashedSeqNum[tid]) { 520 toCommit->squash[tid] = true; 521 522 toCommit->squashedSeqNum[tid] = inst->seqNum; 523 toCommit->pc[tid] = inst->pcState(); 524 toCommit->mispredictInst[tid] = NULL; 525 526 // Must include the memory violator in the squash. 527 toCommit->includeSquashInst[tid] = true; 528 529 wroteToTimeBuffer = true; 530 } 531} 532 533template<class Impl> 534void 535DefaultIEW<Impl>::block(ThreadID tid) 536{ 537 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 538 539 if (dispatchStatus[tid] != Blocked && 540 dispatchStatus[tid] != Unblocking) { 541 toRename->iewBlock[tid] = true; 542 wroteToTimeBuffer = true; 543 } 544 545 // Add the current inputs to the skid buffer so they can be 546 // reprocessed when this stage unblocks. 547 skidInsert(tid); 548 549 dispatchStatus[tid] = Blocked; 550} 551 552template<class Impl> 553void 554DefaultIEW<Impl>::unblock(ThreadID tid) 555{ 556 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 557 "buffer %u.\n",tid, tid); 558 559 // If the skid bufffer is empty, signal back to previous stages to unblock. 560 // Also switch status to running. 561 if (skidBuffer[tid].empty()) { 562 toRename->iewUnblock[tid] = true; 563 wroteToTimeBuffer = true; 564 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 565 dispatchStatus[tid] = Running; 566 } 567} 568 569template<class Impl> 570void 571DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 572{ 573 instQueue.wakeDependents(inst); 574} 575 576template<class Impl> 577void 578DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 579{ 580 instQueue.rescheduleMemInst(inst); 581} 582 583template<class Impl> 584void 585DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 586{ 587 instQueue.replayMemInst(inst); 588} 589 590template<class Impl> 591void 592DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 593{ 594 instQueue.blockMemInst(inst); 595} 596 597template<class Impl> 598void 599DefaultIEW<Impl>::cacheUnblocked() 600{ 601 instQueue.cacheUnblocked(); 602} 603 604template<class Impl> 605void 606DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 607{ 608 // This function should not be called after writebackInsts in a 609 // single cycle. That will cause problems with an instruction 610 // being added to the queue to commit without being processed by 611 // writebackInsts prior to being sent to commit. 612 613 // First check the time slot that this instruction will write 614 // to. If there are free write ports at the time, then go ahead 615 // and write the instruction to that time. If there are not, 616 // keep looking back to see where's the first time there's a 617 // free slot. 618 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 619 ++wbNumInst; 620 if (wbNumInst == wbWidth) { 621 ++wbCycle; 622 wbNumInst = 0; 623 } 624 } 625 626 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 627 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 628 // Add finished instruction to queue to commit. 629 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 630 (*iewQueue)[wbCycle].size++; 631} 632 633template <class Impl> 634unsigned 635DefaultIEW<Impl>::validInstsFromRename() 636{ 637 unsigned inst_count = 0; 638 639 for (int i=0; i<fromRename->size; i++) { 640 if (!fromRename->insts[i]->isSquashed()) 641 inst_count++; 642 } 643 644 return inst_count; 645} 646 647template<class Impl> 648void 649DefaultIEW<Impl>::skidInsert(ThreadID tid) 650{ 651 DynInstPtr inst = NULL; 652 653 while (!insts[tid].empty()) { 654 inst = insts[tid].front(); 655 656 insts[tid].pop(); 657 658 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 659 "dispatch skidBuffer %i\n",tid, inst->seqNum, 660 inst->pcState(),tid); 661 662 skidBuffer[tid].push(inst); 663 } 664 665 assert(skidBuffer[tid].size() <= skidBufferMax && 666 "Skidbuffer Exceeded Max Size"); 667} 668 669template<class Impl> 670int 671DefaultIEW<Impl>::skidCount() 672{ 673 int max=0; 674 675 list<ThreadID>::iterator threads = activeThreads->begin(); 676 list<ThreadID>::iterator end = activeThreads->end(); 677 678 while (threads != end) { 679 ThreadID tid = *threads++; 680 unsigned thread_count = skidBuffer[tid].size(); 681 if (max < thread_count) 682 max = thread_count; 683 } 684 685 return max; 686} 687 688template<class Impl> 689bool 690DefaultIEW<Impl>::skidsEmpty() 691{ 692 list<ThreadID>::iterator threads = activeThreads->begin(); 693 list<ThreadID>::iterator end = activeThreads->end(); 694 695 while (threads != end) { 696 ThreadID tid = *threads++; 697 698 if (!skidBuffer[tid].empty()) 699 return false; 700 } 701 702 return true; 703} 704 705template <class Impl> 706void 707DefaultIEW<Impl>::updateStatus() 708{ 709 bool any_unblocking = false; 710 711 list<ThreadID>::iterator threads = activeThreads->begin(); 712 list<ThreadID>::iterator end = activeThreads->end(); 713 714 while (threads != end) { 715 ThreadID tid = *threads++; 716 717 if (dispatchStatus[tid] == Unblocking) { 718 any_unblocking = true; 719 break; 720 } 721 } 722 723 // If there are no ready instructions waiting to be scheduled by the IQ, 724 // and there's no stores waiting to write back, and dispatch is not 725 // unblocking, then there is no internal activity for the IEW stage. 726 instQueue.intInstQueueReads++; 727 if (_status == Active && !instQueue.hasReadyInsts() && 728 !ldstQueue.willWB() && !any_unblocking) { 729 DPRINTF(IEW, "IEW switching to idle\n"); 730 731 deactivateStage(); 732 733 _status = Inactive; 734 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 735 ldstQueue.willWB() || 736 any_unblocking)) { 737 // Otherwise there is internal activity. Set to active. 738 DPRINTF(IEW, "IEW switching to active\n"); 739 740 activateStage(); 741 742 _status = Active; 743 } 744} 745 746template <class Impl> 747bool 748DefaultIEW<Impl>::checkStall(ThreadID tid) 749{ 750 bool ret_val(false); 751 752 if (fromCommit->commitInfo[tid].robSquashing) { 753 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 754 ret_val = true; 755 } else if (instQueue.isFull(tid)) { 756 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 757 ret_val = true; 758 } 759 760 return ret_val; 761} 762 763template <class Impl> 764void 765DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 766{ 767 // Check if there's a squash signal, squash if there is 768 // Check stall signals, block if there is. 769 // If status was Blocked 770 // if so then go to unblocking 771 // If status was Squashing 772 // check if squashing is not high. Switch to running this cycle. 773 774 if (fromCommit->commitInfo[tid].squash) { 775 squash(tid); 776 777 if (dispatchStatus[tid] == Blocked || 778 dispatchStatus[tid] == Unblocking) { 779 toRename->iewUnblock[tid] = true; 780 wroteToTimeBuffer = true; 781 } 782 783 dispatchStatus[tid] = Squashing; 784 fetchRedirect[tid] = false; 785 return; 786 } 787 788 if (fromCommit->commitInfo[tid].robSquashing) { 789 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 790 791 dispatchStatus[tid] = Squashing; 792 emptyRenameInsts(tid); 793 wroteToTimeBuffer = true; 794 } 795 796 if (checkStall(tid)) { 797 block(tid); 798 dispatchStatus[tid] = Blocked; 799 return; 800 } 801 802 if (dispatchStatus[tid] == Blocked) { 803 // Status from previous cycle was blocked, but there are no more stall 804 // conditions. Switch over to unblocking. 805 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 806 tid); 807 808 dispatchStatus[tid] = Unblocking; 809 810 unblock(tid); 811 812 return; 813 } 814 815 if (dispatchStatus[tid] == Squashing) { 816 // Switch status to running if rename isn't being told to block or 817 // squash this cycle. 818 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 819 tid); 820 821 dispatchStatus[tid] = Running; 822 823 return; 824 } 825} 826 827template <class Impl> 828void 829DefaultIEW<Impl>::sortInsts() 830{ 831 int insts_from_rename = fromRename->size; 832#ifdef DEBUG 833 for (ThreadID tid = 0; tid < numThreads; tid++) 834 assert(insts[tid].empty()); 835#endif 836 for (int i = 0; i < insts_from_rename; ++i) { 837 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 838 } 839} 840 841template <class Impl> 842void 843DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 844{ 845 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 846 847 while (!insts[tid].empty()) { 848 849 if (insts[tid].front()->isLoad()) { 850 toRename->iewInfo[tid].dispatchedToLQ++; 851 } 852 if (insts[tid].front()->isStore()) { 853 toRename->iewInfo[tid].dispatchedToSQ++; 854 } 855 856 toRename->iewInfo[tid].dispatched++; 857 858 insts[tid].pop(); 859 } 860} 861 862template <class Impl> 863void 864DefaultIEW<Impl>::wakeCPU() 865{ 866 cpu->wakeCPU(); 867} 868 869template <class Impl> 870void 871DefaultIEW<Impl>::activityThisCycle() 872{ 873 DPRINTF(Activity, "Activity this cycle.\n"); 874 cpu->activityThisCycle(); 875} 876 877template <class Impl> 878inline void 879DefaultIEW<Impl>::activateStage() 880{ 881 DPRINTF(Activity, "Activating stage.\n"); 882 cpu->activateStage(O3CPU::IEWIdx); 883} 884 885template <class Impl> 886inline void 887DefaultIEW<Impl>::deactivateStage() 888{ 889 DPRINTF(Activity, "Deactivating stage.\n"); 890 cpu->deactivateStage(O3CPU::IEWIdx); 891} 892 893template<class Impl> 894void 895DefaultIEW<Impl>::dispatch(ThreadID tid) 896{ 897 // If status is Running or idle, 898 // call dispatchInsts() 899 // If status is Unblocking, 900 // buffer any instructions coming from rename 901 // continue trying to empty skid buffer 902 // check if stall conditions have passed 903 904 if (dispatchStatus[tid] == Blocked) { 905 ++iewBlockCycles; 906 907 } else if (dispatchStatus[tid] == Squashing) { 908 ++iewSquashCycles; 909 } 910 911 // Dispatch should try to dispatch as many instructions as its bandwidth 912 // will allow, as long as it is not currently blocked. 913 if (dispatchStatus[tid] == Running || 914 dispatchStatus[tid] == Idle) { 915 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 916 "dispatch.\n", tid); 917 918 dispatchInsts(tid); 919 } else if (dispatchStatus[tid] == Unblocking) { 920 // Make sure that the skid buffer has something in it if the 921 // status is unblocking. 922 assert(!skidsEmpty()); 923 924 // If the status was unblocking, then instructions from the skid 925 // buffer were used. Remove those instructions and handle 926 // the rest of unblocking. 927 dispatchInsts(tid); 928 929 ++iewUnblockCycles; 930 931 if (validInstsFromRename()) { 932 // Add the current inputs to the skid buffer so they can be 933 // reprocessed when this stage unblocks. 934 skidInsert(tid); 935 } 936 937 unblock(tid); 938 } 939} 940 941template <class Impl> 942void 943DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 944{ 945 // Obtain instructions from skid buffer if unblocking, or queue from rename 946 // otherwise. 947 std::queue<DynInstPtr> &insts_to_dispatch = 948 dispatchStatus[tid] == Unblocking ? 949 skidBuffer[tid] : insts[tid]; 950 951 int insts_to_add = insts_to_dispatch.size(); 952 953 DynInstPtr inst; 954 bool add_to_iq = false; 955 int dis_num_inst = 0; 956 957 // Loop through the instructions, putting them in the instruction 958 // queue. 959 for ( ; dis_num_inst < insts_to_add && 960 dis_num_inst < dispatchWidth; 961 ++dis_num_inst) 962 { 963 inst = insts_to_dispatch.front(); 964 965 if (dispatchStatus[tid] == Unblocking) { 966 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 967 "buffer\n", tid); 968 } 969 970 // Make sure there's a valid instruction there. 971 assert(inst); 972 973 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 974 "IQ.\n", 975 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 976 977 // Be sure to mark these instructions as ready so that the 978 // commit stage can go ahead and execute them, and mark 979 // them as issued so the IQ doesn't reprocess them. 980 981 // Check for squashed instructions. 982 if (inst->isSquashed()) { 983 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 984 "not adding to IQ.\n", tid); 985 986 ++iewDispSquashedInsts; 987 988 insts_to_dispatch.pop(); 989 990 //Tell Rename That An Instruction has been processed 991 if (inst->isLoad()) { 992 toRename->iewInfo[tid].dispatchedToLQ++; 993 } 994 if (inst->isStore()) { 995 toRename->iewInfo[tid].dispatchedToSQ++; 996 } 997 998 toRename->iewInfo[tid].dispatched++; 999 1000 continue; 1001 } 1002 1003 // Check for full conditions. 1004 if (instQueue.isFull(tid)) { 1005 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1006 1007 // Call function to start blocking. 1008 block(tid); 1009 1010 // Set unblock to false. Special case where we are using 1011 // skidbuffer (unblocking) instructions but then we still 1012 // get full in the IQ. 1013 toRename->iewUnblock[tid] = false; 1014 1015 ++iewIQFullEvents; 1016 break; 1017 } 1018 1019 // Check LSQ if inst is LD/ST 1020 if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 1021 (inst->isStore() && ldstQueue.sqFull(tid))) { 1022 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1023 inst->isLoad() ? "LQ" : "SQ"); 1024 1025 // Call function to start blocking. 1026 block(tid); 1027 1028 // Set unblock to false. Special case where we are using 1029 // skidbuffer (unblocking) instructions but then we still 1030 // get full in the IQ. 1031 toRename->iewUnblock[tid] = false; 1032 1033 ++iewLSQFullEvents; 1034 break; 1035 } 1036 1037 // Otherwise issue the instruction just fine. 1038 if (inst->isLoad()) { 1039 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1040 "encountered, adding to LSQ.\n", tid); 1041 1042 // Reserve a spot in the load store queue for this 1043 // memory access. 1044 ldstQueue.insertLoad(inst); 1045 1046 ++iewDispLoadInsts; 1047 1048 add_to_iq = true; 1049 1050 toRename->iewInfo[tid].dispatchedToLQ++; 1051 } else if (inst->isStore()) { 1052 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1053 "encountered, adding to LSQ.\n", tid); 1054 1055 ldstQueue.insertStore(inst); 1056 1057 ++iewDispStoreInsts; 1058 1059 if (inst->isStoreConditional()) { 1060 // Store conditionals need to be set as "canCommit()" 1061 // so that commit can process them when they reach the 1062 // head of commit. 1063 // @todo: This is somewhat specific to Alpha. 1064 inst->setCanCommit(); 1065 instQueue.insertNonSpec(inst); 1066 add_to_iq = false; 1067 1068 ++iewDispNonSpecInsts; 1069 } else { 1070 add_to_iq = true; 1071 } 1072 1073 toRename->iewInfo[tid].dispatchedToSQ++; 1074 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1075 // Same as non-speculative stores. 1076 inst->setCanCommit(); 1077 instQueue.insertBarrier(inst); 1078 add_to_iq = false; 1079 } else if (inst->isNop()) { 1080 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1081 "skipping.\n", tid); 1082 1083 inst->setIssued(); 1084 inst->setExecuted(); 1085 inst->setCanCommit(); 1086 1087 instQueue.recordProducer(inst); 1088 1089 iewExecutedNop[tid]++; 1090 1091 add_to_iq = false; 1092 } else { 1093 assert(!inst->isExecuted()); 1094 add_to_iq = true; 1095 } 1096 1097 if (add_to_iq && inst->isNonSpeculative()) { 1098 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1099 "encountered, skipping.\n", tid); 1100 1101 // Same as non-speculative stores. 1102 inst->setCanCommit(); 1103 1104 // Specifically insert it as nonspeculative. 1105 instQueue.insertNonSpec(inst); 1106 1107 ++iewDispNonSpecInsts; 1108 1109 add_to_iq = false; 1110 } 1111 1112 // If the instruction queue is not full, then add the 1113 // instruction. 1114 if (add_to_iq) { 1115 instQueue.insert(inst); 1116 } 1117 1118 insts_to_dispatch.pop(); 1119 1120 toRename->iewInfo[tid].dispatched++; 1121 1122 ++iewDispatchedInsts; 1123 1124#if TRACING_ON 1125 inst->dispatchTick = curTick() - inst->fetchTick; 1126#endif 1127 ppDispatch->notify(inst); 1128 } 1129 1130 if (!insts_to_dispatch.empty()) { 1131 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1132 block(tid); 1133 toRename->iewUnblock[tid] = false; 1134 } 1135 1136 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1137 dispatchStatus[tid] = Running; 1138 1139 updatedQueues = true; 1140 } 1141 1142 dis_num_inst = 0; 1143} 1144 1145template <class Impl> 1146void 1147DefaultIEW<Impl>::printAvailableInsts() 1148{ 1149 int inst = 0; 1150 1151 std::cout << "Available Instructions: "; 1152 1153 while (fromIssue->insts[inst]) { 1154 1155 if (inst%3==0) std::cout << "\n\t"; 1156 1157 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1158 << " TN: " << fromIssue->insts[inst]->threadNumber 1159 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1160 1161 inst++; 1162 1163 } 1164 1165 std::cout << "\n"; 1166} 1167 1168template <class Impl> 1169void 1170DefaultIEW<Impl>::executeInsts() 1171{ 1172 wbNumInst = 0; 1173 wbCycle = 0; 1174 1175 list<ThreadID>::iterator threads = activeThreads->begin(); 1176 list<ThreadID>::iterator end = activeThreads->end(); 1177 1178 while (threads != end) { 1179 ThreadID tid = *threads++; 1180 fetchRedirect[tid] = false; 1181 } 1182 1183 // Uncomment this if you want to see all available instructions. 1184 // @todo This doesn't actually work anymore, we should fix it. 1185// printAvailableInsts(); 1186 1187 // Execute/writeback any instructions that are available. 1188 int insts_to_execute = fromIssue->size; 1189 int inst_num = 0; 1190 for (; inst_num < insts_to_execute; 1191 ++inst_num) { 1192 1193 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1194 1195 DynInstPtr inst = instQueue.getInstToExecute(); 1196 1197 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1198 inst->pcState(), inst->threadNumber,inst->seqNum); 1199 1200 // Notify potential listeners that this instruction has started 1201 // executing 1202 ppExecute->notify(inst); 1203 1204 // Check if the instruction is squashed; if so then skip it 1205 if (inst->isSquashed()) { 1206 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 1207 " [sn:%i]\n", inst->pcState(), inst->threadNumber, 1208 inst->seqNum); 1209 1210 // Consider this instruction executed so that commit can go 1211 // ahead and retire the instruction. 1212 inst->setExecuted(); 1213 1214 // Not sure if I should set this here or just let commit try to 1215 // commit any squashed instructions. I like the latter a bit more. 1216 inst->setCanCommit(); 1217 1218 ++iewExecSquashedInsts; 1219 1220 continue; 1221 } 1222 1223 Fault fault = NoFault; 1224 1225 // Execute instruction. 1226 // Note that if the instruction faults, it will be handled 1227 // at the commit stage. 1228 if (inst->isMemRef()) { 1229 DPRINTF(IEW, "Execute: Calculating address for memory " 1230 "reference.\n"); 1231 1232 // Tell the LDSTQ to execute this instruction (if it is a load). 1233 if (inst->isLoad()) { 1234 // Loads will mark themselves as executed, and their writeback 1235 // event adds the instruction to the queue to commit 1236 fault = ldstQueue.executeLoad(inst); 1237 1238 if (inst->isTranslationDelayed() && 1239 fault == NoFault) { 1240 // A hw page table walk is currently going on; the 1241 // instruction must be deferred. 1242 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1243 "load.\n"); 1244 instQueue.deferMemInst(inst); 1245 continue; 1246 } 1247 1248 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1249 inst->fault = NoFault; 1250 } 1251 } else if (inst->isStore()) { 1252 fault = ldstQueue.executeStore(inst); 1253 1254 if (inst->isTranslationDelayed() && 1255 fault == NoFault) { 1256 // A hw page table walk is currently going on; the 1257 // instruction must be deferred. 1258 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1259 "store.\n"); 1260 instQueue.deferMemInst(inst); 1261 continue; 1262 } 1263 1264 // If the store had a fault then it may not have a mem req 1265 if (fault != NoFault || !inst->readPredicate() || 1266 !inst->isStoreConditional()) { 1267 // If the instruction faulted, then we need to send it along 1268 // to commit without the instruction completing. 1269 // Send this instruction to commit, also make sure iew stage 1270 // realizes there is activity. 1271 inst->setExecuted(); 1272 instToCommit(inst); 1273 activityThisCycle(); 1274 } 1275 1276 // Store conditionals will mark themselves as 1277 // executed, and their writeback event will add the 1278 // instruction to the queue to commit. 1279 } else { 1280 panic("Unexpected memory type!\n"); 1281 } 1282 1283 } else { 1284 // If the instruction has already faulted, then skip executing it. 1285 // Such case can happen when it faulted during ITLB translation. 1286 // If we execute the instruction (even if it's a nop) the fault 1287 // will be replaced and we will lose it. 1288 if (inst->getFault() == NoFault) { 1289 inst->execute(); 1290 if (!inst->readPredicate()) 1291 inst->forwardOldRegs(); 1292 } 1293 1294 inst->setExecuted(); 1295 1296 instToCommit(inst); 1297 } 1298 1299 updateExeInstStats(inst); 1300 1301 // Check if branch prediction was correct, if not then we need 1302 // to tell commit to squash in flight instructions. Only 1303 // handle this if there hasn't already been something that 1304 // redirects fetch in this group of instructions. 1305 1306 // This probably needs to prioritize the redirects if a different 1307 // scheduler is used. Currently the scheduler schedules the oldest 1308 // instruction first, so the branch resolution order will be correct. 1309 ThreadID tid = inst->threadNumber; 1310 1311 if (!fetchRedirect[tid] || 1312 !toCommit->squash[tid] || 1313 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1314 1315 // Prevent testing for misprediction on load instructions, 1316 // that have not been executed. 1317 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1318 1319 if (inst->mispredicted() && !loadNotExecuted) { 1320 fetchRedirect[tid] = true; 1321 1322 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1323 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1324 inst->readPredTarg()); 1325 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1326 inst->pcState()); 1327 // If incorrect, then signal the ROB that it must be squashed. 1328 squashDueToBranch(inst, tid); 1329 1330 ppMispredict->notify(inst); 1331 1332 if (inst->readPredTaken()) { 1333 predictedTakenIncorrect++; 1334 } else { 1335 predictedNotTakenIncorrect++; 1336 } 1337 } else if (ldstQueue.violation(tid)) { 1338 assert(inst->isMemRef()); 1339 // If there was an ordering violation, then get the 1340 // DynInst that caused the violation. Note that this 1341 // clears the violation signal. 1342 DynInstPtr violator; 1343 violator = ldstQueue.getMemDepViolator(tid); 1344 1345 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1346 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1347 violator->pcState(), violator->seqNum, 1348 inst->pcState(), inst->seqNum, inst->physEffAddr); 1349 1350 fetchRedirect[tid] = true; 1351 1352 // Tell the instruction queue that a violation has occured. 1353 instQueue.violation(inst, violator); 1354 1355 // Squash. 1356 squashDueToMemOrder(violator, tid); 1357 1358 ++memOrderViolationEvents; 1359 } 1360 } else { 1361 // Reset any state associated with redirects that will not 1362 // be used. 1363 if (ldstQueue.violation(tid)) { 1364 assert(inst->isMemRef()); 1365 1366 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1367 1368 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1369 "%s, inst PC: %s. Addr is: %#x.\n", 1370 violator->pcState(), inst->pcState(), 1371 inst->physEffAddr); 1372 DPRINTF(IEW, "Violation will not be handled because " 1373 "already squashing\n"); 1374 1375 ++memOrderViolationEvents; 1376 } 1377 } 1378 } 1379 1380 // Update and record activity if we processed any instructions. 1381 if (inst_num) { 1382 if (exeStatus == Idle) { 1383 exeStatus = Running; 1384 } 1385 1386 updatedQueues = true; 1387 1388 cpu->activityThisCycle(); 1389 } 1390 1391 // Need to reset this in case a writeback event needs to write into the 1392 // iew queue. That way the writeback event will write into the correct 1393 // spot in the queue. 1394 wbNumInst = 0; 1395 1396} 1397 1398template <class Impl> 1399void 1400DefaultIEW<Impl>::writebackInsts() 1401{ 1402 // Loop through the head of the time buffer and wake any 1403 // dependents. These instructions are about to write back. Also 1404 // mark scoreboard that this instruction is finally complete. 1405 // Either have IEW have direct access to scoreboard, or have this 1406 // as part of backwards communication. 1407 for (int inst_num = 0; inst_num < wbWidth && 1408 toCommit->insts[inst_num]; inst_num++) { 1409 DynInstPtr inst = toCommit->insts[inst_num]; 1410 ThreadID tid = inst->threadNumber; 1411 1412 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1413 inst->seqNum, inst->pcState()); 1414 1415 iewInstsToCommit[tid]++; 1416 // Notify potential listeners that execution is complete for this 1417 // instruction. 1418 ppToCommit->notify(inst); 1419 1420 // Some instructions will be sent to commit without having 1421 // executed because they need commit to handle them. 1422 // E.g. Strictly ordered loads have not actually executed when they 1423 // are first sent to commit. Instead commit must tell the LSQ 1424 // when it's ready to execute the strictly ordered load. 1425 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1426 int dependents = instQueue.wakeDependents(inst); 1427 1428 for (int i = 0; i < inst->numDestRegs(); i++) { 1429 //mark as Ready 1430 DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 1431 inst->renamedDestRegIdx(i)->index(), 1432 inst->renamedDestRegIdx(i)->className()); 1433 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1434 } 1435 1436 if (dependents) { 1437 producerInst[tid]++; 1438 consumerInst[tid]+= dependents; 1439 } 1440 writebackCount[tid]++; 1441 } 1442 } 1443} 1444 1445template<class Impl> 1446void 1447DefaultIEW<Impl>::tick() 1448{ 1449 wbNumInst = 0; 1450 wbCycle = 0; 1451 1452 wroteToTimeBuffer = false; 1453 updatedQueues = false; 1454 1455 ldstQueue.tick(); 1456 1457 sortInsts(); 1458 1459 // Free function units marked as being freed this cycle. 1460 fuPool->processFreeUnits(); 1461 1462 list<ThreadID>::iterator threads = activeThreads->begin(); 1463 list<ThreadID>::iterator end = activeThreads->end(); 1464 1465 // Check stall and squash signals, dispatch any instructions. 1466 while (threads != end) { 1467 ThreadID tid = *threads++; 1468 1469 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1470 1471 checkSignalsAndUpdate(tid); 1472 dispatch(tid); 1473 } 1474 1475 if (exeStatus != Squashing) { 1476 executeInsts(); 1477 1478 writebackInsts(); 1479 1480 // Have the instruction queue try to schedule any ready instructions. 1481 // (In actuality, this scheduling is for instructions that will 1482 // be executed next cycle.) 1483 instQueue.scheduleReadyInsts(); 1484 1485 // Also should advance its own time buffers if the stage ran. 1486 // Not the best place for it, but this works (hopefully). 1487 issueToExecQueue.advance(); 1488 } 1489 1490 bool broadcast_free_entries = false; 1491 1492 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1493 exeStatus = Idle; 1494 updateLSQNextCycle = false; 1495 1496 broadcast_free_entries = true; 1497 } 1498 1499 // Writeback any stores using any leftover bandwidth. 1500 ldstQueue.writebackStores(); 1501 1502 // Check the committed load/store signals to see if there's a load 1503 // or store to commit. Also check if it's being told to execute a 1504 // nonspeculative instruction. 1505 // This is pretty inefficient... 1506 1507 threads = activeThreads->begin(); 1508 while (threads != end) { 1509 ThreadID tid = (*threads++); 1510 1511 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1512 1513 // Update structures based on instructions committed. 1514 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1515 !fromCommit->commitInfo[tid].squash && 1516 !fromCommit->commitInfo[tid].robSquashing) { 1517 1518 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1519 1520 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1521 1522 updateLSQNextCycle = true; 1523 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1524 } 1525 1526 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1527 1528 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1529 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1530 instQueue.replayMemInst( 1531 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1532 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1533 } else { 1534 instQueue.scheduleNonSpec( 1535 fromCommit->commitInfo[tid].nonSpecSeqNum); 1536 } 1537 } 1538 1539 if (broadcast_free_entries) { 1540 toFetch->iewInfo[tid].iqCount = 1541 instQueue.getCount(tid); 1542 toFetch->iewInfo[tid].ldstqCount = 1543 ldstQueue.getCount(tid); 1544 1545 toRename->iewInfo[tid].usedIQ = true; 1546 toRename->iewInfo[tid].freeIQEntries = 1547 instQueue.numFreeEntries(tid); 1548 toRename->iewInfo[tid].usedLSQ = true; 1549 1550 toRename->iewInfo[tid].freeLQEntries = 1551 ldstQueue.numFreeLoadEntries(tid); 1552 toRename->iewInfo[tid].freeSQEntries = 1553 ldstQueue.numFreeStoreEntries(tid); 1554 1555 wroteToTimeBuffer = true; 1556 } 1557 1558 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1559 tid, toRename->iewInfo[tid].dispatched); 1560 } 1561 1562 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1563 "LQ has %i free entries. SQ has %i free entries.\n", 1564 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1565 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1566 1567 updateStatus(); 1568 1569 if (wroteToTimeBuffer) { 1570 DPRINTF(Activity, "Activity this cycle.\n"); 1571 cpu->activityThisCycle(); 1572 } 1573} 1574 1575template <class Impl> 1576void 1577DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 1578{ 1579 ThreadID tid = inst->threadNumber; 1580 1581 iewExecutedInsts++; 1582 1583#if TRACING_ON 1584 if (DTRACE(O3PipeView)) { 1585 inst->completeTick = curTick() - inst->fetchTick; 1586 } 1587#endif 1588 1589 // 1590 // Control operations 1591 // 1592 if (inst->isControl()) 1593 iewExecutedBranches[tid]++; 1594 1595 // 1596 // Memory operations 1597 // 1598 if (inst->isMemRef()) { 1599 iewExecutedRefs[tid]++; 1600 1601 if (inst->isLoad()) { 1602 iewExecLoadInsts[tid]++; 1603 } 1604 } 1605} 1606 1607template <class Impl> 1608void 1609DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 1610{ 1611 ThreadID tid = inst->threadNumber; 1612 1613 if (!fetchRedirect[tid] || 1614 !toCommit->squash[tid] || 1615 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1616 1617 if (inst->mispredicted()) { 1618 fetchRedirect[tid] = true; 1619 1620 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1621 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1622 inst->predInstAddr(), inst->predNextInstAddr()); 1623 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1624 " NPC: %#x.\n", inst->nextInstAddr(), 1625 inst->nextInstAddr()); 1626 // If incorrect, then signal the ROB that it must be squashed. 1627 squashDueToBranch(inst, tid); 1628 1629 if (inst->readPredTaken()) { 1630 predictedTakenIncorrect++; 1631 } else { 1632 predictedNotTakenIncorrect++; 1633 } 1634 } 1635 } 1636} 1637 1638#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1639