iew_impl.hh revision 13429
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147598Sminkyu.jeong@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469944Smatt.horsnell@ARM.com 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 491689SN/A// communication happens simultaneously. 501060SN/A 511060SN/A#include <queue> 521060SN/A 538230Snate@binkert.org#include "arch/utility.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 571717SN/A#include "cpu/o3/iew.hh" 588229Snate@binkert.org#include "cpu/timebuf.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/IEW.hh" 629527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 635529Snate@binkert.org#include "params/DerivO3CPU.hh" 641060SN/A 656221Snate@binkert.orgusing namespace std; 666221Snate@binkert.org 671681SN/Atemplate<class Impl> 685529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 704329Sktlim@umich.edu cpu(_cpu), 714329Sktlim@umich.edu instQueue(_cpu, this, params), 724329Sktlim@umich.edu ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 792820Sktlim@umich.edu wbWidth(params->wbWidth), 809444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 811060SN/A{ 8210172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8310172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8510172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8610172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8710172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 8810172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8910172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9010172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9110172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9210172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9310172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9410172Sdam.sunwoo@arm.com 952292SN/A _status = Active; 962292SN/A exeStatus = Running; 972292SN/A wbStatus = Idle; 981060SN/A 991060SN/A // Setup wire to read instructions coming from issue. 1001060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1011060SN/A 1021060SN/A // Instruction queue needs the queue between issue and execute. 1031060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1041681SN/A 1056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1066221Snate@binkert.org dispatchStatus[tid] = Running; 1076221Snate@binkert.org fetchRedirect[tid] = false; 1082292SN/A } 1092292SN/A 1102292SN/A updateLSQNextCycle = false; 1112292SN/A 11210328Smitch.hayenga@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1132292SN/A} 1142292SN/A 1152292SN/Atemplate <class Impl> 1162292SN/Astd::string 1172292SN/ADefaultIEW<Impl>::name() const 1182292SN/A{ 1192292SN/A return cpu->name() + ".iew"; 1201060SN/A} 1211060SN/A 1221681SN/Atemplate <class Impl> 1231062SN/Avoid 12410023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 12510023Smatt.horsnell@ARM.com{ 12610023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12710023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 12811246Sradhika.jagtap@ARM.com /** 12911246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13011246Sradhika.jagtap@ARM.com * an instruction starts to execute. 13111246Sradhika.jagtap@ARM.com */ 13211246Sradhika.jagtap@ARM.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13311246Sradhika.jagtap@ARM.com "Execute"); 13411246Sradhika.jagtap@ARM.com /** 13511246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13611246Sradhika.jagtap@ARM.com * an instruction execution completes and it is marked ready to commit. 13711246Sradhika.jagtap@ARM.com */ 13811246Sradhika.jagtap@ARM.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13911246Sradhika.jagtap@ARM.com "ToCommit"); 14010023Smatt.horsnell@ARM.com} 14110023Smatt.horsnell@ARM.com 14210023Smatt.horsnell@ARM.comtemplate <class Impl> 14310023Smatt.horsnell@ARM.comvoid 1442292SN/ADefaultIEW<Impl>::regStats() 1451062SN/A{ 1462301SN/A using namespace Stats; 1472301SN/A 1481062SN/A instQueue.regStats(); 1492727Sktlim@umich.edu ldstQueue.regStats(); 1501062SN/A 1511062SN/A iewIdleCycles 1521062SN/A .name(name() + ".iewIdleCycles") 1531062SN/A .desc("Number of cycles IEW is idle"); 1541062SN/A 1551062SN/A iewSquashCycles 1561062SN/A .name(name() + ".iewSquashCycles") 1571062SN/A .desc("Number of cycles IEW is squashing"); 1581062SN/A 1591062SN/A iewBlockCycles 1601062SN/A .name(name() + ".iewBlockCycles") 1611062SN/A .desc("Number of cycles IEW is blocking"); 1621062SN/A 1631062SN/A iewUnblockCycles 1641062SN/A .name(name() + ".iewUnblockCycles") 1651062SN/A .desc("Number of cycles IEW is unblocking"); 1661062SN/A 1671062SN/A iewDispatchedInsts 1681062SN/A .name(name() + ".iewDispatchedInsts") 1691062SN/A .desc("Number of instructions dispatched to IQ"); 1701062SN/A 1711062SN/A iewDispSquashedInsts 1721062SN/A .name(name() + ".iewDispSquashedInsts") 1731062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1741062SN/A 1751062SN/A iewDispLoadInsts 1761062SN/A .name(name() + ".iewDispLoadInsts") 1771062SN/A .desc("Number of dispatched load instructions"); 1781062SN/A 1791062SN/A iewDispStoreInsts 1801062SN/A .name(name() + ".iewDispStoreInsts") 1811062SN/A .desc("Number of dispatched store instructions"); 1821062SN/A 1831062SN/A iewDispNonSpecInsts 1841062SN/A .name(name() + ".iewDispNonSpecInsts") 1851062SN/A .desc("Number of dispatched non-speculative instructions"); 1861062SN/A 1871062SN/A iewIQFullEvents 1881062SN/A .name(name() + ".iewIQFullEvents") 1891062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1901062SN/A 1912292SN/A iewLSQFullEvents 1922292SN/A .name(name() + ".iewLSQFullEvents") 1932292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1942292SN/A 1951062SN/A memOrderViolationEvents 1961062SN/A .name(name() + ".memOrderViolationEvents") 1971062SN/A .desc("Number of memory order violations"); 1981062SN/A 1991062SN/A predictedTakenIncorrect 2001062SN/A .name(name() + ".predictedTakenIncorrect") 2011062SN/A .desc("Number of branches that were predicted taken incorrectly"); 2022292SN/A 2032292SN/A predictedNotTakenIncorrect 2042292SN/A .name(name() + ".predictedNotTakenIncorrect") 2052292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2062292SN/A 2072292SN/A branchMispredicts 2082292SN/A .name(name() + ".branchMispredicts") 2092292SN/A .desc("Number of branch mispredicts detected at execute"); 2102292SN/A 2112292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2122301SN/A 2132727Sktlim@umich.edu iewExecutedInsts 2142353SN/A .name(name() + ".iewExecutedInsts") 2152727Sktlim@umich.edu .desc("Number of executed instructions"); 2162727Sktlim@umich.edu 2172727Sktlim@umich.edu iewExecLoadInsts 2186221Snate@binkert.org .init(cpu->numThreads) 2192353SN/A .name(name() + ".iewExecLoadInsts") 2202727Sktlim@umich.edu .desc("Number of load instructions executed") 2212727Sktlim@umich.edu .flags(total); 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu iewExecSquashedInsts 2242353SN/A .name(name() + ".iewExecSquashedInsts") 2252727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu iewExecutedSwp 2286221Snate@binkert.org .init(cpu->numThreads) 2298240Snate@binkert.org .name(name() + ".exec_swp") 2302301SN/A .desc("number of swp insts executed") 2312727Sktlim@umich.edu .flags(total); 2322301SN/A 2332727Sktlim@umich.edu iewExecutedNop 2346221Snate@binkert.org .init(cpu->numThreads) 2358240Snate@binkert.org .name(name() + ".exec_nop") 2362301SN/A .desc("number of nop insts executed") 2372727Sktlim@umich.edu .flags(total); 2382301SN/A 2392727Sktlim@umich.edu iewExecutedRefs 2406221Snate@binkert.org .init(cpu->numThreads) 2418240Snate@binkert.org .name(name() + ".exec_refs") 2422301SN/A .desc("number of memory reference insts executed") 2432727Sktlim@umich.edu .flags(total); 2442301SN/A 2452727Sktlim@umich.edu iewExecutedBranches 2466221Snate@binkert.org .init(cpu->numThreads) 2478240Snate@binkert.org .name(name() + ".exec_branches") 2482301SN/A .desc("Number of branches executed") 2492727Sktlim@umich.edu .flags(total); 2502301SN/A 2512301SN/A iewExecStoreInsts 2528240Snate@binkert.org .name(name() + ".exec_stores") 2532301SN/A .desc("Number of stores executed") 2542727Sktlim@umich.edu .flags(total); 2552727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2562727Sktlim@umich.edu 2572727Sktlim@umich.edu iewExecRate 2588240Snate@binkert.org .name(name() + ".exec_rate") 2592727Sktlim@umich.edu .desc("Inst execution rate") 2602727Sktlim@umich.edu .flags(total); 2612727Sktlim@umich.edu 2622727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2632301SN/A 2642301SN/A iewInstsToCommit 2656221Snate@binkert.org .init(cpu->numThreads) 2668240Snate@binkert.org .name(name() + ".wb_sent") 2672301SN/A .desc("cumulative count of insts sent to commit") 2682727Sktlim@umich.edu .flags(total); 2692301SN/A 2702326SN/A writebackCount 2716221Snate@binkert.org .init(cpu->numThreads) 2728240Snate@binkert.org .name(name() + ".wb_count") 2732301SN/A .desc("cumulative count of insts written-back") 2742727Sktlim@umich.edu .flags(total); 2752301SN/A 2762326SN/A producerInst 2776221Snate@binkert.org .init(cpu->numThreads) 2788240Snate@binkert.org .name(name() + ".wb_producers") 2792301SN/A .desc("num instructions producing a value") 2802727Sktlim@umich.edu .flags(total); 2812301SN/A 2822326SN/A consumerInst 2836221Snate@binkert.org .init(cpu->numThreads) 2848240Snate@binkert.org .name(name() + ".wb_consumers") 2852301SN/A .desc("num instructions consuming a value") 2862727Sktlim@umich.edu .flags(total); 2872301SN/A 2882326SN/A wbFanout 2898240Snate@binkert.org .name(name() + ".wb_fanout") 2902301SN/A .desc("average fanout of values written-back") 2912727Sktlim@umich.edu .flags(total); 2922301SN/A 2932326SN/A wbFanout = producerInst / consumerInst; 2942301SN/A 2952326SN/A wbRate 2968240Snate@binkert.org .name(name() + ".wb_rate") 2972301SN/A .desc("insts written-back per cycle") 2982727Sktlim@umich.edu .flags(total); 2992326SN/A wbRate = writebackCount / cpu->numCycles; 3001062SN/A} 3011062SN/A 3021681SN/Atemplate<class Impl> 3031060SN/Avoid 3049427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3051060SN/A{ 3066221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3072292SN/A toRename->iewInfo[tid].usedIQ = true; 3082292SN/A toRename->iewInfo[tid].freeIQEntries = 3092292SN/A instQueue.numFreeEntries(tid); 3102292SN/A 3112292SN/A toRename->iewInfo[tid].usedLSQ = true; 31210239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 31310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3142292SN/A } 3152292SN/A 3168887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3178733Sgeoffrey.blake@arm.com if (cpu->checker) { 3188850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3198887Sgeoffrey.blake@arm.com } 3208733Sgeoffrey.blake@arm.com 3212733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3221060SN/A} 3231060SN/A 3241681SN/Atemplate<class Impl> 3251060SN/Avoid 3262292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3271060SN/A{ 3281060SN/A timeBuffer = tb_ptr; 3291060SN/A 3301060SN/A // Setup wire to read information from time buffer, from commit. 3311060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3321060SN/A 3331060SN/A // Setup wire to write information back to previous stages. 3341060SN/A toRename = timeBuffer->getWire(0); 3351060SN/A 3362292SN/A toFetch = timeBuffer->getWire(0); 3372292SN/A 3381060SN/A // Instruction queue also needs main time buffer. 3391060SN/A instQueue.setTimeBuffer(tb_ptr); 3401060SN/A} 3411060SN/A 3421681SN/Atemplate<class Impl> 3431060SN/Avoid 3442292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3451060SN/A{ 3461060SN/A renameQueue = rq_ptr; 3471060SN/A 3481060SN/A // Setup wire to read information from rename queue. 3491060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3501060SN/A} 3511060SN/A 3521681SN/Atemplate<class Impl> 3531060SN/Avoid 3542292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3551060SN/A{ 3561060SN/A iewQueue = iq_ptr; 3571060SN/A 3581060SN/A // Setup wire to write instructions to commit. 3591060SN/A toCommit = iewQueue->getWire(0); 3601060SN/A} 3611060SN/A 3621681SN/Atemplate<class Impl> 3631060SN/Avoid 3646221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3651060SN/A{ 3662292SN/A activeThreads = at_ptr; 3672292SN/A 3682292SN/A ldstQueue.setActiveThreads(at_ptr); 3692292SN/A instQueue.setActiveThreads(at_ptr); 3701060SN/A} 3711060SN/A 3721681SN/Atemplate<class Impl> 3731060SN/Avoid 3742292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3751060SN/A{ 3762292SN/A scoreboard = sb_ptr; 3771060SN/A} 3781060SN/A 3792307SN/Atemplate <class Impl> 3802863Sktlim@umich.edubool 3819444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3822307SN/A{ 38310510Smitch.hayenga@arm.com bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3849444SAndreas.Sandberg@ARM.com 3859444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3869444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3879444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3889444SAndreas.Sandberg@ARM.com drained = false; 3899444SAndreas.Sandberg@ARM.com } 3909444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3919444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3929444SAndreas.Sandberg@ARM.com drained = false; 3939444SAndreas.Sandberg@ARM.com } 39411650Srekai.gonzalezalberquilla@arm.com drained = drained && dispatchStatus[tid] == Running; 3959444SAndreas.Sandberg@ARM.com } 3969444SAndreas.Sandberg@ARM.com 3979783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 3989783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 3999783Sandreas.hansson@arm.com // above 4009783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4019783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4029783Sandreas.hansson@arm.com drained = false; 4039783Sandreas.hansson@arm.com } 4049783Sandreas.hansson@arm.com 4059444SAndreas.Sandberg@ARM.com return drained; 4061681SN/A} 4071681SN/A 4082316SN/Atemplate <class Impl> 4091681SN/Avoid 4109444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4112843Sktlim@umich.edu{ 4129444SAndreas.Sandberg@ARM.com assert(isDrained()); 4132843Sktlim@umich.edu 4149444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4159444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4161681SN/A} 4171681SN/A 4182307SN/Atemplate <class Impl> 4191681SN/Avoid 4202307SN/ADefaultIEW<Impl>::takeOverFrom() 4211060SN/A{ 4222348SN/A // Reset all state. 4232307SN/A _status = Active; 4242307SN/A exeStatus = Running; 4252307SN/A wbStatus = Idle; 4261060SN/A 4272307SN/A instQueue.takeOverFrom(); 4282307SN/A ldstQueue.takeOverFrom(); 4299444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4301060SN/A 4319427SAndreas.Sandberg@ARM.com startupStage(); 4322307SN/A cpu->activityThisCycle(); 4331060SN/A 4346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4356221Snate@binkert.org dispatchStatus[tid] = Running; 4366221Snate@binkert.org fetchRedirect[tid] = false; 4372307SN/A } 4381060SN/A 4392307SN/A updateLSQNextCycle = false; 4402307SN/A 4412873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4422307SN/A issueToExecQueue.advance(); 4431060SN/A } 4441060SN/A} 4451060SN/A 4461681SN/Atemplate<class Impl> 4471060SN/Avoid 4486221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4492107SN/A{ 4506221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4512107SN/A 4522292SN/A // Tell the IQ to start squashing. 4532292SN/A instQueue.squash(tid); 4542107SN/A 4552292SN/A // Tell the LDSTQ to start squashing. 4562326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4572292SN/A updatedQueues = true; 4582107SN/A 4592292SN/A // Clear the skid buffer in case it has any data in it. 4602935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4614632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4622935Sksewell@umich.edu 4632292SN/A while (!skidBuffer[tid].empty()) { 46410239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isLoad()) { 46510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 46610239Sbinhpham@cs.rutgers.edu } 46710239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isStore()) { 46810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 4692292SN/A } 4702107SN/A 4712292SN/A toRename->iewInfo[tid].dispatched++; 4722107SN/A 4732292SN/A skidBuffer[tid].pop(); 4742292SN/A } 4752107SN/A 4762702Sktlim@umich.edu emptyRenameInsts(tid); 4772107SN/A} 4782107SN/A 4792107SN/Atemplate<class Impl> 4802107SN/Avoid 48113429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 4822292SN/A{ 4837720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4847720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4852292SN/A 48610231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 4877852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4887852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4897852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4907852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4912935Sksewell@umich.edu 4927852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4937852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4942292SN/A 4957852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4967852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4977852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4982292SN/A 4997852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5007852SMatt.Horsnell@arm.com } 5017852SMatt.Horsnell@arm.com 5022292SN/A} 5032292SN/A 5042292SN/Atemplate<class Impl> 5052292SN/Avoid 50613429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 5072292SN/A{ 5088513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5098513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5108513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5118513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5128513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5138513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5148513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5158513SGiacomo.Gabrielli@arm.com // the squash. 51610231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5178513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5188513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5192292SN/A 5207852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5218513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5228137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5232292SN/A 5248513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5258513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5262292SN/A 5277852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5287852SMatt.Horsnell@arm.com } 5292292SN/A} 5302292SN/A 5312292SN/Atemplate<class Impl> 5322292SN/Avoid 5336221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5342292SN/A{ 5352292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5362292SN/A 5372292SN/A if (dispatchStatus[tid] != Blocked && 5382292SN/A dispatchStatus[tid] != Unblocking) { 5392292SN/A toRename->iewBlock[tid] = true; 5402292SN/A wroteToTimeBuffer = true; 5412292SN/A } 5422292SN/A 5432292SN/A // Add the current inputs to the skid buffer so they can be 5442292SN/A // reprocessed when this stage unblocks. 5452292SN/A skidInsert(tid); 5462292SN/A 5472292SN/A dispatchStatus[tid] = Blocked; 5482292SN/A} 5492292SN/A 5502292SN/Atemplate<class Impl> 5512292SN/Avoid 5526221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5532292SN/A{ 5542292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5552292SN/A "buffer %u.\n",tid, tid); 5562292SN/A 5572292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5582292SN/A // Also switch status to running. 5592292SN/A if (skidBuffer[tid].empty()) { 5602292SN/A toRename->iewUnblock[tid] = true; 5612292SN/A wroteToTimeBuffer = true; 5622292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5632292SN/A dispatchStatus[tid] = Running; 5642292SN/A } 5652292SN/A} 5662292SN/A 5672292SN/Atemplate<class Impl> 5682292SN/Avoid 56913429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 5701060SN/A{ 5711681SN/A instQueue.wakeDependents(inst); 5721060SN/A} 5731060SN/A 5742292SN/Atemplate<class Impl> 5752292SN/Avoid 57613429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 5772292SN/A{ 5782292SN/A instQueue.rescheduleMemInst(inst); 5792292SN/A} 5801681SN/A 5811681SN/Atemplate<class Impl> 5821060SN/Avoid 58313429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 5841060SN/A{ 5852292SN/A instQueue.replayMemInst(inst); 5862292SN/A} 5871060SN/A 5882292SN/Atemplate<class Impl> 5892292SN/Avoid 59013429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 59110333Smitch.hayenga@arm.com{ 59210333Smitch.hayenga@arm.com instQueue.blockMemInst(inst); 59310333Smitch.hayenga@arm.com} 59410333Smitch.hayenga@arm.com 59510333Smitch.hayenga@arm.comtemplate<class Impl> 59610333Smitch.hayenga@arm.comvoid 59710333Smitch.hayenga@arm.comDefaultIEW<Impl>::cacheUnblocked() 59810333Smitch.hayenga@arm.com{ 59910333Smitch.hayenga@arm.com instQueue.cacheUnblocked(); 60010333Smitch.hayenga@arm.com} 60110333Smitch.hayenga@arm.com 60210333Smitch.hayenga@arm.comtemplate<class Impl> 60310333Smitch.hayenga@arm.comvoid 60413429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 6052292SN/A{ 6063221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6073221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6083221Sktlim@umich.edu // being added to the queue to commit without being processed by 6093221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6103221Sktlim@umich.edu 6112292SN/A // First check the time slot that this instruction will write 6122292SN/A // to. If there are free write ports at the time, then go ahead 6132292SN/A // and write the instruction to that time. If there are not, 6142292SN/A // keep looking back to see where's the first time there's a 6152326SN/A // free slot. 6162292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6172292SN/A ++wbNumInst; 6182820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6192292SN/A ++wbCycle; 6202292SN/A wbNumInst = 0; 6212292SN/A } 6222292SN/A } 6232292SN/A 6242353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6252353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6262292SN/A // Add finished instruction to queue to commit. 6272292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6282292SN/A (*iewQueue)[wbCycle].size++; 6292292SN/A} 6302292SN/A 6312292SN/Atemplate <class Impl> 6322292SN/Aunsigned 6332292SN/ADefaultIEW<Impl>::validInstsFromRename() 6342292SN/A{ 6352292SN/A unsigned inst_count = 0; 6362292SN/A 6372292SN/A for (int i=0; i<fromRename->size; i++) { 6382731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6392292SN/A inst_count++; 6402292SN/A } 6412292SN/A 6422292SN/A return inst_count; 6432292SN/A} 6442292SN/A 6452292SN/Atemplate<class Impl> 6462292SN/Avoid 6476221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6482292SN/A{ 6492292SN/A DynInstPtr inst = NULL; 6502292SN/A 6512292SN/A while (!insts[tid].empty()) { 6522292SN/A inst = insts[tid].front(); 6532292SN/A 6542292SN/A insts[tid].pop(); 6552292SN/A 6569937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6572292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6587720Sgblack@eecs.umich.edu inst->pcState(),tid); 6592292SN/A 6602292SN/A skidBuffer[tid].push(inst); 6612292SN/A } 6622292SN/A 6632292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6642292SN/A "Skidbuffer Exceeded Max Size"); 6652292SN/A} 6662292SN/A 6672292SN/Atemplate<class Impl> 6682292SN/Aint 6692292SN/ADefaultIEW<Impl>::skidCount() 6702292SN/A{ 6712292SN/A int max=0; 6722292SN/A 6736221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6746221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6752292SN/A 6763867Sbinkertn@umich.edu while (threads != end) { 6776221Snate@binkert.org ThreadID tid = *threads++; 6783867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6792292SN/A if (max < thread_count) 6802292SN/A max = thread_count; 6812292SN/A } 6822292SN/A 6832292SN/A return max; 6842292SN/A} 6852292SN/A 6862292SN/Atemplate<class Impl> 6872292SN/Abool 6882292SN/ADefaultIEW<Impl>::skidsEmpty() 6892292SN/A{ 6906221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6916221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6922292SN/A 6933867Sbinkertn@umich.edu while (threads != end) { 6946221Snate@binkert.org ThreadID tid = *threads++; 6953867Sbinkertn@umich.edu 6963867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6972292SN/A return false; 6982292SN/A } 6992292SN/A 7002292SN/A return true; 7011062SN/A} 7021062SN/A 7031681SN/Atemplate <class Impl> 7041062SN/Avoid 7052292SN/ADefaultIEW<Impl>::updateStatus() 7061062SN/A{ 7072292SN/A bool any_unblocking = false; 7081062SN/A 7096221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7106221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7111062SN/A 7123867Sbinkertn@umich.edu while (threads != end) { 7136221Snate@binkert.org ThreadID tid = *threads++; 7141062SN/A 7152292SN/A if (dispatchStatus[tid] == Unblocking) { 7162292SN/A any_unblocking = true; 7172292SN/A break; 7182292SN/A } 7192292SN/A } 7201062SN/A 7212292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7222292SN/A // and there's no stores waiting to write back, and dispatch is not 7232292SN/A // unblocking, then there is no internal activity for the IEW stage. 7247897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7252292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7262292SN/A !ldstQueue.willWB() && !any_unblocking) { 7272292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7281062SN/A 7292292SN/A deactivateStage(); 7301062SN/A 7312292SN/A _status = Inactive; 7322292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7332292SN/A ldstQueue.willWB() || 7342292SN/A any_unblocking)) { 7352292SN/A // Otherwise there is internal activity. Set to active. 7362292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7371062SN/A 7382292SN/A activateStage(); 7391062SN/A 7402292SN/A _status = Active; 7411062SN/A } 7421062SN/A} 7431062SN/A 7441681SN/Atemplate <class Impl> 7451062SN/Avoid 7462292SN/ADefaultIEW<Impl>::resetEntries() 7471062SN/A{ 7482292SN/A instQueue.resetEntries(); 7492292SN/A ldstQueue.resetEntries(); 7502292SN/A} 7511062SN/A 7522292SN/Atemplate <class Impl> 7532292SN/Abool 7546221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7552292SN/A{ 7562292SN/A bool ret_val(false); 7572292SN/A 75810328Smitch.hayenga@arm.com if (fromCommit->commitInfo[tid].robSquashing) { 7592292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7602292SN/A ret_val = true; 7612292SN/A } else if (instQueue.isFull(tid)) { 7622292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7632292SN/A ret_val = true; 7642292SN/A } 7652292SN/A 7662292SN/A return ret_val; 7672292SN/A} 7682292SN/A 7692292SN/Atemplate <class Impl> 7702292SN/Avoid 7716221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7722292SN/A{ 7732292SN/A // Check if there's a squash signal, squash if there is 7742292SN/A // Check stall signals, block if there is. 7752292SN/A // If status was Blocked 7762292SN/A // if so then go to unblocking 7772292SN/A // If status was Squashing 7782292SN/A // check if squashing is not high. Switch to running this cycle. 7792292SN/A 7802292SN/A if (fromCommit->commitInfo[tid].squash) { 7812292SN/A squash(tid); 7822292SN/A 7832292SN/A if (dispatchStatus[tid] == Blocked || 7842292SN/A dispatchStatus[tid] == Unblocking) { 7852292SN/A toRename->iewUnblock[tid] = true; 7862292SN/A wroteToTimeBuffer = true; 7872292SN/A } 7882292SN/A 7892292SN/A dispatchStatus[tid] = Squashing; 7902292SN/A fetchRedirect[tid] = false; 7912292SN/A return; 7922292SN/A } 7932292SN/A 7942292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7952702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7962292SN/A 7972292SN/A dispatchStatus[tid] = Squashing; 7982702Sktlim@umich.edu emptyRenameInsts(tid); 7992702Sktlim@umich.edu wroteToTimeBuffer = true; 8002292SN/A } 8012292SN/A 8022292SN/A if (checkStall(tid)) { 8032292SN/A block(tid); 8042292SN/A dispatchStatus[tid] = Blocked; 8052292SN/A return; 8062292SN/A } 8072292SN/A 8082292SN/A if (dispatchStatus[tid] == Blocked) { 8092292SN/A // Status from previous cycle was blocked, but there are no more stall 8102292SN/A // conditions. Switch over to unblocking. 8112292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8122292SN/A tid); 8132292SN/A 8142292SN/A dispatchStatus[tid] = Unblocking; 8152292SN/A 8162292SN/A unblock(tid); 8172292SN/A 8182292SN/A return; 8192292SN/A } 8202292SN/A 8212292SN/A if (dispatchStatus[tid] == Squashing) { 8222292SN/A // Switch status to running if rename isn't being told to block or 8232292SN/A // squash this cycle. 8242292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8252292SN/A tid); 8262292SN/A 8272292SN/A dispatchStatus[tid] = Running; 8282292SN/A 8292292SN/A return; 8302292SN/A } 8312292SN/A} 8322292SN/A 8332292SN/Atemplate <class Impl> 8342292SN/Avoid 8352292SN/ADefaultIEW<Impl>::sortInsts() 8362292SN/A{ 8372292SN/A int insts_from_rename = fromRename->size; 8382326SN/A#ifdef DEBUG 8396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8406221Snate@binkert.org assert(insts[tid].empty()); 8412326SN/A#endif 8422292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8432292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8442292SN/A } 8452292SN/A} 8462292SN/A 8472292SN/Atemplate <class Impl> 8482292SN/Avoid 8496221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8502702Sktlim@umich.edu{ 8514632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8522935Sksewell@umich.edu 8532702Sktlim@umich.edu while (!insts[tid].empty()) { 8542935Sksewell@umich.edu 85510239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isLoad()) { 85610239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 85710239Sbinhpham@cs.rutgers.edu } 85810239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isStore()) { 85910239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 8602702Sktlim@umich.edu } 8612702Sktlim@umich.edu 8622702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8632702Sktlim@umich.edu 8642702Sktlim@umich.edu insts[tid].pop(); 8652702Sktlim@umich.edu } 8662702Sktlim@umich.edu} 8672702Sktlim@umich.edu 8682702Sktlim@umich.edutemplate <class Impl> 8692702Sktlim@umich.eduvoid 8702292SN/ADefaultIEW<Impl>::wakeCPU() 8712292SN/A{ 8722292SN/A cpu->wakeCPU(); 8732292SN/A} 8742292SN/A 8752292SN/Atemplate <class Impl> 8762292SN/Avoid 8772292SN/ADefaultIEW<Impl>::activityThisCycle() 8782292SN/A{ 8792292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8802292SN/A cpu->activityThisCycle(); 8812292SN/A} 8822292SN/A 8832292SN/Atemplate <class Impl> 8842292SN/Ainline void 8852292SN/ADefaultIEW<Impl>::activateStage() 8862292SN/A{ 8872292SN/A DPRINTF(Activity, "Activating stage.\n"); 8882733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8892292SN/A} 8902292SN/A 8912292SN/Atemplate <class Impl> 8922292SN/Ainline void 8932292SN/ADefaultIEW<Impl>::deactivateStage() 8942292SN/A{ 8952292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8962733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8972292SN/A} 8982292SN/A 8992292SN/Atemplate<class Impl> 9002292SN/Avoid 9016221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9022292SN/A{ 9032292SN/A // If status is Running or idle, 9042292SN/A // call dispatchInsts() 9052292SN/A // If status is Unblocking, 9062292SN/A // buffer any instructions coming from rename 9072292SN/A // continue trying to empty skid buffer 9082292SN/A // check if stall conditions have passed 9092292SN/A 9102292SN/A if (dispatchStatus[tid] == Blocked) { 9112292SN/A ++iewBlockCycles; 9122292SN/A 9132292SN/A } else if (dispatchStatus[tid] == Squashing) { 9142292SN/A ++iewSquashCycles; 9152292SN/A } 9162292SN/A 9172292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9182292SN/A // will allow, as long as it is not currently blocked. 9192292SN/A if (dispatchStatus[tid] == Running || 9202292SN/A dispatchStatus[tid] == Idle) { 9212292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9222292SN/A "dispatch.\n", tid); 9232292SN/A 9242292SN/A dispatchInsts(tid); 9252292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9262292SN/A // Make sure that the skid buffer has something in it if the 9272292SN/A // status is unblocking. 9282292SN/A assert(!skidsEmpty()); 9292292SN/A 9302292SN/A // If the status was unblocking, then instructions from the skid 9312292SN/A // buffer were used. Remove those instructions and handle 9322292SN/A // the rest of unblocking. 9332292SN/A dispatchInsts(tid); 9342292SN/A 9352292SN/A ++iewUnblockCycles; 9362292SN/A 9375215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9382292SN/A // Add the current inputs to the skid buffer so they can be 9392292SN/A // reprocessed when this stage unblocks. 9402292SN/A skidInsert(tid); 9412292SN/A } 9422292SN/A 9432292SN/A unblock(tid); 9442292SN/A } 9452292SN/A} 9462292SN/A 9472292SN/Atemplate <class Impl> 9482292SN/Avoid 9496221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9502292SN/A{ 9512292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9522292SN/A // otherwise. 9532292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9542292SN/A dispatchStatus[tid] == Unblocking ? 9552292SN/A skidBuffer[tid] : insts[tid]; 9562292SN/A 9572292SN/A int insts_to_add = insts_to_dispatch.size(); 9582292SN/A 9592292SN/A DynInstPtr inst; 9602292SN/A bool add_to_iq = false; 9612292SN/A int dis_num_inst = 0; 9622292SN/A 9632292SN/A // Loop through the instructions, putting them in the instruction 9642292SN/A // queue. 9652292SN/A for ( ; dis_num_inst < insts_to_add && 9662820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9672292SN/A ++dis_num_inst) 9682292SN/A { 9692292SN/A inst = insts_to_dispatch.front(); 9702292SN/A 9712292SN/A if (dispatchStatus[tid] == Unblocking) { 9722292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9732292SN/A "buffer\n", tid); 9742292SN/A } 9752292SN/A 9762292SN/A // Make sure there's a valid instruction there. 9772292SN/A assert(inst); 9782292SN/A 9797720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9802292SN/A "IQ.\n", 9817720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9822292SN/A 9832292SN/A // Be sure to mark these instructions as ready so that the 9842292SN/A // commit stage can go ahead and execute them, and mark 9852292SN/A // them as issued so the IQ doesn't reprocess them. 9862292SN/A 9872292SN/A // Check for squashed instructions. 9882292SN/A if (inst->isSquashed()) { 9892292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9902292SN/A "not adding to IQ.\n", tid); 9912292SN/A 9922292SN/A ++iewDispSquashedInsts; 9932292SN/A 9942292SN/A insts_to_dispatch.pop(); 9952292SN/A 9962292SN/A //Tell Rename That An Instruction has been processed 99710239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 99810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 9992292SN/A } 100010239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 100110239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 100210239Sbinhpham@cs.rutgers.edu } 100310239Sbinhpham@cs.rutgers.edu 10042292SN/A toRename->iewInfo[tid].dispatched++; 10052292SN/A 10062292SN/A continue; 10072292SN/A } 10082292SN/A 10092292SN/A // Check for full conditions. 10102292SN/A if (instQueue.isFull(tid)) { 10112292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10122292SN/A 10132292SN/A // Call function to start blocking. 10142292SN/A block(tid); 10152292SN/A 10162292SN/A // Set unblock to false. Special case where we are using 10172292SN/A // skidbuffer (unblocking) instructions but then we still 10182292SN/A // get full in the IQ. 10192292SN/A toRename->iewUnblock[tid] = false; 10202292SN/A 10212292SN/A ++iewIQFullEvents; 10222292SN/A break; 102310240Sbinhpham@cs.rutgers.edu } 102410240Sbinhpham@cs.rutgers.edu 102510240Sbinhpham@cs.rutgers.edu // Check LSQ if inst is LD/ST 102610240Sbinhpham@cs.rutgers.edu if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 102710240Sbinhpham@cs.rutgers.edu (inst->isStore() && ldstQueue.sqFull(tid))) { 102810240Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 102910240Sbinhpham@cs.rutgers.edu inst->isLoad() ? "LQ" : "SQ"); 10302292SN/A 10312292SN/A // Call function to start blocking. 10322292SN/A block(tid); 10332292SN/A 10342292SN/A // Set unblock to false. Special case where we are using 10352292SN/A // skidbuffer (unblocking) instructions but then we still 10362292SN/A // get full in the IQ. 10372292SN/A toRename->iewUnblock[tid] = false; 10382292SN/A 10392292SN/A ++iewLSQFullEvents; 10402292SN/A break; 10412292SN/A } 10422292SN/A 10432292SN/A // Otherwise issue the instruction just fine. 10442292SN/A if (inst->isLoad()) { 10452292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10462292SN/A "encountered, adding to LSQ.\n", tid); 10472292SN/A 10482292SN/A // Reserve a spot in the load store queue for this 10492292SN/A // memory access. 10502292SN/A ldstQueue.insertLoad(inst); 10512292SN/A 10522292SN/A ++iewDispLoadInsts; 10532292SN/A 10542292SN/A add_to_iq = true; 10552292SN/A 105610239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10572292SN/A } else if (inst->isStore()) { 10582292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10592292SN/A "encountered, adding to LSQ.\n", tid); 10602292SN/A 10612292SN/A ldstQueue.insertStore(inst); 10622292SN/A 10632292SN/A ++iewDispStoreInsts; 10642292SN/A 10652336SN/A if (inst->isStoreConditional()) { 10662336SN/A // Store conditionals need to be set as "canCommit()" 10672336SN/A // so that commit can process them when they reach the 10682336SN/A // head of commit. 10692348SN/A // @todo: This is somewhat specific to Alpha. 10702292SN/A inst->setCanCommit(); 10712292SN/A instQueue.insertNonSpec(inst); 10722292SN/A add_to_iq = false; 10732292SN/A 10742292SN/A ++iewDispNonSpecInsts; 10752292SN/A } else { 10762292SN/A add_to_iq = true; 10772292SN/A } 10782292SN/A 107910239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 10802292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10812326SN/A // Same as non-speculative stores. 10822292SN/A inst->setCanCommit(); 10832292SN/A instQueue.insertBarrier(inst); 10842292SN/A add_to_iq = false; 10852292SN/A } else if (inst->isNop()) { 10862292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10872292SN/A "skipping.\n", tid); 10882292SN/A 10892292SN/A inst->setIssued(); 10902292SN/A inst->setExecuted(); 10912292SN/A inst->setCanCommit(); 10922292SN/A 10932326SN/A instQueue.recordProducer(inst); 10942292SN/A 10952727Sktlim@umich.edu iewExecutedNop[tid]++; 10962301SN/A 10972292SN/A add_to_iq = false; 10982292SN/A } else { 109910733Snilay@cs.wisc.edu assert(!inst->isExecuted()); 11002292SN/A add_to_iq = true; 11012292SN/A } 110210733Snilay@cs.wisc.edu 110312537Sandreas.sandberg@arm.com if (add_to_iq && inst->isNonSpeculative()) { 11044033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11054033Sktlim@umich.edu "encountered, skipping.\n", tid); 11064033Sktlim@umich.edu 11074033Sktlim@umich.edu // Same as non-speculative stores. 11084033Sktlim@umich.edu inst->setCanCommit(); 11094033Sktlim@umich.edu 11104033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11114033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11124033Sktlim@umich.edu 11134033Sktlim@umich.edu ++iewDispNonSpecInsts; 11144033Sktlim@umich.edu 11154033Sktlim@umich.edu add_to_iq = false; 11164033Sktlim@umich.edu } 11172292SN/A 11182292SN/A // If the instruction queue is not full, then add the 11192292SN/A // instruction. 11202292SN/A if (add_to_iq) { 11212292SN/A instQueue.insert(inst); 11222292SN/A } 11232292SN/A 11242292SN/A insts_to_dispatch.pop(); 11252292SN/A 11262292SN/A toRename->iewInfo[tid].dispatched++; 11272292SN/A 11282292SN/A ++iewDispatchedInsts; 11298471SGiacomo.Gabrielli@arm.com 11308471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11319046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11328471SGiacomo.Gabrielli@arm.com#endif 113310023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11342292SN/A } 11352292SN/A 11362292SN/A if (!insts_to_dispatch.empty()) { 11372935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11382292SN/A block(tid); 11392292SN/A toRename->iewUnblock[tid] = false; 11402292SN/A } 11412292SN/A 11422292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11432292SN/A dispatchStatus[tid] = Running; 11442292SN/A 11452292SN/A updatedQueues = true; 11462292SN/A } 11472292SN/A 11482292SN/A dis_num_inst = 0; 11492292SN/A} 11502292SN/A 11512292SN/Atemplate <class Impl> 11522292SN/Avoid 11532292SN/ADefaultIEW<Impl>::printAvailableInsts() 11542292SN/A{ 11552292SN/A int inst = 0; 11562292SN/A 11572980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11582292SN/A 11592292SN/A while (fromIssue->insts[inst]) { 11602292SN/A 11612980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11622292SN/A 11637720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11642292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11652292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11662292SN/A 11672292SN/A inst++; 11682292SN/A 11692292SN/A } 11702292SN/A 11712980Sgblack@eecs.umich.edu std::cout << "\n"; 11722292SN/A} 11732292SN/A 11742292SN/Atemplate <class Impl> 11752292SN/Avoid 11762292SN/ADefaultIEW<Impl>::executeInsts() 11772292SN/A{ 11782292SN/A wbNumInst = 0; 11792292SN/A wbCycle = 0; 11802292SN/A 11816221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 11826221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 11832292SN/A 11843867Sbinkertn@umich.edu while (threads != end) { 11856221Snate@binkert.org ThreadID tid = *threads++; 11862292SN/A fetchRedirect[tid] = false; 11872292SN/A } 11882292SN/A 11892698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11907599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 11912698Sktlim@umich.edu// printAvailableInsts(); 11921062SN/A 11931062SN/A // Execute/writeback any instructions that are available. 11942333SN/A int insts_to_execute = fromIssue->size; 11952292SN/A int inst_num = 0; 11962333SN/A for (; inst_num < insts_to_execute; 11972326SN/A ++inst_num) { 11981062SN/A 11992292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12001062SN/A 12012333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12021062SN/A 12037720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12047720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12051062SN/A 120611246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction has started 120711246Sradhika.jagtap@ARM.com // executing 120811246Sradhika.jagtap@ARM.com ppExecute->notify(inst); 120911246Sradhika.jagtap@ARM.com 12101062SN/A // Check if the instruction is squashed; if so then skip it 12111062SN/A if (inst->isSquashed()) { 12128315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12138315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12148315Sgeoffrey.blake@arm.com inst->seqNum); 12151062SN/A 12161062SN/A // Consider this instruction executed so that commit can go 12171062SN/A // ahead and retire the instruction. 12181062SN/A inst->setExecuted(); 12191062SN/A 12202292SN/A // Not sure if I should set this here or just let commit try to 12212292SN/A // commit any squashed instructions. I like the latter a bit more. 12222292SN/A inst->setCanCommit(); 12231062SN/A 12241062SN/A ++iewExecSquashedInsts; 12251062SN/A 12261062SN/A continue; 12271062SN/A } 12281062SN/A 12292292SN/A Fault fault = NoFault; 12301062SN/A 12311062SN/A // Execute instruction. 12321062SN/A // Note that if the instruction faults, it will be handled 12331062SN/A // at the commit stage. 12347850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12352292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12361062SN/A "reference.\n"); 12371062SN/A 12381062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12391062SN/A if (inst->isLoad()) { 12402292SN/A // Loads will mark themselves as executed, and their writeback 12412292SN/A // event adds the instruction to the queue to commit 12422292SN/A fault = ldstQueue.executeLoad(inst); 12437944SGiacomo.Gabrielli@arm.com 12447944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12457944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12467944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12477944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12487944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12497944SGiacomo.Gabrielli@arm.com "load.\n"); 12507944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12517944SGiacomo.Gabrielli@arm.com continue; 12527944SGiacomo.Gabrielli@arm.com } 12537944SGiacomo.Gabrielli@arm.com 12547850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12558073SAli.Saidi@ARM.com inst->fault = NoFault; 12567850SMatt.Horsnell@arm.com } 12571062SN/A } else if (inst->isStore()) { 12582367SN/A fault = ldstQueue.executeStore(inst); 12591062SN/A 12607944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12617944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12627944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12637944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12647944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12657944SGiacomo.Gabrielli@arm.com "store.\n"); 12667944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12677944SGiacomo.Gabrielli@arm.com continue; 12687944SGiacomo.Gabrielli@arm.com } 12697944SGiacomo.Gabrielli@arm.com 12702292SN/A // If the store had a fault then it may not have a mem req 127110231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 12727782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12737782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12747782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12752367SN/A // Send this instruction to commit, also make sure iew stage 12762367SN/A // realizes there is activity. 12772367SN/A inst->setExecuted(); 12782367SN/A instToCommit(inst); 12792367SN/A activityThisCycle(); 12802292SN/A } 12812326SN/A 12822326SN/A // Store conditionals will mark themselves as 12832326SN/A // executed, and their writeback event will add the 12842326SN/A // instruction to the queue to commit. 12851062SN/A } else { 12862292SN/A panic("Unexpected memory type!\n"); 12871062SN/A } 12881062SN/A 12891062SN/A } else { 12907847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 12917847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 12927847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 12937847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 12947847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 12957847Sminkyu.jeong@arm.com inst->execute(); 129610231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 12977848SAli.Saidi@ARM.com inst->forwardOldRegs(); 12987847Sminkyu.jeong@arm.com } 12991062SN/A 13002292SN/A inst->setExecuted(); 13012292SN/A 13022292SN/A instToCommit(inst); 13031062SN/A } 13041062SN/A 13052301SN/A updateExeInstStats(inst); 13061681SN/A 13072326SN/A // Check if branch prediction was correct, if not then we need 13082326SN/A // to tell commit to squash in flight instructions. Only 13092326SN/A // handle this if there hasn't already been something that 13102107SN/A // redirects fetch in this group of instructions. 13111681SN/A 13122292SN/A // This probably needs to prioritize the redirects if a different 13132292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13142292SN/A // instruction first, so the branch resolution order will be correct. 13156221Snate@binkert.org ThreadID tid = inst->threadNumber; 13161062SN/A 13173732Sktlim@umich.edu if (!fetchRedirect[tid] || 13187852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13193732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13201062SN/A 13217856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13227856SMatt.Horsnell@arm.com // that have not been executed. 13237856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13247856SMatt.Horsnell@arm.com 13257856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13262292SN/A fetchRedirect[tid] = true; 13271062SN/A 13282292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13298674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13308674Snilay@cs.wisc.edu inst->readPredTarg()); 13317720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13328674Snilay@cs.wisc.edu inst->pcState()); 13331062SN/A // If incorrect, then signal the ROB that it must be squashed. 13342292SN/A squashDueToBranch(inst, tid); 13351062SN/A 133610023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 133710023Smatt.horsnell@ARM.com 13383795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13391062SN/A predictedTakenIncorrect++; 13402292SN/A } else { 13412292SN/A predictedNotTakenIncorrect++; 13421062SN/A } 13432292SN/A } else if (ldstQueue.violation(tid)) { 13444033Sktlim@umich.edu assert(inst->isMemRef()); 13452326SN/A // If there was an ordering violation, then get the 13462326SN/A // DynInst that caused the violation. Note that this 13472292SN/A // clears the violation signal. 13482292SN/A DynInstPtr violator; 13492292SN/A violator = ldstQueue.getMemDepViolator(tid); 13501062SN/A 13517720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13527720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13537720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 135411097Songal@cs.wisc.edu inst->pcState(), inst->seqNum, inst->physEffAddrLow); 13557720Sgblack@eecs.umich.edu 13563732Sktlim@umich.edu fetchRedirect[tid] = true; 13573732Sktlim@umich.edu 13581062SN/A // Tell the instruction queue that a violation has occured. 13591062SN/A instQueue.violation(inst, violator); 13601062SN/A 13611062SN/A // Squash. 13628513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13631062SN/A 13641062SN/A ++memOrderViolationEvents; 13651062SN/A } 13664033Sktlim@umich.edu } else { 13674033Sktlim@umich.edu // Reset any state associated with redirects that will not 13684033Sktlim@umich.edu // be used. 13694033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13704033Sktlim@umich.edu assert(inst->isMemRef()); 13714033Sktlim@umich.edu 13724033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13734033Sktlim@umich.edu 13744033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13757720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13767720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 137711097Songal@cs.wisc.edu inst->physEffAddrLow); 13784033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13794033Sktlim@umich.edu "already squashing\n"); 13804033Sktlim@umich.edu 13814033Sktlim@umich.edu ++memOrderViolationEvents; 13824033Sktlim@umich.edu } 13831062SN/A } 13841062SN/A } 13852292SN/A 13862348SN/A // Update and record activity if we processed any instructions. 13872292SN/A if (inst_num) { 13882292SN/A if (exeStatus == Idle) { 13892292SN/A exeStatus = Running; 13902292SN/A } 13912292SN/A 13922292SN/A updatedQueues = true; 13932292SN/A 13942292SN/A cpu->activityThisCycle(); 13952292SN/A } 13962292SN/A 13972292SN/A // Need to reset this in case a writeback event needs to write into the 13982292SN/A // iew queue. That way the writeback event will write into the correct 13992292SN/A // spot in the queue. 14002292SN/A wbNumInst = 0; 14017852SMatt.Horsnell@arm.com 14022107SN/A} 14032107SN/A 14042292SN/Atemplate <class Impl> 14052107SN/Avoid 14062292SN/ADefaultIEW<Impl>::writebackInsts() 14072107SN/A{ 14082326SN/A // Loop through the head of the time buffer and wake any 14092326SN/A // dependents. These instructions are about to write back. Also 14102326SN/A // mark scoreboard that this instruction is finally complete. 14112326SN/A // Either have IEW have direct access to scoreboard, or have this 14122326SN/A // as part of backwards communication. 14133958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14142292SN/A toCommit->insts[inst_num]; inst_num++) { 14152107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14166221Snate@binkert.org ThreadID tid = inst->threadNumber; 14172107SN/A 14187720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14197720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14202107SN/A 14212301SN/A iewInstsToCommit[tid]++; 142211246Sradhika.jagtap@ARM.com // Notify potential listeners that execution is complete for this 142311246Sradhika.jagtap@ARM.com // instruction. 142411246Sradhika.jagtap@ARM.com ppToCommit->notify(inst); 14252301SN/A 14262292SN/A // Some instructions will be sent to commit without having 14272292SN/A // executed because they need commit to handle them. 142810824SAndreas.Sandberg@ARM.com // E.g. Strictly ordered loads have not actually executed when they 14292292SN/A // are first sent to commit. Instead commit must tell the LSQ 143010824SAndreas.Sandberg@ARM.com // when it's ready to execute the strictly ordered load. 14312367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14322301SN/A int dependents = instQueue.wakeDependents(inst); 14332107SN/A 14342292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14352292SN/A //mark as Ready 143612105Snathanael.premillieu@arm.com DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 143712106SRekai.GonzalezAlberquilla@arm.com inst->renamedDestRegIdx(i)->index(), 143812106SRekai.GonzalezAlberquilla@arm.com inst->renamedDestRegIdx(i)->className()); 14392292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14402107SN/A } 14412301SN/A 14422348SN/A if (dependents) { 14432348SN/A producerInst[tid]++; 14442348SN/A consumerInst[tid]+= dependents; 14452348SN/A } 14462326SN/A writebackCount[tid]++; 14472107SN/A } 14482107SN/A } 14491060SN/A} 14501060SN/A 14511681SN/Atemplate<class Impl> 14521060SN/Avoid 14532292SN/ADefaultIEW<Impl>::tick() 14541060SN/A{ 14552292SN/A wbNumInst = 0; 14562292SN/A wbCycle = 0; 14571060SN/A 14582292SN/A wroteToTimeBuffer = false; 14592292SN/A updatedQueues = false; 14601060SN/A 14612292SN/A sortInsts(); 14621060SN/A 14632326SN/A // Free function units marked as being freed this cycle. 14642326SN/A fuPool->processFreeUnits(); 14651062SN/A 14666221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14676221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14681060SN/A 14692326SN/A // Check stall and squash signals, dispatch any instructions. 14703867Sbinkertn@umich.edu while (threads != end) { 14716221Snate@binkert.org ThreadID tid = *threads++; 14721060SN/A 14732292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14741060SN/A 14752292SN/A checkSignalsAndUpdate(tid); 14762292SN/A dispatch(tid); 14771060SN/A } 14781060SN/A 14792292SN/A if (exeStatus != Squashing) { 14802292SN/A executeInsts(); 14811060SN/A 14822292SN/A writebackInsts(); 14832292SN/A 14842292SN/A // Have the instruction queue try to schedule any ready instructions. 14852292SN/A // (In actuality, this scheduling is for instructions that will 14862292SN/A // be executed next cycle.) 14872292SN/A instQueue.scheduleReadyInsts(); 14882292SN/A 14892292SN/A // Also should advance its own time buffers if the stage ran. 14902292SN/A // Not the best place for it, but this works (hopefully). 14912292SN/A issueToExecQueue.advance(); 14922292SN/A } 14932292SN/A 14942292SN/A bool broadcast_free_entries = false; 14952292SN/A 14962292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14972292SN/A exeStatus = Idle; 14982292SN/A updateLSQNextCycle = false; 14992292SN/A 15002292SN/A broadcast_free_entries = true; 15012292SN/A } 15022292SN/A 15032292SN/A // Writeback any stores using any leftover bandwidth. 15041681SN/A ldstQueue.writebackStores(); 15051681SN/A 15061061SN/A // Check the committed load/store signals to see if there's a load 15071061SN/A // or store to commit. Also check if it's being told to execute a 15081061SN/A // nonspeculative instruction. 15091681SN/A // This is pretty inefficient... 15102292SN/A 15113867Sbinkertn@umich.edu threads = activeThreads->begin(); 15123867Sbinkertn@umich.edu while (threads != end) { 15136221Snate@binkert.org ThreadID tid = (*threads++); 15142292SN/A 15152292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15162292SN/A 15172348SN/A // Update structures based on instructions committed. 15182292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15192292SN/A !fromCommit->commitInfo[tid].squash && 15202292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15212292SN/A 15222292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15232292SN/A 15242292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15252292SN/A 15262292SN/A updateLSQNextCycle = true; 15272292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15282292SN/A } 15292292SN/A 15302292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15312292SN/A 15322292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 153310824SAndreas.Sandberg@ARM.com if (fromCommit->commitInfo[tid].strictlyOrdered) { 153410824SAndreas.Sandberg@ARM.com instQueue.replayMemInst( 153510824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad); 153610824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 15372292SN/A } else { 15382292SN/A instQueue.scheduleNonSpec( 15392292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15402292SN/A } 15412292SN/A } 15422292SN/A 15432292SN/A if (broadcast_free_entries) { 15442292SN/A toFetch->iewInfo[tid].iqCount = 15452292SN/A instQueue.getCount(tid); 15462292SN/A toFetch->iewInfo[tid].ldstqCount = 15472292SN/A ldstQueue.getCount(tid); 15482292SN/A 15492292SN/A toRename->iewInfo[tid].usedIQ = true; 15502292SN/A toRename->iewInfo[tid].freeIQEntries = 155110164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 15522292SN/A toRename->iewInfo[tid].usedLSQ = true; 155310239Sbinhpham@cs.rutgers.edu 155410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = 155510239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(tid); 155610239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = 155710239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeStoreEntries(tid); 15582292SN/A 15592292SN/A wroteToTimeBuffer = true; 15602292SN/A } 15612292SN/A 15622292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15632292SN/A tid, toRename->iewInfo[tid].dispatched); 15641061SN/A } 15651061SN/A 15662292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 156710239Sbinhpham@cs.rutgers.edu "LQ has %i free entries. SQ has %i free entries.\n", 15682292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 156910239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 15702292SN/A 15712292SN/A updateStatus(); 15722292SN/A 15732292SN/A if (wroteToTimeBuffer) { 15742292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15752292SN/A cpu->activityThisCycle(); 15761061SN/A } 15771060SN/A} 15781060SN/A 15792301SN/Atemplate <class Impl> 15801060SN/Avoid 158113429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 15821060SN/A{ 15836221Snate@binkert.org ThreadID tid = inst->threadNumber; 15841060SN/A 15852669Sktlim@umich.edu iewExecutedInsts++; 15861060SN/A 15878471SGiacomo.Gabrielli@arm.com#if TRACING_ON 15889527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 15899527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 15909527SMatt.Horsnell@arm.com } 15918471SGiacomo.Gabrielli@arm.com#endif 15928471SGiacomo.Gabrielli@arm.com 15932301SN/A // 15942301SN/A // Control operations 15952301SN/A // 15962301SN/A if (inst->isControl()) 15976221Snate@binkert.org iewExecutedBranches[tid]++; 15981060SN/A 15992301SN/A // 16002301SN/A // Memory operations 16012301SN/A // 16022301SN/A if (inst->isMemRef()) { 16036221Snate@binkert.org iewExecutedRefs[tid]++; 16041060SN/A 16052301SN/A if (inst->isLoad()) { 16066221Snate@binkert.org iewExecLoadInsts[tid]++; 16071060SN/A } 16081060SN/A } 16091060SN/A} 16107598Sminkyu.jeong@arm.com 16117598Sminkyu.jeong@arm.comtemplate <class Impl> 16127598Sminkyu.jeong@arm.comvoid 161313429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 16147598Sminkyu.jeong@arm.com{ 16157598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16167598Sminkyu.jeong@arm.com 16177598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16187852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16197598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16207598Sminkyu.jeong@arm.com 16217598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16227598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16237598Sminkyu.jeong@arm.com 16247598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16257598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16267720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16277598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16287720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16297720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16307598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16317598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16327598Sminkyu.jeong@arm.com 16337598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16347598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16357598Sminkyu.jeong@arm.com } else { 16367598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16377598Sminkyu.jeong@arm.com } 16387598Sminkyu.jeong@arm.com } 16397598Sminkyu.jeong@arm.com } 16407598Sminkyu.jeong@arm.com} 16419944Smatt.horsnell@ARM.com 16429944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1643