iew_impl.hh revision 10824
11689SN/A/* 22326SN/A * Copyright (c) 2010-2013 ARM Limited 31689SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * The license below extends only to copyright in the software and shall 71689SN/A * not be construed as granting a license to any other intellectual 81689SN/A * property including but not limited to intellectual property relating 91689SN/A * to a hardware implementation of the functionality of the software 101689SN/A * licensed hereunder. You may use the software subject to the license 111689SN/A * terms below provided that you ensure that this notice is replicated 121689SN/A * unmodified and in its entirety in all distributions of the software, 131689SN/A * modified or unmodified, in source code or in binary form. 141689SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292831Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322064SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354167Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381717SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 401061SN/A * 412292SN/A * Authors: Kevin Lim 422292SN/A */ 432292SN/A 442292SN/A#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 452326SN/A#define __CPU_O3_IEW_IMPL_IMPL_HH__ 461060SN/A 472292SN/A// @todo: Fix the instantaneous communication among all the stages within 482292SN/A// iew. There's a clear delay between issue and execute, yet backwards 492292SN/A// communication happens simultaneously. 502292SN/A 512292SN/A#include <queue> 522292SN/A 532292SN/A#include "arch/utility.hh" 542326SN/A#include "config/the_isa.hh" 552292SN/A#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 572292SN/A#include "cpu/o3/iew.hh" 582292SN/A#include "cpu/timebuf.hh" 592292SN/A#include "debug/Activity.hh" 602292SN/A#include "debug/Drain.hh" 612292SN/A#include "debug/IEW.hh" 622292SN/A#include "debug/O3PipeView.hh" 632292SN/A#include "params/DerivO3CPU.hh" 642292SN/A 652292SN/Ausing namespace std; 662292SN/A 672292SN/Atemplate<class Impl> 682669Sktlim@umich.eduDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692292SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 702292SN/A cpu(_cpu), 712292SN/A instQueue(_cpu, this, params), 722292SN/A ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772307SN/A dispatchWidth(params->dispatchWidth), 782307SN/A issueWidth(params->issueWidth), 792292SN/A wbWidth(params->wbWidth), 801060SN/A numThreads(params->numThreads) 811060SN/A{ 821060SN/A if (dispatchWidth > Impl::MaxWidth) 831060SN/A fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 841060SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 851060SN/A dispatchWidth, static_cast<int>(Impl::MaxWidth)); 862326SN/A if (issueWidth > Impl::MaxWidth) 871060SN/A fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 881060SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 891060SN/A issueWidth, static_cast<int>(Impl::MaxWidth)); 901060SN/A if (wbWidth > Impl::MaxWidth) 912292SN/A fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 922292SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 932292SN/A wbWidth, static_cast<int>(Impl::MaxWidth)); 942292SN/A 951060SN/A _status = Active; 961060SN/A exeStatus = Running; 972307SN/A wbStatus = Idle; 982292SN/A 992980Sgblack@eecs.umich.edu // Setup wire to read instructions coming from issue. 1002292SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1012292SN/A 1022292SN/A // Instruction queue needs the queue between issue and execute. 1032292SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1042292SN/A 1052292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1062292SN/A dispatchStatus[tid] = Running; 1072292SN/A fetchRedirect[tid] = false; 1082292SN/A } 1092292SN/A 1102292SN/A updateLSQNextCycle = false; 1112292SN/A 1122292SN/A skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1132292SN/A} 1142292SN/A 1152292SN/Atemplate <class Impl> 1162292SN/Astd::string 1172292SN/ADefaultIEW<Impl>::name() const 1182292SN/A{ 1192292SN/A return cpu->name() + ".iew"; 1202292SN/A} 1212292SN/A 1222292SN/Atemplate <class Impl> 1232292SN/Avoid 1242292SN/ADefaultIEW<Impl>::regProbePoints() 1254318Sktlim@umich.edu{ 1262831Sksewell@umich.edu ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1272292SN/A ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1284318Sktlim@umich.edu} 1292292SN/A 1302292SN/Atemplate <class Impl> 1312292SN/Avoid 1322292SN/ADefaultIEW<Impl>::regStats() 1332292SN/A{ 1342292SN/A using namespace Stats; 1352292SN/A 1362292SN/A instQueue.regStats(); 1372292SN/A ldstQueue.regStats(); 1382292SN/A 1392292SN/A iewIdleCycles 1402292SN/A .name(name() + ".iewIdleCycles") 1412292SN/A .desc("Number of cycles IEW is idle"); 1424318Sktlim@umich.edu 1432831Sksewell@umich.edu iewSquashCycles 1442292SN/A .name(name() + ".iewSquashCycles") 1454318Sktlim@umich.edu .desc("Number of cycles IEW is squashing"); 1462292SN/A 1472292SN/A iewBlockCycles 1482292SN/A .name(name() + ".iewBlockCycles") 1492292SN/A .desc("Number of cycles IEW is blocking"); 1502292SN/A 1512292SN/A iewUnblockCycles 1522292SN/A .name(name() + ".iewUnblockCycles") 1532292SN/A .desc("Number of cycles IEW is unblocking"); 1542292SN/A 1552326SN/A iewDispatchedInsts 1562348SN/A .name(name() + ".iewDispatchedInsts") 1572326SN/A .desc("Number of instructions dispatched to IQ"); 1582326SN/A 1592348SN/A iewDispSquashedInsts 1602292SN/A .name(name() + ".iewDispSquashedInsts") 1612292SN/A .desc("Number of squashed instructions skipped by dispatch"); 1622292SN/A 1632292SN/A iewDispLoadInsts 1642292SN/A .name(name() + ".iewDispLoadInsts") 1652292SN/A .desc("Number of dispatched load instructions"); 1662292SN/A 1671060SN/A iewDispStoreInsts 1681060SN/A .name(name() + ".iewDispStoreInsts") 1691061SN/A .desc("Number of dispatched store instructions"); 1701060SN/A 1711062SN/A iewDispNonSpecInsts 1721062SN/A .name(name() + ".iewDispNonSpecInsts") 1732301SN/A .desc("Number of dispatched non-speculative instructions"); 1741062SN/A 1751062SN/A iewIQFullEvents 1761062SN/A .name(name() + ".iewIQFullEvents") 1771062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1781062SN/A 1791062SN/A iewLSQFullEvents 1801062SN/A .name(name() + ".iewLSQFullEvents") 1811062SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1821062SN/A 1831062SN/A memOrderViolationEvents 1842301SN/A .name(name() + ".memOrderViolationEvents") 1852301SN/A .desc("Number of memory order violations"); 1862301SN/A 1872301SN/A predictedTakenIncorrect 1881062SN/A .name(name() + ".predictedTakenIncorrect") 1891062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1901062SN/A 1911062SN/A predictedNotTakenIncorrect 1921062SN/A .name(name() + ".predictedNotTakenIncorrect") 1931062SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1941062SN/A 1951062SN/A branchMispredicts 1961062SN/A .name(name() + ".branchMispredicts") 1971062SN/A .desc("Number of branch mispredicts detected at execute"); 1981062SN/A 1991062SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2001062SN/A 2011062SN/A iewExecutedInsts 2021062SN/A .name(name() + ".iewExecutedInsts") 2031062SN/A .desc("Number of executed instructions"); 2041062SN/A 2051062SN/A iewExecLoadInsts 2061062SN/A .init(cpu->numThreads) 2071062SN/A .name(name() + ".iewExecLoadInsts") 2081062SN/A .desc("Number of load instructions executed") 2091062SN/A .flags(total); 2101062SN/A 2111062SN/A iewExecSquashedInsts 2121062SN/A .name(name() + ".iewExecSquashedInsts") 2131062SN/A .desc("Number of squashed instructions skipped in execute"); 2141062SN/A 2151062SN/A iewExecutedSwp 2161062SN/A .init(cpu->numThreads) 2171062SN/A .name(name() + ".exec_swp") 2181062SN/A .desc("number of swp insts executed") 2191062SN/A .flags(total); 2201062SN/A 2211062SN/A iewExecutedNop 2221062SN/A .init(cpu->numThreads) 2231062SN/A .name(name() + ".exec_nop") 2241062SN/A .desc("number of nop insts executed") 2251062SN/A .flags(total); 2261062SN/A 2271062SN/A iewExecutedRefs 2281062SN/A .init(cpu->numThreads) 2291062SN/A .name(name() + ".exec_refs") 2301062SN/A .desc("number of memory reference insts executed") 2311062SN/A .flags(total); 2321062SN/A 2331062SN/A iewExecutedBranches 2341062SN/A .init(cpu->numThreads) 2352361SN/A .name(name() + ".exec_branches") 2362326SN/A .desc("Number of branches executed") 2372301SN/A .flags(total); 2382301SN/A 2392301SN/A iewExecStoreInsts 2402301SN/A .name(name() + ".exec_stores") 2412301SN/A .desc("Number of stores executed") 2422301SN/A .flags(total); 2432326SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2442301SN/A 2452361SN/A iewExecRate 2462326SN/A .name(name() + ".exec_rate") 2472307SN/A .desc("Inst execution rate") 2482301SN/A .flags(total); 2492301SN/A 2502307SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2512301SN/A 2522301SN/A iewInstsToCommit 2532301SN/A .init(cpu->numThreads) 2542301SN/A .name(name() + ".wb_sent") 2552301SN/A .desc("cumulative count of insts sent to commit") 2562301SN/A .flags(total); 2572301SN/A 2582301SN/A writebackCount 2592301SN/A .init(cpu->numThreads) 2602301SN/A .name(name() + ".wb_count") 2612301SN/A .desc("cumulative count of insts written-back") 2622301SN/A .flags(total); 2632326SN/A 2642301SN/A producerInst 2652301SN/A .init(cpu->numThreads) 2662301SN/A .name(name() + ".wb_producers") 2672301SN/A .desc("num instructions producing a value") 2682301SN/A .flags(total); 2692326SN/A 2702301SN/A consumerInst 2712301SN/A .init(cpu->numThreads) 2722301SN/A .name(name() + ".wb_consumers") 2732301SN/A .desc("num instructions consuming a value") 2742361SN/A .flags(total); 2752326SN/A 2762301SN/A wbPenalized 2772301SN/A .init(cpu->numThreads) 2782301SN/A .name(name() + ".wb_penalized") 2792301SN/A .desc("number of instrctions required to write to 'other' IQ") 2802301SN/A .flags(total); 2812301SN/A 2822301SN/A wbPenalizedRate 2832980Sgblack@eecs.umich.edu .name(name() + ".wb_penalized_rate") 2842301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2852326SN/A .flags(total); 2862301SN/A 2872361SN/A wbPenalizedRate = wbPenalized / writebackCount; 2882326SN/A 2892301SN/A wbFanout 2902301SN/A .name(name() + ".wb_fanout") 2912301SN/A .desc("average fanout of values written-back") 2922301SN/A .flags(total); 2932326SN/A 2942727Sktlim@umich.edu wbFanout = producerInst / consumerInst; 2952326SN/A 2962301SN/A wbRate 2972301SN/A .name(name() + ".wb_rate") 2982301SN/A .desc("insts written-back per cycle") 2992301SN/A .flags(total); 3002301SN/A wbRate = writebackCount / cpu->numCycles; 3012301SN/A} 3022326SN/A 3032301SN/Atemplate<class Impl> 3042301SN/Avoid 3052326SN/ADefaultIEW<Impl>::startupStage() 3062301SN/A{ 3072301SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3082301SN/A toRename->iewInfo[tid].usedIQ = true; 3092301SN/A toRename->iewInfo[tid].freeIQEntries = 3102301SN/A instQueue.numFreeEntries(tid); 3112301SN/A 3122326SN/A toRename->iewInfo[tid].usedLSQ = true; 3132301SN/A toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3142301SN/A toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3152301SN/A } 3162301SN/A 3172326SN/A // Initialize the checker's dcache port here 3182301SN/A if (cpu->checker) { 3192292SN/A cpu->checker->setDcachePort(&cpu->getDataPort()); 3202292SN/A } 3212292SN/A 3222292SN/A cpu->activateStage(O3CPU::IEWIdx); 3231062SN/A} 3241062SN/A 3251062SN/Atemplate<class Impl> 3261062SN/Avoid 3272307SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3281060SN/A{ 3292307SN/A timeBuffer = tb_ptr; 3302307SN/A 3312307SN/A // Setup wire to read information from time buffer, from commit. 3322307SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3332307SN/A 3341060SN/A // Setup wire to write information back to previous stages. 3352307SN/A toRename = timeBuffer->getWire(0); 3362307SN/A 3372307SN/A toFetch = timeBuffer->getWire(0); 3382307SN/A 3392307SN/A // Instruction queue also needs main time buffer. 3402307SN/A instQueue.setTimeBuffer(tb_ptr); 3412307SN/A} 3422307SN/A 3432307SN/Atemplate<class Impl> 3442307SN/Avoid 3452307SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3462307SN/A{ 3472307SN/A renameQueue = rq_ptr; 3482307SN/A 3492307SN/A // Setup wire to read information from rename queue. 3502307SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3512307SN/A} 3522307SN/A 3532307SN/Atemplate<class Impl> 3542307SN/Avoid 3552307SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3562307SN/A{ 3572307SN/A iewQueue = iq_ptr; 3582307SN/A 3591060SN/A // Setup wire to write instructions to commit. 3601060SN/A toCommit = iewQueue->getWire(0); 3611061SN/A} 3621060SN/A 3632980Sgblack@eecs.umich.edutemplate<class Impl> 3641060SN/Avoid 3652292SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3662064SN/A{ 3672064SN/A activeThreads = at_ptr; 3682064SN/A 3692064SN/A ldstQueue.setActiveThreads(at_ptr); 3702292SN/A instQueue.setActiveThreads(at_ptr); 3712064SN/A} 3724318Sktlim@umich.edu 3731060SN/Atemplate<class Impl> 3741060SN/Avoid 3751061SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3761060SN/A{ 3771060SN/A scoreboard = sb_ptr; 3781060SN/A} 3791060SN/A 3801060SN/Atemplate <class Impl> 3811060SN/Abool 3821060SN/ADefaultIEW<Impl>::isDrained() const 3831060SN/A{ 3841684SN/A bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3852307SN/A 3862307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3872307SN/A if (!insts[tid].empty()) { 3882367SN/A DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3892367SN/A drained = false; 3902367SN/A } 3912367SN/A if (!skidBuffer[tid].empty()) { 3922367SN/A DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3932367SN/A drained = false; 3942367SN/A } 3952307SN/A } 3962326SN/A 3972367SN/A // Also check the FU pool as instructions are "stored" in FU 3982307SN/A // completion events until they are done and not accounted for 3992307SN/A // above 4002307SN/A if (drained && !fuPool->isDrained()) { 4012307SN/A DPRINTF(Drain, "FU pool still busy.\n"); 4022307SN/A drained = false; 4032307SN/A } 4042307SN/A 4052307SN/A return drained; 4062307SN/A} 4072307SN/A 4082307SN/Atemplate <class Impl> 4092307SN/Avoid 4102307SN/ADefaultIEW<Impl>::drainSanityCheck() const 4112307SN/A{ 4122292SN/A assert(isDrained()); 4132292SN/A 4142292SN/A instQueue.drainSanityCheck(); 4152292SN/A ldstQueue.drainSanityCheck(); 4162292SN/A} 4172292SN/A 4182292SN/Atemplate <class Impl> 4192292SN/Avoid 4202292SN/ADefaultIEW<Impl>::takeOverFrom() 4212292SN/A{ 4222292SN/A // Reset all state. 4232292SN/A _status = Active; 4242292SN/A exeStatus = Running; 4252292SN/A wbStatus = Idle; 4262292SN/A 4272292SN/A instQueue.takeOverFrom(); 4283867Sbinkertn@umich.edu ldstQueue.takeOverFrom(); 4292292SN/A fuPool->takeOverFrom(); 4303867Sbinkertn@umich.edu 4313867Sbinkertn@umich.edu startupStage(); 4322292SN/A cpu->activityThisCycle(); 4333867Sbinkertn@umich.edu 4343867Sbinkertn@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 4353867Sbinkertn@umich.edu dispatchStatus[tid] = Running; 4362292SN/A fetchRedirect[tid] = false; 4373867Sbinkertn@umich.edu } 4382292SN/A 4393867Sbinkertn@umich.edu updateLSQNextCycle = false; 4402292SN/A 4412292SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4422292SN/A issueToExecQueue.advance(); 4432292SN/A } 4442292SN/A} 4452292SN/A 4461684SN/Atemplate<class Impl> 4471684SN/Avoid 4481684SN/ADefaultIEW<Impl>::squash(ThreadID tid) 4491684SN/A{ 4501684SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4511684SN/A 4522292SN/A // Tell the IQ to start squashing. 4532292SN/A instQueue.squash(tid); 4542292SN/A 4552292SN/A // Tell the LDSTQ to start squashing. 4562292SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4572292SN/A updatedQueues = true; 4582292SN/A 4591060SN/A // Clear the skid buffer in case it has any data in it. 4601060SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4611061SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4621060SN/A 4631060SN/A while (!skidBuffer[tid].empty()) { 4641060SN/A if (skidBuffer[tid].front()->isLoad()) { 4651060SN/A toRename->iewInfo[tid].dispatchedToLQ++; 4661060SN/A } 4671060SN/A if (skidBuffer[tid].front()->isStore()) { 4681060SN/A toRename->iewInfo[tid].dispatchedToSQ++; 4691060SN/A } 4701060SN/A 4711060SN/A toRename->iewInfo[tid].dispatched++; 4721061SN/A 4732292SN/A skidBuffer[tid].pop(); 4742292SN/A } 4752292SN/A 4762292SN/A emptyRenameInsts(tid); 4772292SN/A} 4782292SN/A 4792292SN/Atemplate<class Impl> 4802292SN/Avoid 4812292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4822292SN/A{ 4832292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4842292SN/A "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4852292SN/A 4862292SN/A if (!toCommit->squash[tid] || 4872292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4882292SN/A toCommit->squash[tid] = true; 4892292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4902292SN/A toCommit->branchTaken[tid] = inst->pcState().branching(); 4912292SN/A 4922292SN/A TheISA::PCState pc = inst->pcState(); 4932292SN/A TheISA::advancePC(pc, inst->staticInst); 4942292SN/A 4952292SN/A toCommit->pc[tid] = pc; 4962292SN/A toCommit->mispredictInst[tid] = inst; 4972292SN/A toCommit->includeSquashInst[tid] = false; 4982292SN/A 4992292SN/A wroteToTimeBuffer = true; 5002292SN/A } 5011060SN/A 5021061SN/A} 5031060SN/A 5041060SN/Atemplate<class Impl> 5051060SN/Avoid 5061060SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 5072326SN/A{ 5082326SN/A DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5091060SN/A "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5101060SN/A // Need to include inst->seqNum in the following comparison to cover the 5111060SN/A // corner case when a branch misprediction and a memory violation for the 5122292SN/A // same instruction (e.g. load PC) are detected in the same cycle. In this 5131060SN/A // case the memory violator should take precedence over the branch 5142064SN/A // misprediction because it requires the violator itself to be included in 5151060SN/A // the squash. 5162292SN/A if (!toCommit->squash[tid] || 5171060SN/A inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5181060SN/A toCommit->squash[tid] = true; 5191060SN/A 5201060SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5211060SN/A toCommit->pc[tid] = inst->pcState(); 5221060SN/A toCommit->mispredictInst[tid] = NULL; 5231060SN/A 5242326SN/A // Must include the memory violator in the squash. 5251060SN/A toCommit->includeSquashInst[tid] = true; 5261061SN/A 5272292SN/A wroteToTimeBuffer = true; 5281062SN/A } 5291062SN/A} 5301061SN/A 5311061SN/Atemplate<class Impl> 5321062SN/Avoid 5331060SN/ADefaultIEW<Impl>::block(ThreadID tid) 5342292SN/A{ 5352292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5361060SN/A 5371060SN/A if (dispatchStatus[tid] != Blocked && 5381060SN/A dispatchStatus[tid] != Unblocking) { 5391061SN/A toRename->iewBlock[tid] = true; 5401061SN/A wroteToTimeBuffer = true; 5412292SN/A } 5421061SN/A 5431061SN/A // Add the current inputs to the skid buffer so they can be 5441061SN/A // reprocessed when this stage unblocks. 5451061SN/A skidInsert(tid); 5462292SN/A 5471061SN/A dispatchStatus[tid] = Blocked; 5482292SN/A} 5491061SN/A 5502326SN/Atemplate<class Impl> 5512326SN/Avoid 5522326SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5532064SN/A{ 5541061SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5551061SN/A "buffer %u.\n",tid, tid); 5562292SN/A 5571061SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5582064SN/A // Also switch status to running. 5591061SN/A if (skidBuffer[tid].empty()) { 5602292SN/A toRename->iewUnblock[tid] = true; 5611061SN/A wroteToTimeBuffer = true; 5621061SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5631061SN/A dispatchStatus[tid] = Running; 5642326SN/A } 5651061SN/A} 5661061SN/A 5671061SN/Atemplate<class Impl> 5682292SN/Avoid 5692292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5701061SN/A{ 5711062SN/A instQueue.wakeDependents(inst); 5721062SN/A} 5732292SN/A 5742292SN/Atemplate<class Impl> 5752292SN/Avoid 5762292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5771061SN/A{ 5781061SN/A instQueue.rescheduleMemInst(inst); 5791061SN/A} 5801060SN/A 5812292SN/Atemplate<class Impl> 5821060SN/Avoid 5832292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5841060SN/A{ 5852292SN/A instQueue.replayMemInst(inst); 5862292SN/A} 5871060SN/A 5882064SN/Atemplate<class Impl> 5892333SN/Avoid 5902333SN/ADefaultIEW<Impl>::blockMemInst(DynInstPtr& inst) 5912333SN/A{ 5922333SN/A instQueue.blockMemInst(inst); 5932333SN/A} 5942333SN/A 5952333SN/Atemplate<class Impl> 5962333SN/Avoid 5971060SN/ADefaultIEW<Impl>::cacheUnblocked() 5982333SN/A{ 5992064SN/A instQueue.cacheUnblocked(); 6002292SN/A} 6012292SN/A 6022292SN/Atemplate<class Impl> 6032292SN/Avoid 6042292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6052292SN/A{ 6062292SN/A // This function should not be called after writebackInsts in a 6072292SN/A // single cycle. That will cause problems with an instruction 6082292SN/A // being added to the queue to commit without being processed by 6092292SN/A // writebackInsts prior to being sent to commit. 6102292SN/A 6112292SN/A // First check the time slot that this instruction will write 6122292SN/A // to. If there are free write ports at the time, then go ahead 6132292SN/A // and write the instruction to that time. If there are not, 6142292SN/A // keep looking back to see where's the first time there's a 6152292SN/A // free slot. 6162292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6172292SN/A ++wbNumInst; 6182292SN/A if (wbNumInst == wbWidth) { 6191060SN/A ++wbCycle; 6201060SN/A wbNumInst = 0; 6212292SN/A } 6222292SN/A } 6232292SN/A 6241060SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6252292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6262292SN/A // Add finished instruction to queue to commit. 6272292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6282292SN/A (*iewQueue)[wbCycle].size++; 6292292SN/A} 6302292SN/A 6312292SN/Atemplate <class Impl> 6322292SN/Aunsigned 6332292SN/ADefaultIEW<Impl>::validInstsFromRename() 6342292SN/A{ 6352292SN/A unsigned inst_count = 0; 6362292SN/A 6372292SN/A for (int i=0; i<fromRename->size; i++) { 6382292SN/A if (!fromRename->insts[i]->isSquashed()) 6392292SN/A inst_count++; 6402292SN/A } 6412292SN/A 6422292SN/A return inst_count; 6432292SN/A} 6442292SN/A 6452292SN/Atemplate<class Impl> 6461060SN/Avoid 6471060SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6482292SN/A{ 6491060SN/A DynInstPtr inst = NULL; 6501060SN/A 6512292SN/A while (!insts[tid].empty()) { 6522292SN/A inst = insts[tid].front(); 6532292SN/A 6542292SN/A insts[tid].pop(); 6552367SN/A 6562292SN/A DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6572292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6582307SN/A inst->pcState(),tid); 6592367SN/A 6602367SN/A skidBuffer[tid].push(inst); 6612307SN/A } 6622307SN/A 6632307SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6642292SN/A "Skidbuffer Exceeded Max Size"); 6652292SN/A} 6662326SN/A 6672326SN/Atemplate<class Impl> 6682292SN/Aint 6692326SN/ADefaultIEW<Impl>::skidCount() 6702326SN/A{ 6712326SN/A int max=0; 6722333SN/A 6732333SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6742292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6752292SN/A 6761061SN/A while (threads != end) { 6771061SN/A ThreadID tid = *threads++; 6781061SN/A unsigned thread_count = skidBuffer[tid].size(); 6791061SN/A if (max < thread_count) 6801060SN/A max = thread_count; 6811060SN/A } 6821060SN/A 6832292SN/A return max; 6842292SN/A} 6851060SN/A 6861060SN/Atemplate<class Impl> 6871060SN/Abool 6882292SN/ADefaultIEW<Impl>::skidsEmpty() 6892292SN/A{ 6902292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6912292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6922292SN/A 6932292SN/A while (threads != end) { 6942292SN/A ThreadID tid = *threads++; 6952292SN/A 6962292SN/A if (!skidBuffer[tid].empty()) 6972292SN/A return false; 6982292SN/A } 6991060SN/A 7002333SN/A return true; 7012820Sktlim@umich.edu} 7022326SN/A 7032292SN/Atemplate <class Impl> 7041060SN/Avoid 7052292SN/ADefaultIEW<Impl>::updateStatus() 7061060SN/A{ 7072292SN/A bool any_unblocking = false; 7081060SN/A 7092292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7101060SN/A list<ThreadID>::iterator end = activeThreads->end(); 7112292SN/A 7122292SN/A while (threads != end) { 7131060SN/A ThreadID tid = *threads++; 7142292SN/A 7152292SN/A if (dispatchStatus[tid] == Unblocking) { 7162292SN/A any_unblocking = true; 7172292SN/A break; 7182292SN/A } 7191060SN/A } 7201060SN/A 7212292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7221060SN/A // and there's no stores waiting to write back, and dispatch is not 7232292SN/A // unblocking, then there is no internal activity for the IEW stage. 7242292SN/A instQueue.intInstQueueReads++; 7252292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7261060SN/A !ldstQueue.willWB() && !any_unblocking) { 7271060SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7282326SN/A 7292326SN/A deactivateStage(); 7302301SN/A 7311060SN/A _status = Inactive; 7322326SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7332326SN/A ldstQueue.willWB() || 7341060SN/A any_unblocking)) { 7352326SN/A // Otherwise there is internal activity. Set to active. 7362326SN/A DPRINTF(IEW, "IEW switching to active\n"); 7371060SN/A 7381060SN/A activateStage(); 7391060SN/A 7402348SN/A _status = Active; 7412348SN/A } 7422326SN/A} 7432292SN/A 7442292SN/Atemplate <class Impl> 7452333SN/Avoid 7461060SN/ADefaultIEW<Impl>::resetEntries() 7472326SN/A{ 7482326SN/A instQueue.resetEntries(); 7492326SN/A ldstQueue.resetEntries(); 7502326SN/A} 7512292SN/A 7522292SN/Atemplate <class Impl> 7532326SN/Abool 7542326SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7552326SN/A{ 7561060SN/A bool ret_val(false); 7572326SN/A 7581060SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7592326SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7602292SN/A ret_val = true; 7612348SN/A } else if (instQueue.isFull(tid)) { 7622348SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7632326SN/A ret_val = true; 7642292SN/A } 7652292SN/A 7662326SN/A return ret_val; 7672292SN/A} 7681060SN/A 7691060SN/Atemplate <class Impl> 7702292SN/Avoid 7712292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7722301SN/A{ 7732292SN/A // Check if there's a squash signal, squash if there is 7741060SN/A // Check stall signals, block if there is. 7752292SN/A // If status was Blocked 7761061SN/A // if so then go to unblocking 7772292SN/A // If status was Squashing 7782292SN/A // check if squashing is not high. Switch to running this cycle. 7792292SN/A 7802292SN/A if (fromCommit->commitInfo[tid].squash) { 7812292SN/A squash(tid); 7821060SN/A 7831060SN/A if (dispatchStatus[tid] == Blocked || 7842064SN/A dispatchStatus[tid] == Unblocking) { 7852292SN/A toRename->iewUnblock[tid] = true; 7862064SN/A wroteToTimeBuffer = true; 7872292SN/A } 7882292SN/A 7892292SN/A dispatchStatus[tid] = Squashing; 7902292SN/A fetchRedirect[tid] = false; 7912301SN/A return; 7922731Sktlim@umich.edu } 7932292SN/A 7942301SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7952292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7962292SN/A 7972292SN/A dispatchStatus[tid] = Squashing; 7982326SN/A emptyRenameInsts(tid); 7992820Sktlim@umich.edu wroteToTimeBuffer = true; 8002292SN/A } 8012326SN/A 8022326SN/A if (checkStall(tid)) { 8032292SN/A block(tid); 8041060SN/A dispatchStatus[tid] = Blocked; 8051060SN/A return; 8061062SN/A } 8072326SN/A 8082326SN/A if (dispatchStatus[tid] == Blocked) { 8092307SN/A // Status from previous cycle was blocked, but there are no more stall 8102348SN/A // conditions. Switch over to unblocking. 8112292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8122292SN/A tid); 8132292SN/A 8142292SN/A dispatchStatus[tid] = Unblocking; 8152292SN/A 8161060SN/A unblock(tid); 8171060SN/A 8181061SN/A return; 8191060SN/A } 8201061SN/A 8211060SN/A if (dispatchStatus[tid] == Squashing) { 8222292SN/A // Switch status to running if rename isn't being told to block or 8232292SN/A // squash this cycle. 8241062SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8252292SN/A tid); 8261060SN/A 8271061SN/A dispatchStatus[tid] = Running; 8281060SN/A 8292292SN/A return; 8302292SN/A } 8314033Sktlim@umich.edu} 8324033Sktlim@umich.edu 8331061SN/Atemplate <class Impl> 8341060SN/Avoid 8351062SN/ADefaultIEW<Impl>::sortInsts() 8361062SN/A{ 8371062SN/A int insts_from_rename = fromRename->size; 8382292SN/A#ifdef DEBUG 8391062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8401060SN/A assert(insts[tid].empty()); 8412292SN/A#endif 8422292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8431061SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8441060SN/A } 8451060SN/A} 8461061SN/A 8471061SN/Atemplate <class Impl> 8482292SN/Avoid 8492292SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8502292SN/A{ 8512292SN/A DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8522292SN/A 8532292SN/A while (!insts[tid].empty()) { 8542292SN/A 8552292SN/A if (insts[tid].front()->isLoad()) { 8562292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 8572292SN/A } 8582292SN/A if (insts[tid].front()->isStore()) { 8592292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 8602292SN/A } 8612292SN/A 8622292SN/A toRename->iewInfo[tid].dispatched++; 8632292SN/A 8642292SN/A insts[tid].pop(); 8652301SN/A } 8661684SN/A} 8671684SN/A 8682301SN/Atemplate <class Impl> 8692301SN/Avoid 8702292SN/ADefaultIEW<Impl>::wakeCPU() 8712292SN/A{ 8722292SN/A cpu->wakeCPU(); 8731684SN/A} 8741684SN/A 8752292SN/Atemplate <class Impl> 8762326SN/Avoid 8772326SN/ADefaultIEW<Impl>::activityThisCycle() 8782326SN/A{ 8792326SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8801684SN/A cpu->activityThisCycle(); 8812292SN/A} 8822292SN/A 8832292SN/Atemplate <class Impl> 8842292SN/Ainline void 8852292SN/ADefaultIEW<Impl>::activateStage() 8861684SN/A{ 8871684SN/A DPRINTF(Activity, "Activating stage.\n"); 8881684SN/A cpu->activateStage(O3CPU::IEWIdx); 8891684SN/A} 8901684SN/A 8911684SN/Atemplate <class Impl> 8921684SN/Ainline void 8931684SN/ADefaultIEW<Impl>::deactivateStage() 8941684SN/A{ 8951684SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8961684SN/A cpu->deactivateStage(O3CPU::IEWIdx); 8971684SN/A} 8981684SN/A 8991684SN/Atemplate<class Impl> 9001684SN/Avoid 9011684SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9022292SN/A{ 9031684SN/A // If status is Running or idle, 9041684SN/A // call dispatchInsts() 9052326SN/A // If status is Unblocking, 9062326SN/A // buffer any instructions coming from rename 9072326SN/A // continue trying to empty skid buffer 9081684SN/A // check if stall conditions have passed 9092326SN/A 9102292SN/A if (dispatchStatus[tid] == Blocked) { 9112326SN/A ++iewBlockCycles; 9121684SN/A 9131684SN/A } else if (dispatchStatus[tid] == Squashing) { 9142326SN/A ++iewSquashCycles; 9152326SN/A } 9162326SN/A 9172326SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9181684SN/A // will allow, as long as it is not currently blocked. 9192326SN/A if (dispatchStatus[tid] == Running || 9201684SN/A dispatchStatus[tid] == Idle) { 9212326SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9221684SN/A "dispatch.\n", tid); 9232301SN/A 9241684SN/A dispatchInsts(tid); 9251684SN/A } else if (dispatchStatus[tid] == Unblocking) { 9262326SN/A // Make sure that the skid buffer has something in it if the 9272326SN/A // status is unblocking. 9282326SN/A assert(!skidsEmpty()); 9292326SN/A 9301684SN/A // If the status was unblocking, then instructions from the skid 9311684SN/A // buffer were used. Remove those instructions and handle 9321684SN/A // the rest of unblocking. 9331684SN/A dispatchInsts(tid); 9342301SN/A 9352064SN/A ++iewUnblockCycles; 9362064SN/A 9372064SN/A if (validInstsFromRename()) { 9382064SN/A // Add the current inputs to the skid buffer so they can be 9392292SN/A // reprocessed when this stage unblocks. 9402064SN/A skidInsert(tid); 9412292SN/A } 9422292SN/A 9432292SN/A unblock(tid); 9442292SN/A } 9452326SN/A} 9462326SN/A 9472326SN/Atemplate <class Impl> 9482326SN/Avoid 9492326SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9502326SN/A{ 9512326SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9522326SN/A // otherwise. 9532326SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9542326SN/A dispatchStatus[tid] == Unblocking ? 9552292SN/A skidBuffer[tid] : insts[tid]; 9562292SN/A 9572292SN/A int insts_to_add = insts_to_dispatch.size(); 9582064SN/A 9592064SN/A DynInstPtr inst; 9602064SN/A bool add_to_iq = false; 9612064SN/A int dis_num_inst = 0; 9622292SN/A 9632064SN/A // Loop through the instructions, putting them in the instruction 9644033Sktlim@umich.edu // queue. 9654033Sktlim@umich.edu for ( ; dis_num_inst < insts_to_add && 9662292SN/A dis_num_inst < dispatchWidth; 9672064SN/A ++dis_num_inst) 9682064SN/A { 9692064SN/A inst = insts_to_dispatch.front(); 9702064SN/A 9712292SN/A if (dispatchStatus[tid] == Unblocking) { 9722064SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9732292SN/A "buffer\n", tid); 9742292SN/A } 9752292SN/A 9762292SN/A // Make sure there's a valid instruction there. 9772292SN/A assert(inst); 9782292SN/A 9792292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9802292SN/A "IQ.\n", 9812292SN/A tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9822292SN/A 9832292SN/A // Be sure to mark these instructions as ready so that the 9842292SN/A // commit stage can go ahead and execute them, and mark 9852292SN/A // them as issued so the IQ doesn't reprocess them. 9862292SN/A 9872292SN/A // Check for squashed instructions. 9882292SN/A if (inst->isSquashed()) { 9892292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9902292SN/A "not adding to IQ.\n", tid); 9911684SN/A 9921684SN/A ++iewDispSquashedInsts; 9931684SN/A 9941684SN/A insts_to_dispatch.pop(); 9951061SN/A 9961061SN/A //Tell Rename That An Instruction has been processed 9971061SN/A if (inst->isLoad()) { 9982292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 9991061SN/A } 10001061SN/A if (inst->isStore()) { 10011061SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10021060SN/A } 10032292SN/A 10041060SN/A toRename->iewInfo[tid].dispatched++; 10052292SN/A 10062292SN/A continue; 10071060SN/A } 10081060SN/A 10091060SN/A // Check for full conditions. 10103093Sksewell@umich.edu if (instQueue.isFull(tid)) { 10113093Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10123093Sksewell@umich.edu 10132292SN/A // Call function to start blocking. 10142935Sksewell@umich.edu block(tid); 10151060SN/A 10161681SN/A // Set unblock to false. Special case where we are using 10172292SN/A // skidbuffer (unblocking) instructions but then we still 10182292SN/A // get full in the IQ. 10191681SN/A toRename->iewUnblock[tid] = false; 10201061SN/A 10211061SN/A ++iewIQFullEvents; 10222292SN/A break; 10231060SN/A } 10241060SN/A 10251061SN/A // Check LSQ if inst is LD/ST 10261061SN/A if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 10272292SN/A (inst->isStore() && ldstQueue.sqFull(tid))) { 10281061SN/A DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 10292326SN/A inst->isLoad() ? "LQ" : "SQ"); 10302326SN/A 10312326SN/A // Call function to start blocking. 10321061SN/A block(tid); 10332292SN/A 10342292SN/A // Set unblock to false. Special case where we are using 10351061SN/A // skidbuffer (unblocking) instructions but then we still 10361061SN/A // get full in the IQ. 10371061SN/A toRename->iewUnblock[tid] = false; 10382326SN/A 10392326SN/A ++iewLSQFullEvents; 10402292SN/A break; 10412326SN/A } 10421061SN/A 10431061SN/A // Otherwise issue the instruction just fine. 10441061SN/A if (inst->isLoad()) { 10452292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10462292SN/A "encountered, adding to LSQ.\n", tid); 10472326SN/A 10482292SN/A // Reserve a spot in the load store queue for this 10492292SN/A // memory access. 10502292SN/A ldstQueue.insertLoad(inst); 10512292SN/A 10522292SN/A ++iewDispLoadInsts; 10532292SN/A 10541062SN/A add_to_iq = true; 10552367SN/A 10562367SN/A toRename->iewInfo[tid].dispatchedToLQ++; 10572367SN/A } else if (inst->isStore()) { 10582367SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10591061SN/A "encountered, adding to LSQ.\n", tid); 10602292SN/A 10612336SN/A ldstQueue.insertStore(inst); 10622292SN/A 10632292SN/A ++iewDispStoreInsts; 10641061SN/A 10651061SN/A if (inst->isStoreConditional()) { 10661681SN/A // Store conditionals need to be set as "canCommit()" 10671061SN/A // so that commit can process them when they reach the 10681061SN/A // head of commit. 10691061SN/A // @todo: This is somewhat specific to Alpha. 10701061SN/A inst->setCanCommit(); 10711061SN/A instQueue.insertNonSpec(inst); 10722326SN/A add_to_iq = false; 10732326SN/A 10742326SN/A ++iewDispNonSpecInsts; 10752326SN/A } else { 10762326SN/A add_to_iq = true; 10772326SN/A } 10782326SN/A 10792326SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10802292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10811061SN/A // Same as non-speculative stores. 10821061SN/A inst->setCanCommit(); 10832326SN/A instQueue.insertBarrier(inst); 10841061SN/A add_to_iq = false; 10851062SN/A } else if (inst->isNop()) { 10862292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10871062SN/A "skipping.\n", tid); 10881061SN/A 10894033Sktlim@umich.edu inst->setIssued(); 10904033Sktlim@umich.edu inst->setExecuted(); 10912292SN/A inst->setCanCommit(); 10922292SN/A 10932292SN/A instQueue.recordProducer(inst); 10944033Sktlim@umich.edu 10954033Sktlim@umich.edu iewExecutedNop[tid]++; 10964033Sktlim@umich.edu 10971062SN/A add_to_iq = false; 10984033Sktlim@umich.edu } else { 10991681SN/A assert(!inst->isExecuted()); 11004033Sktlim@umich.edu add_to_iq = true; 11011062SN/A } 11024033Sktlim@umich.edu 11034033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11041061SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11051061SN/A "encountered, skipping.\n", tid); 11061061SN/A 11071061SN/A // Same as non-speculative stores. 11081061SN/A inst->setCanCommit(); 11091061SN/A 11101061SN/A // Specifically insert it as nonspeculative. 11112292SN/A instQueue.insertNonSpec(inst); 11122292SN/A 11131681SN/A ++iewDispNonSpecInsts; 11141681SN/A 11152731Sktlim@umich.edu add_to_iq = false; 11162292SN/A } 11172292SN/A 11182292SN/A // If the instruction queue is not full, then add the 11191681SN/A // instruction. 11201681SN/A if (add_to_iq) { 11211061SN/A instQueue.insert(inst); 11221061SN/A } 11232326SN/A 11241062SN/A insts_to_dispatch.pop(); 11251061SN/A 11261060SN/A toRename->iewInfo[tid].dispatched++; 11271060SN/A 11281061SN/A ++iewDispatchedInsts; 11291060SN/A 11301061SN/A#if TRACING_ON 11311060SN/A inst->dispatchTick = curTick() - inst->fetchTick; 11321060SN/A#endif 11331060SN/A ppDispatch->notify(inst); 11341060SN/A } 11351060SN/A 11361060SN/A if (!insts_to_dispatch.empty()) { 11371060SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11381060SN/A block(tid); 11391060SN/A toRename->iewUnblock[tid] = false; 11401060SN/A } 11411060SN/A 11421060SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11431060SN/A dispatchStatus[tid] = Running; 11441060SN/A 11451060SN/A updatedQueues = true; 11461060SN/A } 11471060SN/A 11481060SN/A dis_num_inst = 0; 11491061SN/A} 11501061SN/A 11511061SN/Atemplate <class Impl> 11522292SN/Avoid 11531060SN/ADefaultIEW<Impl>::printAvailableInsts() 11541060SN/A{ 11551060SN/A int inst = 0; 11562326SN/A 11571060SN/A std::cout << "Available Instructions: "; 11581060SN/A 11591060SN/A while (fromIssue->insts[inst]) { 11601060SN/A 11611060SN/A if (inst%3==0) std::cout << "\n\t"; 11622292SN/A 11631060SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11641060SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11651060SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11662326SN/A 11671060SN/A inst++; 11681060SN/A 11691060SN/A } 11701060SN/A 11711060SN/A std::cout << "\n"; 11721060SN/A} 11731060SN/A 11741061SN/Atemplate <class Impl> 11751060SN/Avoid 11762326SN/ADefaultIEW<Impl>::executeInsts() 11771060SN/A{ 11782326SN/A wbNumInst = 0; 11792326SN/A wbCycle = 0; 11802326SN/A 11812326SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 11821060SN/A list<ThreadID>::iterator end = activeThreads->end(); 11831060SN/A 11841060SN/A while (threads != end) { 11851060SN/A ThreadID tid = *threads++; 11861060SN/A fetchRedirect[tid] = false; 11871060SN/A } 11881061SN/A 11891061SN/A // Uncomment this if you want to see all available instructions. 11901061SN/A // @todo This doesn't actually work anymore, we should fix it. 11911061SN/A// printAvailableInsts(); 11921061SN/A 11931061SN/A // Execute/writeback any instructions that are available. 11941061SN/A int insts_to_execute = fromIssue->size; 11951061SN/A int inst_num = 0; 11961060SN/A for (; inst_num < insts_to_execute; 11971060SN/A ++inst_num) { 11982326SN/A 11992326SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12002292SN/A 12012064SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12021062SN/A 12032326SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12041062SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12051060SN/A 12061060SN/A // Check if the instruction is squashed; if so then skip it 12071060SN/A if (inst->isSquashed()) { 12081060SN/A DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12091060SN/A " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12101061SN/A inst->seqNum); 12111060SN/A 12121061SN/A // Consider this instruction executed so that commit can go 12131060SN/A // ahead and retire the instruction. 12142326SN/A inst->setExecuted(); 12151060SN/A 12161060SN/A // Not sure if I should set this here or just let commit try to 12171061SN/A // commit any squashed instructions. I like the latter a bit more. 12181060SN/A inst->setCanCommit(); 12192292SN/A 12201061SN/A ++iewExecSquashedInsts; 12212292SN/A 12221061SN/A continue; 12231062SN/A } 12241062SN/A 12252292SN/A Fault fault = NoFault; 12261062SN/A 12272292SN/A // Execute instruction. 12282292SN/A // Note that if the instruction faults, it will be handled 12291062SN/A // at the commit stage. 12302292SN/A if (inst->isMemRef()) { 12311061SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12322292SN/A "reference.\n"); 12332292SN/A 12342292SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12351061SN/A if (inst->isLoad()) { 12362292SN/A // Loads will mark themselves as executed, and their writeback 12371061SN/A // event adds the instruction to the queue to commit 12382326SN/A fault = ldstQueue.executeLoad(inst); 12392326SN/A 12402326SN/A if (inst->isTranslationDelayed() && 12412326SN/A fault == NoFault) { 12422326SN/A // A hw page table walk is currently going on; the 12432326SN/A // instruction must be deferred. 12442326SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12452326SN/A "load.\n"); 12461060SN/A instQueue.deferMemInst(inst); 12471060SN/A continue; 12481060SN/A } 12491060SN/A 12501061SN/A if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12511061SN/A inst->fault = NoFault; 12521061SN/A } 12531061SN/A } else if (inst->isStore()) { 12542698Sktlim@umich.edu fault = ldstQueue.executeStore(inst); 12552292SN/A 12562292SN/A if (inst->isTranslationDelayed() && 12572292SN/A fault == NoFault) { 12582698Sktlim@umich.edu // A hw page table walk is currently going on; the 12591061SN/A // instruction must be deferred. 12601061SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12612292SN/A "store.\n"); 12622292SN/A instQueue.deferMemInst(inst); 12631681SN/A continue; 12642292SN/A } 12652292SN/A 12662292SN/A // If the store had a fault then it may not have a mem req 12672292SN/A if (fault != NoFault || !inst->readPredicate() || 12682292SN/A !inst->isStoreConditional()) { 12692292SN/A // If the instruction faulted, then we need to send it along 12702292SN/A // to commit without the instruction completing. 12712292SN/A // Send this instruction to commit, also make sure iew stage 12722292SN/A // realizes there is activity. 12732292SN/A inst->setExecuted(); 12742292SN/A instToCommit(inst); 12752292SN/A activityThisCycle(); 12762292SN/A } 12771061SN/A 12781061SN/A // Store conditionals will mark themselves as 12791061SN/A // executed, and their writeback event will add the 12801061SN/A // instruction to the queue to commit. 12812292SN/A } else { 12822292SN/A panic("Unexpected memory type!\n"); 12832292SN/A } 12841681SN/A 12851681SN/A } else { 12861681SN/A // If the instruction has already faulted, then skip executing it. 12871681SN/A // Such case can happen when it faulted during ITLB translation. 12881061SN/A // If we execute the instruction (even if it's a nop) the fault 12891061SN/A // will be replaced and we will lose it. 12902292SN/A if (inst->getFault() == NoFault) { 12912292SN/A inst->execute(); 12921061SN/A if (!inst->readPredicate()) 12932292SN/A inst->forwardOldRegs(); 12942292SN/A } 12951061SN/A 12961061SN/A inst->setExecuted(); 12971061SN/A 12982292SN/A instToCommit(inst); 12992292SN/A } 13001061SN/A 13011061SN/A updateExeInstStats(inst); 13021061SN/A 13032292SN/A // Check if branch prediction was correct, if not then we need 13042292SN/A // to tell commit to squash in flight instructions. Only 13052292SN/A // handle this if there hasn't already been something that 13061061SN/A // redirects fetch in this group of instructions. 13071061SN/A 13081061SN/A // This probably needs to prioritize the redirects if a different 13091061SN/A // scheduler is used. Currently the scheduler schedules the oldest 13101061SN/A // instruction first, so the branch resolution order will be correct. 13112292SN/A ThreadID tid = inst->threadNumber; 13122292SN/A 13132292SN/A if (!fetchRedirect[tid] || 13142292SN/A !toCommit->squash[tid] || 13152292SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 13162292SN/A 13172292SN/A // Prevent testing for misprediction on load instructions, 13182292SN/A // that have not been executed. 13192292SN/A bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13202292SN/A 13212292SN/A if (inst->mispredicted() && !loadNotExecuted) { 13222292SN/A fetchRedirect[tid] = true; 13232292SN/A 13242292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13252292SN/A DPRINTF(IEW, "Predicted target was PC: %s.\n", 13261061SN/A inst->readPredTarg()); 13272292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13282292SN/A inst->pcState()); 13292292SN/A // If incorrect, then signal the ROB that it must be squashed. 13302292SN/A squashDueToBranch(inst, tid); 13312292SN/A 13322292SN/A ppMispredict->notify(inst); 13332292SN/A 13342292SN/A if (inst->readPredTaken()) { 13352292SN/A predictedTakenIncorrect++; 13362292SN/A } else { 13372292SN/A predictedNotTakenIncorrect++; 13382292SN/A } 13392292SN/A } else if (ldstQueue.violation(tid)) { 13402292SN/A assert(inst->isMemRef()); 13412292SN/A // If there was an ordering violation, then get the 13422292SN/A // DynInst that caused the violation. Note that this 13432292SN/A // clears the violation signal. 13442292SN/A DynInstPtr violator; 13452292SN/A violator = ldstQueue.getMemDepViolator(tid); 13462292SN/A 13472292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13482326SN/A "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13492326SN/A violator->pcState(), violator->seqNum, 13502292SN/A inst->pcState(), inst->seqNum, inst->physEffAddr); 13512292SN/A 13522292SN/A fetchRedirect[tid] = true; 13532292SN/A 13542292SN/A // Tell the instruction queue that a violation has occured. 13552292SN/A instQueue.violation(inst, violator); 13562292SN/A 13572292SN/A // Squash. 13582292SN/A squashDueToMemOrder(violator, tid); 13592292SN/A 13602292SN/A ++memOrderViolationEvents; 13612292SN/A } 13622292SN/A } else { 13632292SN/A // Reset any state associated with redirects that will not 13642292SN/A // be used. 13652292SN/A if (ldstQueue.violation(tid)) { 13662292SN/A assert(inst->isMemRef()); 13672292SN/A 13682292SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13692292SN/A 13702292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13712292SN/A "%s, inst PC: %s. Addr is: %#x.\n", 13722292SN/A violator->pcState(), inst->pcState(), 13732348SN/A inst->physEffAddr); 13742348SN/A DPRINTF(IEW, "Violation will not be handled because " 13752348SN/A "already squashing\n"); 13762348SN/A 13772348SN/A ++memOrderViolationEvents; 13782348SN/A } 13792348SN/A } 13802348SN/A } 13812348SN/A 13822348SN/A // Update and record activity if we processed any instructions. 13832348SN/A if (inst_num) { 13842348SN/A if (exeStatus == Idle) { 13852348SN/A exeStatus = Running; 13862348SN/A } 13872348SN/A 13882348SN/A updatedQueues = true; 13892348SN/A 13902348SN/A cpu->activityThisCycle(); 13912348SN/A } 13922348SN/A 13932348SN/A // Need to reset this in case a writeback event needs to write into the 13942348SN/A // iew queue. That way the writeback event will write into the correct 13952348SN/A // spot in the queue. 13962348SN/A wbNumInst = 0; 13972348SN/A 13982348SN/A} 13992348SN/A 14002348SN/Atemplate <class Impl> 14012348SN/Avoid 14022348SN/ADefaultIEW<Impl>::writebackInsts() 14032348SN/A{ 14042348SN/A // Loop through the head of the time buffer and wake any 14052348SN/A // dependents. These instructions are about to write back. Also 14062348SN/A // mark scoreboard that this instruction is finally complete. 14072348SN/A // Either have IEW have direct access to scoreboard, or have this 14082348SN/A // as part of backwards communication. 14092348SN/A for (int inst_num = 0; inst_num < wbWidth && 14102348SN/A toCommit->insts[inst_num]; inst_num++) { 14112348SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14122348SN/A ThreadID tid = inst->threadNumber; 14132348SN/A 14142292SN/A DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1415 inst->seqNum, inst->pcState()); 1416 1417 iewInstsToCommit[tid]++; 1418 1419 // Some instructions will be sent to commit without having 1420 // executed because they need commit to handle them. 1421 // E.g. Strictly ordered loads have not actually executed when they 1422 // are first sent to commit. Instead commit must tell the LSQ 1423 // when it's ready to execute the strictly ordered load. 1424 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1425 int dependents = instQueue.wakeDependents(inst); 1426 1427 for (int i = 0; i < inst->numDestRegs(); i++) { 1428 //mark as Ready 1429 DPRINTF(IEW,"Setting Destination Register %i\n", 1430 inst->renamedDestRegIdx(i)); 1431 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1432 } 1433 1434 if (dependents) { 1435 producerInst[tid]++; 1436 consumerInst[tid]+= dependents; 1437 } 1438 writebackCount[tid]++; 1439 } 1440 } 1441} 1442 1443template<class Impl> 1444void 1445DefaultIEW<Impl>::tick() 1446{ 1447 wbNumInst = 0; 1448 wbCycle = 0; 1449 1450 wroteToTimeBuffer = false; 1451 updatedQueues = false; 1452 1453 sortInsts(); 1454 1455 // Free function units marked as being freed this cycle. 1456 fuPool->processFreeUnits(); 1457 1458 list<ThreadID>::iterator threads = activeThreads->begin(); 1459 list<ThreadID>::iterator end = activeThreads->end(); 1460 1461 // Check stall and squash signals, dispatch any instructions. 1462 while (threads != end) { 1463 ThreadID tid = *threads++; 1464 1465 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1466 1467 checkSignalsAndUpdate(tid); 1468 dispatch(tid); 1469 } 1470 1471 if (exeStatus != Squashing) { 1472 executeInsts(); 1473 1474 writebackInsts(); 1475 1476 // Have the instruction queue try to schedule any ready instructions. 1477 // (In actuality, this scheduling is for instructions that will 1478 // be executed next cycle.) 1479 instQueue.scheduleReadyInsts(); 1480 1481 // Also should advance its own time buffers if the stage ran. 1482 // Not the best place for it, but this works (hopefully). 1483 issueToExecQueue.advance(); 1484 } 1485 1486 bool broadcast_free_entries = false; 1487 1488 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1489 exeStatus = Idle; 1490 updateLSQNextCycle = false; 1491 1492 broadcast_free_entries = true; 1493 } 1494 1495 // Writeback any stores using any leftover bandwidth. 1496 ldstQueue.writebackStores(); 1497 1498 // Check the committed load/store signals to see if there's a load 1499 // or store to commit. Also check if it's being told to execute a 1500 // nonspeculative instruction. 1501 // This is pretty inefficient... 1502 1503 threads = activeThreads->begin(); 1504 while (threads != end) { 1505 ThreadID tid = (*threads++); 1506 1507 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1508 1509 // Update structures based on instructions committed. 1510 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1511 !fromCommit->commitInfo[tid].squash && 1512 !fromCommit->commitInfo[tid].robSquashing) { 1513 1514 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1515 1516 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1517 1518 updateLSQNextCycle = true; 1519 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1520 } 1521 1522 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1523 1524 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1525 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1526 instQueue.replayMemInst( 1527 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1528 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1529 } else { 1530 instQueue.scheduleNonSpec( 1531 fromCommit->commitInfo[tid].nonSpecSeqNum); 1532 } 1533 } 1534 1535 if (broadcast_free_entries) { 1536 toFetch->iewInfo[tid].iqCount = 1537 instQueue.getCount(tid); 1538 toFetch->iewInfo[tid].ldstqCount = 1539 ldstQueue.getCount(tid); 1540 1541 toRename->iewInfo[tid].usedIQ = true; 1542 toRename->iewInfo[tid].freeIQEntries = 1543 instQueue.numFreeEntries(tid); 1544 toRename->iewInfo[tid].usedLSQ = true; 1545 1546 toRename->iewInfo[tid].freeLQEntries = 1547 ldstQueue.numFreeLoadEntries(tid); 1548 toRename->iewInfo[tid].freeSQEntries = 1549 ldstQueue.numFreeStoreEntries(tid); 1550 1551 wroteToTimeBuffer = true; 1552 } 1553 1554 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1555 tid, toRename->iewInfo[tid].dispatched); 1556 } 1557 1558 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1559 "LQ has %i free entries. SQ has %i free entries.\n", 1560 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1561 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1562 1563 updateStatus(); 1564 1565 if (wroteToTimeBuffer) { 1566 DPRINTF(Activity, "Activity this cycle.\n"); 1567 cpu->activityThisCycle(); 1568 } 1569} 1570 1571template <class Impl> 1572void 1573DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1574{ 1575 ThreadID tid = inst->threadNumber; 1576 1577 iewExecutedInsts++; 1578 1579#if TRACING_ON 1580 if (DTRACE(O3PipeView)) { 1581 inst->completeTick = curTick() - inst->fetchTick; 1582 } 1583#endif 1584 1585 // 1586 // Control operations 1587 // 1588 if (inst->isControl()) 1589 iewExecutedBranches[tid]++; 1590 1591 // 1592 // Memory operations 1593 // 1594 if (inst->isMemRef()) { 1595 iewExecutedRefs[tid]++; 1596 1597 if (inst->isLoad()) { 1598 iewExecLoadInsts[tid]++; 1599 } 1600 } 1601} 1602 1603template <class Impl> 1604void 1605DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1606{ 1607 ThreadID tid = inst->threadNumber; 1608 1609 if (!fetchRedirect[tid] || 1610 !toCommit->squash[tid] || 1611 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1612 1613 if (inst->mispredicted()) { 1614 fetchRedirect[tid] = true; 1615 1616 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1617 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1618 inst->predInstAddr(), inst->predNextInstAddr()); 1619 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1620 " NPC: %#x.\n", inst->nextInstAddr(), 1621 inst->nextInstAddr()); 1622 // If incorrect, then signal the ROB that it must be squashed. 1623 squashDueToBranch(inst, tid); 1624 1625 if (inst->readPredTaken()) { 1626 predictedTakenIncorrect++; 1627 } else { 1628 predictedNotTakenIncorrect++; 1629 } 1630 } 1631 } 1632} 1633 1634#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1635