iew_impl.hh revision 1061
14876Sstever@eecs.umich.edu// @todo: Fix the instantaneous communication among all the stages within 23646Srdreslin@umich.edu// iew. There's a clear delay between issue and execute, yet backwards 33646Srdreslin@umich.edu// communication happens simultaneously. Might not be that bad really... 43646Srdreslin@umich.edu// it might skew stats a bit though. Issue would otherwise try to issue 53646Srdreslin@umich.edu// instructions that would never be executed if there were a delay; without 63646Srdreslin@umich.edu// it issue will simply squash. Make this stage block properly. 73646Srdreslin@umich.edu// Update the statuses for each stage. 83646Srdreslin@umich.edu// Actually read instructions out of the skid buffer. 93646Srdreslin@umich.edu 103646Srdreslin@umich.edu#include <queue> 113646Srdreslin@umich.edu 123646Srdreslin@umich.edu#include "base/timebuf.hh" 133646Srdreslin@umich.edu#include "cpu/beta_cpu/iew.hh" 143646Srdreslin@umich.edu 153646Srdreslin@umich.edutemplate<class Impl, class IQ> 163646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::SimpleIEW(Params ¶ms) 173646Srdreslin@umich.edu : // Just make this time buffer really big for now 183646Srdreslin@umich.edu issueToExecQueue(5, 5), 193646Srdreslin@umich.edu instQueue(params), 203646Srdreslin@umich.edu ldstQueue(params), 213646Srdreslin@umich.edu commitToIEWDelay(params.commitToIEWDelay), 223646Srdreslin@umich.edu renameToIEWDelay(params.renameToIEWDelay), 233646Srdreslin@umich.edu issueToExecuteDelay(params.issueToExecuteDelay), 243646Srdreslin@umich.edu issueReadWidth(params.issueWidth), 253646Srdreslin@umich.edu issueWidth(params.issueWidth), 263646Srdreslin@umich.edu executeWidth(params.executeWidth) 273646Srdreslin@umich.edu{ 283646Srdreslin@umich.edu DPRINTF(IEW, "IEW: executeIntWidth: %i.\n", params.executeIntWidth); 293646Srdreslin@umich.edu _status = Idle; 303646Srdreslin@umich.edu _issueStatus = Idle; 313646Srdreslin@umich.edu _exeStatus = Idle; 323646Srdreslin@umich.edu _wbStatus = Idle; 336654Snate@binkert.org 346654Snate@binkert.org // Setup wire to read instructions coming from issue. 356654Snate@binkert.org fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 366654Snate@binkert.org 373646Srdreslin@umich.edu // Instruction queue needs the queue between issue and execute. 383646Srdreslin@umich.edu instQueue.setIssueToExecuteQueue(&issueToExecQueue); 396654Snate@binkert.org} 406654Snate@binkert.org 413646Srdreslin@umich.edutemplate<class Impl, class IQ> 423646Srdreslin@umich.eduvoid 433646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::setCPU(FullCPU *cpu_ptr) 443646Srdreslin@umich.edu{ 453646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Setting CPU pointer.\n"); 463646Srdreslin@umich.edu cpu = cpu_ptr; 473646Srdreslin@umich.edu 483646Srdreslin@umich.edu instQueue.setCPU(cpu_ptr); 493646Srdreslin@umich.edu ldstQueue.setCPU(cpu_ptr); 503646Srdreslin@umich.edu} 513646Srdreslin@umich.edu 523646Srdreslin@umich.edutemplate<class Impl, class IQ> 533646Srdreslin@umich.eduvoid 543646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 553646Srdreslin@umich.edu{ 563646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Setting time buffer pointer.\n"); 573646Srdreslin@umich.edu timeBuffer = tb_ptr; 583646Srdreslin@umich.edu 593646Srdreslin@umich.edu // Setup wire to read information from time buffer, from commit. 603646Srdreslin@umich.edu fromCommit = timeBuffer->getWire(-commitToIEWDelay); 613646Srdreslin@umich.edu 623646Srdreslin@umich.edu // Setup wire to write information back to previous stages. 633646Srdreslin@umich.edu toRename = timeBuffer->getWire(0); 643646Srdreslin@umich.edu 653646Srdreslin@umich.edu // Instruction queue also needs main time buffer. 663646Srdreslin@umich.edu instQueue.setTimeBuffer(tb_ptr); 673646Srdreslin@umich.edu} 683646Srdreslin@umich.edu 693646Srdreslin@umich.edutemplate<class Impl, class IQ> 703646Srdreslin@umich.eduvoid 713646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 723646Srdreslin@umich.edu{ 733646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Setting rename queue pointer.\n"); 743646Srdreslin@umich.edu renameQueue = rq_ptr; 753646Srdreslin@umich.edu 763646Srdreslin@umich.edu // Setup wire to read information from rename queue. 773646Srdreslin@umich.edu fromRename = renameQueue->getWire(-renameToIEWDelay); 783646Srdreslin@umich.edu} 793646Srdreslin@umich.edu 803646Srdreslin@umich.edutemplate<class Impl, class IQ> 813646Srdreslin@umich.eduvoid 823646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 833646Srdreslin@umich.edu{ 843646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Setting IEW queue pointer.\n"); 853646Srdreslin@umich.edu iewQueue = iq_ptr; 863646Srdreslin@umich.edu 873646Srdreslin@umich.edu // Setup wire to write instructions to commit. 883646Srdreslin@umich.edu toCommit = iewQueue->getWire(0); 893646Srdreslin@umich.edu} 903646Srdreslin@umich.edu 913646Srdreslin@umich.edutemplate<class Impl, class IQ> 923646Srdreslin@umich.eduvoid 933646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::setRenameMap(RenameMap *rm_ptr) 943646Srdreslin@umich.edu{ 953646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Setting rename map pointer.\n"); 963646Srdreslin@umich.edu renameMap = rm_ptr; 973646Srdreslin@umich.edu} 983646Srdreslin@umich.edu 993646Srdreslin@umich.edutemplate<class Impl, class IQ> 1003646Srdreslin@umich.eduvoid 1013646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::wakeDependents(DynInstPtr &inst) 1023646Srdreslin@umich.edu{ 1033646Srdreslin@umich.edu instQueue.wakeDependents(inst); 1043646Srdreslin@umich.edu} 1053646Srdreslin@umich.edu 1063646Srdreslin@umich.edutemplate<class Impl, class IQ> 1073646Srdreslin@umich.eduvoid 1083646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::block() 1093646Srdreslin@umich.edu{ 1103646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Blocking.\n"); 1113646Srdreslin@umich.edu // Set the status to Blocked. 1123646Srdreslin@umich.edu _status = Blocked; 1133646Srdreslin@umich.edu 1143646Srdreslin@umich.edu // Add the current inputs to the skid buffer so they can be 1153646Srdreslin@umich.edu // reprocessed when this stage unblocks. 1163646Srdreslin@umich.edu skidBuffer.push(*fromRename); 1173646Srdreslin@umich.edu 1183646Srdreslin@umich.edu // Note that this stage only signals previous stages to stall when 1193646Srdreslin@umich.edu // it is the cause of the stall originates at this stage. Otherwise 1203646Srdreslin@umich.edu // the previous stages are expected to check all possible stall signals. 1213646Srdreslin@umich.edu} 1223646Srdreslin@umich.edu 1233646Srdreslin@umich.edutemplate<class Impl, class IQ> 1243646Srdreslin@umich.eduinline void 1253646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::unblock() 1263646Srdreslin@umich.edu{ 1273646Srdreslin@umich.edu // Check if there's information in the skid buffer. If there is, then 1283646Srdreslin@umich.edu // set status to unblocking, otherwise set it directly to running. 1293646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Reading instructions out of the skid " 1303646Srdreslin@umich.edu "buffer.\n"); 1313646Srdreslin@umich.edu // Remove the now processed instructions from the skid buffer. 1323646Srdreslin@umich.edu skidBuffer.pop(); 1333646Srdreslin@umich.edu 1343646Srdreslin@umich.edu // If there's still information in the skid buffer, then 1353646Srdreslin@umich.edu // continue to tell previous stages to stall. They will be 1363646Srdreslin@umich.edu // able to restart once the skid buffer is empty. 1373646Srdreslin@umich.edu if (!skidBuffer.empty()) { 1383646Srdreslin@umich.edu toRename->iewInfo.stall = true; 1393646Srdreslin@umich.edu } else { 1403646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Stage is done unblocking.\n"); 1413646Srdreslin@umich.edu _status = Running; 1423646Srdreslin@umich.edu } 1433646Srdreslin@umich.edu} 1443646Srdreslin@umich.edu 1453646Srdreslin@umich.edutemplate<class Impl, class IQ> 1463646Srdreslin@umich.eduvoid 1473646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::squash() 1483646Srdreslin@umich.edu{ 1493646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Squashing all instructions.\n"); 1503646Srdreslin@umich.edu _status = Squashing; 1513646Srdreslin@umich.edu 1523646Srdreslin@umich.edu // Tell the IQ to start squashing. 1533646Srdreslin@umich.edu instQueue.squash(); 1543646Srdreslin@umich.edu 1553646Srdreslin@umich.edu // Tell the LDSTQ to start squashing. 1563646Srdreslin@umich.edu ldstQueue.squash(fromCommit->commitInfo.doneSeqNum); 1573646Srdreslin@umich.edu} 1583646Srdreslin@umich.edu 1593646Srdreslin@umich.edutemplate<class Impl, class IQ> 1603646Srdreslin@umich.eduvoid 1613646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::squash(DynInstPtr &inst) 1623646Srdreslin@umich.edu{ 1633646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Squashing from a specific instruction, PC: %#x.\n", 1643646Srdreslin@umich.edu inst->PC); 1653646Srdreslin@umich.edu // Perhaps leave the squashing up to the ROB stage to tell it when to 1663646Srdreslin@umich.edu // squash? 1673646Srdreslin@umich.edu _status = Squashing; 1683646Srdreslin@umich.edu 1693646Srdreslin@umich.edu // Tell rename to squash through the time buffer. 1703646Srdreslin@umich.edu toRename->iewInfo.squash = true; 1713646Srdreslin@umich.edu // Also send PC update information back to prior stages. 1723646Srdreslin@umich.edu toRename->iewInfo.squashedSeqNum = inst->seqNum; 1733646Srdreslin@umich.edu toRename->iewInfo.mispredPC = inst->readPC(); 1743646Srdreslin@umich.edu toRename->iewInfo.nextPC = inst->readCalcTarg(); 1753646Srdreslin@umich.edu toRename->iewInfo.branchMispredict = true; 1763646Srdreslin@umich.edu // Prediction was incorrect, so send back inverse. 1773646Srdreslin@umich.edu toRename->iewInfo.branchTaken = !(inst->predTaken()); 1783646Srdreslin@umich.edu} 1793646Srdreslin@umich.edu 1803646Srdreslin@umich.edutemplate<class Impl, class IQ> 1813646Srdreslin@umich.eduvoid 1823646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::tick() 1833646Srdreslin@umich.edu{ 1843646Srdreslin@umich.edu // Considering putting all the state-determining stuff in this section. 1853646Srdreslin@umich.edu 1863646Srdreslin@umich.edu // Try to fill up issue queue with as many instructions as bandwidth 1873646Srdreslin@umich.edu // allows. 1883646Srdreslin@umich.edu // Decode should try to execute as many instructions as its bandwidth 1893646Srdreslin@umich.edu // will allow, as long as it is not currently blocked. 1903646Srdreslin@umich.edu 1913646Srdreslin@umich.edu // Check if the stage is in a running status. 1923646Srdreslin@umich.edu if (_status != Blocked && _status != Squashing) { 1933646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Status is not blocked, attempting to run " 1943646Srdreslin@umich.edu "stage.\n"); 1953646Srdreslin@umich.edu iew(); 1963646Srdreslin@umich.edu 1973646Srdreslin@umich.edu // If it's currently unblocking, check to see if it should switch 1983646Srdreslin@umich.edu // to running. 1993646Srdreslin@umich.edu if (_status == Unblocking) { 2003646Srdreslin@umich.edu unblock(); 2013646Srdreslin@umich.edu } 2023646Srdreslin@umich.edu } else if (_status == Squashing) { 2033646Srdreslin@umich.edu 2043646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Still squashing.\n"); 2053646Srdreslin@umich.edu 2063646Srdreslin@umich.edu // Check if stage should remain squashing. Stop squashing if the 2073646Srdreslin@umich.edu // squash signal clears. 2083646Srdreslin@umich.edu if (!fromCommit->commitInfo.squash && 2093646Srdreslin@umich.edu !fromCommit->commitInfo.robSquashing) { 2103646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Done squashing, changing status to " 2113646Srdreslin@umich.edu "running.\n"); 2123646Srdreslin@umich.edu 2133646Srdreslin@umich.edu _status = Running; 2143646Srdreslin@umich.edu instQueue.stopSquash(); 2153646Srdreslin@umich.edu } else { 2163646Srdreslin@umich.edu instQueue.doSquash(); 2173646Srdreslin@umich.edu } 2183646Srdreslin@umich.edu 2193646Srdreslin@umich.edu // Also should advance its own time buffers if the stage ran. 2203646Srdreslin@umich.edu // Not sure about this... 2213646Srdreslin@umich.edu// issueToExecQueue.advance(); 2223646Srdreslin@umich.edu } else if (_status == Blocked) { 2233646Srdreslin@umich.edu // Continue to tell previous stage to stall. 2243646Srdreslin@umich.edu toRename->iewInfo.stall = true; 2253646Srdreslin@umich.edu 2263646Srdreslin@umich.edu // Check if possible stall conditions have cleared. 2273646Srdreslin@umich.edu if (!fromCommit->commitInfo.stall && 2283646Srdreslin@umich.edu !instQueue.isFull()) { 2293646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Stall signals cleared, going to unblock.\n"); 2303646Srdreslin@umich.edu _status = Unblocking; 2313646Srdreslin@umich.edu } 2323646Srdreslin@umich.edu 2333646Srdreslin@umich.edu // If there's still instructions coming from rename, continue to 2343646Srdreslin@umich.edu // put them on the skid buffer. 2353646Srdreslin@umich.edu if (fromRename->insts[0]) { 2363646Srdreslin@umich.edu block(); 2373646Srdreslin@umich.edu } 2383646Srdreslin@umich.edu 2393646Srdreslin@umich.edu if (fromCommit->commitInfo.squash || 2403646Srdreslin@umich.edu fromCommit->commitInfo.robSquashing) { 2413646Srdreslin@umich.edu squash(); 2423646Srdreslin@umich.edu } 2433646Srdreslin@umich.edu } 2443646Srdreslin@umich.edu 2453646Srdreslin@umich.edu // @todo: Maybe put these at the beginning, so if it's idle it can 2463646Srdreslin@umich.edu // return early. 2473646Srdreslin@umich.edu // Write back number of free IQ entries here. 2483646Srdreslin@umich.edu toRename->iewInfo.freeIQEntries = instQueue.numFreeEntries(); 2493646Srdreslin@umich.edu 2503646Srdreslin@umich.edu // Check the committed load/store signals to see if there's a load 2513646Srdreslin@umich.edu // or store to commit. Also check if it's being told to execute a 2523646Srdreslin@umich.edu // nonspeculative instruction. 2533646Srdreslin@umich.edu if (fromCommit->commitInfo.commitIsStore) { 2543646Srdreslin@umich.edu ldstQueue.commitStores(fromCommit->commitInfo.doneSeqNum); 2553646Srdreslin@umich.edu } else if (fromCommit->commitInfo.commitIsLoad) { 2563646Srdreslin@umich.edu ldstQueue.commitLoads(fromCommit->commitInfo.doneSeqNum); 2573646Srdreslin@umich.edu } 2583646Srdreslin@umich.edu 2593646Srdreslin@umich.edu if (fromCommit->commitInfo.nonSpecSeqNum != 0) { 2603646Srdreslin@umich.edu instQueue.scheduleNonSpec(fromCommit->commitInfo.nonSpecSeqNum); 2613646Srdreslin@umich.edu } 2623646Srdreslin@umich.edu 2633646Srdreslin@umich.edu DPRINTF(IEW, "IEW: IQ has %i free entries.\n", 2643646Srdreslin@umich.edu instQueue.numFreeEntries()); 2653646Srdreslin@umich.edu} 2663646Srdreslin@umich.edu 2673646Srdreslin@umich.edutemplate<class Impl, class IQ> 2683646Srdreslin@umich.eduvoid 2693646Srdreslin@umich.eduSimpleIEW<Impl, IQ>::iew() 2703646Srdreslin@umich.edu{ 2713646Srdreslin@umich.edu // Might want to put all state checks in the tick() function. 2723646Srdreslin@umich.edu // Check if being told to stall from commit. 2736654Snate@binkert.org if (fromCommit->commitInfo.stall) { 2746654Snate@binkert.org block(); 2756654Snate@binkert.org return; 2766654Snate@binkert.org } else if (fromCommit->commitInfo.squash || 2776654Snate@binkert.org fromCommit->commitInfo.robSquashing) { 2783646Srdreslin@umich.edu // Also check if commit is telling this stage to squash. 2793646Srdreslin@umich.edu squash(); 2803646Srdreslin@umich.edu return; 2813646Srdreslin@umich.edu } 2823646Srdreslin@umich.edu 2833646Srdreslin@umich.edu //////////////////////////////////////// 2843646Srdreslin@umich.edu // DISPATCH/ISSUE stage 2853646Srdreslin@umich.edu //////////////////////////////////////// 2863646Srdreslin@umich.edu 2873646Srdreslin@umich.edu //Put into its own function? 2883646Srdreslin@umich.edu //Add instructions to IQ if there are any instructions there 2893646Srdreslin@umich.edu 2903646Srdreslin@umich.edu // Check if there are any instructions coming from rename, and we're. 2913646Srdreslin@umich.edu // not squashing. 2923646Srdreslin@umich.edu if (fromRename->insts[0] && _status != Squashing) { 2933646Srdreslin@umich.edu 2943646Srdreslin@umich.edu // Loop through the instructions, putting them in the instruction 2953646Srdreslin@umich.edu // queue. 2963646Srdreslin@umich.edu for (int inst_num = 0; inst_num < issueReadWidth; ++inst_num) 2973646Srdreslin@umich.edu { 2983646Srdreslin@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 2993646Srdreslin@umich.edu 3003646Srdreslin@umich.edu // Make sure there's a valid instruction there. 3013646Srdreslin@umich.edu if (!inst) 3023646Srdreslin@umich.edu break; 3033646Srdreslin@umich.edu 3043646Srdreslin@umich.edu DPRINTF(IEW, "IEW: Issue: Adding PC %#x to IQ.\n", 305 inst->readPC()); 306 307 // If it's a memory reference, don't put it in the 308 // instruction queue. These will only be executed at commit. 309 // Do the same for nonspeculative instructions and nops. 310 // Be sure to mark these instructions as ready so that the 311 // commit stage can go ahead and execute them, and mark 312 // them as issued so the IQ doesn't reprocess them. 313 if (inst->isSquashed()) { 314 continue; 315 } else if (inst->isLoad()) { 316 DPRINTF(IEW, "IEW: Issue: Memory instruction " 317 "encountered, adding to LDSTQ.\n"); 318 319 // Reserve a spot in the load store queue for this 320 // memory access. 321 ldstQueue.insertLoad(inst); 322 323 } else if (inst->isStore()) { 324 ldstQueue.insertStore(inst); 325 326 // A bit of a hack. Set that it can commit so that 327 // the commit stage will try committing it, and then 328 // once commit realizes it's a store it will send back 329 // a signal to this stage to issue and execute that 330 // store. 331 inst->setCanCommit(); 332 333 instQueue.insertNonSpec(inst); 334 continue; 335 } else if (inst->isNonSpeculative()) { 336 DPRINTF(IEW, "IEW: Issue: Nonspeculative instruction " 337 "encountered, skipping.\n"); 338 339 // Same hack as with stores. 340 inst->setCanCommit(); 341 342 // Specificall insert it as nonspeculative. 343 instQueue.insertNonSpec(inst); 344 345 continue; 346 } else if (inst->isNop()) { 347 DPRINTF(IEW, "IEW: Issue: Nop instruction encountered " 348 ", skipping.\n"); 349 350 inst->setIssued(); 351 inst->setExecuted(); 352 inst->setCanCommit(); 353 354 instQueue.advanceTail(inst); 355 continue; 356 } else if (instQueue.isFull()) { 357 DPRINTF(IEW, "IEW: Issue: IQ has become full.\n"); 358 // Call function to start blocking. 359 block(); 360 // Tell previous stage to stall. 361 toRename->iewInfo.stall = true; 362 break; 363 } 364 365 // If the instruction queue is not full, then add the 366 // instruction. 367 instQueue.insert(fromRename->insts[inst_num]); 368 } 369 } 370 371 // Have the instruction queue try to schedule any ready instructions. 372 instQueue.scheduleReadyInsts(); 373 374 //////////////////////////////////////// 375 //EXECUTE/WRITEBACK stage 376 //////////////////////////////////////// 377 378 //Put into its own function? 379 //Similarly should probably have separate execution for int vs FP. 380 // Above comment is handled by the issue queue only issuing a valid 381 // mix of int/fp instructions. 382 //Actually okay to just have one execution, buuuuuut will need 383 //somewhere that defines the execution latency of all instructions. 384 // @todo: Move to the FU pool used in the current full cpu. 385 386 int fu_usage = 0; 387 bool fetch_redirect = false; 388 389 // Execute/writeback any instructions that are available. 390 for (int inst_num = 0; 391 fu_usage < executeWidth && /* Haven't exceeded available FU's. */ 392 inst_num < issueWidth && /* Haven't exceeded issue width. */ 393 fromIssue->insts[inst_num]; /* There are available instructions. */ 394 ++inst_num) { 395 DPRINTF(IEW, "IEW: Execute: Executing instructions from IQ.\n"); 396 397 // Get instruction from issue's queue. 398 DynInstPtr inst = fromIssue->insts[inst_num]; 399 400 DPRINTF(IEW, "IEW: Execute: Processing PC %#x.\n", inst->readPC()); 401 402 // Check if the instruction is squashed; if so then skip it 403 // and don't count it towards the FU usage. 404 if (inst->isSquashed()) { 405 DPRINTF(IEW, "IEW: Execute: Instruction was squashed.\n"); 406 407 // Consider this instruction executed so that commit can go 408 // ahead and retire the instruction. 409 inst->setExecuted(); 410 411 toCommit->insts[inst_num] = inst; 412 413 continue; 414 } 415 416 inst->setExecuted(); 417 418 // If an instruction is executed, then count it towards FU usage. 419 ++fu_usage; 420 421 // Execute instruction. 422 // Note that if the instruction faults, it will be handled 423 // at the commit stage. 424 if (inst->isMemRef()) { 425 DPRINTF(IEW, "IEW: Execute: Calculating address for memory " 426 "reference.\n"); 427 428 // Tell the LDSTQ to execute this instruction (if it is a load). 429 if (inst->isLoad()) { 430 ldstQueue.executeLoad(inst); 431 } else if (inst->isStore()) { 432 ldstQueue.executeStore(); 433 } else { 434 panic("IEW: Unexpected memory type!\n"); 435 } 436 437 } else { 438 inst->execute(); 439 } 440 441 // First check the time slot that this instruction will write 442 // to. If there are free write ports at the time, then go ahead 443 // and write the instruction to that time. If there are not, 444 // keep looking back to see where's the first time there's a 445 // free slot. What happens if you run out of free spaces? 446 // For now naively assume that all instructions take one cycle. 447 // Otherwise would have to look into the time buffer based on the 448 // latency of the instruction. 449 450 // Add finished instruction to queue to commit. 451 toCommit->insts[inst_num] = inst; 452 453 // Check if branch was correct. This check happens after the 454 // instruction is added to the queue because even if the branch 455 // is mispredicted, the branch instruction itself is still valid. 456 // Only handle this if there hasn't already been something that 457 // redirects fetch in this group of instructions. 458 if (!fetch_redirect) { 459 if (inst->mispredicted()) { 460 fetch_redirect = true; 461 462 DPRINTF(IEW, "IEW: Execute: Branch mispredict detected.\n"); 463 DPRINTF(IEW, "IEW: Execute: Redirecting fetch to PC: %#x.\n", 464 inst->nextPC); 465 466 // If incorrect, then signal the ROB that it must be squashed. 467 squash(inst); 468 } else if (ldstQueue.violation()) { 469 fetch_redirect = true; 470 471 DynInstPtr violator = ldstQueue.getMemDepViolator(); 472 473 DPRINTF(IEW, "IEW: LDSTQ detected a violation. Violator PC: " 474 "%#x, inst PC: %#x. Addr is: %#x.\n", 475 violator->readPC(), inst->readPC(), inst->physEffAddr); 476 477 instQueue.violation(inst, violator); 478 479 squash(inst); 480 // Otherwise check if there was a memory ordering violation. 481 // If there was, then signal ROB that it must be squashed. Also 482 // signal IQ that there was a violation. 483 } 484 } 485 } 486 487 // Loop through the head of the time buffer and wake any dependents. 488 // These instructions are about to write back. In the simple model 489 // this loop can really happen within the previous loop, but when 490 // instructions have actual latencies, this loop must be separate. 491 // Also mark scoreboard that this instruction is finally complete. 492 // Either have IEW have direct access to rename map, or have this as 493 // part of backwards communication. 494 for (int inst_num = 0; inst_num < executeWidth && 495 toCommit->insts[inst_num]; inst_num++) 496 { 497 DynInstPtr inst = toCommit->insts[inst_num]; 498 499 DPRINTF(IEW, "IEW: Sending instructions to commit, PC %#x.\n", 500 inst->readPC()); 501 502 if(!inst->isSquashed()) { 503 instQueue.wakeDependents(inst); 504 505 for (int i = 0; i < inst->numDestRegs(); i++) 506 { 507 renameMap->markAsReady(inst->renamedDestRegIdx(i)); 508 } 509 } 510 } 511 512 // Also should advance its own time buffers if the stage ran. 513 // Not the best place for it, but this works (hopefully). 514 issueToExecQueue.advance(); 515} 516