iew_impl.hh revision 1060
11689SN/A// @todo: Fix the instantaneous communication among all the stages within 29783Sandreas.hansson@arm.com// iew. There's a clear delay between issue and execute, yet backwards 310239Sbinhpham@cs.rutgers.edu// communication happens simultaneously. Might not be that bad really... 47598Sminkyu.jeong@arm.com// it might skew stats a bit though. Issue would otherwise try to issue 57598Sminkyu.jeong@arm.com// instructions that would never be executed if there were a delay; without 67598Sminkyu.jeong@arm.com// it issue will simply squash. Make this stage block properly. Make this 77598Sminkyu.jeong@arm.com// stage delay after a squash properly. Update the statuses for each stage. 87598Sminkyu.jeong@arm.com// Actually read instructions out of the skid buffer. 97598Sminkyu.jeong@arm.com 107598Sminkyu.jeong@arm.com#include <queue> 117598Sminkyu.jeong@arm.com 127598Sminkyu.jeong@arm.com#include "base/timebuf.hh" 137598Sminkyu.jeong@arm.com#include "cpu/beta_cpu/iew.hh" 147598Sminkyu.jeong@arm.com 152326SN/Atemplate<class Impl, class IQ> 161689SN/ASimpleIEW<Impl, IQ>::SimpleIEW(Params ¶ms) 171689SN/A : // Just make this time buffer really big for now 181689SN/A issueToExecQueue(20, 20), 191689SN/A instQueue(params), 201689SN/A commitToIEWDelay(params.commitToIEWDelay), 211689SN/A renameToIEWDelay(params.renameToIEWDelay), 221689SN/A issueToExecuteDelay(params.issueToExecuteDelay), 231689SN/A issueReadWidth(params.issueWidth), 241689SN/A issueWidth(params.issueWidth), 251689SN/A executeWidth(params.executeWidth) 261689SN/A{ 271689SN/A DPRINTF(IEW, "IEW: executeIntWidth: %i.\n", params.executeIntWidth); 281689SN/A _status = Idle; 291689SN/A _issueStatus = Idle; 301689SN/A _exeStatus = Idle; 311689SN/A _wbStatus = Idle; 321689SN/A 331689SN/A // Setup wire to read instructions coming from issue. 341689SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 351689SN/A 361689SN/A // Instruction queue needs the queue between issue and execute. 371689SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 381689SN/A} 391689SN/A 402665Ssaidi@eecs.umich.edutemplate<class Impl, class IQ> 412665Ssaidi@eecs.umich.eduvoid 421689SN/ASimpleIEW<Impl, IQ>::setCPU(FullCPU *cpu_ptr) 431689SN/A{ 449944Smatt.horsnell@ARM.com DPRINTF(IEW, "IEW: Setting CPU pointer.\n"); 459944Smatt.horsnell@ARM.com cpu = cpu_ptr; 469944Smatt.horsnell@ARM.com 471060SN/A instQueue.setCPU(cpu_ptr); 481060SN/A} 491689SN/A 501060SN/Atemplate<class Impl, class IQ> 511060SN/Avoid 521060SN/ASimpleIEW<Impl, IQ>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 538230Snate@binkert.org{ 546658Snate@binkert.org DPRINTF(IEW, "IEW: Setting time buffer pointer.\n"); 558887Sgeoffrey.blake@arm.com timeBuffer = tb_ptr; 562292SN/A 571717SN/A // Setup wire to read information from time buffer, from commit. 588229Snate@binkert.org fromCommit = timeBuffer->getWire(-commitToIEWDelay); 598232Snate@binkert.org 609444SAndreas.Sandberg@ARM.com // Setup wire to write information back to previous stages. 618232Snate@binkert.org toRename = timeBuffer->getWire(0); 629527SMatt.Horsnell@arm.com 635529Snate@binkert.org // Instruction queue also needs main time buffer. 641060SN/A instQueue.setTimeBuffer(tb_ptr); 656221Snate@binkert.org} 666221Snate@binkert.org 671681SN/Atemplate<class Impl, class IQ> 685529Snate@binkert.orgvoid 692873Sktlim@umich.eduSimpleIEW<Impl, IQ>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 704329Sktlim@umich.edu{ 714329Sktlim@umich.edu DPRINTF(IEW, "IEW: Setting rename queue pointer.\n"); 724329Sktlim@umich.edu renameQueue = rq_ptr; 732292SN/A 742292SN/A // Setup wire to read information from rename queue. 752292SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 762292SN/A} 772820Sktlim@umich.edu 782292SN/Atemplate<class Impl, class IQ> 792820Sktlim@umich.eduvoid 809444SAndreas.Sandberg@ARM.comSimpleIEW<Impl, IQ>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 811060SN/A{ 8210172Sdam.sunwoo@arm.com DPRINTF(IEW, "IEW: Setting IEW queue pointer.\n"); 8310172Sdam.sunwoo@arm.com iewQueue = iq_ptr; 8410172Sdam.sunwoo@arm.com 8510172Sdam.sunwoo@arm.com // Setup wire to write instructions to commit. 8610172Sdam.sunwoo@arm.com toCommit = iewQueue->getWire(0); 8710172Sdam.sunwoo@arm.com} 8810172Sdam.sunwoo@arm.com 8910172Sdam.sunwoo@arm.comtemplate<class Impl, class IQ> 9010172Sdam.sunwoo@arm.comvoid 9110172Sdam.sunwoo@arm.comSimpleIEW<Impl, IQ>::setRenameMap(RenameMap *rm_ptr) 9210172Sdam.sunwoo@arm.com{ 9310172Sdam.sunwoo@arm.com DPRINTF(IEW, "IEW: Setting rename map pointer.\n"); 9410172Sdam.sunwoo@arm.com renameMap = rm_ptr; 952292SN/A} 962292SN/A 972292SN/Atemplate<class Impl, class IQ> 981060SN/Avoid 991060SN/ASimpleIEW<Impl, IQ>::wakeDependents(DynInst *inst) 1001060SN/A{ 1011060SN/A instQueue.wakeDependents(inst); 1021060SN/A} 1031060SN/A 1041681SN/Atemplate<class Impl, class IQ> 1056221Snate@binkert.orgvoid 1066221Snate@binkert.orgSimpleIEW<Impl, IQ>::block() 1076221Snate@binkert.org{ 1082292SN/A DPRINTF(IEW, "IEW: Blocking.\n"); 1092292SN/A // Set the status to Blocked. 1102292SN/A _status = Blocked; 1112292SN/A 11210328Smitch.hayenga@arm.com // Add the current inputs to the skid buffer so they can be 1132292SN/A // reprocessed when this stage unblocks. 1142292SN/A skidBuffer.push(*fromRename); 1152292SN/A 1162292SN/A // Note that this stage only signals previous stages to stall when 1172292SN/A // it is the cause of the stall originates at this stage. Otherwise 1182292SN/A // the previous stages are expected to check all possible stall signals. 1192292SN/A} 1201060SN/A 1211060SN/Atemplate<class Impl, class IQ> 1221681SN/Ainline void 1231062SN/ASimpleIEW<Impl, IQ>::unblock() 12410023Smatt.horsnell@ARM.com{ 12510023Smatt.horsnell@ARM.com // Check if there's information in the skid buffer. If there is, then 12610023Smatt.horsnell@ARM.com // set status to unblocking, otherwise set it directly to running. 12710023Smatt.horsnell@ARM.com DPRINTF(IEW, "IEW: Reading instructions out of the skid " 12811246Sradhika.jagtap@ARM.com "buffer.\n"); 12911246Sradhika.jagtap@ARM.com // Remove the now processed instructions from the skid buffer. 13011246Sradhika.jagtap@ARM.com skidBuffer.pop(); 13111246Sradhika.jagtap@ARM.com 13211246Sradhika.jagtap@ARM.com // If there's still information in the skid buffer, then 13311246Sradhika.jagtap@ARM.com // continue to tell previous stages to stall. They will be 13411246Sradhika.jagtap@ARM.com // able to restart once the skid buffer is empty. 13511246Sradhika.jagtap@ARM.com if (!skidBuffer.empty()) { 13611246Sradhika.jagtap@ARM.com toRename->iewInfo.stall = true; 13711246Sradhika.jagtap@ARM.com } else { 13811246Sradhika.jagtap@ARM.com DPRINTF(IEW, "IEW: Stage is done unblocking.\n"); 13911246Sradhika.jagtap@ARM.com _status = Running; 14010023Smatt.horsnell@ARM.com } 14110023Smatt.horsnell@ARM.com} 14210023Smatt.horsnell@ARM.com 14310023Smatt.horsnell@ARM.comtemplate<class Impl, class IQ> 1442292SN/Avoid 1451062SN/ASimpleIEW<Impl, IQ>::squash() 1462301SN/A{ 1472301SN/A DPRINTF(IEW, "IEW: Squashing all instructions.\n"); 1481062SN/A _status = Squashing; 1492727Sktlim@umich.edu 1501062SN/A // Tell the IQ to start squashing. 1511062SN/A instQueue.squash(); 1521062SN/A 1531062SN/A // Tell rename to squash through the time buffer. 1541062SN/A // This communication may be redundant depending upon where squash() 1551062SN/A // is called. 1561062SN/A// toRename->iewInfo.squash = true; 1571062SN/A} 1581062SN/A 1591062SN/Atemplate<class Impl, class IQ> 1601062SN/Avoid 1611062SN/ASimpleIEW<Impl, IQ>::squash(DynInst *inst) 1621062SN/A{ 1631062SN/A DPRINTF(IEW, "IEW: Squashing from a specific instruction, PC:%#x.\n", 1641062SN/A inst->PC); 1651062SN/A // Perhaps leave the squashing up to the ROB stage to tell it when to 1661062SN/A // squash? 1671062SN/A _status = Squashing; 1681062SN/A 1691062SN/A // Tell rename to squash through the time buffer. 1701062SN/A toRename->iewInfo.squash = true; 1711062SN/A // Also send PC update information back to prior stages. 1721062SN/A toRename->iewInfo.squashedSeqNum = inst->seqNum; 1731062SN/A toRename->iewInfo.nextPC = inst->readCalcTarg(); 1741062SN/A toRename->iewInfo.predIncorrect = true; 1751062SN/A} 1761062SN/A 1771062SN/Atemplate<class Impl, class IQ> 1781062SN/Avoid 1791062SN/ASimpleIEW<Impl, IQ>::tick() 1801062SN/A{ 1811062SN/A // Considering putting all the state-determining stuff in this section. 1821062SN/A 1831062SN/A // Try to fill up issue queue with as many instructions as bandwidth 1841062SN/A // allows. 1851062SN/A // Decode should try to execute as many instructions as its bandwidth 1861062SN/A // will allow, as long as it is not currently blocked. 1871062SN/A 1881062SN/A // Check if the stage is in a running status. 1891062SN/A if (_status != Blocked && _status != Squashing) { 1901062SN/A DPRINTF(IEW, "IEW: Status is not blocked, attempting to run " 1912292SN/A "stage.\n"); 1922292SN/A iew(); 1932292SN/A 1942292SN/A // If it's currently unblocking, check to see if it should switch 1951062SN/A // to running. 1961062SN/A if (_status == Unblocking) { 1971062SN/A unblock(); 1981062SN/A } 1991062SN/A } else if (_status == Squashing) { 2001062SN/A 2011062SN/A DPRINTF(IEW, "IEW: Still squashing.\n"); 2022292SN/A 2032292SN/A // Check if stage should remain squashing. Stop squashing if the 2042292SN/A // squash signal clears. 2052292SN/A if (!fromCommit->commitInfo.squash && 2062292SN/A !fromCommit->commitInfo.robSquashing) { 2072292SN/A DPRINTF(IEW, "IEW: Done squashing, changing status to " 2082292SN/A "running.\n"); 2092292SN/A 2102292SN/A _status = Running; 2112292SN/A instQueue.stopSquash(); 2122301SN/A } else { 2132727Sktlim@umich.edu instQueue.doSquash(); 2142353SN/A } 2152727Sktlim@umich.edu 2162727Sktlim@umich.edu // Also should advance its own time buffers if the stage ran. 2172727Sktlim@umich.edu // Not sure about this... 2186221Snate@binkert.org// issueToExecQueue.advance(); 2192353SN/A } else if (_status == Blocked) { 2202727Sktlim@umich.edu // Continue to tell previous stage to stall. 2212727Sktlim@umich.edu toRename->iewInfo.stall = true; 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu // Check if possible stall conditions have cleared. 2242353SN/A if (!fromCommit->commitInfo.stall && 2252727Sktlim@umich.edu !instQueue.isFull()) { 2262727Sktlim@umich.edu DPRINTF(IEW, "IEW: Stall signals cleared, going to unblock.\n"); 2272727Sktlim@umich.edu _status = Unblocking; 2286221Snate@binkert.org } 2298240Snate@binkert.org 2302301SN/A // If there's still instructions coming from rename, continue to 2312727Sktlim@umich.edu // put them on the skid buffer. 2322301SN/A if (fromRename->insts[0] != NULL) { 2332727Sktlim@umich.edu block(); 2346221Snate@binkert.org } 2358240Snate@binkert.org 2362301SN/A if (fromCommit->commitInfo.squash || 2372727Sktlim@umich.edu fromCommit->commitInfo.robSquashing) { 2382301SN/A squash(); 2392727Sktlim@umich.edu } 2406221Snate@binkert.org } 2418240Snate@binkert.org 2422301SN/A // @todo: Maybe put these at the beginning, so if it's idle it can 2432727Sktlim@umich.edu // return early. 2442301SN/A // Write back number of free IQ entries here. 2452727Sktlim@umich.edu toRename->iewInfo.freeIQEntries = instQueue.numFreeEntries(); 2466221Snate@binkert.org 2478240Snate@binkert.org DPRINTF(IEW, "IEW: IQ has %i free entries.\n", 2482301SN/A instQueue.numFreeEntries()); 2492727Sktlim@umich.edu} 2502301SN/A 2512301SN/Atemplate<class Impl, class IQ> 2528240Snate@binkert.orgvoid 2532301SN/ASimpleIEW<Impl, IQ>::iew() 2542727Sktlim@umich.edu{ 2552727Sktlim@umich.edu // Might want to put all state checks in the tick() function. 2562727Sktlim@umich.edu // Check if being told to stall from commit. 2572727Sktlim@umich.edu if (fromCommit->commitInfo.stall) { 2588240Snate@binkert.org block(); 2592727Sktlim@umich.edu return; 2602727Sktlim@umich.edu } else if (fromCommit->commitInfo.squash || 2612727Sktlim@umich.edu fromCommit->commitInfo.robSquashing) { 2622727Sktlim@umich.edu // Also check if commit is telling this stage to squash. 2632301SN/A squash(); 2642301SN/A return; 2656221Snate@binkert.org } 2668240Snate@binkert.org 2672301SN/A //////////////////////////////////////// 2682727Sktlim@umich.edu //ISSUE stage 2692301SN/A //////////////////////////////////////// 2702326SN/A 2716221Snate@binkert.org //Put into its own function? 2728240Snate@binkert.org //Add instructions to IQ if there are any instructions there 2732301SN/A 2742727Sktlim@umich.edu // Check if there are any instructions coming from rename, and we're. 2752301SN/A // not squashing. 2762326SN/A if (fromRename->insts[0] != NULL && _status != Squashing) { 2776221Snate@binkert.org 2788240Snate@binkert.org // Loop through the instructions, putting them in the instruction 2792301SN/A // queue. 2802727Sktlim@umich.edu for (int inst_num = 0; inst_num < issueReadWidth; ++inst_num) 2812301SN/A { 2822326SN/A DynInst *inst = fromRename->insts[inst_num]; 2836221Snate@binkert.org 2848240Snate@binkert.org // Make sure there's a valid instruction there. 2852301SN/A if (inst == NULL) 2862727Sktlim@umich.edu break; 2872301SN/A 2882326SN/A DPRINTF(IEW, "IEW: Issue: Adding PC %#x to IQ.\n", 2898240Snate@binkert.org inst->readPC()); 2902301SN/A 2912727Sktlim@umich.edu // If it's a memory reference, don't put it in the 2922301SN/A // instruction queue. These will only be executed at commit. 2932326SN/A // Do the same for nonspeculative instructions and nops. 2942301SN/A // Be sure to mark these instructions as ready so that the 2952326SN/A // commit stage can go ahead and execute them, and mark 2968240Snate@binkert.org // them as issued so the IQ doesn't reprocess them. 2972301SN/A if (inst->isMemRef()) { 2982727Sktlim@umich.edu DPRINTF(IEW, "IEW: Issue: Memory instruction " 2992326SN/A "encountered, skipping.\n"); 3001062SN/A 3011062SN/A inst->setIssued(); 3021681SN/A inst->setExecuted(); 3031060SN/A inst->setCanCommit(); 3049427SAndreas.Sandberg@ARM.com 3051060SN/A instQueue.advanceTail(inst); 3066221Snate@binkert.org continue; 3072292SN/A } else if (inst->isNonSpeculative()) { 3082292SN/A DPRINTF(IEW, "IEW: Issue: Nonspeculative instruction " 3092292SN/A "encountered, skipping.\n"); 3102292SN/A 3112292SN/A inst->setIssued(); 31210239Sbinhpham@cs.rutgers.edu inst->setExecuted(); 31310239Sbinhpham@cs.rutgers.edu inst->setCanCommit(); 3142292SN/A 3152292SN/A instQueue.advanceTail(inst); 3168887Sgeoffrey.blake@arm.com continue; 3178733Sgeoffrey.blake@arm.com } else if (inst->isNop()) { 3188850Sandreas.hansson@arm.com DPRINTF(IEW, "IEW: Issue: Nop instruction encountered " 3198887Sgeoffrey.blake@arm.com ", skipping.\n"); 3208733Sgeoffrey.blake@arm.com 3212733Sktlim@umich.edu inst->setIssued(); 3221060SN/A inst->setExecuted(); 3231060SN/A inst->setCanCommit(); 3241681SN/A 3251060SN/A instQueue.advanceTail(inst); 3262292SN/A continue; 3271060SN/A } else if (instQueue.isFull()) { 3281060SN/A DPRINTF(IEW, "IEW: Issue: IQ has become full.\n"); 3291060SN/A // Call function to start blocking. 3301060SN/A block(); 3311060SN/A // Tell previous stage to stall. 3321060SN/A toRename->iewInfo.stall = true; 3331060SN/A break; 3341060SN/A } 3351060SN/A 3362292SN/A // If the instruction queue is not full, then add the 3372292SN/A // instruction. 3381060SN/A instQueue.insert(fromRename->insts[inst_num]); 3391060SN/A } 3401060SN/A } 3411060SN/A 3421681SN/A // Have the instruction queue try to schedule any ready instructions. 3431060SN/A instQueue.scheduleReadyInsts(); 3442292SN/A 3451060SN/A //////////////////////////////////////// 3461060SN/A //EXECUTE/WRITEBACK stage 3471060SN/A //////////////////////////////////////// 3481060SN/A 3491060SN/A //Put into its own function? 3501060SN/A //Similarly should probably have separate execution for int vs FP. 3511060SN/A // Above comment is handled by the issue queue only issuing a valid 3521681SN/A // mix of int/fp instructions. 3531060SN/A //Actually okay to just have one execution, buuuuuut will need 3542292SN/A //somewhere that defines the execution latency of all instructions. 3551060SN/A // @todo: Move to the FU pool used in the current full cpu. 3561060SN/A 3571060SN/A int fu_usage = 0; 3581060SN/A 3591060SN/A // Execute/writeback any instructions that are available. 3601060SN/A for (int inst_num = 0; 3611060SN/A fu_usage < executeWidth && /* Haven't exceeded available FU's. */ 3621681SN/A inst_num < issueWidth && /* Haven't exceeded issue width. */ 3631060SN/A fromIssue->insts[inst_num]; /* There are available instructions. */ 3646221Snate@binkert.org ++inst_num) { 3651060SN/A DPRINTF(IEW, "IEW: Execute: Executing instructions from IQ.\n"); 3662292SN/A 3672292SN/A // Get instruction from issue's queue. 3682292SN/A DynInst *inst = fromIssue->insts[inst_num]; 3692292SN/A 3701060SN/A DPRINTF(IEW, "IEW: Execute: Processing PC %#x.\n", inst->readPC()); 3711060SN/A 3721681SN/A inst->setExecuted(); 3731060SN/A 3742292SN/A // Check if the instruction is squashed; if so then skip it 3751060SN/A // and don't count it towards the FU usage. 3762292SN/A if (inst->isSquashed()) { 3771060SN/A DPRINTF(IEW, "IEW: Execute: Instruction was squashed.\n"); 3781060SN/A continue; 3792307SN/A } 3802863Sktlim@umich.edu 3819444SAndreas.Sandberg@ARM.com // If an instruction is executed, then count it towards FU usage. 3822307SN/A ++fu_usage; 38310510Smitch.hayenga@arm.com 3849444SAndreas.Sandberg@ARM.com // Execute instruction. 3859444SAndreas.Sandberg@ARM.com // Note that if the instruction faults, it will be handled 3869444SAndreas.Sandberg@ARM.com // at the commit stage. 3879444SAndreas.Sandberg@ARM.com inst->execute(); 3889444SAndreas.Sandberg@ARM.com 3899444SAndreas.Sandberg@ARM.com // First check the time slot that this instruction will write 3909444SAndreas.Sandberg@ARM.com // to. If there are free write ports at the time, then go ahead 3919444SAndreas.Sandberg@ARM.com // and write the instruction to that time. If there are not, 3929444SAndreas.Sandberg@ARM.com // keep looking back to see where's the first time there's a 3939444SAndreas.Sandberg@ARM.com // free slot. What happens if you run out of free spaces? 39411650Srekai.gonzalezalberquilla@arm.com // For now naively assume that all instructions take one cycle. 3959444SAndreas.Sandberg@ARM.com // Otherwise would have to look into the time buffer based on the 3969444SAndreas.Sandberg@ARM.com // latency of the instruction. 3979783Sandreas.hansson@arm.com 3989783Sandreas.hansson@arm.com // Add finished instruction to queue to commit. 3999783Sandreas.hansson@arm.com toCommit->insts[inst_num] = inst; 4009783Sandreas.hansson@arm.com 4019783Sandreas.hansson@arm.com // Check if branch was correct. This check happens after the 4029783Sandreas.hansson@arm.com // instruction is added to the queue because even if the branch 4039783Sandreas.hansson@arm.com // is mispredicted, the branch instruction itself is still valid. 4049783Sandreas.hansson@arm.com if (inst->mispredicted()) { 4059444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "IEW: Execute: Branch mispredict detected.\n"); 4061681SN/A DPRINTF(IEW, "IEW: Execute: Redirecting fetch to PC: %#x.\n", 4071681SN/A inst->nextPC); 4082316SN/A 4091681SN/A // If incorrect, then signal the ROB that it must be squashed. 4109444SAndreas.Sandberg@ARM.com squash(inst); 4112843Sktlim@umich.edu 4129444SAndreas.Sandberg@ARM.com // Not sure it really needs to break. 4132843Sktlim@umich.edu// break; 4149444SAndreas.Sandberg@ARM.com } 4159444SAndreas.Sandberg@ARM.com } 4161681SN/A 4171681SN/A // Loop through the head of the time buffer and wake any dependents. 4182307SN/A // These instructions are about to write back. In the simple model 4191681SN/A // this loop can really happen within the previous loop, but when 4202307SN/A // instructions have actual latencies, this loop must be separate. 4211060SN/A // Also mark scoreboard that this instruction is finally complete. 4222348SN/A // Either have IEW have direct access to rename map, or have this as 4232307SN/A // part of backwards communication. 4242307SN/A for (int inst_num = 0; inst_num < executeWidth && 4252307SN/A toCommit->insts[inst_num] != NULL; inst_num++) 4261060SN/A { 4272307SN/A DynInst *inst = toCommit->insts[inst_num]; 4282307SN/A 4299444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "IEW: Sending instructions to commit, PC %#x.\n", 4301060SN/A inst->readPC()); 4319427SAndreas.Sandberg@ARM.com 4322307SN/A instQueue.wakeDependents(inst); 4331060SN/A 4346221Snate@binkert.org for (int i = 0; i < inst->numDestRegs(); i++) 4356221Snate@binkert.org { 4366221Snate@binkert.org renameMap->markAsReady(inst->renamedDestRegIdx(i)); 4372307SN/A } 4381060SN/A } 4392307SN/A 4402307SN/A // Also should advance its own time buffers if the stage ran. 4412873Sktlim@umich.edu // Not the best place for it, but this works (hopefully). 4422307SN/A issueToExecQueue.advance(); 4431060SN/A} 4441060SN/A