iew_impl.hh revision 10239
11689SN/A/* 22326SN/A * Copyright (c) 2010-2013 ARM Limited 31689SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * The license below extends only to copyright in the software and shall 71689SN/A * not be construed as granting a license to any other intellectual 81689SN/A * property including but not limited to intellectual property relating 91689SN/A * to a hardware implementation of the functionality of the software 101689SN/A * licensed hereunder. You may use the software subject to the license 111689SN/A * terms below provided that you ensure that this notice is replicated 121689SN/A * unmodified and in its entirety in all distributions of the software, 131689SN/A * modified or unmodified, in source code or in binary form. 141689SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391717SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 401060SN/A * 411681SN/A * Authors: Kevin Lim 424329Sktlim@umich.edu */ 432873Sktlim@umich.edu 444329Sktlim@umich.edu#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 454329Sktlim@umich.edu#define __CPU_O3_IEW_IMPL_IMPL_HH__ 464329Sktlim@umich.edu 472292SN/A// @todo: Fix the instantaneous communication among all the stages within 482292SN/A// iew. There's a clear delay between issue and execute, yet backwards 492292SN/A// communication happens simultaneously. 502292SN/A 512820Sktlim@umich.edu#include <queue> 522292SN/A 532820Sktlim@umich.edu#include "arch/utility.hh" 542820Sktlim@umich.edu#include "config/the_isa.hh" 552307SN/A#include "cpu/checker/cpu.hh" 562307SN/A#include "cpu/o3/fu_pool.hh" 571060SN/A#include "cpu/o3/iew.hh" 582292SN/A#include "cpu/timebuf.hh" 592292SN/A#include "debug/Activity.hh" 602292SN/A#include "debug/Drain.hh" 611060SN/A#include "debug/IEW.hh" 621060SN/A#include "debug/O3PipeView.hh" 631060SN/A#include "params/DerivO3CPU.hh" 641060SN/A 651060SN/Ausing namespace std; 661060SN/A 671681SN/Atemplate<class Impl> 682292SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692292SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 702292SN/A cpu(_cpu), 712292SN/A instQueue(_cpu, this, params), 722292SN/A ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742820Sktlim@umich.edu commitToIEWDelay(params->commitToIEWDelay), 752820Sktlim@umich.edu renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772292SN/A dispatchWidth(params->dispatchWidth), 782820Sktlim@umich.edu issueWidth(params->issueWidth), 792820Sktlim@umich.edu wbOutstanding(0), 802292SN/A wbWidth(params->wbWidth), 812292SN/A numThreads(params->numThreads) 822292SN/A{ 832292SN/A if (dispatchWidth > Impl::MaxWidth) 842292SN/A fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 852292SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 862292SN/A dispatchWidth, static_cast<int>(Impl::MaxWidth)); 872292SN/A if (issueWidth > Impl::MaxWidth) 881060SN/A fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 891060SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 901681SN/A issueWidth, static_cast<int>(Impl::MaxWidth)); 911062SN/A if (wbWidth > Impl::MaxWidth) 922292SN/A fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 931062SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 942301SN/A wbWidth, static_cast<int>(Impl::MaxWidth)); 952301SN/A 961062SN/A _status = Active; 972727Sktlim@umich.edu exeStatus = Running; 981062SN/A wbStatus = Idle; 991062SN/A 1001062SN/A // Setup wire to read instructions coming from issue. 1011062SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1021062SN/A 1031062SN/A // Instruction queue needs the queue between issue and execute. 1041062SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1051062SN/A 1061062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1071062SN/A dispatchStatus[tid] = Running; 1081062SN/A stalls[tid].commit = false; 1091062SN/A fetchRedirect[tid] = false; 1101062SN/A } 1111062SN/A 1121062SN/A wbMax = wbWidth * params->wbDepth; 1131062SN/A 1141062SN/A updateLSQNextCycle = false; 1151062SN/A 1161062SN/A ableToIssue = true; 1171062SN/A 1181062SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1191062SN/A} 1201062SN/A 1211062SN/Atemplate <class Impl> 1221062SN/Astd::string 1231062SN/ADefaultIEW<Impl>::name() const 1241062SN/A{ 1251062SN/A return cpu->name() + ".iew"; 1261062SN/A} 1271062SN/A 1281062SN/Atemplate <class Impl> 1291062SN/Avoid 1301062SN/ADefaultIEW<Impl>::regProbePoints() 1311062SN/A{ 1321062SN/A ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1331062SN/A ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1341062SN/A} 1351062SN/A 1361062SN/Atemplate <class Impl> 1371062SN/Avoid 1381062SN/ADefaultIEW<Impl>::regStats() 1392292SN/A{ 1402292SN/A using namespace Stats; 1412292SN/A 1422292SN/A instQueue.regStats(); 1431062SN/A ldstQueue.regStats(); 1441062SN/A 1451062SN/A iewIdleCycles 1461062SN/A .name(name() + ".iewIdleCycles") 1471062SN/A .desc("Number of cycles IEW is idle"); 1481062SN/A 1491062SN/A iewSquashCycles 1502292SN/A .name(name() + ".iewSquashCycles") 1512292SN/A .desc("Number of cycles IEW is squashing"); 1522292SN/A 1532292SN/A iewBlockCycles 1542292SN/A .name(name() + ".iewBlockCycles") 1552292SN/A .desc("Number of cycles IEW is blocking"); 1562292SN/A 1572292SN/A iewUnblockCycles 1582292SN/A .name(name() + ".iewUnblockCycles") 1592292SN/A .desc("Number of cycles IEW is unblocking"); 1602301SN/A 1612727Sktlim@umich.edu iewDispatchedInsts 1622353SN/A .name(name() + ".iewDispatchedInsts") 1632727Sktlim@umich.edu .desc("Number of instructions dispatched to IQ"); 1642727Sktlim@umich.edu 1652727Sktlim@umich.edu iewDispSquashedInsts 1662727Sktlim@umich.edu .name(name() + ".iewDispSquashedInsts") 1672353SN/A .desc("Number of squashed instructions skipped by dispatch"); 1682727Sktlim@umich.edu 1692727Sktlim@umich.edu iewDispLoadInsts 1702727Sktlim@umich.edu .name(name() + ".iewDispLoadInsts") 1712727Sktlim@umich.edu .desc("Number of dispatched load instructions"); 1722353SN/A 1732727Sktlim@umich.edu iewDispStoreInsts 1742727Sktlim@umich.edu .name(name() + ".iewDispStoreInsts") 1752727Sktlim@umich.edu .desc("Number of dispatched store instructions"); 1762301SN/A 1772301SN/A iewDispNonSpecInsts 1782301SN/A .name(name() + ".iewDispNonSpecInsts") 1792727Sktlim@umich.edu .desc("Number of dispatched non-speculative instructions"); 1802301SN/A 1812727Sktlim@umich.edu iewIQFullEvents 1822301SN/A .name(name() + ".iewIQFullEvents") 1832301SN/A .desc("Number of times the IQ has become full, causing a stall"); 1842301SN/A 1852727Sktlim@umich.edu iewLSQFullEvents 1862301SN/A .name(name() + ".iewLSQFullEvents") 1872727Sktlim@umich.edu .desc("Number of times the LSQ has become full, causing a stall"); 1882301SN/A 1892301SN/A memOrderViolationEvents 1902301SN/A .name(name() + ".memOrderViolationEvents") 1912727Sktlim@umich.edu .desc("Number of memory order violations"); 1922301SN/A 1932727Sktlim@umich.edu predictedTakenIncorrect 1942301SN/A .name(name() + ".predictedTakenIncorrect") 1952301SN/A .desc("Number of branches that were predicted taken incorrectly"); 1962301SN/A 1972727Sktlim@umich.edu predictedNotTakenIncorrect 1982301SN/A .name(name() + ".predictedNotTakenIncorrect") 1992301SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2002301SN/A 2012301SN/A branchMispredicts 2022727Sktlim@umich.edu .name(name() + ".branchMispredicts") 2032727Sktlim@umich.edu .desc("Number of branch mispredicts detected at execute"); 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2062727Sktlim@umich.edu 2072727Sktlim@umich.edu iewExecutedInsts 2082727Sktlim@umich.edu .name(name() + ".iewExecutedInsts") 2092727Sktlim@umich.edu .desc("Number of executed instructions"); 2102727Sktlim@umich.edu 2112301SN/A iewExecLoadInsts 2122301SN/A .init(cpu->numThreads) 2132301SN/A .name(name() + ".iewExecLoadInsts") 2142301SN/A .desc("Number of load instructions executed") 2152301SN/A .flags(total); 2162727Sktlim@umich.edu 2172301SN/A iewExecSquashedInsts 2182326SN/A .name(name() + ".iewExecSquashedInsts") 2192301SN/A .desc("Number of squashed instructions skipped in execute"); 2202301SN/A 2212301SN/A iewExecutedSwp 2222727Sktlim@umich.edu .init(cpu->numThreads) 2232301SN/A .name(name() + ".exec_swp") 2242326SN/A .desc("number of swp insts executed") 2252301SN/A .flags(total); 2262301SN/A 2272301SN/A iewExecutedNop 2282727Sktlim@umich.edu .init(cpu->numThreads) 2292301SN/A .name(name() + ".exec_nop") 2302326SN/A .desc("number of nop insts executed") 2312301SN/A .flags(total); 2322301SN/A 2332301SN/A iewExecutedRefs 2342727Sktlim@umich.edu .init(cpu->numThreads) 2352301SN/A .name(name() + ".exec_refs") 2362326SN/A .desc("number of memory reference insts executed") 2372301SN/A .flags(total); 2382301SN/A 2392301SN/A iewExecutedBranches 2402727Sktlim@umich.edu .init(cpu->numThreads) 2412301SN/A .name(name() + ".exec_branches") 2422326SN/A .desc("Number of branches executed") 2432301SN/A .flags(total); 2442301SN/A 2452727Sktlim@umich.edu iewExecStoreInsts 2462301SN/A .name(name() + ".exec_stores") 2472326SN/A .desc("Number of stores executed") 2482301SN/A .flags(total); 2492326SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2502301SN/A 2512301SN/A iewExecRate 2522727Sktlim@umich.edu .name(name() + ".exec_rate") 2532301SN/A .desc("Inst execution rate") 2542326SN/A .flags(total); 2552301SN/A 2562326SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2572301SN/A 2582301SN/A iewInstsToCommit 2592727Sktlim@umich.edu .init(cpu->numThreads) 2602326SN/A .name(name() + ".wb_sent") 2611062SN/A .desc("cumulative count of insts sent to commit") 2621062SN/A .flags(total); 2631681SN/A 2641060SN/A writebackCount 2652292SN/A .init(cpu->numThreads) 2661060SN/A .name(name() + ".wb_count") 2672292SN/A .desc("cumulative count of insts written-back") 2682292SN/A .flags(total); 2692292SN/A 2702292SN/A producerInst 2712292SN/A .init(cpu->numThreads) 2722292SN/A .name(name() + ".wb_producers") 2732292SN/A .desc("num instructions producing a value") 2742292SN/A .flags(total); 2752292SN/A 2762292SN/A consumerInst 2772733Sktlim@umich.edu .init(cpu->numThreads) 2781060SN/A .name(name() + ".wb_consumers") 2791060SN/A .desc("num instructions consuming a value") 2801681SN/A .flags(total); 2811060SN/A 2822292SN/A wbPenalized 2831060SN/A .init(cpu->numThreads) 2841060SN/A .name(name() + ".wb_penalized") 2851060SN/A .desc("number of instrctions required to write to 'other' IQ") 2861060SN/A .flags(total); 2871060SN/A 2881060SN/A wbPenalizedRate 2891060SN/A .name(name() + ".wb_penalized_rate") 2901060SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2911060SN/A .flags(total); 2922292SN/A 2932292SN/A wbPenalizedRate = wbPenalized / writebackCount; 2941060SN/A 2951060SN/A wbFanout 2961060SN/A .name(name() + ".wb_fanout") 2971060SN/A .desc("average fanout of values written-back") 2981681SN/A .flags(total); 2991060SN/A 3002292SN/A wbFanout = producerInst / consumerInst; 3011060SN/A 3021060SN/A wbRate 3031060SN/A .name(name() + ".wb_rate") 3041060SN/A .desc("insts written-back per cycle") 3051060SN/A .flags(total); 3061060SN/A wbRate = writebackCount / cpu->numCycles; 3071060SN/A} 3081681SN/A 3091060SN/Atemplate<class Impl> 3102292SN/Avoid 3111060SN/ADefaultIEW<Impl>::startupStage() 3121060SN/A{ 3131060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3141060SN/A toRename->iewInfo[tid].usedIQ = true; 3151060SN/A toRename->iewInfo[tid].freeIQEntries = 3161060SN/A instQueue.numFreeEntries(tid); 3171060SN/A 3181681SN/A toRename->iewInfo[tid].usedLSQ = true; 3191060SN/A toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3202980Sgblack@eecs.umich.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3211060SN/A } 3222292SN/A 3232292SN/A // Initialize the checker's dcache port here 3242292SN/A if (cpu->checker) { 3252292SN/A cpu->checker->setDcachePort(&cpu->getDataPort()); 3261060SN/A } 3271060SN/A 3281681SN/A cpu->activateStage(O3CPU::IEWIdx); 3291060SN/A} 3302292SN/A 3311060SN/Atemplate<class Impl> 3322292SN/Avoid 3331060SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3341060SN/A{ 3352307SN/A timeBuffer = tb_ptr; 3362863Sktlim@umich.edu 3372843Sktlim@umich.edu // Setup wire to read information from time buffer, from commit. 3382307SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3392843Sktlim@umich.edu 3402843Sktlim@umich.edu // Setup wire to write information back to previous stages. 3412863Sktlim@umich.edu toRename = timeBuffer->getWire(0); 3421681SN/A 3431681SN/A toFetch = timeBuffer->getWire(0); 3442316SN/A 3451681SN/A // Instruction queue also needs main time buffer. 3462843Sktlim@umich.edu instQueue.setTimeBuffer(tb_ptr); 3472843Sktlim@umich.edu} 3482843Sktlim@umich.edu 3492843Sktlim@umich.edutemplate<class Impl> 3502843Sktlim@umich.eduvoid 3512843Sktlim@umich.eduDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3522843Sktlim@umich.edu{ 3531681SN/A renameQueue = rq_ptr; 3542348SN/A 3552307SN/A // Setup wire to read information from rename queue. 3562367SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3572367SN/A} 3581681SN/A 3592307SN/Atemplate<class Impl> 3602307SN/Avoid 3612307SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3622307SN/A{ 3632307SN/A iewQueue = iq_ptr; 3642307SN/A 3652307SN/A // Setup wire to write instructions to commit. 3662307SN/A toCommit = iewQueue->getWire(0); 3672307SN/A} 3682307SN/A 3691681SN/Atemplate<class Impl> 3701681SN/Avoid 3712307SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3721681SN/A{ 3732307SN/A activeThreads = at_ptr; 3741060SN/A 3752348SN/A ldstQueue.setActiveThreads(at_ptr); 3762307SN/A instQueue.setActiveThreads(at_ptr); 3772307SN/A} 3782307SN/A 3792307SN/Atemplate<class Impl> 3801060SN/Avoid 3812307SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3822307SN/A{ 3832307SN/A scoreboard = sb_ptr; 3841060SN/A} 3852307SN/A 3862307SN/Atemplate <class Impl> 3871060SN/Abool 3882307SN/ADefaultIEW<Impl>::isDrained() const 3892307SN/A{ 3902307SN/A bool drained(ldstQueue.isDrained()); 3912307SN/A 3922307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3931060SN/A if (!insts[tid].empty()) { 3942307SN/A DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3952307SN/A drained = false; 3962873Sktlim@umich.edu } 3972307SN/A if (!skidBuffer[tid].empty()) { 3981060SN/A DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3991060SN/A drained = false; 4001060SN/A } 4011681SN/A } 4021060SN/A 4032292SN/A // Also check the FU pool as instructions are "stored" in FU 4042107SN/A // completion events until they are done and not accounted for 4052292SN/A // above 4062292SN/A if (drained && !fuPool->isDrained()) { 4072107SN/A DPRINTF(Drain, "FU pool still busy.\n"); 4082292SN/A drained = false; 4092292SN/A } 4102107SN/A 4112292SN/A return drained; 4122326SN/A} 4132292SN/A 4142107SN/Atemplate <class Impl> 4152292SN/Avoid 4162935Sksewell@umich.eduDefaultIEW<Impl>::drainSanityCheck() const 4174632Sgblack@eecs.umich.edu{ 4182935Sksewell@umich.edu assert(isDrained()); 4192292SN/A 4202292SN/A instQueue.drainSanityCheck(); 4212292SN/A ldstQueue.drainSanityCheck(); 4222292SN/A} 4232292SN/A 4242107SN/Atemplate <class Impl> 4252292SN/Avoid 4262107SN/ADefaultIEW<Impl>::takeOverFrom() 4272292SN/A{ 4282292SN/A // Reset all state. 4292107SN/A _status = Active; 4302702Sktlim@umich.edu exeStatus = Running; 4312107SN/A wbStatus = Idle; 4322107SN/A 4332107SN/A instQueue.takeOverFrom(); 4342107SN/A ldstQueue.takeOverFrom(); 4352292SN/A fuPool->takeOverFrom(); 4362292SN/A 4372292SN/A startupStage(); 4382292SN/A cpu->activityThisCycle(); 4392292SN/A 4402292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4412292SN/A dispatchStatus[tid] = Running; 4422292SN/A stalls[tid].commit = false; 4432292SN/A fetchRedirect[tid] = false; 4442935Sksewell@umich.edu } 4454632Sgblack@eecs.umich.edu 4463969Sgblack@eecs.umich.edu updateLSQNextCycle = false; 4474632Sgblack@eecs.umich.edu 4483795Sgblack@eecs.umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4493795Sgblack@eecs.umich.edu issueToExecQueue.advance(); 4503795Sgblack@eecs.umich.edu } 4513093Sksewell@umich.edu} 4523093Sksewell@umich.edu 4533093Sksewell@umich.edutemplate<class Impl> 4544632Sgblack@eecs.umich.eduvoid 4553093Sksewell@umich.eduDefaultIEW<Impl>::squash(ThreadID tid) 4564632Sgblack@eecs.umich.edu{ 4574636Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4582292SN/A 4592292SN/A // Tell the IQ to start squashing. 4602292SN/A instQueue.squash(tid); 4612292SN/A 4622292SN/A // Tell the LDSTQ to start squashing. 4632292SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4642292SN/A updatedQueues = true; 4652292SN/A 4662292SN/A // Clear the skid buffer in case it has any data in it. 4672292SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4682292SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4692292SN/A 4702292SN/A while (!skidBuffer[tid].empty()) { 4712292SN/A if (skidBuffer[tid].front()->isLoad()) { 4722292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 4732292SN/A } 4743795Sgblack@eecs.umich.edu if (skidBuffer[tid].front()->isStore()) { 4753732Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToSQ++; 4762292SN/A } 4772292SN/A 4782292SN/A toRename->iewInfo[tid].dispatched++; 4792292SN/A 4802292SN/A skidBuffer[tid].pop(); 4812292SN/A } 4822292SN/A 4832292SN/A emptyRenameInsts(tid); 4842292SN/A} 4852292SN/A 4862292SN/Atemplate<class Impl> 4872292SN/Avoid 4882292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4892292SN/A{ 4902292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4912292SN/A "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4923958Sgblack@eecs.umich.edu 4933732Sktlim@umich.edu if (!toCommit->squash[tid] || 4942292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4952348SN/A toCommit->squash[tid] = true; 4962292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4972292SN/A toCommit->branchTaken[tid] = inst->pcState().branching(); 4982292SN/A 4992292SN/A TheISA::PCState pc = inst->pcState(); 5002292SN/A TheISA::advancePC(pc, inst->staticInst); 5012292SN/A 5022292SN/A toCommit->pc[tid] = pc; 5032292SN/A toCommit->mispredictInst[tid] = inst; 5042292SN/A toCommit->includeSquashInst[tid] = false; 5052292SN/A 5062292SN/A wroteToTimeBuffer = true; 5072292SN/A } 5082292SN/A 5092292SN/A} 5102292SN/A 5112292SN/Atemplate<class Impl> 5122292SN/Avoid 5132292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 5142292SN/A{ 5152292SN/A DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5162292SN/A "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5172292SN/A // Need to include inst->seqNum in the following comparison to cover the 5182292SN/A // corner case when a branch misprediction and a memory violation for the 5192292SN/A // same instruction (e.g. load PC) are detected in the same cycle. In this 5202292SN/A // case the memory violator should take precedence over the branch 5212292SN/A // misprediction because it requires the violator itself to be included in 5222292SN/A // the squash. 5232292SN/A if (!toCommit->squash[tid] || 5242292SN/A inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5252292SN/A toCommit->squash[tid] = true; 5262292SN/A 5272292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5282292SN/A toCommit->pc[tid] = inst->pcState(); 5292292SN/A toCommit->mispredictInst[tid] = NULL; 5302292SN/A 5312292SN/A // Must include the memory violator in the squash. 5322292SN/A toCommit->includeSquashInst[tid] = true; 5332292SN/A 5342292SN/A wroteToTimeBuffer = true; 5352292SN/A } 5362292SN/A} 5372292SN/A 5382292SN/Atemplate<class Impl> 5392292SN/Avoid 5402292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5412292SN/A{ 5421060SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5431681SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5441060SN/A if (!toCommit->squash[tid] || 5451060SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 5462292SN/A toCommit->squash[tid] = true; 5472292SN/A 5482292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5492292SN/A toCommit->pc[tid] = inst->pcState(); 5502292SN/A toCommit->mispredictInst[tid] = NULL; 5512292SN/A 5521681SN/A // Must include the broadcasted SN in the squash. 5531681SN/A toCommit->includeSquashInst[tid] = true; 5541060SN/A 5552292SN/A ldstQueue.setLoadBlockedHandled(tid); 5561060SN/A 5572292SN/A wroteToTimeBuffer = true; 5582292SN/A } 5591060SN/A} 5602292SN/A 5612292SN/Atemplate<class Impl> 5622292SN/Avoid 5632292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5643221Sktlim@umich.edu{ 5653221Sktlim@umich.edu DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5663221Sktlim@umich.edu 5673221Sktlim@umich.edu if (dispatchStatus[tid] != Blocked && 5683221Sktlim@umich.edu dispatchStatus[tid] != Unblocking) { 5692292SN/A toRename->iewBlock[tid] = true; 5702292SN/A wroteToTimeBuffer = true; 5712292SN/A } 5722292SN/A 5732326SN/A // Add the current inputs to the skid buffer so they can be 5742292SN/A // reprocessed when this stage unblocks. 5752292SN/A skidInsert(tid); 5762820Sktlim@umich.edu 5772292SN/A dispatchStatus[tid] = Blocked; 5782292SN/A} 5792292SN/A 5802292SN/Atemplate<class Impl> 5812353SN/Avoid 5822292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5832292SN/A{ 5842353SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5852353SN/A "buffer %u.\n",tid, tid); 5862292SN/A 5872292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5882292SN/A // Also switch status to running. 5892292SN/A if (skidBuffer[tid].empty()) { 5902292SN/A toRename->iewUnblock[tid] = true; 5912292SN/A wroteToTimeBuffer = true; 5922292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5932292SN/A dispatchStatus[tid] = Running; 5942292SN/A } 5952292SN/A} 5962292SN/A 5972292SN/Atemplate<class Impl> 5982731Sktlim@umich.eduvoid 5992292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 6002292SN/A{ 6012292SN/A instQueue.wakeDependents(inst); 6022292SN/A} 6032292SN/A 6042292SN/Atemplate<class Impl> 6052292SN/Avoid 6062292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6072292SN/A{ 6082292SN/A instQueue.rescheduleMemInst(inst); 6092292SN/A} 6102292SN/A 6112292SN/Atemplate<class Impl> 6122292SN/Avoid 6132292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6142292SN/A{ 6152292SN/A instQueue.replayMemInst(inst); 6162292SN/A} 6172292SN/A 6182292SN/Atemplate<class Impl> 6192292SN/Avoid 6202292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6212292SN/A{ 6222292SN/A // This function should not be called after writebackInsts in a 6232292SN/A // single cycle. That will cause problems with an instruction 6242292SN/A // being added to the queue to commit without being processed by 6252292SN/A // writebackInsts prior to being sent to commit. 6262292SN/A 6272292SN/A // First check the time slot that this instruction will write 6282292SN/A // to. If there are free write ports at the time, then go ahead 6292292SN/A // and write the instruction to that time. If there are not, 6302292SN/A // keep looking back to see where's the first time there's a 6312292SN/A // free slot. 6322292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6333867Sbinkertn@umich.edu ++wbNumInst; 6343867Sbinkertn@umich.edu if (wbNumInst == wbWidth) { 6352292SN/A ++wbCycle; 6363867Sbinkertn@umich.edu wbNumInst = 0; 6373867Sbinkertn@umich.edu } 6383867Sbinkertn@umich.edu 6392292SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6402292SN/A } 6412292SN/A 6422292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6432292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6442292SN/A // Add finished instruction to queue to commit. 6452292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6462292SN/A (*iewQueue)[wbCycle].size++; 6472292SN/A} 6482292SN/A 6492292SN/Atemplate <class Impl> 6503867Sbinkertn@umich.eduunsigned 6513867Sbinkertn@umich.eduDefaultIEW<Impl>::validInstsFromRename() 6522292SN/A{ 6533867Sbinkertn@umich.edu unsigned inst_count = 0; 6543867Sbinkertn@umich.edu 6553867Sbinkertn@umich.edu for (int i=0; i<fromRename->size; i++) { 6563867Sbinkertn@umich.edu if (!fromRename->insts[i]->isSquashed()) 6572292SN/A inst_count++; 6582292SN/A } 6592292SN/A 6602292SN/A return inst_count; 6611062SN/A} 6621062SN/A 6631681SN/Atemplate<class Impl> 6641062SN/Avoid 6652292SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6661062SN/A{ 6672292SN/A DynInstPtr inst = NULL; 6681062SN/A 6693867Sbinkertn@umich.edu while (!insts[tid].empty()) { 6703867Sbinkertn@umich.edu inst = insts[tid].front(); 6711062SN/A 6723867Sbinkertn@umich.edu insts[tid].pop(); 6732292SN/A 6741062SN/A DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6752292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6762292SN/A inst->pcState(),tid); 6772292SN/A 6782292SN/A skidBuffer[tid].push(inst); 6792292SN/A } 6801062SN/A 6812292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6822292SN/A "Skidbuffer Exceeded Max Size"); 6832292SN/A} 6842292SN/A 6852292SN/Atemplate<class Impl> 6862292SN/Aint 6871062SN/ADefaultIEW<Impl>::skidCount() 6882292SN/A{ 6891062SN/A int max=0; 6902292SN/A 6912292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6922292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6932292SN/A 6942292SN/A while (threads != end) { 6952292SN/A ThreadID tid = *threads++; 6961062SN/A unsigned thread_count = skidBuffer[tid].size(); 6972292SN/A if (max < thread_count) 6981062SN/A max = thread_count; 6992292SN/A } 7001062SN/A 7011062SN/A return max; 7021062SN/A} 7031681SN/A 7041062SN/Atemplate<class Impl> 7052292SN/Abool 7061062SN/ADefaultIEW<Impl>::skidsEmpty() 7072292SN/A{ 7082292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7092292SN/A list<ThreadID>::iterator end = activeThreads->end(); 7101062SN/A 7112292SN/A while (threads != end) { 7122292SN/A ThreadID tid = *threads++; 7132292SN/A 7142292SN/A if (!skidBuffer[tid].empty()) 7152292SN/A return false; 7162292SN/A } 7172292SN/A 7181062SN/A return true; 7192292SN/A} 7202292SN/A 7212292SN/Atemplate <class Impl> 7222292SN/Avoid 7232292SN/ADefaultIEW<Impl>::updateStatus() 7242292SN/A{ 7252292SN/A bool any_unblocking = false; 7262292SN/A 7272292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7282292SN/A list<ThreadID>::iterator end = activeThreads->end(); 7292292SN/A 7302292SN/A while (threads != end) { 7312292SN/A ThreadID tid = *threads++; 7322292SN/A 7332292SN/A if (dispatchStatus[tid] == Unblocking) { 7342292SN/A any_unblocking = true; 7352292SN/A break; 7362292SN/A } 7372292SN/A } 7382292SN/A 7392292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7402292SN/A // and there's no stores waiting to write back, and dispatch is not 7412292SN/A // unblocking, then there is no internal activity for the IEW stage. 7422292SN/A instQueue.intInstQueueReads++; 7432292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7442292SN/A !ldstQueue.willWB() && !any_unblocking) { 7452292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7462292SN/A 7472292SN/A deactivateStage(); 7482292SN/A 7492292SN/A _status = Inactive; 7502292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7512292SN/A ldstQueue.willWB() || 7522292SN/A any_unblocking)) { 7532292SN/A // Otherwise there is internal activity. Set to active. 7542292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7552292SN/A 7562292SN/A activateStage(); 7572292SN/A 7582292SN/A _status = Active; 7592292SN/A } 7602292SN/A} 7612292SN/A 7622292SN/Atemplate <class Impl> 7632292SN/Avoid 7642292SN/ADefaultIEW<Impl>::resetEntries() 7652292SN/A{ 7662292SN/A instQueue.resetEntries(); 7672292SN/A ldstQueue.resetEntries(); 7682292SN/A} 7692292SN/A 7702292SN/Atemplate <class Impl> 7712292SN/Avoid 7722292SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7732292SN/A{ 7742292SN/A if (fromCommit->commitBlock[tid]) { 7752292SN/A stalls[tid].commit = true; 7762292SN/A } 7772292SN/A 7782292SN/A if (fromCommit->commitUnblock[tid]) { 7792292SN/A assert(stalls[tid].commit); 7802292SN/A stalls[tid].commit = false; 7812292SN/A } 7822292SN/A} 7832292SN/A 7842292SN/Atemplate <class Impl> 7852292SN/Abool 7862292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7872292SN/A{ 7882292SN/A bool ret_val(false); 7892292SN/A 7902702Sktlim@umich.edu if (stalls[tid].commit) { 7912292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7922292SN/A ret_val = true; 7932292SN/A } else if (instQueue.isFull(tid)) { 7942702Sktlim@umich.edu DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7952702Sktlim@umich.edu ret_val = true; 7962292SN/A } else if (ldstQueue.isFull(tid)) { 7972292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7982292SN/A 7992292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 8002292SN/A 8012292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 8022292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 8032292SN/A } 8042292SN/A 8052292SN/A if (ldstQueue.numStores(tid) > 0) { 8062292SN/A 8072292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8082292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8092292SN/A } 8102292SN/A 8112292SN/A ret_val = true; 8122292SN/A } else if (ldstQueue.isStalled(tid)) { 8132292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8142292SN/A ret_val = true; 8152292SN/A } 8162292SN/A 8172292SN/A return ret_val; 8182292SN/A} 8192292SN/A 8202292SN/Atemplate <class Impl> 8212292SN/Avoid 8222292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 8232292SN/A{ 8242292SN/A // Check if there's a squash signal, squash if there is 8252292SN/A // Check stall signals, block if there is. 8262292SN/A // If status was Blocked 8272292SN/A // if so then go to unblocking 8282292SN/A // If status was Squashing 8292292SN/A // check if squashing is not high. Switch to running this cycle. 8302292SN/A 8312292SN/A readStallSignals(tid); 8322292SN/A 8332292SN/A if (fromCommit->commitInfo[tid].squash) { 8342292SN/A squash(tid); 8352326SN/A 8362292SN/A if (dispatchStatus[tid] == Blocked || 8372292SN/A dispatchStatus[tid] == Unblocking) { 8382326SN/A toRename->iewUnblock[tid] = true; 8392292SN/A wroteToTimeBuffer = true; 8402292SN/A } 8412292SN/A 8422292SN/A dispatchStatus[tid] = Squashing; 8432292SN/A fetchRedirect[tid] = false; 8442292SN/A return; 8452292SN/A } 8462702Sktlim@umich.edu 8472702Sktlim@umich.edu if (fromCommit->commitInfo[tid].robSquashing) { 8484632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8492935Sksewell@umich.edu 8502702Sktlim@umich.edu dispatchStatus[tid] = Squashing; 8512935Sksewell@umich.edu emptyRenameInsts(tid); 8522702Sktlim@umich.edu wroteToTimeBuffer = true; 8532702Sktlim@umich.edu return; 8542702Sktlim@umich.edu } 8552702Sktlim@umich.edu 8562702Sktlim@umich.edu if (checkStall(tid)) { 8572702Sktlim@umich.edu block(tid); 8582702Sktlim@umich.edu dispatchStatus[tid] = Blocked; 8592702Sktlim@umich.edu return; 8602702Sktlim@umich.edu } 8612702Sktlim@umich.edu 8622702Sktlim@umich.edu if (dispatchStatus[tid] == Blocked) { 8632702Sktlim@umich.edu // Status from previous cycle was blocked, but there are no more stall 8642702Sktlim@umich.edu // conditions. Switch over to unblocking. 8652292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8662292SN/A tid); 8672292SN/A 8682292SN/A dispatchStatus[tid] = Unblocking; 8692292SN/A 8702292SN/A unblock(tid); 8712292SN/A 8722292SN/A return; 8732292SN/A } 8742292SN/A 8752292SN/A if (dispatchStatus[tid] == Squashing) { 8762292SN/A // Switch status to running if rename isn't being told to block or 8772292SN/A // squash this cycle. 8782292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8792292SN/A tid); 8802292SN/A 8812292SN/A dispatchStatus[tid] = Running; 8822292SN/A 8832733Sktlim@umich.edu return; 8842292SN/A } 8852292SN/A} 8862292SN/A 8872292SN/Atemplate <class Impl> 8882292SN/Avoid 8892292SN/ADefaultIEW<Impl>::sortInsts() 8902292SN/A{ 8912733Sktlim@umich.edu int insts_from_rename = fromRename->size; 8922292SN/A#ifdef DEBUG 8932292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8942292SN/A assert(insts[tid].empty()); 8952292SN/A#endif 8962292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8972292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8982292SN/A } 8992292SN/A} 9002292SN/A 9012292SN/Atemplate <class Impl> 9022292SN/Avoid 9032292SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 9042292SN/A{ 9052292SN/A DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 9062292SN/A 9072292SN/A while (!insts[tid].empty()) { 9082292SN/A 9092292SN/A if (insts[tid].front()->isLoad()) { 9102292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 9112292SN/A } 9122292SN/A if (insts[tid].front()->isStore()) { 9132292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 9142292SN/A } 9152292SN/A 9162292SN/A toRename->iewInfo[tid].dispatched++; 9172292SN/A 9182292SN/A insts[tid].pop(); 9192292SN/A } 9202292SN/A} 9212292SN/A 9222292SN/Atemplate <class Impl> 9232292SN/Avoid 9242292SN/ADefaultIEW<Impl>::wakeCPU() 9252292SN/A{ 9262292SN/A cpu->wakeCPU(); 9272292SN/A} 9282292SN/A 9292292SN/Atemplate <class Impl> 9302292SN/Avoid 9312292SN/ADefaultIEW<Impl>::activityThisCycle() 9325215Sgblack@eecs.umich.edu{ 9332292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9342292SN/A cpu->activityThisCycle(); 9352292SN/A} 9362292SN/A 9372292SN/Atemplate <class Impl> 9382292SN/Ainline void 9392292SN/ADefaultIEW<Impl>::activateStage() 9402292SN/A{ 9412292SN/A DPRINTF(Activity, "Activating stage.\n"); 9422292SN/A cpu->activateStage(O3CPU::IEWIdx); 9432292SN/A} 9442292SN/A 9452292SN/Atemplate <class Impl> 9462292SN/Ainline void 9472292SN/ADefaultIEW<Impl>::deactivateStage() 9482292SN/A{ 9492292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9502292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 9512292SN/A} 9522292SN/A 9532292SN/Atemplate<class Impl> 9542292SN/Avoid 9552292SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9562292SN/A{ 9572292SN/A // If status is Running or idle, 9582292SN/A // call dispatchInsts() 9592292SN/A // If status is Unblocking, 9602292SN/A // buffer any instructions coming from rename 9612820Sktlim@umich.edu // continue trying to empty skid buffer 9622292SN/A // check if stall conditions have passed 9632292SN/A 9642292SN/A if (dispatchStatus[tid] == Blocked) { 9652292SN/A ++iewBlockCycles; 9662292SN/A 9672292SN/A } else if (dispatchStatus[tid] == Squashing) { 9682292SN/A ++iewSquashCycles; 9692292SN/A } 9702292SN/A 9712292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9722292SN/A // will allow, as long as it is not currently blocked. 9732292SN/A if (dispatchStatus[tid] == Running || 9742292SN/A dispatchStatus[tid] == Idle) { 9752292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9762292SN/A "dispatch.\n", tid); 9772292SN/A 9782292SN/A dispatchInsts(tid); 9792292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9802292SN/A // Make sure that the skid buffer has something in it if the 9812292SN/A // status is unblocking. 9822292SN/A assert(!skidsEmpty()); 9832292SN/A 9842292SN/A // If the status was unblocking, then instructions from the skid 9852292SN/A // buffer were used. Remove those instructions and handle 9862292SN/A // the rest of unblocking. 9872292SN/A dispatchInsts(tid); 9882292SN/A 9892292SN/A ++iewUnblockCycles; 9902292SN/A 9912292SN/A if (validInstsFromRename()) { 9922292SN/A // Add the current inputs to the skid buffer so they can be 9932292SN/A // reprocessed when this stage unblocks. 9942292SN/A skidInsert(tid); 9952292SN/A } 9962292SN/A 9972292SN/A unblock(tid); 9982292SN/A } 9992292SN/A} 10002292SN/A 10012292SN/Atemplate <class Impl> 10022292SN/Avoid 10032292SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 10042292SN/A{ 10052292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 10062292SN/A // otherwise. 10072292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 10082292SN/A dispatchStatus[tid] == Unblocking ? 10092292SN/A skidBuffer[tid] : insts[tid]; 10102292SN/A 10112292SN/A int insts_to_add = insts_to_dispatch.size(); 10122292SN/A 10132292SN/A DynInstPtr inst; 10142292SN/A bool add_to_iq = false; 10152292SN/A int dis_num_inst = 0; 10162292SN/A 10172292SN/A // Loop through the instructions, putting them in the instruction 10182292SN/A // queue. 10192292SN/A for ( ; dis_num_inst < insts_to_add && 10202292SN/A dis_num_inst < dispatchWidth; 10212292SN/A ++dis_num_inst) 10222292SN/A { 10232292SN/A inst = insts_to_dispatch.front(); 10242292SN/A 10252292SN/A if (dispatchStatus[tid] == Unblocking) { 10262292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10272292SN/A "buffer\n", tid); 10282292SN/A } 10292292SN/A 10302292SN/A // Make sure there's a valid instruction there. 10312292SN/A assert(inst); 10322292SN/A 10332292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10342292SN/A "IQ.\n", 10352292SN/A tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10362292SN/A 10372292SN/A // Be sure to mark these instructions as ready so that the 10382292SN/A // commit stage can go ahead and execute them, and mark 10392292SN/A // them as issued so the IQ doesn't reprocess them. 10402292SN/A 10412292SN/A // Check for squashed instructions. 10422292SN/A if (inst->isSquashed()) { 10432292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10442292SN/A "not adding to IQ.\n", tid); 10452292SN/A 10462292SN/A ++iewDispSquashedInsts; 10472292SN/A 10482292SN/A insts_to_dispatch.pop(); 10492292SN/A 10502292SN/A //Tell Rename That An Instruction has been processed 10512336SN/A if (inst->isLoad()) { 10522336SN/A toRename->iewInfo[tid].dispatchedToLQ++; 10532336SN/A } 10542336SN/A if (inst->isStore()) { 10552348SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10562292SN/A } 10572292SN/A 10582292SN/A toRename->iewInfo[tid].dispatched++; 10592292SN/A 10602292SN/A continue; 10612292SN/A } 10622292SN/A 10632292SN/A // Check for full conditions. 10642292SN/A if (instQueue.isFull(tid)) { 10652292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10662292SN/A 10672326SN/A // Call function to start blocking. 10682292SN/A block(tid); 10692292SN/A 10702292SN/A // Set unblock to false. Special case where we are using 10712292SN/A // skidbuffer (unblocking) instructions but then we still 10722292SN/A // get full in the IQ. 10732292SN/A toRename->iewUnblock[tid] = false; 10742292SN/A 10752292SN/A ++iewIQFullEvents; 10762292SN/A break; 10772292SN/A } else if (ldstQueue.isFull(tid)) { 10782292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10792326SN/A 10802292SN/A // Call function to start blocking. 10812727Sktlim@umich.edu block(tid); 10822301SN/A 10832292SN/A // Set unblock to false. Special case where we are using 10842292SN/A // skidbuffer (unblocking) instructions but then we still 10852292SN/A // get full in the IQ. 10862292SN/A toRename->iewUnblock[tid] = false; 10872292SN/A 10882292SN/A ++iewLSQFullEvents; 10892292SN/A break; 10902292SN/A } 10912292SN/A 10922326SN/A // Otherwise issue the instruction just fine. 10932292SN/A if (inst->isLoad()) { 10942292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10952292SN/A "encountered, adding to LSQ.\n", tid); 10962292SN/A 10972292SN/A // Reserve a spot in the load store queue for this 10984033Sktlim@umich.edu // memory access. 10994033Sktlim@umich.edu ldstQueue.insertLoad(inst); 11004033Sktlim@umich.edu 11014033Sktlim@umich.edu ++iewDispLoadInsts; 11024033Sktlim@umich.edu 11034033Sktlim@umich.edu add_to_iq = true; 11044033Sktlim@umich.edu 11054033Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLQ++; 11064033Sktlim@umich.edu } else if (inst->isStore()) { 11074033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 11084033Sktlim@umich.edu "encountered, adding to LSQ.\n", tid); 11094033Sktlim@umich.edu 11104033Sktlim@umich.edu ldstQueue.insertStore(inst); 11114033Sktlim@umich.edu 11122292SN/A ++iewDispStoreInsts; 11132292SN/A 11142292SN/A if (inst->isStoreConditional()) { 11152292SN/A // Store conditionals need to be set as "canCommit()" 11162292SN/A // so that commit can process them when they reach the 11172292SN/A // head of commit. 11182292SN/A // @todo: This is somewhat specific to Alpha. 11192292SN/A inst->setCanCommit(); 11202292SN/A instQueue.insertNonSpec(inst); 11212292SN/A add_to_iq = false; 11222292SN/A 11232292SN/A ++iewDispNonSpecInsts; 11242292SN/A } else { 11252292SN/A add_to_iq = true; 11262292SN/A } 11272935Sksewell@umich.edu 11282292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 11292292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11302292SN/A // Same as non-speculative stores. 11312292SN/A inst->setCanCommit(); 11322292SN/A instQueue.insertBarrier(inst); 11332292SN/A add_to_iq = false; 11342292SN/A } else if (inst->isNop()) { 11352292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11362292SN/A "skipping.\n", tid); 11372292SN/A 11382292SN/A inst->setIssued(); 11392292SN/A inst->setExecuted(); 11402292SN/A inst->setCanCommit(); 11412292SN/A 11422292SN/A instQueue.recordProducer(inst); 11432292SN/A 11442292SN/A iewExecutedNop[tid]++; 11452292SN/A 11462292SN/A add_to_iq = false; 11472980Sgblack@eecs.umich.edu } else if (inst->isExecuted()) { 11482292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11492292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11502292SN/A "skipping.\n"); 11512980Sgblack@eecs.umich.edu 11522292SN/A inst->setIssued(); 11532980Sgblack@eecs.umich.edu inst->setCanCommit(); 11542292SN/A 11552292SN/A instQueue.recordProducer(inst); 11562292SN/A 11572292SN/A add_to_iq = false; 11582292SN/A } else { 11592292SN/A add_to_iq = true; 11602292SN/A } 11612980Sgblack@eecs.umich.edu if (inst->isNonSpeculative()) { 11622292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11632292SN/A "encountered, skipping.\n", tid); 11642292SN/A 11652292SN/A // Same as non-speculative stores. 11662292SN/A inst->setCanCommit(); 11672292SN/A 11682292SN/A // Specifically insert it as nonspeculative. 11692292SN/A instQueue.insertNonSpec(inst); 11702292SN/A 11713867Sbinkertn@umich.edu ++iewDispNonSpecInsts; 11723867Sbinkertn@umich.edu 11732292SN/A add_to_iq = false; 11743867Sbinkertn@umich.edu } 11752292SN/A 11762292SN/A // If the instruction queue is not full, then add the 11772292SN/A // instruction. 11782292SN/A if (add_to_iq) { 11792698Sktlim@umich.edu instQueue.insert(inst); 11802698Sktlim@umich.edu } 11811062SN/A 11821062SN/A insts_to_dispatch.pop(); 11832333SN/A 11842292SN/A toRename->iewInfo[tid].dispatched++; 11852333SN/A 11862326SN/A ++iewDispatchedInsts; 11871062SN/A 11882292SN/A#if TRACING_ON 11891062SN/A inst->dispatchTick = curTick() - inst->fetchTick; 11902333SN/A#endif 11911062SN/A ppDispatch->notify(inst); 11922292SN/A } 11932292SN/A 11941062SN/A if (!insts_to_dispatch.empty()) { 11951062SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11961062SN/A block(tid); 11972292SN/A toRename->iewUnblock[tid] = false; 11981062SN/A } 11991062SN/A 12001062SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 12011062SN/A dispatchStatus[tid] = Running; 12021062SN/A 12032292SN/A updatedQueues = true; 12042292SN/A } 12052292SN/A 12061062SN/A dis_num_inst = 0; 12071062SN/A} 12081062SN/A 12092820Sktlim@umich.edutemplate <class Impl> 12101062SN/Avoid 12111062SN/ADefaultIEW<Impl>::printAvailableInsts() 12121062SN/A{ 12132292SN/A int inst = 0; 12141062SN/A 12151062SN/A std::cout << "Available Instructions: "; 12161062SN/A 12171062SN/A while (fromIssue->insts[inst]) { 12182292SN/A 12192292SN/A if (inst%3==0) std::cout << "\n\t"; 12202292SN/A 12211062SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 12221062SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12231062SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12241062SN/A 12252292SN/A inst++; 12262292SN/A 12272292SN/A } 12281062SN/A 12292367SN/A std::cout << "\n"; 12301062SN/A} 12312292SN/A 12322367SN/Atemplate <class Impl> 12332292SN/Avoid 12342292SN/ADefaultIEW<Impl>::executeInsts() 12352292SN/A{ 12362367SN/A wbNumInst = 0; 12372367SN/A wbCycle = 0; 12382367SN/A 12393732Sktlim@umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 12403732Sktlim@umich.edu list<ThreadID>::iterator end = activeThreads->end(); 12412367SN/A 12422367SN/A while (threads != end) { 12432367SN/A ThreadID tid = *threads++; 12442367SN/A fetchRedirect[tid] = false; 12452367SN/A } 12462367SN/A 12472367SN/A // Uncomment this if you want to see all available instructions. 12482292SN/A // @todo This doesn't actually work anymore, we should fix it. 12492326SN/A// printAvailableInsts(); 12502326SN/A 12512326SN/A // Execute/writeback any instructions that are available. 12522326SN/A int insts_to_execute = fromIssue->size; 12531062SN/A int inst_num = 0; 12542292SN/A for (; inst_num < insts_to_execute; 12551062SN/A ++inst_num) { 12561062SN/A 12571062SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12581062SN/A 12591062SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12602292SN/A 12612292SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12622292SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12631062SN/A 12641062SN/A // Check if the instruction is squashed; if so then skip it 12652301SN/A if (inst->isSquashed()) { 12661681SN/A DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12672326SN/A " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12682326SN/A inst->seqNum); 12692326SN/A 12702107SN/A // Consider this instruction executed so that commit can go 12711681SN/A // ahead and retire the instruction. 12722292SN/A inst->setExecuted(); 12732292SN/A 12742292SN/A // Not sure if I should set this here or just let commit try to 12752292SN/A // commit any squashed instructions. I like the latter a bit more. 12761062SN/A inst->setCanCommit(); 12773732Sktlim@umich.edu 12783732Sktlim@umich.edu ++iewExecSquashedInsts; 12791062SN/A 12801062SN/A decrWb(inst->seqNum); 12812292SN/A continue; 12821062SN/A } 12832292SN/A 12843969Sgblack@eecs.umich.edu Fault fault = NoFault; 12853969Sgblack@eecs.umich.edu 12863969Sgblack@eecs.umich.edu // Execute instruction. 12873969Sgblack@eecs.umich.edu // Note that if the instruction faults, it will be handled 12883969Sgblack@eecs.umich.edu // at the commit stage. 12891062SN/A if (inst->isMemRef()) { 12902292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12911062SN/A "reference.\n"); 12923795Sgblack@eecs.umich.edu 12931062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12942292SN/A if (inst->isLoad()) { 12952292SN/A // Loads will mark themselves as executed, and their writeback 12961062SN/A // event adds the instruction to the queue to commit 12972292SN/A fault = ldstQueue.executeLoad(inst); 12984033Sktlim@umich.edu 12992326SN/A if (inst->isTranslationDelayed() && 13002326SN/A fault == NoFault) { 13012292SN/A // A hw page table walk is currently going on; the 13022292SN/A // instruction must be deferred. 13032292SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 13041062SN/A "load.\n"); 13052292SN/A instQueue.deferMemInst(inst); 13061062SN/A continue; 13071062SN/A } 13081062SN/A 13093732Sktlim@umich.edu if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 13103732Sktlim@umich.edu inst->fault = NoFault; 13114033Sktlim@umich.edu } 13124033Sktlim@umich.edu } else if (inst->isStore()) { 13133732Sktlim@umich.edu fault = ldstQueue.executeStore(inst); 13144033Sktlim@umich.edu 13153732Sktlim@umich.edu if (inst->isTranslationDelayed() && 13163732Sktlim@umich.edu fault == NoFault) { 13171062SN/A // A hw page table walk is currently going on; the 13181062SN/A // instruction must be deferred. 13191062SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 13201062SN/A "store.\n"); 13212292SN/A instQueue.deferMemInst(inst); 13221062SN/A continue; 13231062SN/A } 13242292SN/A 13252292SN/A // If the store had a fault then it may not have a mem req 13262292SN/A if (fault != NoFault || !inst->readPredicate() || 13272292SN/A !inst->isStoreConditional()) { 13282292SN/A // If the instruction faulted, then we need to send it along 13292292SN/A // to commit without the instruction completing. 13302292SN/A // Send this instruction to commit, also make sure iew stage 13312292SN/A // realizes there is activity. 13322292SN/A inst->setExecuted(); 13331062SN/A instToCommit(inst); 13344033Sktlim@umich.edu activityThisCycle(); 13354033Sktlim@umich.edu } 13364033Sktlim@umich.edu 13374033Sktlim@umich.edu // Store conditionals will mark themselves as 13384033Sktlim@umich.edu // executed, and their writeback event will add the 13394033Sktlim@umich.edu // instruction to the queue to commit. 13404033Sktlim@umich.edu } else { 13414033Sktlim@umich.edu panic("Unexpected memory type!\n"); 13424033Sktlim@umich.edu } 13434033Sktlim@umich.edu 13444033Sktlim@umich.edu } else { 13454033Sktlim@umich.edu // If the instruction has already faulted, then skip executing it. 13464033Sktlim@umich.edu // Such case can happen when it faulted during ITLB translation. 13474033Sktlim@umich.edu // If we execute the instruction (even if it's a nop) the fault 13484033Sktlim@umich.edu // will be replaced and we will lose it. 13494033Sktlim@umich.edu if (inst->getFault() == NoFault) { 13504033Sktlim@umich.edu inst->execute(); 13514033Sktlim@umich.edu if (!inst->readPredicate()) 13524033Sktlim@umich.edu inst->forwardOldRegs(); 13534033Sktlim@umich.edu } 13544033Sktlim@umich.edu 13554033Sktlim@umich.edu inst->setExecuted(); 13564033Sktlim@umich.edu 13574033Sktlim@umich.edu instToCommit(inst); 13584033Sktlim@umich.edu } 13594033Sktlim@umich.edu 13604033Sktlim@umich.edu updateExeInstStats(inst); 13611062SN/A 13621062SN/A // Check if branch prediction was correct, if not then we need 13632292SN/A // to tell commit to squash in flight instructions. Only 13642348SN/A // handle this if there hasn't already been something that 13652292SN/A // redirects fetch in this group of instructions. 13662292SN/A 13672292SN/A // This probably needs to prioritize the redirects if a different 13682292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13692292SN/A // instruction first, so the branch resolution order will be correct. 13702292SN/A ThreadID tid = inst->threadNumber; 13712292SN/A 13722292SN/A if (!fetchRedirect[tid] || 13732292SN/A !toCommit->squash[tid] || 13742292SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 13752292SN/A 13762292SN/A // Prevent testing for misprediction on load instructions, 13772292SN/A // that have not been executed. 13782292SN/A bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13792107SN/A 13802107SN/A if (inst->mispredicted() && !loadNotExecuted) { 13812292SN/A fetchRedirect[tid] = true; 13822107SN/A 13832292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13842107SN/A DPRINTF(IEW, "Predicted target was PC: %s.\n", 13852326SN/A inst->readPredTarg()); 13862326SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13872326SN/A inst->pcState()); 13882326SN/A // If incorrect, then signal the ROB that it must be squashed. 13892326SN/A squashDueToBranch(inst, tid); 13903958Sgblack@eecs.umich.edu 13912292SN/A ppMispredict->notify(inst); 13922107SN/A 13932301SN/A if (inst->readPredTaken()) { 13942107SN/A predictedTakenIncorrect++; 13952698Sktlim@umich.edu } else { 13962698Sktlim@umich.edu predictedNotTakenIncorrect++; 13972107SN/A } 13982301SN/A } else if (ldstQueue.violation(tid)) { 13992301SN/A assert(inst->isMemRef()); 14002292SN/A // If there was an ordering violation, then get the 14012292SN/A // DynInst that caused the violation. Note that this 14022292SN/A // clears the violation signal. 14032292SN/A DynInstPtr violator; 14042292SN/A violator = ldstQueue.getMemDepViolator(tid); 14052367SN/A 14062301SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 14072107SN/A "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 14082292SN/A violator->pcState(), violator->seqNum, 14092292SN/A inst->pcState(), inst->seqNum, inst->physEffAddr); 14102292SN/A 14112292SN/A fetchRedirect[tid] = true; 14122292SN/A 14132107SN/A // Tell the instruction queue that a violation has occured. 14142301SN/A instQueue.violation(inst, violator); 14152348SN/A 14162348SN/A // Squash. 14172348SN/A squashDueToMemOrder(violator, tid); 14182348SN/A 14192326SN/A ++memOrderViolationEvents; 14202107SN/A } else if (ldstQueue.loadBlocked(tid) && 14212820Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14222820Sktlim@umich.edu fetchRedirect[tid] = true; 14232107SN/A 14241060SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 14251060SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 14261681SN/A inst->pcState(), inst->seqNum); 14271060SN/A 14282292SN/A squashDueToMemBlocked(inst, tid); 14291060SN/A } 14302292SN/A } else { 14312292SN/A // Reset any state associated with redirects that will not 14321060SN/A // be used. 14332292SN/A if (ldstQueue.violation(tid)) { 14342292SN/A assert(inst->isMemRef()); 14351060SN/A 14362292SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14371060SN/A 14382326SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14392326SN/A "%s, inst PC: %s. Addr is: %#x.\n", 14401062SN/A violator->pcState(), inst->pcState(), 14413867Sbinkertn@umich.edu inst->physEffAddr); 14423867Sbinkertn@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14431060SN/A "already squashing\n"); 14442326SN/A 14453867Sbinkertn@umich.edu ++memOrderViolationEvents; 14463867Sbinkertn@umich.edu } 14471060SN/A if (ldstQueue.loadBlocked(tid) && 14482292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 14491060SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 14502292SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 14512292SN/A inst->pcState(), inst->seqNum); 14521060SN/A DPRINTF(IEW, "Blocked load will not be handled because " 14531060SN/A "already squashing\n"); 14542292SN/A 14552292SN/A ldstQueue.setLoadBlockedHandled(tid); 14561060SN/A } 14572292SN/A 14582292SN/A } 14592292SN/A } 14602292SN/A 14612292SN/A // Update and record activity if we processed any instructions. 14622292SN/A if (inst_num) { 14632292SN/A if (exeStatus == Idle) { 14642292SN/A exeStatus = Running; 14652292SN/A } 14662292SN/A 14672292SN/A updatedQueues = true; 14682292SN/A 14692292SN/A cpu->activityThisCycle(); 14702292SN/A } 14712292SN/A 14722292SN/A // Need to reset this in case a writeback event needs to write into the 14732292SN/A // iew queue. That way the writeback event will write into the correct 14742292SN/A // spot in the queue. 14752292SN/A wbNumInst = 0; 14762292SN/A 14772292SN/A} 14782292SN/A 14791681SN/Atemplate <class Impl> 14801681SN/Avoid 14811061SN/ADefaultIEW<Impl>::writebackInsts() 14821061SN/A{ 14831061SN/A // Loop through the head of the time buffer and wake any 14841681SN/A // dependents. These instructions are about to write back. Also 14852292SN/A // mark scoreboard that this instruction is finally complete. 14863867Sbinkertn@umich.edu // Either have IEW have direct access to scoreboard, or have this 14873867Sbinkertn@umich.edu // as part of backwards communication. 14882292SN/A for (int inst_num = 0; inst_num < wbWidth && 14892292SN/A toCommit->insts[inst_num]; inst_num++) { 14902292SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14912292SN/A ThreadID tid = inst->threadNumber; 14922348SN/A 14932292SN/A DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14942292SN/A inst->seqNum, inst->pcState()); 14952292SN/A 14962292SN/A iewInstsToCommit[tid]++; 14972292SN/A 14982292SN/A // Some instructions will be sent to commit without having 14992292SN/A // executed because they need commit to handle them. 15002292SN/A // E.g. Uncached loads have not actually executed when they 15012292SN/A // are first sent to commit. Instead commit must tell the LSQ 15022292SN/A // when it's ready to execute the uncached load. 15032292SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 15042292SN/A int dependents = instQueue.wakeDependents(inst); 15052292SN/A 15062292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 15072292SN/A //mark as Ready 15082292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 15092292SN/A inst->renamedDestRegIdx(i)); 15104033Sktlim@umich.edu scoreboard->setReg(inst->renamedDestRegIdx(i)); 15112292SN/A } 15122292SN/A 15132292SN/A if (dependents) { 15142292SN/A producerInst[tid]++; 15152292SN/A consumerInst[tid]+= dependents; 15162292SN/A } 15172292SN/A writebackCount[tid]++; 15182292SN/A } 15192292SN/A 15202292SN/A decrWb(inst->seqNum); 15212292SN/A } 15222292SN/A} 15232292SN/A 15242292SN/Atemplate<class Impl> 15252292SN/Avoid 15262292SN/ADefaultIEW<Impl>::tick() 15272292SN/A{ 15282292SN/A wbNumInst = 0; 15292292SN/A wbCycle = 0; 15302292SN/A 15312292SN/A wroteToTimeBuffer = false; 15322292SN/A updatedQueues = false; 15332292SN/A 15342292SN/A sortInsts(); 15351061SN/A 15361061SN/A // Free function units marked as being freed this cycle. 15372292SN/A fuPool->processFreeUnits(); 15382292SN/A 15392292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 15402292SN/A list<ThreadID>::iterator end = activeThreads->end(); 15412292SN/A 15422292SN/A // Check stall and squash signals, dispatch any instructions. 15432292SN/A while (threads != end) { 15442292SN/A ThreadID tid = *threads++; 15452292SN/A 15462292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15471061SN/A 15481060SN/A checkSignalsAndUpdate(tid); 15491060SN/A dispatch(tid); 15502301SN/A } 15511060SN/A 15522301SN/A if (exeStatus != Squashing) { 15531060SN/A executeInsts(); 15542301SN/A 15551060SN/A writebackInsts(); 15562301SN/A 15572301SN/A // Have the instruction queue try to schedule any ready instructions. 15582301SN/A // (In actuality, this scheduling is for instructions that will 15592301SN/A // be executed next cycle.) 15602301SN/A instQueue.scheduleReadyInsts(); 15612727Sktlim@umich.edu 15622301SN/A // Also should advance its own time buffers if the stage ran. 15632727Sktlim@umich.edu // Not the best place for it, but this works (hopefully). 15642301SN/A issueToExecQueue.advance(); 15652669Sktlim@umich.edu } 15662301SN/A 15671060SN/A bool broadcast_free_entries = false; 15682301SN/A 15692301SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15702301SN/A exeStatus = Idle; 15712301SN/A updateLSQNextCycle = false; 15722727Sktlim@umich.edu 15731060SN/A broadcast_free_entries = true; 15742301SN/A } 15752301SN/A 15762301SN/A // Writeback any stores using any leftover bandwidth. 15772301SN/A ldstQueue.writebackStores(); 15782727Sktlim@umich.edu 15791060SN/A // Check the committed load/store signals to see if there's a load 15802301SN/A // or store to commit. Also check if it's being told to execute a 15812301SN/A // nonspeculative instruction. 15821060SN/A // This is pretty inefficient... 15831060SN/A 15841060SN/A threads = activeThreads->begin(); 1585 while (threads != end) { 1586 ThreadID tid = (*threads++); 1587 1588 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1589 1590 // Update structures based on instructions committed. 1591 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1592 !fromCommit->commitInfo[tid].squash && 1593 !fromCommit->commitInfo[tid].robSquashing) { 1594 1595 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1596 1597 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1598 1599 updateLSQNextCycle = true; 1600 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1601 } 1602 1603 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1604 1605 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1606 if (fromCommit->commitInfo[tid].uncached) { 1607 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1608 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1609 } else { 1610 instQueue.scheduleNonSpec( 1611 fromCommit->commitInfo[tid].nonSpecSeqNum); 1612 } 1613 } 1614 1615 if (broadcast_free_entries) { 1616 toFetch->iewInfo[tid].iqCount = 1617 instQueue.getCount(tid); 1618 toFetch->iewInfo[tid].ldstqCount = 1619 ldstQueue.getCount(tid); 1620 1621 toRename->iewInfo[tid].usedIQ = true; 1622 toRename->iewInfo[tid].freeIQEntries = 1623 instQueue.numFreeEntries(tid); 1624 toRename->iewInfo[tid].usedLSQ = true; 1625 1626 toRename->iewInfo[tid].freeLQEntries = 1627 ldstQueue.numFreeLoadEntries(tid); 1628 toRename->iewInfo[tid].freeSQEntries = 1629 ldstQueue.numFreeStoreEntries(tid); 1630 1631 wroteToTimeBuffer = true; 1632 } 1633 1634 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1635 tid, toRename->iewInfo[tid].dispatched); 1636 } 1637 1638 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1639 "LQ has %i free entries. SQ has %i free entries.\n", 1640 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1641 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1642 1643 updateStatus(); 1644 1645 if (wroteToTimeBuffer) { 1646 DPRINTF(Activity, "Activity this cycle.\n"); 1647 cpu->activityThisCycle(); 1648 } 1649} 1650 1651template <class Impl> 1652void 1653DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1654{ 1655 ThreadID tid = inst->threadNumber; 1656 1657 iewExecutedInsts++; 1658 1659#if TRACING_ON 1660 if (DTRACE(O3PipeView)) { 1661 inst->completeTick = curTick() - inst->fetchTick; 1662 } 1663#endif 1664 1665 // 1666 // Control operations 1667 // 1668 if (inst->isControl()) 1669 iewExecutedBranches[tid]++; 1670 1671 // 1672 // Memory operations 1673 // 1674 if (inst->isMemRef()) { 1675 iewExecutedRefs[tid]++; 1676 1677 if (inst->isLoad()) { 1678 iewExecLoadInsts[tid]++; 1679 } 1680 } 1681} 1682 1683template <class Impl> 1684void 1685DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1686{ 1687 ThreadID tid = inst->threadNumber; 1688 1689 if (!fetchRedirect[tid] || 1690 !toCommit->squash[tid] || 1691 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1692 1693 if (inst->mispredicted()) { 1694 fetchRedirect[tid] = true; 1695 1696 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1697 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1698 inst->predInstAddr(), inst->predNextInstAddr()); 1699 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1700 " NPC: %#x.\n", inst->nextInstAddr(), 1701 inst->nextInstAddr()); 1702 // If incorrect, then signal the ROB that it must be squashed. 1703 squashDueToBranch(inst, tid); 1704 1705 if (inst->readPredTaken()) { 1706 predictedTakenIncorrect++; 1707 } else { 1708 predictedNotTakenIncorrect++; 1709 } 1710 } 1711 } 1712} 1713 1714#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1715