iew_impl.hh revision 10231
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com 461060SN/A// @todo: Fix the instantaneous communication among all the stages within 471060SN/A// iew. There's a clear delay between issue and execute, yet backwards 481689SN/A// communication happens simultaneously. 491060SN/A 501060SN/A#include <queue> 511060SN/A 528230Snate@binkert.org#include "arch/utility.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 552292SN/A#include "cpu/o3/fu_pool.hh" 561717SN/A#include "cpu/o3/iew.hh" 578229Snate@binkert.org#include "cpu/timebuf.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/IEW.hh" 619527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 625529Snate@binkert.org#include "params/DerivO3CPU.hh" 631060SN/A 646221Snate@binkert.orgusing namespace std; 656221Snate@binkert.org 661681SN/Atemplate<class Impl> 675529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 682873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 694329Sktlim@umich.edu cpu(_cpu), 704329Sktlim@umich.edu instQueue(_cpu, this, params), 714329Sktlim@umich.edu ldstQueue(_cpu, this, params), 722292SN/A fuPool(params->fuPool), 732292SN/A commitToIEWDelay(params->commitToIEWDelay), 742292SN/A renameToIEWDelay(params->renameToIEWDelay), 752292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 762820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 772292SN/A issueWidth(params->issueWidth), 782820Sktlim@umich.edu wbOutstanding(0), 792820Sktlim@umich.edu wbWidth(params->wbWidth), 809444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 811060SN/A{ 8210172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8310172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8510172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8610172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8710172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 8810172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8910172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9010172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9110172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9210172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9310172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9410172Sdam.sunwoo@arm.com 952292SN/A _status = Active; 962292SN/A exeStatus = Running; 972292SN/A wbStatus = Idle; 981060SN/A 991060SN/A // Setup wire to read instructions coming from issue. 1001060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1011060SN/A 1021060SN/A // Instruction queue needs the queue between issue and execute. 1031060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1041681SN/A 1056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1066221Snate@binkert.org dispatchStatus[tid] = Running; 1076221Snate@binkert.org stalls[tid].commit = false; 1086221Snate@binkert.org fetchRedirect[tid] = false; 1092292SN/A } 1102292SN/A 1112820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 1122820Sktlim@umich.edu 1132292SN/A updateLSQNextCycle = false; 1142292SN/A 1152820Sktlim@umich.edu ableToIssue = true; 1162820Sktlim@umich.edu 1172292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1182292SN/A} 1192292SN/A 1202292SN/Atemplate <class Impl> 1212292SN/Astd::string 1222292SN/ADefaultIEW<Impl>::name() const 1232292SN/A{ 1242292SN/A return cpu->name() + ".iew"; 1251060SN/A} 1261060SN/A 1271681SN/Atemplate <class Impl> 1281062SN/Avoid 12910023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 13010023Smatt.horsnell@ARM.com{ 13110023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 13210023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13310023Smatt.horsnell@ARM.com} 13410023Smatt.horsnell@ARM.com 13510023Smatt.horsnell@ARM.comtemplate <class Impl> 13610023Smatt.horsnell@ARM.comvoid 1372292SN/ADefaultIEW<Impl>::regStats() 1381062SN/A{ 1392301SN/A using namespace Stats; 1402301SN/A 1411062SN/A instQueue.regStats(); 1422727Sktlim@umich.edu ldstQueue.regStats(); 1431062SN/A 1441062SN/A iewIdleCycles 1451062SN/A .name(name() + ".iewIdleCycles") 1461062SN/A .desc("Number of cycles IEW is idle"); 1471062SN/A 1481062SN/A iewSquashCycles 1491062SN/A .name(name() + ".iewSquashCycles") 1501062SN/A .desc("Number of cycles IEW is squashing"); 1511062SN/A 1521062SN/A iewBlockCycles 1531062SN/A .name(name() + ".iewBlockCycles") 1541062SN/A .desc("Number of cycles IEW is blocking"); 1551062SN/A 1561062SN/A iewUnblockCycles 1571062SN/A .name(name() + ".iewUnblockCycles") 1581062SN/A .desc("Number of cycles IEW is unblocking"); 1591062SN/A 1601062SN/A iewDispatchedInsts 1611062SN/A .name(name() + ".iewDispatchedInsts") 1621062SN/A .desc("Number of instructions dispatched to IQ"); 1631062SN/A 1641062SN/A iewDispSquashedInsts 1651062SN/A .name(name() + ".iewDispSquashedInsts") 1661062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1671062SN/A 1681062SN/A iewDispLoadInsts 1691062SN/A .name(name() + ".iewDispLoadInsts") 1701062SN/A .desc("Number of dispatched load instructions"); 1711062SN/A 1721062SN/A iewDispStoreInsts 1731062SN/A .name(name() + ".iewDispStoreInsts") 1741062SN/A .desc("Number of dispatched store instructions"); 1751062SN/A 1761062SN/A iewDispNonSpecInsts 1771062SN/A .name(name() + ".iewDispNonSpecInsts") 1781062SN/A .desc("Number of dispatched non-speculative instructions"); 1791062SN/A 1801062SN/A iewIQFullEvents 1811062SN/A .name(name() + ".iewIQFullEvents") 1821062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1831062SN/A 1842292SN/A iewLSQFullEvents 1852292SN/A .name(name() + ".iewLSQFullEvents") 1862292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1872292SN/A 1881062SN/A memOrderViolationEvents 1891062SN/A .name(name() + ".memOrderViolationEvents") 1901062SN/A .desc("Number of memory order violations"); 1911062SN/A 1921062SN/A predictedTakenIncorrect 1931062SN/A .name(name() + ".predictedTakenIncorrect") 1941062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1952292SN/A 1962292SN/A predictedNotTakenIncorrect 1972292SN/A .name(name() + ".predictedNotTakenIncorrect") 1982292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1992292SN/A 2002292SN/A branchMispredicts 2012292SN/A .name(name() + ".branchMispredicts") 2022292SN/A .desc("Number of branch mispredicts detected at execute"); 2032292SN/A 2042292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2052301SN/A 2062727Sktlim@umich.edu iewExecutedInsts 2072353SN/A .name(name() + ".iewExecutedInsts") 2082727Sktlim@umich.edu .desc("Number of executed instructions"); 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu iewExecLoadInsts 2116221Snate@binkert.org .init(cpu->numThreads) 2122353SN/A .name(name() + ".iewExecLoadInsts") 2132727Sktlim@umich.edu .desc("Number of load instructions executed") 2142727Sktlim@umich.edu .flags(total); 2152727Sktlim@umich.edu 2162727Sktlim@umich.edu iewExecSquashedInsts 2172353SN/A .name(name() + ".iewExecSquashedInsts") 2182727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2192727Sktlim@umich.edu 2202727Sktlim@umich.edu iewExecutedSwp 2216221Snate@binkert.org .init(cpu->numThreads) 2228240Snate@binkert.org .name(name() + ".exec_swp") 2232301SN/A .desc("number of swp insts executed") 2242727Sktlim@umich.edu .flags(total); 2252301SN/A 2262727Sktlim@umich.edu iewExecutedNop 2276221Snate@binkert.org .init(cpu->numThreads) 2288240Snate@binkert.org .name(name() + ".exec_nop") 2292301SN/A .desc("number of nop insts executed") 2302727Sktlim@umich.edu .flags(total); 2312301SN/A 2322727Sktlim@umich.edu iewExecutedRefs 2336221Snate@binkert.org .init(cpu->numThreads) 2348240Snate@binkert.org .name(name() + ".exec_refs") 2352301SN/A .desc("number of memory reference insts executed") 2362727Sktlim@umich.edu .flags(total); 2372301SN/A 2382727Sktlim@umich.edu iewExecutedBranches 2396221Snate@binkert.org .init(cpu->numThreads) 2408240Snate@binkert.org .name(name() + ".exec_branches") 2412301SN/A .desc("Number of branches executed") 2422727Sktlim@umich.edu .flags(total); 2432301SN/A 2442301SN/A iewExecStoreInsts 2458240Snate@binkert.org .name(name() + ".exec_stores") 2462301SN/A .desc("Number of stores executed") 2472727Sktlim@umich.edu .flags(total); 2482727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2492727Sktlim@umich.edu 2502727Sktlim@umich.edu iewExecRate 2518240Snate@binkert.org .name(name() + ".exec_rate") 2522727Sktlim@umich.edu .desc("Inst execution rate") 2532727Sktlim@umich.edu .flags(total); 2542727Sktlim@umich.edu 2552727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2562301SN/A 2572301SN/A iewInstsToCommit 2586221Snate@binkert.org .init(cpu->numThreads) 2598240Snate@binkert.org .name(name() + ".wb_sent") 2602301SN/A .desc("cumulative count of insts sent to commit") 2612727Sktlim@umich.edu .flags(total); 2622301SN/A 2632326SN/A writebackCount 2646221Snate@binkert.org .init(cpu->numThreads) 2658240Snate@binkert.org .name(name() + ".wb_count") 2662301SN/A .desc("cumulative count of insts written-back") 2672727Sktlim@umich.edu .flags(total); 2682301SN/A 2692326SN/A producerInst 2706221Snate@binkert.org .init(cpu->numThreads) 2718240Snate@binkert.org .name(name() + ".wb_producers") 2722301SN/A .desc("num instructions producing a value") 2732727Sktlim@umich.edu .flags(total); 2742301SN/A 2752326SN/A consumerInst 2766221Snate@binkert.org .init(cpu->numThreads) 2778240Snate@binkert.org .name(name() + ".wb_consumers") 2782301SN/A .desc("num instructions consuming a value") 2792727Sktlim@umich.edu .flags(total); 2802301SN/A 2812326SN/A wbPenalized 2826221Snate@binkert.org .init(cpu->numThreads) 2838240Snate@binkert.org .name(name() + ".wb_penalized") 2842301SN/A .desc("number of instrctions required to write to 'other' IQ") 2852727Sktlim@umich.edu .flags(total); 2862301SN/A 2872326SN/A wbPenalizedRate 2888240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2892301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2902727Sktlim@umich.edu .flags(total); 2912301SN/A 2922326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2932301SN/A 2942326SN/A wbFanout 2958240Snate@binkert.org .name(name() + ".wb_fanout") 2962301SN/A .desc("average fanout of values written-back") 2972727Sktlim@umich.edu .flags(total); 2982301SN/A 2992326SN/A wbFanout = producerInst / consumerInst; 3002301SN/A 3012326SN/A wbRate 3028240Snate@binkert.org .name(name() + ".wb_rate") 3032301SN/A .desc("insts written-back per cycle") 3042727Sktlim@umich.edu .flags(total); 3052326SN/A wbRate = writebackCount / cpu->numCycles; 3061062SN/A} 3071062SN/A 3081681SN/Atemplate<class Impl> 3091060SN/Avoid 3109427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3111060SN/A{ 3126221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3132292SN/A toRename->iewInfo[tid].usedIQ = true; 3142292SN/A toRename->iewInfo[tid].freeIQEntries = 3152292SN/A instQueue.numFreeEntries(tid); 3162292SN/A 3172292SN/A toRename->iewInfo[tid].usedLSQ = true; 3182292SN/A toRename->iewInfo[tid].freeLSQEntries = 3192292SN/A ldstQueue.numFreeEntries(tid); 3202292SN/A } 3212292SN/A 3228887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3238733Sgeoffrey.blake@arm.com if (cpu->checker) { 3248850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3258887Sgeoffrey.blake@arm.com } 3268733Sgeoffrey.blake@arm.com 3272733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3281060SN/A} 3291060SN/A 3301681SN/Atemplate<class Impl> 3311060SN/Avoid 3322292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3331060SN/A{ 3341060SN/A timeBuffer = tb_ptr; 3351060SN/A 3361060SN/A // Setup wire to read information from time buffer, from commit. 3371060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3381060SN/A 3391060SN/A // Setup wire to write information back to previous stages. 3401060SN/A toRename = timeBuffer->getWire(0); 3411060SN/A 3422292SN/A toFetch = timeBuffer->getWire(0); 3432292SN/A 3441060SN/A // Instruction queue also needs main time buffer. 3451060SN/A instQueue.setTimeBuffer(tb_ptr); 3461060SN/A} 3471060SN/A 3481681SN/Atemplate<class Impl> 3491060SN/Avoid 3502292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3511060SN/A{ 3521060SN/A renameQueue = rq_ptr; 3531060SN/A 3541060SN/A // Setup wire to read information from rename queue. 3551060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3561060SN/A} 3571060SN/A 3581681SN/Atemplate<class Impl> 3591060SN/Avoid 3602292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3611060SN/A{ 3621060SN/A iewQueue = iq_ptr; 3631060SN/A 3641060SN/A // Setup wire to write instructions to commit. 3651060SN/A toCommit = iewQueue->getWire(0); 3661060SN/A} 3671060SN/A 3681681SN/Atemplate<class Impl> 3691060SN/Avoid 3706221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3711060SN/A{ 3722292SN/A activeThreads = at_ptr; 3732292SN/A 3742292SN/A ldstQueue.setActiveThreads(at_ptr); 3752292SN/A instQueue.setActiveThreads(at_ptr); 3761060SN/A} 3771060SN/A 3781681SN/Atemplate<class Impl> 3791060SN/Avoid 3802292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3811060SN/A{ 3822292SN/A scoreboard = sb_ptr; 3831060SN/A} 3841060SN/A 3852307SN/Atemplate <class Impl> 3862863Sktlim@umich.edubool 3879444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3882307SN/A{ 3899444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3909444SAndreas.Sandberg@ARM.com 3919444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3929444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3939444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3949444SAndreas.Sandberg@ARM.com drained = false; 3959444SAndreas.Sandberg@ARM.com } 3969444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3979444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3989444SAndreas.Sandberg@ARM.com drained = false; 3999444SAndreas.Sandberg@ARM.com } 4009444SAndreas.Sandberg@ARM.com } 4019444SAndreas.Sandberg@ARM.com 4029783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 4039783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 4049783Sandreas.hansson@arm.com // above 4059783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4069783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4079783Sandreas.hansson@arm.com drained = false; 4089783Sandreas.hansson@arm.com } 4099783Sandreas.hansson@arm.com 4109444SAndreas.Sandberg@ARM.com return drained; 4111681SN/A} 4121681SN/A 4132316SN/Atemplate <class Impl> 4141681SN/Avoid 4159444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4162843Sktlim@umich.edu{ 4179444SAndreas.Sandberg@ARM.com assert(isDrained()); 4182843Sktlim@umich.edu 4199444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4209444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4211681SN/A} 4221681SN/A 4232307SN/Atemplate <class Impl> 4241681SN/Avoid 4252307SN/ADefaultIEW<Impl>::takeOverFrom() 4261060SN/A{ 4272348SN/A // Reset all state. 4282307SN/A _status = Active; 4292307SN/A exeStatus = Running; 4302307SN/A wbStatus = Idle; 4311060SN/A 4322307SN/A instQueue.takeOverFrom(); 4332307SN/A ldstQueue.takeOverFrom(); 4349444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4351060SN/A 4369427SAndreas.Sandberg@ARM.com startupStage(); 4372307SN/A cpu->activityThisCycle(); 4381060SN/A 4396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4406221Snate@binkert.org dispatchStatus[tid] = Running; 4416221Snate@binkert.org stalls[tid].commit = false; 4426221Snate@binkert.org fetchRedirect[tid] = false; 4432307SN/A } 4441060SN/A 4452307SN/A updateLSQNextCycle = false; 4462307SN/A 4472873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4482307SN/A issueToExecQueue.advance(); 4491060SN/A } 4501060SN/A} 4511060SN/A 4521681SN/Atemplate<class Impl> 4531060SN/Avoid 4546221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4552107SN/A{ 4566221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4572107SN/A 4582292SN/A // Tell the IQ to start squashing. 4592292SN/A instQueue.squash(tid); 4602107SN/A 4612292SN/A // Tell the LDSTQ to start squashing. 4622326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4632292SN/A updatedQueues = true; 4642107SN/A 4652292SN/A // Clear the skid buffer in case it has any data in it. 4662935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4674632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4682935Sksewell@umich.edu 4692292SN/A while (!skidBuffer[tid].empty()) { 4702292SN/A if (skidBuffer[tid].front()->isLoad() || 4712292SN/A skidBuffer[tid].front()->isStore() ) { 4722292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4732292SN/A } 4742107SN/A 4752292SN/A toRename->iewInfo[tid].dispatched++; 4762107SN/A 4772292SN/A skidBuffer[tid].pop(); 4782292SN/A } 4792107SN/A 4802702Sktlim@umich.edu emptyRenameInsts(tid); 4812107SN/A} 4822107SN/A 4832107SN/Atemplate<class Impl> 4842107SN/Avoid 4856221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4862292SN/A{ 4877720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4887720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4892292SN/A 49010231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 4917852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4927852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4937852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4947852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4952935Sksewell@umich.edu 4967852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4977852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4982292SN/A 4997852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 5007852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 5017852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5022292SN/A 5037852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5047852SMatt.Horsnell@arm.com } 5057852SMatt.Horsnell@arm.com 5062292SN/A} 5072292SN/A 5082292SN/Atemplate<class Impl> 5092292SN/Avoid 5106221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 5112292SN/A{ 5128513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5138513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5148513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5158513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5168513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5178513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5188513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5198513SGiacomo.Gabrielli@arm.com // the squash. 52010231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5218513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5228513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5232292SN/A 5247852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5258513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5268137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5272292SN/A 5288513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5298513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5302292SN/A 5317852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5327852SMatt.Horsnell@arm.com } 5332292SN/A} 5342292SN/A 5352292SN/Atemplate<class Impl> 5362292SN/Avoid 5376221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5382292SN/A{ 5392292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5407720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 54110231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5427852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5437852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5442292SN/A 5457852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5467852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5478137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5482292SN/A 5497852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5507852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5512292SN/A 5527852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5532292SN/A 5547852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5557852SMatt.Horsnell@arm.com } 5562292SN/A} 5572292SN/A 5582292SN/Atemplate<class Impl> 5592292SN/Avoid 5606221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5612292SN/A{ 5622292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5632292SN/A 5642292SN/A if (dispatchStatus[tid] != Blocked && 5652292SN/A dispatchStatus[tid] != Unblocking) { 5662292SN/A toRename->iewBlock[tid] = true; 5672292SN/A wroteToTimeBuffer = true; 5682292SN/A } 5692292SN/A 5702292SN/A // Add the current inputs to the skid buffer so they can be 5712292SN/A // reprocessed when this stage unblocks. 5722292SN/A skidInsert(tid); 5732292SN/A 5742292SN/A dispatchStatus[tid] = Blocked; 5752292SN/A} 5762292SN/A 5772292SN/Atemplate<class Impl> 5782292SN/Avoid 5796221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5802292SN/A{ 5812292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5822292SN/A "buffer %u.\n",tid, tid); 5832292SN/A 5842292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5852292SN/A // Also switch status to running. 5862292SN/A if (skidBuffer[tid].empty()) { 5872292SN/A toRename->iewUnblock[tid] = true; 5882292SN/A wroteToTimeBuffer = true; 5892292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5902292SN/A dispatchStatus[tid] = Running; 5912292SN/A } 5922292SN/A} 5932292SN/A 5942292SN/Atemplate<class Impl> 5952292SN/Avoid 5962292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5971060SN/A{ 5981681SN/A instQueue.wakeDependents(inst); 5991060SN/A} 6001060SN/A 6012292SN/Atemplate<class Impl> 6022292SN/Avoid 6032292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6042292SN/A{ 6052292SN/A instQueue.rescheduleMemInst(inst); 6062292SN/A} 6071681SN/A 6081681SN/Atemplate<class Impl> 6091060SN/Avoid 6102292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6111060SN/A{ 6122292SN/A instQueue.replayMemInst(inst); 6132292SN/A} 6141060SN/A 6152292SN/Atemplate<class Impl> 6162292SN/Avoid 6172292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6182292SN/A{ 6193221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6203221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6213221Sktlim@umich.edu // being added to the queue to commit without being processed by 6223221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6233221Sktlim@umich.edu 6242292SN/A // First check the time slot that this instruction will write 6252292SN/A // to. If there are free write ports at the time, then go ahead 6262292SN/A // and write the instruction to that time. If there are not, 6272292SN/A // keep looking back to see where's the first time there's a 6282326SN/A // free slot. 6292292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6302292SN/A ++wbNumInst; 6312820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6322292SN/A ++wbCycle; 6332292SN/A wbNumInst = 0; 6342292SN/A } 6352292SN/A 6362353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6372292SN/A } 6382292SN/A 6392353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6402353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6412292SN/A // Add finished instruction to queue to commit. 6422292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6432292SN/A (*iewQueue)[wbCycle].size++; 6442292SN/A} 6452292SN/A 6462292SN/Atemplate <class Impl> 6472292SN/Aunsigned 6482292SN/ADefaultIEW<Impl>::validInstsFromRename() 6492292SN/A{ 6502292SN/A unsigned inst_count = 0; 6512292SN/A 6522292SN/A for (int i=0; i<fromRename->size; i++) { 6532731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6542292SN/A inst_count++; 6552292SN/A } 6562292SN/A 6572292SN/A return inst_count; 6582292SN/A} 6592292SN/A 6602292SN/Atemplate<class Impl> 6612292SN/Avoid 6626221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6632292SN/A{ 6642292SN/A DynInstPtr inst = NULL; 6652292SN/A 6662292SN/A while (!insts[tid].empty()) { 6672292SN/A inst = insts[tid].front(); 6682292SN/A 6692292SN/A insts[tid].pop(); 6702292SN/A 6719937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6722292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6737720Sgblack@eecs.umich.edu inst->pcState(),tid); 6742292SN/A 6752292SN/A skidBuffer[tid].push(inst); 6762292SN/A } 6772292SN/A 6782292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6792292SN/A "Skidbuffer Exceeded Max Size"); 6802292SN/A} 6812292SN/A 6822292SN/Atemplate<class Impl> 6832292SN/Aint 6842292SN/ADefaultIEW<Impl>::skidCount() 6852292SN/A{ 6862292SN/A int max=0; 6872292SN/A 6886221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6896221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6902292SN/A 6913867Sbinkertn@umich.edu while (threads != end) { 6926221Snate@binkert.org ThreadID tid = *threads++; 6933867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6942292SN/A if (max < thread_count) 6952292SN/A max = thread_count; 6962292SN/A } 6972292SN/A 6982292SN/A return max; 6992292SN/A} 7002292SN/A 7012292SN/Atemplate<class Impl> 7022292SN/Abool 7032292SN/ADefaultIEW<Impl>::skidsEmpty() 7042292SN/A{ 7056221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7066221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7072292SN/A 7083867Sbinkertn@umich.edu while (threads != end) { 7096221Snate@binkert.org ThreadID tid = *threads++; 7103867Sbinkertn@umich.edu 7113867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7122292SN/A return false; 7132292SN/A } 7142292SN/A 7152292SN/A return true; 7161062SN/A} 7171062SN/A 7181681SN/Atemplate <class Impl> 7191062SN/Avoid 7202292SN/ADefaultIEW<Impl>::updateStatus() 7211062SN/A{ 7222292SN/A bool any_unblocking = false; 7231062SN/A 7246221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7256221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7261062SN/A 7273867Sbinkertn@umich.edu while (threads != end) { 7286221Snate@binkert.org ThreadID tid = *threads++; 7291062SN/A 7302292SN/A if (dispatchStatus[tid] == Unblocking) { 7312292SN/A any_unblocking = true; 7322292SN/A break; 7332292SN/A } 7342292SN/A } 7351062SN/A 7362292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7372292SN/A // and there's no stores waiting to write back, and dispatch is not 7382292SN/A // unblocking, then there is no internal activity for the IEW stage. 7397897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7402292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7412292SN/A !ldstQueue.willWB() && !any_unblocking) { 7422292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7431062SN/A 7442292SN/A deactivateStage(); 7451062SN/A 7462292SN/A _status = Inactive; 7472292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7482292SN/A ldstQueue.willWB() || 7492292SN/A any_unblocking)) { 7502292SN/A // Otherwise there is internal activity. Set to active. 7512292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7521062SN/A 7532292SN/A activateStage(); 7541062SN/A 7552292SN/A _status = Active; 7561062SN/A } 7571062SN/A} 7581062SN/A 7591681SN/Atemplate <class Impl> 7601062SN/Avoid 7612292SN/ADefaultIEW<Impl>::resetEntries() 7621062SN/A{ 7632292SN/A instQueue.resetEntries(); 7642292SN/A ldstQueue.resetEntries(); 7652292SN/A} 7661062SN/A 7672292SN/Atemplate <class Impl> 7682292SN/Avoid 7696221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7702292SN/A{ 7712292SN/A if (fromCommit->commitBlock[tid]) { 7722292SN/A stalls[tid].commit = true; 7732292SN/A } 7741062SN/A 7752292SN/A if (fromCommit->commitUnblock[tid]) { 7762292SN/A assert(stalls[tid].commit); 7772292SN/A stalls[tid].commit = false; 7782292SN/A } 7792292SN/A} 7802292SN/A 7812292SN/Atemplate <class Impl> 7822292SN/Abool 7836221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7842292SN/A{ 7852292SN/A bool ret_val(false); 7862292SN/A 7872292SN/A if (stalls[tid].commit) { 7882292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7892292SN/A ret_val = true; 7902292SN/A } else if (instQueue.isFull(tid)) { 7912292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7922292SN/A ret_val = true; 7932292SN/A } else if (ldstQueue.isFull(tid)) { 7942292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7952292SN/A 7962292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7972292SN/A 7982292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7992292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 8002292SN/A } 8012292SN/A 8022292SN/A if (ldstQueue.numStores(tid) > 0) { 8032292SN/A 8042292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8052292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8062292SN/A } 8072292SN/A 8082292SN/A ret_val = true; 8092292SN/A } else if (ldstQueue.isStalled(tid)) { 8102292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8112292SN/A ret_val = true; 8122292SN/A } 8132292SN/A 8142292SN/A return ret_val; 8152292SN/A} 8162292SN/A 8172292SN/Atemplate <class Impl> 8182292SN/Avoid 8196221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 8202292SN/A{ 8212292SN/A // Check if there's a squash signal, squash if there is 8222292SN/A // Check stall signals, block if there is. 8232292SN/A // If status was Blocked 8242292SN/A // if so then go to unblocking 8252292SN/A // If status was Squashing 8262292SN/A // check if squashing is not high. Switch to running this cycle. 8272292SN/A 8282292SN/A readStallSignals(tid); 8292292SN/A 8302292SN/A if (fromCommit->commitInfo[tid].squash) { 8312292SN/A squash(tid); 8322292SN/A 8332292SN/A if (dispatchStatus[tid] == Blocked || 8342292SN/A dispatchStatus[tid] == Unblocking) { 8352292SN/A toRename->iewUnblock[tid] = true; 8362292SN/A wroteToTimeBuffer = true; 8372292SN/A } 8382292SN/A 8392292SN/A dispatchStatus[tid] = Squashing; 8402292SN/A fetchRedirect[tid] = false; 8412292SN/A return; 8422292SN/A } 8432292SN/A 8442292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8452702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8462292SN/A 8472292SN/A dispatchStatus[tid] = Squashing; 8482702Sktlim@umich.edu emptyRenameInsts(tid); 8492702Sktlim@umich.edu wroteToTimeBuffer = true; 8502292SN/A return; 8512292SN/A } 8522292SN/A 8532292SN/A if (checkStall(tid)) { 8542292SN/A block(tid); 8552292SN/A dispatchStatus[tid] = Blocked; 8562292SN/A return; 8572292SN/A } 8582292SN/A 8592292SN/A if (dispatchStatus[tid] == Blocked) { 8602292SN/A // Status from previous cycle was blocked, but there are no more stall 8612292SN/A // conditions. Switch over to unblocking. 8622292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8632292SN/A tid); 8642292SN/A 8652292SN/A dispatchStatus[tid] = Unblocking; 8662292SN/A 8672292SN/A unblock(tid); 8682292SN/A 8692292SN/A return; 8702292SN/A } 8712292SN/A 8722292SN/A if (dispatchStatus[tid] == Squashing) { 8732292SN/A // Switch status to running if rename isn't being told to block or 8742292SN/A // squash this cycle. 8752292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8762292SN/A tid); 8772292SN/A 8782292SN/A dispatchStatus[tid] = Running; 8792292SN/A 8802292SN/A return; 8812292SN/A } 8822292SN/A} 8832292SN/A 8842292SN/Atemplate <class Impl> 8852292SN/Avoid 8862292SN/ADefaultIEW<Impl>::sortInsts() 8872292SN/A{ 8882292SN/A int insts_from_rename = fromRename->size; 8892326SN/A#ifdef DEBUG 8906221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8916221Snate@binkert.org assert(insts[tid].empty()); 8922326SN/A#endif 8932292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8942292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8952292SN/A } 8962292SN/A} 8972292SN/A 8982292SN/Atemplate <class Impl> 8992292SN/Avoid 9006221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 9012702Sktlim@umich.edu{ 9024632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 9032935Sksewell@umich.edu 9042702Sktlim@umich.edu while (!insts[tid].empty()) { 9052935Sksewell@umich.edu 9062702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 9072702Sktlim@umich.edu insts[tid].front()->isStore() ) { 9082702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 9092702Sktlim@umich.edu } 9102702Sktlim@umich.edu 9112702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 9122702Sktlim@umich.edu 9132702Sktlim@umich.edu insts[tid].pop(); 9142702Sktlim@umich.edu } 9152702Sktlim@umich.edu} 9162702Sktlim@umich.edu 9172702Sktlim@umich.edutemplate <class Impl> 9182702Sktlim@umich.eduvoid 9192292SN/ADefaultIEW<Impl>::wakeCPU() 9202292SN/A{ 9212292SN/A cpu->wakeCPU(); 9222292SN/A} 9232292SN/A 9242292SN/Atemplate <class Impl> 9252292SN/Avoid 9262292SN/ADefaultIEW<Impl>::activityThisCycle() 9272292SN/A{ 9282292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9292292SN/A cpu->activityThisCycle(); 9302292SN/A} 9312292SN/A 9322292SN/Atemplate <class Impl> 9332292SN/Ainline void 9342292SN/ADefaultIEW<Impl>::activateStage() 9352292SN/A{ 9362292SN/A DPRINTF(Activity, "Activating stage.\n"); 9372733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9382292SN/A} 9392292SN/A 9402292SN/Atemplate <class Impl> 9412292SN/Ainline void 9422292SN/ADefaultIEW<Impl>::deactivateStage() 9432292SN/A{ 9442292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9452733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9462292SN/A} 9472292SN/A 9482292SN/Atemplate<class Impl> 9492292SN/Avoid 9506221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9512292SN/A{ 9522292SN/A // If status is Running or idle, 9532292SN/A // call dispatchInsts() 9542292SN/A // If status is Unblocking, 9552292SN/A // buffer any instructions coming from rename 9562292SN/A // continue trying to empty skid buffer 9572292SN/A // check if stall conditions have passed 9582292SN/A 9592292SN/A if (dispatchStatus[tid] == Blocked) { 9602292SN/A ++iewBlockCycles; 9612292SN/A 9622292SN/A } else if (dispatchStatus[tid] == Squashing) { 9632292SN/A ++iewSquashCycles; 9642292SN/A } 9652292SN/A 9662292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9672292SN/A // will allow, as long as it is not currently blocked. 9682292SN/A if (dispatchStatus[tid] == Running || 9692292SN/A dispatchStatus[tid] == Idle) { 9702292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9712292SN/A "dispatch.\n", tid); 9722292SN/A 9732292SN/A dispatchInsts(tid); 9742292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9752292SN/A // Make sure that the skid buffer has something in it if the 9762292SN/A // status is unblocking. 9772292SN/A assert(!skidsEmpty()); 9782292SN/A 9792292SN/A // If the status was unblocking, then instructions from the skid 9802292SN/A // buffer were used. Remove those instructions and handle 9812292SN/A // the rest of unblocking. 9822292SN/A dispatchInsts(tid); 9832292SN/A 9842292SN/A ++iewUnblockCycles; 9852292SN/A 9865215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9872292SN/A // Add the current inputs to the skid buffer so they can be 9882292SN/A // reprocessed when this stage unblocks. 9892292SN/A skidInsert(tid); 9902292SN/A } 9912292SN/A 9922292SN/A unblock(tid); 9932292SN/A } 9942292SN/A} 9952292SN/A 9962292SN/Atemplate <class Impl> 9972292SN/Avoid 9986221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9992292SN/A{ 10002292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 10012292SN/A // otherwise. 10022292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 10032292SN/A dispatchStatus[tid] == Unblocking ? 10042292SN/A skidBuffer[tid] : insts[tid]; 10052292SN/A 10062292SN/A int insts_to_add = insts_to_dispatch.size(); 10072292SN/A 10082292SN/A DynInstPtr inst; 10092292SN/A bool add_to_iq = false; 10102292SN/A int dis_num_inst = 0; 10112292SN/A 10122292SN/A // Loop through the instructions, putting them in the instruction 10132292SN/A // queue. 10142292SN/A for ( ; dis_num_inst < insts_to_add && 10152820Sktlim@umich.edu dis_num_inst < dispatchWidth; 10162292SN/A ++dis_num_inst) 10172292SN/A { 10182292SN/A inst = insts_to_dispatch.front(); 10192292SN/A 10202292SN/A if (dispatchStatus[tid] == Unblocking) { 10212292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10222292SN/A "buffer\n", tid); 10232292SN/A } 10242292SN/A 10252292SN/A // Make sure there's a valid instruction there. 10262292SN/A assert(inst); 10272292SN/A 10287720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10292292SN/A "IQ.\n", 10307720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10312292SN/A 10322292SN/A // Be sure to mark these instructions as ready so that the 10332292SN/A // commit stage can go ahead and execute them, and mark 10342292SN/A // them as issued so the IQ doesn't reprocess them. 10352292SN/A 10362292SN/A // Check for squashed instructions. 10372292SN/A if (inst->isSquashed()) { 10382292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10392292SN/A "not adding to IQ.\n", tid); 10402292SN/A 10412292SN/A ++iewDispSquashedInsts; 10422292SN/A 10432292SN/A insts_to_dispatch.pop(); 10442292SN/A 10452292SN/A //Tell Rename That An Instruction has been processed 10462292SN/A if (inst->isLoad() || inst->isStore()) { 10472292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10482292SN/A } 10492292SN/A toRename->iewInfo[tid].dispatched++; 10502292SN/A 10512292SN/A continue; 10522292SN/A } 10532292SN/A 10542292SN/A // Check for full conditions. 10552292SN/A if (instQueue.isFull(tid)) { 10562292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10572292SN/A 10582292SN/A // Call function to start blocking. 10592292SN/A block(tid); 10602292SN/A 10612292SN/A // Set unblock to false. Special case where we are using 10622292SN/A // skidbuffer (unblocking) instructions but then we still 10632292SN/A // get full in the IQ. 10642292SN/A toRename->iewUnblock[tid] = false; 10652292SN/A 10662292SN/A ++iewIQFullEvents; 10672292SN/A break; 10682292SN/A } else if (ldstQueue.isFull(tid)) { 10692292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10702292SN/A 10712292SN/A // Call function to start blocking. 10722292SN/A block(tid); 10732292SN/A 10742292SN/A // Set unblock to false. Special case where we are using 10752292SN/A // skidbuffer (unblocking) instructions but then we still 10762292SN/A // get full in the IQ. 10772292SN/A toRename->iewUnblock[tid] = false; 10782292SN/A 10792292SN/A ++iewLSQFullEvents; 10802292SN/A break; 10812292SN/A } 10822292SN/A 10832292SN/A // Otherwise issue the instruction just fine. 10842292SN/A if (inst->isLoad()) { 10852292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10862292SN/A "encountered, adding to LSQ.\n", tid); 10872292SN/A 10882292SN/A // Reserve a spot in the load store queue for this 10892292SN/A // memory access. 10902292SN/A ldstQueue.insertLoad(inst); 10912292SN/A 10922292SN/A ++iewDispLoadInsts; 10932292SN/A 10942292SN/A add_to_iq = true; 10952292SN/A 10962292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10972292SN/A } else if (inst->isStore()) { 10982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10992292SN/A "encountered, adding to LSQ.\n", tid); 11002292SN/A 11012292SN/A ldstQueue.insertStore(inst); 11022292SN/A 11032292SN/A ++iewDispStoreInsts; 11042292SN/A 11052336SN/A if (inst->isStoreConditional()) { 11062336SN/A // Store conditionals need to be set as "canCommit()" 11072336SN/A // so that commit can process them when they reach the 11082336SN/A // head of commit. 11092348SN/A // @todo: This is somewhat specific to Alpha. 11102292SN/A inst->setCanCommit(); 11112292SN/A instQueue.insertNonSpec(inst); 11122292SN/A add_to_iq = false; 11132292SN/A 11142292SN/A ++iewDispNonSpecInsts; 11152292SN/A } else { 11162292SN/A add_to_iq = true; 11172292SN/A } 11182292SN/A 11192292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11202292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11212326SN/A // Same as non-speculative stores. 11222292SN/A inst->setCanCommit(); 11232292SN/A instQueue.insertBarrier(inst); 11242292SN/A add_to_iq = false; 11252292SN/A } else if (inst->isNop()) { 11262292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11272292SN/A "skipping.\n", tid); 11282292SN/A 11292292SN/A inst->setIssued(); 11302292SN/A inst->setExecuted(); 11312292SN/A inst->setCanCommit(); 11322292SN/A 11332326SN/A instQueue.recordProducer(inst); 11342292SN/A 11352727Sktlim@umich.edu iewExecutedNop[tid]++; 11362301SN/A 11372292SN/A add_to_iq = false; 11382292SN/A } else if (inst->isExecuted()) { 11392292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11402292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11412292SN/A "skipping.\n"); 11422292SN/A 11432292SN/A inst->setIssued(); 11442292SN/A inst->setCanCommit(); 11452292SN/A 11462326SN/A instQueue.recordProducer(inst); 11472292SN/A 11482292SN/A add_to_iq = false; 11492292SN/A } else { 11502292SN/A add_to_iq = true; 11512292SN/A } 11524033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11534033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11544033Sktlim@umich.edu "encountered, skipping.\n", tid); 11554033Sktlim@umich.edu 11564033Sktlim@umich.edu // Same as non-speculative stores. 11574033Sktlim@umich.edu inst->setCanCommit(); 11584033Sktlim@umich.edu 11594033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11604033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11614033Sktlim@umich.edu 11624033Sktlim@umich.edu ++iewDispNonSpecInsts; 11634033Sktlim@umich.edu 11644033Sktlim@umich.edu add_to_iq = false; 11654033Sktlim@umich.edu } 11662292SN/A 11672292SN/A // If the instruction queue is not full, then add the 11682292SN/A // instruction. 11692292SN/A if (add_to_iq) { 11702292SN/A instQueue.insert(inst); 11712292SN/A } 11722292SN/A 11732292SN/A insts_to_dispatch.pop(); 11742292SN/A 11752292SN/A toRename->iewInfo[tid].dispatched++; 11762292SN/A 11772292SN/A ++iewDispatchedInsts; 11788471SGiacomo.Gabrielli@arm.com 11798471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11809046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11818471SGiacomo.Gabrielli@arm.com#endif 118210023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11832292SN/A } 11842292SN/A 11852292SN/A if (!insts_to_dispatch.empty()) { 11862935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11872292SN/A block(tid); 11882292SN/A toRename->iewUnblock[tid] = false; 11892292SN/A } 11902292SN/A 11912292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11922292SN/A dispatchStatus[tid] = Running; 11932292SN/A 11942292SN/A updatedQueues = true; 11952292SN/A } 11962292SN/A 11972292SN/A dis_num_inst = 0; 11982292SN/A} 11992292SN/A 12002292SN/Atemplate <class Impl> 12012292SN/Avoid 12022292SN/ADefaultIEW<Impl>::printAvailableInsts() 12032292SN/A{ 12042292SN/A int inst = 0; 12052292SN/A 12062980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 12072292SN/A 12082292SN/A while (fromIssue->insts[inst]) { 12092292SN/A 12102980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 12112292SN/A 12127720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 12132292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12142292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12152292SN/A 12162292SN/A inst++; 12172292SN/A 12182292SN/A } 12192292SN/A 12202980Sgblack@eecs.umich.edu std::cout << "\n"; 12212292SN/A} 12222292SN/A 12232292SN/Atemplate <class Impl> 12242292SN/Avoid 12252292SN/ADefaultIEW<Impl>::executeInsts() 12262292SN/A{ 12272292SN/A wbNumInst = 0; 12282292SN/A wbCycle = 0; 12292292SN/A 12306221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12316221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12322292SN/A 12333867Sbinkertn@umich.edu while (threads != end) { 12346221Snate@binkert.org ThreadID tid = *threads++; 12352292SN/A fetchRedirect[tid] = false; 12362292SN/A } 12372292SN/A 12382698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12397599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12402698Sktlim@umich.edu// printAvailableInsts(); 12411062SN/A 12421062SN/A // Execute/writeback any instructions that are available. 12432333SN/A int insts_to_execute = fromIssue->size; 12442292SN/A int inst_num = 0; 12452333SN/A for (; inst_num < insts_to_execute; 12462326SN/A ++inst_num) { 12471062SN/A 12482292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12491062SN/A 12502333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12511062SN/A 12527720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12537720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12541062SN/A 12551062SN/A // Check if the instruction is squashed; if so then skip it 12561062SN/A if (inst->isSquashed()) { 12578315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12588315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12598315Sgeoffrey.blake@arm.com inst->seqNum); 12601062SN/A 12611062SN/A // Consider this instruction executed so that commit can go 12621062SN/A // ahead and retire the instruction. 12631062SN/A inst->setExecuted(); 12641062SN/A 12652292SN/A // Not sure if I should set this here or just let commit try to 12662292SN/A // commit any squashed instructions. I like the latter a bit more. 12672292SN/A inst->setCanCommit(); 12681062SN/A 12691062SN/A ++iewExecSquashedInsts; 12701062SN/A 12712820Sktlim@umich.edu decrWb(inst->seqNum); 12721062SN/A continue; 12731062SN/A } 12741062SN/A 12752292SN/A Fault fault = NoFault; 12761062SN/A 12771062SN/A // Execute instruction. 12781062SN/A // Note that if the instruction faults, it will be handled 12791062SN/A // at the commit stage. 12807850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12812292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12821062SN/A "reference.\n"); 12831062SN/A 12841062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12851062SN/A if (inst->isLoad()) { 12862292SN/A // Loads will mark themselves as executed, and their writeback 12872292SN/A // event adds the instruction to the queue to commit 12882292SN/A fault = ldstQueue.executeLoad(inst); 12897944SGiacomo.Gabrielli@arm.com 12907944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12917944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12927944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12937944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12947944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12957944SGiacomo.Gabrielli@arm.com "load.\n"); 12967944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12977944SGiacomo.Gabrielli@arm.com continue; 12987944SGiacomo.Gabrielli@arm.com } 12997944SGiacomo.Gabrielli@arm.com 13007850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 13018073SAli.Saidi@ARM.com inst->fault = NoFault; 13027850SMatt.Horsnell@arm.com } 13031062SN/A } else if (inst->isStore()) { 13042367SN/A fault = ldstQueue.executeStore(inst); 13051062SN/A 13067944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 13077944SGiacomo.Gabrielli@arm.com fault == NoFault) { 13087944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 13097944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 13107944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 13117944SGiacomo.Gabrielli@arm.com "store.\n"); 13127944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 13137944SGiacomo.Gabrielli@arm.com continue; 13147944SGiacomo.Gabrielli@arm.com } 13157944SGiacomo.Gabrielli@arm.com 13162292SN/A // If the store had a fault then it may not have a mem req 131710231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 13187782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 13197782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 13207782Sminkyu.jeong@arm.com // to commit without the instruction completing. 13212367SN/A // Send this instruction to commit, also make sure iew stage 13222367SN/A // realizes there is activity. 13232367SN/A inst->setExecuted(); 13242367SN/A instToCommit(inst); 13252367SN/A activityThisCycle(); 13262292SN/A } 13272326SN/A 13282326SN/A // Store conditionals will mark themselves as 13292326SN/A // executed, and their writeback event will add the 13302326SN/A // instruction to the queue to commit. 13311062SN/A } else { 13322292SN/A panic("Unexpected memory type!\n"); 13331062SN/A } 13341062SN/A 13351062SN/A } else { 13367847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13377847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13387847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13397847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13407847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13417847Sminkyu.jeong@arm.com inst->execute(); 134210231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 13437848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13447847Sminkyu.jeong@arm.com } 13451062SN/A 13462292SN/A inst->setExecuted(); 13472292SN/A 13482292SN/A instToCommit(inst); 13491062SN/A } 13501062SN/A 13512301SN/A updateExeInstStats(inst); 13521681SN/A 13532326SN/A // Check if branch prediction was correct, if not then we need 13542326SN/A // to tell commit to squash in flight instructions. Only 13552326SN/A // handle this if there hasn't already been something that 13562107SN/A // redirects fetch in this group of instructions. 13571681SN/A 13582292SN/A // This probably needs to prioritize the redirects if a different 13592292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13602292SN/A // instruction first, so the branch resolution order will be correct. 13616221Snate@binkert.org ThreadID tid = inst->threadNumber; 13621062SN/A 13633732Sktlim@umich.edu if (!fetchRedirect[tid] || 13647852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13653732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13661062SN/A 13677856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13687856SMatt.Horsnell@arm.com // that have not been executed. 13697856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13707856SMatt.Horsnell@arm.com 13717856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13722292SN/A fetchRedirect[tid] = true; 13731062SN/A 13742292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13758674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13768674Snilay@cs.wisc.edu inst->readPredTarg()); 13777720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13788674Snilay@cs.wisc.edu inst->pcState()); 13791062SN/A // If incorrect, then signal the ROB that it must be squashed. 13802292SN/A squashDueToBranch(inst, tid); 13811062SN/A 138210023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 138310023Smatt.horsnell@ARM.com 13843795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13851062SN/A predictedTakenIncorrect++; 13862292SN/A } else { 13872292SN/A predictedNotTakenIncorrect++; 13881062SN/A } 13892292SN/A } else if (ldstQueue.violation(tid)) { 13904033Sktlim@umich.edu assert(inst->isMemRef()); 13912326SN/A // If there was an ordering violation, then get the 13922326SN/A // DynInst that caused the violation. Note that this 13932292SN/A // clears the violation signal. 13942292SN/A DynInstPtr violator; 13952292SN/A violator = ldstQueue.getMemDepViolator(tid); 13961062SN/A 13977720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13987720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13997720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 14007720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 14017720Sgblack@eecs.umich.edu 14023732Sktlim@umich.edu fetchRedirect[tid] = true; 14033732Sktlim@umich.edu 14041062SN/A // Tell the instruction queue that a violation has occured. 14051062SN/A instQueue.violation(inst, violator); 14061062SN/A 14071062SN/A // Squash. 14088513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 14091062SN/A 14101062SN/A ++memOrderViolationEvents; 14112292SN/A } else if (ldstQueue.loadBlocked(tid) && 14122292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 14132292SN/A fetchRedirect[tid] = true; 14142292SN/A 14152292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 14167720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14177720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14182292SN/A 14192292SN/A squashDueToMemBlocked(inst, tid); 14201062SN/A } 14214033Sktlim@umich.edu } else { 14224033Sktlim@umich.edu // Reset any state associated with redirects that will not 14234033Sktlim@umich.edu // be used. 14244033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14254033Sktlim@umich.edu assert(inst->isMemRef()); 14264033Sktlim@umich.edu 14274033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14284033Sktlim@umich.edu 14294033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14307720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14317720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 14327720Sgblack@eecs.umich.edu inst->physEffAddr); 14334033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14344033Sktlim@umich.edu "already squashing\n"); 14354033Sktlim@umich.edu 14364033Sktlim@umich.edu ++memOrderViolationEvents; 14374033Sktlim@umich.edu } 14384033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14394033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14404033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14417720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14427720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14434033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14444033Sktlim@umich.edu "already squashing\n"); 14454033Sktlim@umich.edu 14464033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14474033Sktlim@umich.edu } 14484033Sktlim@umich.edu 14491062SN/A } 14501062SN/A } 14512292SN/A 14522348SN/A // Update and record activity if we processed any instructions. 14532292SN/A if (inst_num) { 14542292SN/A if (exeStatus == Idle) { 14552292SN/A exeStatus = Running; 14562292SN/A } 14572292SN/A 14582292SN/A updatedQueues = true; 14592292SN/A 14602292SN/A cpu->activityThisCycle(); 14612292SN/A } 14622292SN/A 14632292SN/A // Need to reset this in case a writeback event needs to write into the 14642292SN/A // iew queue. That way the writeback event will write into the correct 14652292SN/A // spot in the queue. 14662292SN/A wbNumInst = 0; 14677852SMatt.Horsnell@arm.com 14682107SN/A} 14692107SN/A 14702292SN/Atemplate <class Impl> 14712107SN/Avoid 14722292SN/ADefaultIEW<Impl>::writebackInsts() 14732107SN/A{ 14742326SN/A // Loop through the head of the time buffer and wake any 14752326SN/A // dependents. These instructions are about to write back. Also 14762326SN/A // mark scoreboard that this instruction is finally complete. 14772326SN/A // Either have IEW have direct access to scoreboard, or have this 14782326SN/A // as part of backwards communication. 14793958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14802292SN/A toCommit->insts[inst_num]; inst_num++) { 14812107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14826221Snate@binkert.org ThreadID tid = inst->threadNumber; 14832107SN/A 14847720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14857720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14862107SN/A 14872301SN/A iewInstsToCommit[tid]++; 14882301SN/A 14892292SN/A // Some instructions will be sent to commit without having 14902292SN/A // executed because they need commit to handle them. 14912292SN/A // E.g. Uncached loads have not actually executed when they 14922292SN/A // are first sent to commit. Instead commit must tell the LSQ 14932292SN/A // when it's ready to execute the uncached load. 14942367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14952301SN/A int dependents = instQueue.wakeDependents(inst); 14962107SN/A 14972292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14982292SN/A //mark as Ready 14992292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 15002292SN/A inst->renamedDestRegIdx(i)); 15012292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 15022107SN/A } 15032301SN/A 15042348SN/A if (dependents) { 15052348SN/A producerInst[tid]++; 15062348SN/A consumerInst[tid]+= dependents; 15072348SN/A } 15082326SN/A writebackCount[tid]++; 15092107SN/A } 15102820Sktlim@umich.edu 15112820Sktlim@umich.edu decrWb(inst->seqNum); 15122107SN/A } 15131060SN/A} 15141060SN/A 15151681SN/Atemplate<class Impl> 15161060SN/Avoid 15172292SN/ADefaultIEW<Impl>::tick() 15181060SN/A{ 15192292SN/A wbNumInst = 0; 15202292SN/A wbCycle = 0; 15211060SN/A 15222292SN/A wroteToTimeBuffer = false; 15232292SN/A updatedQueues = false; 15241060SN/A 15252292SN/A sortInsts(); 15261060SN/A 15272326SN/A // Free function units marked as being freed this cycle. 15282326SN/A fuPool->processFreeUnits(); 15291062SN/A 15306221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15316221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15321060SN/A 15332326SN/A // Check stall and squash signals, dispatch any instructions. 15343867Sbinkertn@umich.edu while (threads != end) { 15356221Snate@binkert.org ThreadID tid = *threads++; 15361060SN/A 15372292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15381060SN/A 15392292SN/A checkSignalsAndUpdate(tid); 15402292SN/A dispatch(tid); 15411060SN/A } 15421060SN/A 15432292SN/A if (exeStatus != Squashing) { 15442292SN/A executeInsts(); 15451060SN/A 15462292SN/A writebackInsts(); 15472292SN/A 15482292SN/A // Have the instruction queue try to schedule any ready instructions. 15492292SN/A // (In actuality, this scheduling is for instructions that will 15502292SN/A // be executed next cycle.) 15512292SN/A instQueue.scheduleReadyInsts(); 15522292SN/A 15532292SN/A // Also should advance its own time buffers if the stage ran. 15542292SN/A // Not the best place for it, but this works (hopefully). 15552292SN/A issueToExecQueue.advance(); 15562292SN/A } 15572292SN/A 15582292SN/A bool broadcast_free_entries = false; 15592292SN/A 15602292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15612292SN/A exeStatus = Idle; 15622292SN/A updateLSQNextCycle = false; 15632292SN/A 15642292SN/A broadcast_free_entries = true; 15652292SN/A } 15662292SN/A 15672292SN/A // Writeback any stores using any leftover bandwidth. 15681681SN/A ldstQueue.writebackStores(); 15691681SN/A 15701061SN/A // Check the committed load/store signals to see if there's a load 15711061SN/A // or store to commit. Also check if it's being told to execute a 15721061SN/A // nonspeculative instruction. 15731681SN/A // This is pretty inefficient... 15742292SN/A 15753867Sbinkertn@umich.edu threads = activeThreads->begin(); 15763867Sbinkertn@umich.edu while (threads != end) { 15776221Snate@binkert.org ThreadID tid = (*threads++); 15782292SN/A 15792292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15802292SN/A 15812348SN/A // Update structures based on instructions committed. 15822292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15832292SN/A !fromCommit->commitInfo[tid].squash && 15842292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15852292SN/A 15862292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15872292SN/A 15882292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15892292SN/A 15902292SN/A updateLSQNextCycle = true; 15912292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15922292SN/A } 15932292SN/A 15942292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15952292SN/A 15962292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15972292SN/A if (fromCommit->commitInfo[tid].uncached) { 15982292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15994033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 16002292SN/A } else { 16012292SN/A instQueue.scheduleNonSpec( 16022292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 16032292SN/A } 16042292SN/A } 16052292SN/A 16062292SN/A if (broadcast_free_entries) { 16072292SN/A toFetch->iewInfo[tid].iqCount = 16082292SN/A instQueue.getCount(tid); 16092292SN/A toFetch->iewInfo[tid].ldstqCount = 16102292SN/A ldstQueue.getCount(tid); 16112292SN/A 16122292SN/A toRename->iewInfo[tid].usedIQ = true; 16132292SN/A toRename->iewInfo[tid].freeIQEntries = 161410164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 16152292SN/A toRename->iewInfo[tid].usedLSQ = true; 16162292SN/A toRename->iewInfo[tid].freeLSQEntries = 16172292SN/A ldstQueue.numFreeEntries(tid); 16182292SN/A 16192292SN/A wroteToTimeBuffer = true; 16202292SN/A } 16212292SN/A 16222292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 16232292SN/A tid, toRename->iewInfo[tid].dispatched); 16241061SN/A } 16251061SN/A 16262292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 16272292SN/A "LSQ has %i free entries.\n", 16282292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 16292292SN/A ldstQueue.numFreeEntries()); 16302292SN/A 16312292SN/A updateStatus(); 16322292SN/A 16332292SN/A if (wroteToTimeBuffer) { 16342292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16352292SN/A cpu->activityThisCycle(); 16361061SN/A } 16371060SN/A} 16381060SN/A 16392301SN/Atemplate <class Impl> 16401060SN/Avoid 16412301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16421060SN/A{ 16436221Snate@binkert.org ThreadID tid = inst->threadNumber; 16441060SN/A 16452669Sktlim@umich.edu iewExecutedInsts++; 16461060SN/A 16478471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16489527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16499527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16509527SMatt.Horsnell@arm.com } 16518471SGiacomo.Gabrielli@arm.com#endif 16528471SGiacomo.Gabrielli@arm.com 16532301SN/A // 16542301SN/A // Control operations 16552301SN/A // 16562301SN/A if (inst->isControl()) 16576221Snate@binkert.org iewExecutedBranches[tid]++; 16581060SN/A 16592301SN/A // 16602301SN/A // Memory operations 16612301SN/A // 16622301SN/A if (inst->isMemRef()) { 16636221Snate@binkert.org iewExecutedRefs[tid]++; 16641060SN/A 16652301SN/A if (inst->isLoad()) { 16666221Snate@binkert.org iewExecLoadInsts[tid]++; 16671060SN/A } 16681060SN/A } 16691060SN/A} 16707598Sminkyu.jeong@arm.com 16717598Sminkyu.jeong@arm.comtemplate <class Impl> 16727598Sminkyu.jeong@arm.comvoid 16737598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16747598Sminkyu.jeong@arm.com{ 16757598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16767598Sminkyu.jeong@arm.com 16777598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16787852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16797598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16807598Sminkyu.jeong@arm.com 16817598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16827598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16837598Sminkyu.jeong@arm.com 16847598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16857598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16867720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16877598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16887720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16897720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16907598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16917598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16927598Sminkyu.jeong@arm.com 16937598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16947598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16957598Sminkyu.jeong@arm.com } else { 16967598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16977598Sminkyu.jeong@arm.com } 16987598Sminkyu.jeong@arm.com } 16997598Sminkyu.jeong@arm.com } 17007598Sminkyu.jeong@arm.com} 17019944Smatt.horsnell@ARM.com 17029944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1703