iew_impl.hh revision 10023
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com 461060SN/A// @todo: Fix the instantaneous communication among all the stages within 471060SN/A// iew. There's a clear delay between issue and execute, yet backwards 481689SN/A// communication happens simultaneously. 491060SN/A 501060SN/A#include <queue> 511060SN/A 528230Snate@binkert.org#include "arch/utility.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 552292SN/A#include "cpu/o3/fu_pool.hh" 561717SN/A#include "cpu/o3/iew.hh" 578229Snate@binkert.org#include "cpu/timebuf.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/IEW.hh" 619527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 625529Snate@binkert.org#include "params/DerivO3CPU.hh" 631060SN/A 646221Snate@binkert.orgusing namespace std; 656221Snate@binkert.org 661681SN/Atemplate<class Impl> 675529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 682873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 694329Sktlim@umich.edu cpu(_cpu), 704329Sktlim@umich.edu instQueue(_cpu, this, params), 714329Sktlim@umich.edu ldstQueue(_cpu, this, params), 722292SN/A fuPool(params->fuPool), 732292SN/A commitToIEWDelay(params->commitToIEWDelay), 742292SN/A renameToIEWDelay(params->renameToIEWDelay), 752292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 762820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 772292SN/A issueWidth(params->issueWidth), 782820Sktlim@umich.edu wbOutstanding(0), 792820Sktlim@umich.edu wbWidth(params->wbWidth), 809444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 811060SN/A{ 822292SN/A _status = Active; 832292SN/A exeStatus = Running; 842292SN/A wbStatus = Idle; 851060SN/A 861060SN/A // Setup wire to read instructions coming from issue. 871060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 881060SN/A 891060SN/A // Instruction queue needs the queue between issue and execute. 901060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 911681SN/A 926221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 936221Snate@binkert.org dispatchStatus[tid] = Running; 946221Snate@binkert.org stalls[tid].commit = false; 956221Snate@binkert.org fetchRedirect[tid] = false; 962292SN/A } 972292SN/A 982820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 992820Sktlim@umich.edu 1002292SN/A updateLSQNextCycle = false; 1012292SN/A 1022820Sktlim@umich.edu ableToIssue = true; 1032820Sktlim@umich.edu 1042292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1052292SN/A} 1062292SN/A 1072292SN/Atemplate <class Impl> 1082292SN/Astd::string 1092292SN/ADefaultIEW<Impl>::name() const 1102292SN/A{ 1112292SN/A return cpu->name() + ".iew"; 1121060SN/A} 1131060SN/A 1141681SN/Atemplate <class Impl> 1151062SN/Avoid 11610023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 11710023Smatt.horsnell@ARM.com{ 11810023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 11910023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 12010023Smatt.horsnell@ARM.com} 12110023Smatt.horsnell@ARM.com 12210023Smatt.horsnell@ARM.comtemplate <class Impl> 12310023Smatt.horsnell@ARM.comvoid 1242292SN/ADefaultIEW<Impl>::regStats() 1251062SN/A{ 1262301SN/A using namespace Stats; 1272301SN/A 1281062SN/A instQueue.regStats(); 1292727Sktlim@umich.edu ldstQueue.regStats(); 1301062SN/A 1311062SN/A iewIdleCycles 1321062SN/A .name(name() + ".iewIdleCycles") 1331062SN/A .desc("Number of cycles IEW is idle"); 1341062SN/A 1351062SN/A iewSquashCycles 1361062SN/A .name(name() + ".iewSquashCycles") 1371062SN/A .desc("Number of cycles IEW is squashing"); 1381062SN/A 1391062SN/A iewBlockCycles 1401062SN/A .name(name() + ".iewBlockCycles") 1411062SN/A .desc("Number of cycles IEW is blocking"); 1421062SN/A 1431062SN/A iewUnblockCycles 1441062SN/A .name(name() + ".iewUnblockCycles") 1451062SN/A .desc("Number of cycles IEW is unblocking"); 1461062SN/A 1471062SN/A iewDispatchedInsts 1481062SN/A .name(name() + ".iewDispatchedInsts") 1491062SN/A .desc("Number of instructions dispatched to IQ"); 1501062SN/A 1511062SN/A iewDispSquashedInsts 1521062SN/A .name(name() + ".iewDispSquashedInsts") 1531062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1541062SN/A 1551062SN/A iewDispLoadInsts 1561062SN/A .name(name() + ".iewDispLoadInsts") 1571062SN/A .desc("Number of dispatched load instructions"); 1581062SN/A 1591062SN/A iewDispStoreInsts 1601062SN/A .name(name() + ".iewDispStoreInsts") 1611062SN/A .desc("Number of dispatched store instructions"); 1621062SN/A 1631062SN/A iewDispNonSpecInsts 1641062SN/A .name(name() + ".iewDispNonSpecInsts") 1651062SN/A .desc("Number of dispatched non-speculative instructions"); 1661062SN/A 1671062SN/A iewIQFullEvents 1681062SN/A .name(name() + ".iewIQFullEvents") 1691062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1701062SN/A 1712292SN/A iewLSQFullEvents 1722292SN/A .name(name() + ".iewLSQFullEvents") 1732292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1742292SN/A 1751062SN/A memOrderViolationEvents 1761062SN/A .name(name() + ".memOrderViolationEvents") 1771062SN/A .desc("Number of memory order violations"); 1781062SN/A 1791062SN/A predictedTakenIncorrect 1801062SN/A .name(name() + ".predictedTakenIncorrect") 1811062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1822292SN/A 1832292SN/A predictedNotTakenIncorrect 1842292SN/A .name(name() + ".predictedNotTakenIncorrect") 1852292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1862292SN/A 1872292SN/A branchMispredicts 1882292SN/A .name(name() + ".branchMispredicts") 1892292SN/A .desc("Number of branch mispredicts detected at execute"); 1902292SN/A 1912292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1922301SN/A 1932727Sktlim@umich.edu iewExecutedInsts 1942353SN/A .name(name() + ".iewExecutedInsts") 1952727Sktlim@umich.edu .desc("Number of executed instructions"); 1962727Sktlim@umich.edu 1972727Sktlim@umich.edu iewExecLoadInsts 1986221Snate@binkert.org .init(cpu->numThreads) 1992353SN/A .name(name() + ".iewExecLoadInsts") 2002727Sktlim@umich.edu .desc("Number of load instructions executed") 2012727Sktlim@umich.edu .flags(total); 2022727Sktlim@umich.edu 2032727Sktlim@umich.edu iewExecSquashedInsts 2042353SN/A .name(name() + ".iewExecSquashedInsts") 2052727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2062727Sktlim@umich.edu 2072727Sktlim@umich.edu iewExecutedSwp 2086221Snate@binkert.org .init(cpu->numThreads) 2098240Snate@binkert.org .name(name() + ".exec_swp") 2102301SN/A .desc("number of swp insts executed") 2112727Sktlim@umich.edu .flags(total); 2122301SN/A 2132727Sktlim@umich.edu iewExecutedNop 2146221Snate@binkert.org .init(cpu->numThreads) 2158240Snate@binkert.org .name(name() + ".exec_nop") 2162301SN/A .desc("number of nop insts executed") 2172727Sktlim@umich.edu .flags(total); 2182301SN/A 2192727Sktlim@umich.edu iewExecutedRefs 2206221Snate@binkert.org .init(cpu->numThreads) 2218240Snate@binkert.org .name(name() + ".exec_refs") 2222301SN/A .desc("number of memory reference insts executed") 2232727Sktlim@umich.edu .flags(total); 2242301SN/A 2252727Sktlim@umich.edu iewExecutedBranches 2266221Snate@binkert.org .init(cpu->numThreads) 2278240Snate@binkert.org .name(name() + ".exec_branches") 2282301SN/A .desc("Number of branches executed") 2292727Sktlim@umich.edu .flags(total); 2302301SN/A 2312301SN/A iewExecStoreInsts 2328240Snate@binkert.org .name(name() + ".exec_stores") 2332301SN/A .desc("Number of stores executed") 2342727Sktlim@umich.edu .flags(total); 2352727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2362727Sktlim@umich.edu 2372727Sktlim@umich.edu iewExecRate 2388240Snate@binkert.org .name(name() + ".exec_rate") 2392727Sktlim@umich.edu .desc("Inst execution rate") 2402727Sktlim@umich.edu .flags(total); 2412727Sktlim@umich.edu 2422727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2432301SN/A 2442301SN/A iewInstsToCommit 2456221Snate@binkert.org .init(cpu->numThreads) 2468240Snate@binkert.org .name(name() + ".wb_sent") 2472301SN/A .desc("cumulative count of insts sent to commit") 2482727Sktlim@umich.edu .flags(total); 2492301SN/A 2502326SN/A writebackCount 2516221Snate@binkert.org .init(cpu->numThreads) 2528240Snate@binkert.org .name(name() + ".wb_count") 2532301SN/A .desc("cumulative count of insts written-back") 2542727Sktlim@umich.edu .flags(total); 2552301SN/A 2562326SN/A producerInst 2576221Snate@binkert.org .init(cpu->numThreads) 2588240Snate@binkert.org .name(name() + ".wb_producers") 2592301SN/A .desc("num instructions producing a value") 2602727Sktlim@umich.edu .flags(total); 2612301SN/A 2622326SN/A consumerInst 2636221Snate@binkert.org .init(cpu->numThreads) 2648240Snate@binkert.org .name(name() + ".wb_consumers") 2652301SN/A .desc("num instructions consuming a value") 2662727Sktlim@umich.edu .flags(total); 2672301SN/A 2682326SN/A wbPenalized 2696221Snate@binkert.org .init(cpu->numThreads) 2708240Snate@binkert.org .name(name() + ".wb_penalized") 2712301SN/A .desc("number of instrctions required to write to 'other' IQ") 2722727Sktlim@umich.edu .flags(total); 2732301SN/A 2742326SN/A wbPenalizedRate 2758240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2762301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2772727Sktlim@umich.edu .flags(total); 2782301SN/A 2792326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2802301SN/A 2812326SN/A wbFanout 2828240Snate@binkert.org .name(name() + ".wb_fanout") 2832301SN/A .desc("average fanout of values written-back") 2842727Sktlim@umich.edu .flags(total); 2852301SN/A 2862326SN/A wbFanout = producerInst / consumerInst; 2872301SN/A 2882326SN/A wbRate 2898240Snate@binkert.org .name(name() + ".wb_rate") 2902301SN/A .desc("insts written-back per cycle") 2912727Sktlim@umich.edu .flags(total); 2922326SN/A wbRate = writebackCount / cpu->numCycles; 2931062SN/A} 2941062SN/A 2951681SN/Atemplate<class Impl> 2961060SN/Avoid 2979427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 2981060SN/A{ 2996221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3002292SN/A toRename->iewInfo[tid].usedIQ = true; 3012292SN/A toRename->iewInfo[tid].freeIQEntries = 3022292SN/A instQueue.numFreeEntries(tid); 3032292SN/A 3042292SN/A toRename->iewInfo[tid].usedLSQ = true; 3052292SN/A toRename->iewInfo[tid].freeLSQEntries = 3062292SN/A ldstQueue.numFreeEntries(tid); 3072292SN/A } 3082292SN/A 3098887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3108733Sgeoffrey.blake@arm.com if (cpu->checker) { 3118850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3128887Sgeoffrey.blake@arm.com } 3138733Sgeoffrey.blake@arm.com 3142733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3151060SN/A} 3161060SN/A 3171681SN/Atemplate<class Impl> 3181060SN/Avoid 3192292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3201060SN/A{ 3211060SN/A timeBuffer = tb_ptr; 3221060SN/A 3231060SN/A // Setup wire to read information from time buffer, from commit. 3241060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3251060SN/A 3261060SN/A // Setup wire to write information back to previous stages. 3271060SN/A toRename = timeBuffer->getWire(0); 3281060SN/A 3292292SN/A toFetch = timeBuffer->getWire(0); 3302292SN/A 3311060SN/A // Instruction queue also needs main time buffer. 3321060SN/A instQueue.setTimeBuffer(tb_ptr); 3331060SN/A} 3341060SN/A 3351681SN/Atemplate<class Impl> 3361060SN/Avoid 3372292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3381060SN/A{ 3391060SN/A renameQueue = rq_ptr; 3401060SN/A 3411060SN/A // Setup wire to read information from rename queue. 3421060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3431060SN/A} 3441060SN/A 3451681SN/Atemplate<class Impl> 3461060SN/Avoid 3472292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3481060SN/A{ 3491060SN/A iewQueue = iq_ptr; 3501060SN/A 3511060SN/A // Setup wire to write instructions to commit. 3521060SN/A toCommit = iewQueue->getWire(0); 3531060SN/A} 3541060SN/A 3551681SN/Atemplate<class Impl> 3561060SN/Avoid 3576221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3581060SN/A{ 3592292SN/A activeThreads = at_ptr; 3602292SN/A 3612292SN/A ldstQueue.setActiveThreads(at_ptr); 3622292SN/A instQueue.setActiveThreads(at_ptr); 3631060SN/A} 3641060SN/A 3651681SN/Atemplate<class Impl> 3661060SN/Avoid 3672292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3681060SN/A{ 3692292SN/A scoreboard = sb_ptr; 3701060SN/A} 3711060SN/A 3722307SN/Atemplate <class Impl> 3732863Sktlim@umich.edubool 3749444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3752307SN/A{ 3769444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3779444SAndreas.Sandberg@ARM.com 3789444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3799444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3809444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3819444SAndreas.Sandberg@ARM.com drained = false; 3829444SAndreas.Sandberg@ARM.com } 3839444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3849444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3859444SAndreas.Sandberg@ARM.com drained = false; 3869444SAndreas.Sandberg@ARM.com } 3879444SAndreas.Sandberg@ARM.com } 3889444SAndreas.Sandberg@ARM.com 3899783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 3909783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 3919783Sandreas.hansson@arm.com // above 3929783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 3939783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 3949783Sandreas.hansson@arm.com drained = false; 3959783Sandreas.hansson@arm.com } 3969783Sandreas.hansson@arm.com 3979444SAndreas.Sandberg@ARM.com return drained; 3981681SN/A} 3991681SN/A 4002316SN/Atemplate <class Impl> 4011681SN/Avoid 4029444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4032843Sktlim@umich.edu{ 4049444SAndreas.Sandberg@ARM.com assert(isDrained()); 4052843Sktlim@umich.edu 4069444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4079444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4081681SN/A} 4091681SN/A 4102307SN/Atemplate <class Impl> 4111681SN/Avoid 4122307SN/ADefaultIEW<Impl>::takeOverFrom() 4131060SN/A{ 4142348SN/A // Reset all state. 4152307SN/A _status = Active; 4162307SN/A exeStatus = Running; 4172307SN/A wbStatus = Idle; 4181060SN/A 4192307SN/A instQueue.takeOverFrom(); 4202307SN/A ldstQueue.takeOverFrom(); 4219444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4221060SN/A 4239427SAndreas.Sandberg@ARM.com startupStage(); 4242307SN/A cpu->activityThisCycle(); 4251060SN/A 4266221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4276221Snate@binkert.org dispatchStatus[tid] = Running; 4286221Snate@binkert.org stalls[tid].commit = false; 4296221Snate@binkert.org fetchRedirect[tid] = false; 4302307SN/A } 4311060SN/A 4322307SN/A updateLSQNextCycle = false; 4332307SN/A 4342873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4352307SN/A issueToExecQueue.advance(); 4361060SN/A } 4371060SN/A} 4381060SN/A 4391681SN/Atemplate<class Impl> 4401060SN/Avoid 4416221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4422107SN/A{ 4436221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4442107SN/A 4452292SN/A // Tell the IQ to start squashing. 4462292SN/A instQueue.squash(tid); 4472107SN/A 4482292SN/A // Tell the LDSTQ to start squashing. 4492326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4502292SN/A updatedQueues = true; 4512107SN/A 4522292SN/A // Clear the skid buffer in case it has any data in it. 4532935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4544632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4552935Sksewell@umich.edu 4562292SN/A while (!skidBuffer[tid].empty()) { 4572292SN/A if (skidBuffer[tid].front()->isLoad() || 4582292SN/A skidBuffer[tid].front()->isStore() ) { 4592292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4602292SN/A } 4612107SN/A 4622292SN/A toRename->iewInfo[tid].dispatched++; 4632107SN/A 4642292SN/A skidBuffer[tid].pop(); 4652292SN/A } 4662107SN/A 4672702Sktlim@umich.edu emptyRenameInsts(tid); 4682107SN/A} 4692107SN/A 4702107SN/Atemplate<class Impl> 4712107SN/Avoid 4726221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4732292SN/A{ 4747720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4757720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4762292SN/A 4777852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4787852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4797852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4807852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4817852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4822935Sksewell@umich.edu 4837852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4847852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4852292SN/A 4867852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4877852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4887852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4892292SN/A 4907852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4917852SMatt.Horsnell@arm.com } 4927852SMatt.Horsnell@arm.com 4932292SN/A} 4942292SN/A 4952292SN/Atemplate<class Impl> 4962292SN/Avoid 4976221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4982292SN/A{ 4998513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5008513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5018513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5028513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5038513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5048513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5058513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5068513SGiacomo.Gabrielli@arm.com // the squash. 5078513SGiacomo.Gabrielli@arm.com if (toCommit->squash[tid] == false || 5088513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5098513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5102292SN/A 5117852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5128513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5138137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5142292SN/A 5158513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5168513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5172292SN/A 5187852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5197852SMatt.Horsnell@arm.com } 5202292SN/A} 5212292SN/A 5222292SN/Atemplate<class Impl> 5232292SN/Avoid 5246221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5252292SN/A{ 5262292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5277720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5287852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5297852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5307852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5312292SN/A 5327852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5337852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5348137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5352292SN/A 5367852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5377852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5382292SN/A 5397852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5402292SN/A 5417852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5427852SMatt.Horsnell@arm.com } 5432292SN/A} 5442292SN/A 5452292SN/Atemplate<class Impl> 5462292SN/Avoid 5476221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5482292SN/A{ 5492292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5502292SN/A 5512292SN/A if (dispatchStatus[tid] != Blocked && 5522292SN/A dispatchStatus[tid] != Unblocking) { 5532292SN/A toRename->iewBlock[tid] = true; 5542292SN/A wroteToTimeBuffer = true; 5552292SN/A } 5562292SN/A 5572292SN/A // Add the current inputs to the skid buffer so they can be 5582292SN/A // reprocessed when this stage unblocks. 5592292SN/A skidInsert(tid); 5602292SN/A 5612292SN/A dispatchStatus[tid] = Blocked; 5622292SN/A} 5632292SN/A 5642292SN/Atemplate<class Impl> 5652292SN/Avoid 5666221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5672292SN/A{ 5682292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5692292SN/A "buffer %u.\n",tid, tid); 5702292SN/A 5712292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5722292SN/A // Also switch status to running. 5732292SN/A if (skidBuffer[tid].empty()) { 5742292SN/A toRename->iewUnblock[tid] = true; 5752292SN/A wroteToTimeBuffer = true; 5762292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5772292SN/A dispatchStatus[tid] = Running; 5782292SN/A } 5792292SN/A} 5802292SN/A 5812292SN/Atemplate<class Impl> 5822292SN/Avoid 5832292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5841060SN/A{ 5851681SN/A instQueue.wakeDependents(inst); 5861060SN/A} 5871060SN/A 5882292SN/Atemplate<class Impl> 5892292SN/Avoid 5902292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5912292SN/A{ 5922292SN/A instQueue.rescheduleMemInst(inst); 5932292SN/A} 5941681SN/A 5951681SN/Atemplate<class Impl> 5961060SN/Avoid 5972292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5981060SN/A{ 5992292SN/A instQueue.replayMemInst(inst); 6002292SN/A} 6011060SN/A 6022292SN/Atemplate<class Impl> 6032292SN/Avoid 6042292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6052292SN/A{ 6063221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6073221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6083221Sktlim@umich.edu // being added to the queue to commit without being processed by 6093221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6103221Sktlim@umich.edu 6112292SN/A // First check the time slot that this instruction will write 6122292SN/A // to. If there are free write ports at the time, then go ahead 6132292SN/A // and write the instruction to that time. If there are not, 6142292SN/A // keep looking back to see where's the first time there's a 6152326SN/A // free slot. 6162292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6172292SN/A ++wbNumInst; 6182820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6192292SN/A ++wbCycle; 6202292SN/A wbNumInst = 0; 6212292SN/A } 6222292SN/A 6232353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6242292SN/A } 6252292SN/A 6262353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6272353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6282292SN/A // Add finished instruction to queue to commit. 6292292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6302292SN/A (*iewQueue)[wbCycle].size++; 6312292SN/A} 6322292SN/A 6332292SN/Atemplate <class Impl> 6342292SN/Aunsigned 6352292SN/ADefaultIEW<Impl>::validInstsFromRename() 6362292SN/A{ 6372292SN/A unsigned inst_count = 0; 6382292SN/A 6392292SN/A for (int i=0; i<fromRename->size; i++) { 6402731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6412292SN/A inst_count++; 6422292SN/A } 6432292SN/A 6442292SN/A return inst_count; 6452292SN/A} 6462292SN/A 6472292SN/Atemplate<class Impl> 6482292SN/Avoid 6496221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6502292SN/A{ 6512292SN/A DynInstPtr inst = NULL; 6522292SN/A 6532292SN/A while (!insts[tid].empty()) { 6542292SN/A inst = insts[tid].front(); 6552292SN/A 6562292SN/A insts[tid].pop(); 6572292SN/A 6589937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6592292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6607720Sgblack@eecs.umich.edu inst->pcState(),tid); 6612292SN/A 6622292SN/A skidBuffer[tid].push(inst); 6632292SN/A } 6642292SN/A 6652292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6662292SN/A "Skidbuffer Exceeded Max Size"); 6672292SN/A} 6682292SN/A 6692292SN/Atemplate<class Impl> 6702292SN/Aint 6712292SN/ADefaultIEW<Impl>::skidCount() 6722292SN/A{ 6732292SN/A int max=0; 6742292SN/A 6756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6772292SN/A 6783867Sbinkertn@umich.edu while (threads != end) { 6796221Snate@binkert.org ThreadID tid = *threads++; 6803867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6812292SN/A if (max < thread_count) 6822292SN/A max = thread_count; 6832292SN/A } 6842292SN/A 6852292SN/A return max; 6862292SN/A} 6872292SN/A 6882292SN/Atemplate<class Impl> 6892292SN/Abool 6902292SN/ADefaultIEW<Impl>::skidsEmpty() 6912292SN/A{ 6926221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6936221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6942292SN/A 6953867Sbinkertn@umich.edu while (threads != end) { 6966221Snate@binkert.org ThreadID tid = *threads++; 6973867Sbinkertn@umich.edu 6983867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6992292SN/A return false; 7002292SN/A } 7012292SN/A 7022292SN/A return true; 7031062SN/A} 7041062SN/A 7051681SN/Atemplate <class Impl> 7061062SN/Avoid 7072292SN/ADefaultIEW<Impl>::updateStatus() 7081062SN/A{ 7092292SN/A bool any_unblocking = false; 7101062SN/A 7116221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7126221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7131062SN/A 7143867Sbinkertn@umich.edu while (threads != end) { 7156221Snate@binkert.org ThreadID tid = *threads++; 7161062SN/A 7172292SN/A if (dispatchStatus[tid] == Unblocking) { 7182292SN/A any_unblocking = true; 7192292SN/A break; 7202292SN/A } 7212292SN/A } 7221062SN/A 7232292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7242292SN/A // and there's no stores waiting to write back, and dispatch is not 7252292SN/A // unblocking, then there is no internal activity for the IEW stage. 7267897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7272292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7282292SN/A !ldstQueue.willWB() && !any_unblocking) { 7292292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7301062SN/A 7312292SN/A deactivateStage(); 7321062SN/A 7332292SN/A _status = Inactive; 7342292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7352292SN/A ldstQueue.willWB() || 7362292SN/A any_unblocking)) { 7372292SN/A // Otherwise there is internal activity. Set to active. 7382292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7391062SN/A 7402292SN/A activateStage(); 7411062SN/A 7422292SN/A _status = Active; 7431062SN/A } 7441062SN/A} 7451062SN/A 7461681SN/Atemplate <class Impl> 7471062SN/Avoid 7482292SN/ADefaultIEW<Impl>::resetEntries() 7491062SN/A{ 7502292SN/A instQueue.resetEntries(); 7512292SN/A ldstQueue.resetEntries(); 7522292SN/A} 7531062SN/A 7542292SN/Atemplate <class Impl> 7552292SN/Avoid 7566221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7572292SN/A{ 7582292SN/A if (fromCommit->commitBlock[tid]) { 7592292SN/A stalls[tid].commit = true; 7602292SN/A } 7611062SN/A 7622292SN/A if (fromCommit->commitUnblock[tid]) { 7632292SN/A assert(stalls[tid].commit); 7642292SN/A stalls[tid].commit = false; 7652292SN/A } 7662292SN/A} 7672292SN/A 7682292SN/Atemplate <class Impl> 7692292SN/Abool 7706221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7712292SN/A{ 7722292SN/A bool ret_val(false); 7732292SN/A 7742292SN/A if (stalls[tid].commit) { 7752292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7762292SN/A ret_val = true; 7772292SN/A } else if (instQueue.isFull(tid)) { 7782292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7792292SN/A ret_val = true; 7802292SN/A } else if (ldstQueue.isFull(tid)) { 7812292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7822292SN/A 7832292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7842292SN/A 7852292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7862292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7872292SN/A } 7882292SN/A 7892292SN/A if (ldstQueue.numStores(tid) > 0) { 7902292SN/A 7912292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7922292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7932292SN/A } 7942292SN/A 7952292SN/A ret_val = true; 7962292SN/A } else if (ldstQueue.isStalled(tid)) { 7972292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7982292SN/A ret_val = true; 7992292SN/A } 8002292SN/A 8012292SN/A return ret_val; 8022292SN/A} 8032292SN/A 8042292SN/Atemplate <class Impl> 8052292SN/Avoid 8066221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 8072292SN/A{ 8082292SN/A // Check if there's a squash signal, squash if there is 8092292SN/A // Check stall signals, block if there is. 8102292SN/A // If status was Blocked 8112292SN/A // if so then go to unblocking 8122292SN/A // If status was Squashing 8132292SN/A // check if squashing is not high. Switch to running this cycle. 8142292SN/A 8152292SN/A readStallSignals(tid); 8162292SN/A 8172292SN/A if (fromCommit->commitInfo[tid].squash) { 8182292SN/A squash(tid); 8192292SN/A 8202292SN/A if (dispatchStatus[tid] == Blocked || 8212292SN/A dispatchStatus[tid] == Unblocking) { 8222292SN/A toRename->iewUnblock[tid] = true; 8232292SN/A wroteToTimeBuffer = true; 8242292SN/A } 8252292SN/A 8262292SN/A dispatchStatus[tid] = Squashing; 8272292SN/A fetchRedirect[tid] = false; 8282292SN/A return; 8292292SN/A } 8302292SN/A 8312292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8322702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8332292SN/A 8342292SN/A dispatchStatus[tid] = Squashing; 8352702Sktlim@umich.edu emptyRenameInsts(tid); 8362702Sktlim@umich.edu wroteToTimeBuffer = true; 8372292SN/A return; 8382292SN/A } 8392292SN/A 8402292SN/A if (checkStall(tid)) { 8412292SN/A block(tid); 8422292SN/A dispatchStatus[tid] = Blocked; 8432292SN/A return; 8442292SN/A } 8452292SN/A 8462292SN/A if (dispatchStatus[tid] == Blocked) { 8472292SN/A // Status from previous cycle was blocked, but there are no more stall 8482292SN/A // conditions. Switch over to unblocking. 8492292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8502292SN/A tid); 8512292SN/A 8522292SN/A dispatchStatus[tid] = Unblocking; 8532292SN/A 8542292SN/A unblock(tid); 8552292SN/A 8562292SN/A return; 8572292SN/A } 8582292SN/A 8592292SN/A if (dispatchStatus[tid] == Squashing) { 8602292SN/A // Switch status to running if rename isn't being told to block or 8612292SN/A // squash this cycle. 8622292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8632292SN/A tid); 8642292SN/A 8652292SN/A dispatchStatus[tid] = Running; 8662292SN/A 8672292SN/A return; 8682292SN/A } 8692292SN/A} 8702292SN/A 8712292SN/Atemplate <class Impl> 8722292SN/Avoid 8732292SN/ADefaultIEW<Impl>::sortInsts() 8742292SN/A{ 8752292SN/A int insts_from_rename = fromRename->size; 8762326SN/A#ifdef DEBUG 8776221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8786221Snate@binkert.org assert(insts[tid].empty()); 8792326SN/A#endif 8802292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8812292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8822292SN/A } 8832292SN/A} 8842292SN/A 8852292SN/Atemplate <class Impl> 8862292SN/Avoid 8876221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8882702Sktlim@umich.edu{ 8894632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8902935Sksewell@umich.edu 8912702Sktlim@umich.edu while (!insts[tid].empty()) { 8922935Sksewell@umich.edu 8932702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8942702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8952702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8962702Sktlim@umich.edu } 8972702Sktlim@umich.edu 8982702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8992702Sktlim@umich.edu 9002702Sktlim@umich.edu insts[tid].pop(); 9012702Sktlim@umich.edu } 9022702Sktlim@umich.edu} 9032702Sktlim@umich.edu 9042702Sktlim@umich.edutemplate <class Impl> 9052702Sktlim@umich.eduvoid 9062292SN/ADefaultIEW<Impl>::wakeCPU() 9072292SN/A{ 9082292SN/A cpu->wakeCPU(); 9092292SN/A} 9102292SN/A 9112292SN/Atemplate <class Impl> 9122292SN/Avoid 9132292SN/ADefaultIEW<Impl>::activityThisCycle() 9142292SN/A{ 9152292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9162292SN/A cpu->activityThisCycle(); 9172292SN/A} 9182292SN/A 9192292SN/Atemplate <class Impl> 9202292SN/Ainline void 9212292SN/ADefaultIEW<Impl>::activateStage() 9222292SN/A{ 9232292SN/A DPRINTF(Activity, "Activating stage.\n"); 9242733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9252292SN/A} 9262292SN/A 9272292SN/Atemplate <class Impl> 9282292SN/Ainline void 9292292SN/ADefaultIEW<Impl>::deactivateStage() 9302292SN/A{ 9312292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9322733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9332292SN/A} 9342292SN/A 9352292SN/Atemplate<class Impl> 9362292SN/Avoid 9376221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9382292SN/A{ 9392292SN/A // If status is Running or idle, 9402292SN/A // call dispatchInsts() 9412292SN/A // If status is Unblocking, 9422292SN/A // buffer any instructions coming from rename 9432292SN/A // continue trying to empty skid buffer 9442292SN/A // check if stall conditions have passed 9452292SN/A 9462292SN/A if (dispatchStatus[tid] == Blocked) { 9472292SN/A ++iewBlockCycles; 9482292SN/A 9492292SN/A } else if (dispatchStatus[tid] == Squashing) { 9502292SN/A ++iewSquashCycles; 9512292SN/A } 9522292SN/A 9532292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9542292SN/A // will allow, as long as it is not currently blocked. 9552292SN/A if (dispatchStatus[tid] == Running || 9562292SN/A dispatchStatus[tid] == Idle) { 9572292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9582292SN/A "dispatch.\n", tid); 9592292SN/A 9602292SN/A dispatchInsts(tid); 9612292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9622292SN/A // Make sure that the skid buffer has something in it if the 9632292SN/A // status is unblocking. 9642292SN/A assert(!skidsEmpty()); 9652292SN/A 9662292SN/A // If the status was unblocking, then instructions from the skid 9672292SN/A // buffer were used. Remove those instructions and handle 9682292SN/A // the rest of unblocking. 9692292SN/A dispatchInsts(tid); 9702292SN/A 9712292SN/A ++iewUnblockCycles; 9722292SN/A 9735215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9742292SN/A // Add the current inputs to the skid buffer so they can be 9752292SN/A // reprocessed when this stage unblocks. 9762292SN/A skidInsert(tid); 9772292SN/A } 9782292SN/A 9792292SN/A unblock(tid); 9802292SN/A } 9812292SN/A} 9822292SN/A 9832292SN/Atemplate <class Impl> 9842292SN/Avoid 9856221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9862292SN/A{ 9872292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9882292SN/A // otherwise. 9892292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9902292SN/A dispatchStatus[tid] == Unblocking ? 9912292SN/A skidBuffer[tid] : insts[tid]; 9922292SN/A 9932292SN/A int insts_to_add = insts_to_dispatch.size(); 9942292SN/A 9952292SN/A DynInstPtr inst; 9962292SN/A bool add_to_iq = false; 9972292SN/A int dis_num_inst = 0; 9982292SN/A 9992292SN/A // Loop through the instructions, putting them in the instruction 10002292SN/A // queue. 10012292SN/A for ( ; dis_num_inst < insts_to_add && 10022820Sktlim@umich.edu dis_num_inst < dispatchWidth; 10032292SN/A ++dis_num_inst) 10042292SN/A { 10052292SN/A inst = insts_to_dispatch.front(); 10062292SN/A 10072292SN/A if (dispatchStatus[tid] == Unblocking) { 10082292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10092292SN/A "buffer\n", tid); 10102292SN/A } 10112292SN/A 10122292SN/A // Make sure there's a valid instruction there. 10132292SN/A assert(inst); 10142292SN/A 10157720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10162292SN/A "IQ.\n", 10177720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10182292SN/A 10192292SN/A // Be sure to mark these instructions as ready so that the 10202292SN/A // commit stage can go ahead and execute them, and mark 10212292SN/A // them as issued so the IQ doesn't reprocess them. 10222292SN/A 10232292SN/A // Check for squashed instructions. 10242292SN/A if (inst->isSquashed()) { 10252292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10262292SN/A "not adding to IQ.\n", tid); 10272292SN/A 10282292SN/A ++iewDispSquashedInsts; 10292292SN/A 10302292SN/A insts_to_dispatch.pop(); 10312292SN/A 10322292SN/A //Tell Rename That An Instruction has been processed 10332292SN/A if (inst->isLoad() || inst->isStore()) { 10342292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10352292SN/A } 10362292SN/A toRename->iewInfo[tid].dispatched++; 10372292SN/A 10382292SN/A continue; 10392292SN/A } 10402292SN/A 10412292SN/A // Check for full conditions. 10422292SN/A if (instQueue.isFull(tid)) { 10432292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10442292SN/A 10452292SN/A // Call function to start blocking. 10462292SN/A block(tid); 10472292SN/A 10482292SN/A // Set unblock to false. Special case where we are using 10492292SN/A // skidbuffer (unblocking) instructions but then we still 10502292SN/A // get full in the IQ. 10512292SN/A toRename->iewUnblock[tid] = false; 10522292SN/A 10532292SN/A ++iewIQFullEvents; 10542292SN/A break; 10552292SN/A } else if (ldstQueue.isFull(tid)) { 10562292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10572292SN/A 10582292SN/A // Call function to start blocking. 10592292SN/A block(tid); 10602292SN/A 10612292SN/A // Set unblock to false. Special case where we are using 10622292SN/A // skidbuffer (unblocking) instructions but then we still 10632292SN/A // get full in the IQ. 10642292SN/A toRename->iewUnblock[tid] = false; 10652292SN/A 10662292SN/A ++iewLSQFullEvents; 10672292SN/A break; 10682292SN/A } 10692292SN/A 10702292SN/A // Otherwise issue the instruction just fine. 10712292SN/A if (inst->isLoad()) { 10722292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10732292SN/A "encountered, adding to LSQ.\n", tid); 10742292SN/A 10752292SN/A // Reserve a spot in the load store queue for this 10762292SN/A // memory access. 10772292SN/A ldstQueue.insertLoad(inst); 10782292SN/A 10792292SN/A ++iewDispLoadInsts; 10802292SN/A 10812292SN/A add_to_iq = true; 10822292SN/A 10832292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10842292SN/A } else if (inst->isStore()) { 10852292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10862292SN/A "encountered, adding to LSQ.\n", tid); 10872292SN/A 10882292SN/A ldstQueue.insertStore(inst); 10892292SN/A 10902292SN/A ++iewDispStoreInsts; 10912292SN/A 10922336SN/A if (inst->isStoreConditional()) { 10932336SN/A // Store conditionals need to be set as "canCommit()" 10942336SN/A // so that commit can process them when they reach the 10952336SN/A // head of commit. 10962348SN/A // @todo: This is somewhat specific to Alpha. 10972292SN/A inst->setCanCommit(); 10982292SN/A instQueue.insertNonSpec(inst); 10992292SN/A add_to_iq = false; 11002292SN/A 11012292SN/A ++iewDispNonSpecInsts; 11022292SN/A } else { 11032292SN/A add_to_iq = true; 11042292SN/A } 11052292SN/A 11062292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11072292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11082326SN/A // Same as non-speculative stores. 11092292SN/A inst->setCanCommit(); 11102292SN/A instQueue.insertBarrier(inst); 11112292SN/A add_to_iq = false; 11122292SN/A } else if (inst->isNop()) { 11132292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11142292SN/A "skipping.\n", tid); 11152292SN/A 11162292SN/A inst->setIssued(); 11172292SN/A inst->setExecuted(); 11182292SN/A inst->setCanCommit(); 11192292SN/A 11202326SN/A instQueue.recordProducer(inst); 11212292SN/A 11222727Sktlim@umich.edu iewExecutedNop[tid]++; 11232301SN/A 11242292SN/A add_to_iq = false; 11252292SN/A } else if (inst->isExecuted()) { 11262292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11272292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11282292SN/A "skipping.\n"); 11292292SN/A 11302292SN/A inst->setIssued(); 11312292SN/A inst->setCanCommit(); 11322292SN/A 11332326SN/A instQueue.recordProducer(inst); 11342292SN/A 11352292SN/A add_to_iq = false; 11362292SN/A } else { 11372292SN/A add_to_iq = true; 11382292SN/A } 11394033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11404033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11414033Sktlim@umich.edu "encountered, skipping.\n", tid); 11424033Sktlim@umich.edu 11434033Sktlim@umich.edu // Same as non-speculative stores. 11444033Sktlim@umich.edu inst->setCanCommit(); 11454033Sktlim@umich.edu 11464033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11474033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11484033Sktlim@umich.edu 11494033Sktlim@umich.edu ++iewDispNonSpecInsts; 11504033Sktlim@umich.edu 11514033Sktlim@umich.edu add_to_iq = false; 11524033Sktlim@umich.edu } 11532292SN/A 11542292SN/A // If the instruction queue is not full, then add the 11552292SN/A // instruction. 11562292SN/A if (add_to_iq) { 11572292SN/A instQueue.insert(inst); 11582292SN/A } 11592292SN/A 11602292SN/A insts_to_dispatch.pop(); 11612292SN/A 11622292SN/A toRename->iewInfo[tid].dispatched++; 11632292SN/A 11642292SN/A ++iewDispatchedInsts; 11658471SGiacomo.Gabrielli@arm.com 11668471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11679046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11688471SGiacomo.Gabrielli@arm.com#endif 116910023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11702292SN/A } 11712292SN/A 11722292SN/A if (!insts_to_dispatch.empty()) { 11732935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11742292SN/A block(tid); 11752292SN/A toRename->iewUnblock[tid] = false; 11762292SN/A } 11772292SN/A 11782292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11792292SN/A dispatchStatus[tid] = Running; 11802292SN/A 11812292SN/A updatedQueues = true; 11822292SN/A } 11832292SN/A 11842292SN/A dis_num_inst = 0; 11852292SN/A} 11862292SN/A 11872292SN/Atemplate <class Impl> 11882292SN/Avoid 11892292SN/ADefaultIEW<Impl>::printAvailableInsts() 11902292SN/A{ 11912292SN/A int inst = 0; 11922292SN/A 11932980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11942292SN/A 11952292SN/A while (fromIssue->insts[inst]) { 11962292SN/A 11972980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11982292SN/A 11997720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 12002292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12012292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12022292SN/A 12032292SN/A inst++; 12042292SN/A 12052292SN/A } 12062292SN/A 12072980Sgblack@eecs.umich.edu std::cout << "\n"; 12082292SN/A} 12092292SN/A 12102292SN/Atemplate <class Impl> 12112292SN/Avoid 12122292SN/ADefaultIEW<Impl>::executeInsts() 12132292SN/A{ 12142292SN/A wbNumInst = 0; 12152292SN/A wbCycle = 0; 12162292SN/A 12176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12192292SN/A 12203867Sbinkertn@umich.edu while (threads != end) { 12216221Snate@binkert.org ThreadID tid = *threads++; 12222292SN/A fetchRedirect[tid] = false; 12232292SN/A } 12242292SN/A 12252698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12267599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12272698Sktlim@umich.edu// printAvailableInsts(); 12281062SN/A 12291062SN/A // Execute/writeback any instructions that are available. 12302333SN/A int insts_to_execute = fromIssue->size; 12312292SN/A int inst_num = 0; 12322333SN/A for (; inst_num < insts_to_execute; 12332326SN/A ++inst_num) { 12341062SN/A 12352292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12361062SN/A 12372333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12381062SN/A 12397720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12407720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12411062SN/A 12421062SN/A // Check if the instruction is squashed; if so then skip it 12431062SN/A if (inst->isSquashed()) { 12448315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12458315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12468315Sgeoffrey.blake@arm.com inst->seqNum); 12471062SN/A 12481062SN/A // Consider this instruction executed so that commit can go 12491062SN/A // ahead and retire the instruction. 12501062SN/A inst->setExecuted(); 12511062SN/A 12522292SN/A // Not sure if I should set this here or just let commit try to 12532292SN/A // commit any squashed instructions. I like the latter a bit more. 12542292SN/A inst->setCanCommit(); 12551062SN/A 12561062SN/A ++iewExecSquashedInsts; 12571062SN/A 12582820Sktlim@umich.edu decrWb(inst->seqNum); 12591062SN/A continue; 12601062SN/A } 12611062SN/A 12622292SN/A Fault fault = NoFault; 12631062SN/A 12641062SN/A // Execute instruction. 12651062SN/A // Note that if the instruction faults, it will be handled 12661062SN/A // at the commit stage. 12677850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12682292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12691062SN/A "reference.\n"); 12701062SN/A 12711062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12721062SN/A if (inst->isLoad()) { 12732292SN/A // Loads will mark themselves as executed, and their writeback 12742292SN/A // event adds the instruction to the queue to commit 12752292SN/A fault = ldstQueue.executeLoad(inst); 12767944SGiacomo.Gabrielli@arm.com 12777944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12787944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12797944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12807944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12817944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12827944SGiacomo.Gabrielli@arm.com "load.\n"); 12837944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12847944SGiacomo.Gabrielli@arm.com continue; 12857944SGiacomo.Gabrielli@arm.com } 12867944SGiacomo.Gabrielli@arm.com 12877850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12888073SAli.Saidi@ARM.com inst->fault = NoFault; 12897850SMatt.Horsnell@arm.com } 12901062SN/A } else if (inst->isStore()) { 12912367SN/A fault = ldstQueue.executeStore(inst); 12921062SN/A 12937944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12947944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12957944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12967944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12977944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12987944SGiacomo.Gabrielli@arm.com "store.\n"); 12997944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 13007944SGiacomo.Gabrielli@arm.com continue; 13017944SGiacomo.Gabrielli@arm.com } 13027944SGiacomo.Gabrielli@arm.com 13032292SN/A // If the store had a fault then it may not have a mem req 13047782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 13057782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 13067782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 13077782Sminkyu.jeong@arm.com // to commit without the instruction completing. 13082367SN/A // Send this instruction to commit, also make sure iew stage 13092367SN/A // realizes there is activity. 13102367SN/A inst->setExecuted(); 13112367SN/A instToCommit(inst); 13122367SN/A activityThisCycle(); 13132292SN/A } 13142326SN/A 13152326SN/A // Store conditionals will mark themselves as 13162326SN/A // executed, and their writeback event will add the 13172326SN/A // instruction to the queue to commit. 13181062SN/A } else { 13192292SN/A panic("Unexpected memory type!\n"); 13201062SN/A } 13211062SN/A 13221062SN/A } else { 13237847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13247847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13257847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13267847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13277847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13287847Sminkyu.jeong@arm.com inst->execute(); 13297848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 13307848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13317847Sminkyu.jeong@arm.com } 13321062SN/A 13332292SN/A inst->setExecuted(); 13342292SN/A 13352292SN/A instToCommit(inst); 13361062SN/A } 13371062SN/A 13382301SN/A updateExeInstStats(inst); 13391681SN/A 13402326SN/A // Check if branch prediction was correct, if not then we need 13412326SN/A // to tell commit to squash in flight instructions. Only 13422326SN/A // handle this if there hasn't already been something that 13432107SN/A // redirects fetch in this group of instructions. 13441681SN/A 13452292SN/A // This probably needs to prioritize the redirects if a different 13462292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13472292SN/A // instruction first, so the branch resolution order will be correct. 13486221Snate@binkert.org ThreadID tid = inst->threadNumber; 13491062SN/A 13503732Sktlim@umich.edu if (!fetchRedirect[tid] || 13517852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13523732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13531062SN/A 13547856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13557856SMatt.Horsnell@arm.com // that have not been executed. 13567856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13577856SMatt.Horsnell@arm.com 13587856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13592292SN/A fetchRedirect[tid] = true; 13601062SN/A 13612292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13628674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13638674Snilay@cs.wisc.edu inst->readPredTarg()); 13647720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13658674Snilay@cs.wisc.edu inst->pcState()); 13661062SN/A // If incorrect, then signal the ROB that it must be squashed. 13672292SN/A squashDueToBranch(inst, tid); 13681062SN/A 136910023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 137010023Smatt.horsnell@ARM.com 13713795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13721062SN/A predictedTakenIncorrect++; 13732292SN/A } else { 13742292SN/A predictedNotTakenIncorrect++; 13751062SN/A } 13762292SN/A } else if (ldstQueue.violation(tid)) { 13774033Sktlim@umich.edu assert(inst->isMemRef()); 13782326SN/A // If there was an ordering violation, then get the 13792326SN/A // DynInst that caused the violation. Note that this 13802292SN/A // clears the violation signal. 13812292SN/A DynInstPtr violator; 13822292SN/A violator = ldstQueue.getMemDepViolator(tid); 13831062SN/A 13847720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13857720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13867720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13877720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13887720Sgblack@eecs.umich.edu 13893732Sktlim@umich.edu fetchRedirect[tid] = true; 13903732Sktlim@umich.edu 13911062SN/A // Tell the instruction queue that a violation has occured. 13921062SN/A instQueue.violation(inst, violator); 13931062SN/A 13941062SN/A // Squash. 13958513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13961062SN/A 13971062SN/A ++memOrderViolationEvents; 13982292SN/A } else if (ldstQueue.loadBlocked(tid) && 13992292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 14002292SN/A fetchRedirect[tid] = true; 14012292SN/A 14022292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 14037720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14047720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14052292SN/A 14062292SN/A squashDueToMemBlocked(inst, tid); 14071062SN/A } 14084033Sktlim@umich.edu } else { 14094033Sktlim@umich.edu // Reset any state associated with redirects that will not 14104033Sktlim@umich.edu // be used. 14114033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14124033Sktlim@umich.edu assert(inst->isMemRef()); 14134033Sktlim@umich.edu 14144033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14154033Sktlim@umich.edu 14164033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14177720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14187720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 14197720Sgblack@eecs.umich.edu inst->physEffAddr); 14204033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14214033Sktlim@umich.edu "already squashing\n"); 14224033Sktlim@umich.edu 14234033Sktlim@umich.edu ++memOrderViolationEvents; 14244033Sktlim@umich.edu } 14254033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14264033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14274033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14287720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14297720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14304033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14314033Sktlim@umich.edu "already squashing\n"); 14324033Sktlim@umich.edu 14334033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14344033Sktlim@umich.edu } 14354033Sktlim@umich.edu 14361062SN/A } 14371062SN/A } 14382292SN/A 14392348SN/A // Update and record activity if we processed any instructions. 14402292SN/A if (inst_num) { 14412292SN/A if (exeStatus == Idle) { 14422292SN/A exeStatus = Running; 14432292SN/A } 14442292SN/A 14452292SN/A updatedQueues = true; 14462292SN/A 14472292SN/A cpu->activityThisCycle(); 14482292SN/A } 14492292SN/A 14502292SN/A // Need to reset this in case a writeback event needs to write into the 14512292SN/A // iew queue. That way the writeback event will write into the correct 14522292SN/A // spot in the queue. 14532292SN/A wbNumInst = 0; 14547852SMatt.Horsnell@arm.com 14552107SN/A} 14562107SN/A 14572292SN/Atemplate <class Impl> 14582107SN/Avoid 14592292SN/ADefaultIEW<Impl>::writebackInsts() 14602107SN/A{ 14612326SN/A // Loop through the head of the time buffer and wake any 14622326SN/A // dependents. These instructions are about to write back. Also 14632326SN/A // mark scoreboard that this instruction is finally complete. 14642326SN/A // Either have IEW have direct access to scoreboard, or have this 14652326SN/A // as part of backwards communication. 14663958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14672292SN/A toCommit->insts[inst_num]; inst_num++) { 14682107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14696221Snate@binkert.org ThreadID tid = inst->threadNumber; 14702107SN/A 14717720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14727720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14732107SN/A 14742301SN/A iewInstsToCommit[tid]++; 14752301SN/A 14762292SN/A // Some instructions will be sent to commit without having 14772292SN/A // executed because they need commit to handle them. 14782292SN/A // E.g. Uncached loads have not actually executed when they 14792292SN/A // are first sent to commit. Instead commit must tell the LSQ 14802292SN/A // when it's ready to execute the uncached load. 14812367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14822301SN/A int dependents = instQueue.wakeDependents(inst); 14832107SN/A 14842292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14852292SN/A //mark as Ready 14862292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14872292SN/A inst->renamedDestRegIdx(i)); 14882292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14892107SN/A } 14902301SN/A 14912348SN/A if (dependents) { 14922348SN/A producerInst[tid]++; 14932348SN/A consumerInst[tid]+= dependents; 14942348SN/A } 14952326SN/A writebackCount[tid]++; 14962107SN/A } 14972820Sktlim@umich.edu 14982820Sktlim@umich.edu decrWb(inst->seqNum); 14992107SN/A } 15001060SN/A} 15011060SN/A 15021681SN/Atemplate<class Impl> 15031060SN/Avoid 15042292SN/ADefaultIEW<Impl>::tick() 15051060SN/A{ 15062292SN/A wbNumInst = 0; 15072292SN/A wbCycle = 0; 15081060SN/A 15092292SN/A wroteToTimeBuffer = false; 15102292SN/A updatedQueues = false; 15111060SN/A 15122292SN/A sortInsts(); 15131060SN/A 15142326SN/A // Free function units marked as being freed this cycle. 15152326SN/A fuPool->processFreeUnits(); 15161062SN/A 15176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15191060SN/A 15202326SN/A // Check stall and squash signals, dispatch any instructions. 15213867Sbinkertn@umich.edu while (threads != end) { 15226221Snate@binkert.org ThreadID tid = *threads++; 15231060SN/A 15242292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15251060SN/A 15262292SN/A checkSignalsAndUpdate(tid); 15272292SN/A dispatch(tid); 15281060SN/A } 15291060SN/A 15302292SN/A if (exeStatus != Squashing) { 15312292SN/A executeInsts(); 15321060SN/A 15332292SN/A writebackInsts(); 15342292SN/A 15352292SN/A // Have the instruction queue try to schedule any ready instructions. 15362292SN/A // (In actuality, this scheduling is for instructions that will 15372292SN/A // be executed next cycle.) 15382292SN/A instQueue.scheduleReadyInsts(); 15392292SN/A 15402292SN/A // Also should advance its own time buffers if the stage ran. 15412292SN/A // Not the best place for it, but this works (hopefully). 15422292SN/A issueToExecQueue.advance(); 15432292SN/A } 15442292SN/A 15452292SN/A bool broadcast_free_entries = false; 15462292SN/A 15472292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15482292SN/A exeStatus = Idle; 15492292SN/A updateLSQNextCycle = false; 15502292SN/A 15512292SN/A broadcast_free_entries = true; 15522292SN/A } 15532292SN/A 15542292SN/A // Writeback any stores using any leftover bandwidth. 15551681SN/A ldstQueue.writebackStores(); 15561681SN/A 15571061SN/A // Check the committed load/store signals to see if there's a load 15581061SN/A // or store to commit. Also check if it's being told to execute a 15591061SN/A // nonspeculative instruction. 15601681SN/A // This is pretty inefficient... 15612292SN/A 15623867Sbinkertn@umich.edu threads = activeThreads->begin(); 15633867Sbinkertn@umich.edu while (threads != end) { 15646221Snate@binkert.org ThreadID tid = (*threads++); 15652292SN/A 15662292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15672292SN/A 15682348SN/A // Update structures based on instructions committed. 15692292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15702292SN/A !fromCommit->commitInfo[tid].squash && 15712292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15722292SN/A 15732292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15742292SN/A 15752292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15762292SN/A 15772292SN/A updateLSQNextCycle = true; 15782292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15792292SN/A } 15802292SN/A 15812292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15822292SN/A 15832292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15842292SN/A if (fromCommit->commitInfo[tid].uncached) { 15852292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15864033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15872292SN/A } else { 15882292SN/A instQueue.scheduleNonSpec( 15892292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15902292SN/A } 15912292SN/A } 15922292SN/A 15932292SN/A if (broadcast_free_entries) { 15942292SN/A toFetch->iewInfo[tid].iqCount = 15952292SN/A instQueue.getCount(tid); 15962292SN/A toFetch->iewInfo[tid].ldstqCount = 15972292SN/A ldstQueue.getCount(tid); 15982292SN/A 15992292SN/A toRename->iewInfo[tid].usedIQ = true; 16002292SN/A toRename->iewInfo[tid].freeIQEntries = 16012292SN/A instQueue.numFreeEntries(); 16022292SN/A toRename->iewInfo[tid].usedLSQ = true; 16032292SN/A toRename->iewInfo[tid].freeLSQEntries = 16042292SN/A ldstQueue.numFreeEntries(tid); 16052292SN/A 16062292SN/A wroteToTimeBuffer = true; 16072292SN/A } 16082292SN/A 16092292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 16102292SN/A tid, toRename->iewInfo[tid].dispatched); 16111061SN/A } 16121061SN/A 16132292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 16142292SN/A "LSQ has %i free entries.\n", 16152292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 16162292SN/A ldstQueue.numFreeEntries()); 16172292SN/A 16182292SN/A updateStatus(); 16192292SN/A 16202292SN/A if (wroteToTimeBuffer) { 16212292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16222292SN/A cpu->activityThisCycle(); 16231061SN/A } 16241060SN/A} 16251060SN/A 16262301SN/Atemplate <class Impl> 16271060SN/Avoid 16282301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16291060SN/A{ 16306221Snate@binkert.org ThreadID tid = inst->threadNumber; 16311060SN/A 16322669Sktlim@umich.edu iewExecutedInsts++; 16331060SN/A 16348471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16359527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16369527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16379527SMatt.Horsnell@arm.com } 16388471SGiacomo.Gabrielli@arm.com#endif 16398471SGiacomo.Gabrielli@arm.com 16402301SN/A // 16412301SN/A // Control operations 16422301SN/A // 16432301SN/A if (inst->isControl()) 16446221Snate@binkert.org iewExecutedBranches[tid]++; 16451060SN/A 16462301SN/A // 16472301SN/A // Memory operations 16482301SN/A // 16492301SN/A if (inst->isMemRef()) { 16506221Snate@binkert.org iewExecutedRefs[tid]++; 16511060SN/A 16522301SN/A if (inst->isLoad()) { 16536221Snate@binkert.org iewExecLoadInsts[tid]++; 16541060SN/A } 16551060SN/A } 16561060SN/A} 16577598Sminkyu.jeong@arm.com 16587598Sminkyu.jeong@arm.comtemplate <class Impl> 16597598Sminkyu.jeong@arm.comvoid 16607598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16617598Sminkyu.jeong@arm.com{ 16627598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16637598Sminkyu.jeong@arm.com 16647598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16657852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16667598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16677598Sminkyu.jeong@arm.com 16687598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16697598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16707598Sminkyu.jeong@arm.com 16717598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16727598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16737720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16747598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16757720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16767720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16777598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16787598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16797598Sminkyu.jeong@arm.com 16807598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16817598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16827598Sminkyu.jeong@arm.com } else { 16837598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16847598Sminkyu.jeong@arm.com } 16857598Sminkyu.jeong@arm.com } 16867598Sminkyu.jeong@arm.com } 16877598Sminkyu.jeong@arm.com} 16889944Smatt.horsnell@ARM.com 16899944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1690