iew.hh revision 9476:4a14ff47b8e3
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_IEW_HH__ 44#define __CPU_O3_IEW_HH__ 45 46#include <queue> 47#include <set> 48 49#include "base/statistics.hh" 50#include "cpu/o3/comm.hh" 51#include "cpu/o3/lsq.hh" 52#include "cpu/o3/scoreboard.hh" 53#include "cpu/timebuf.hh" 54#include "debug/IEW.hh" 55 56struct DerivO3CPUParams; 57class FUPool; 58 59/** 60 * DefaultIEW handles both single threaded and SMT IEW 61 * (issue/execute/writeback). It handles the dispatching of 62 * instructions to the LSQ/IQ as part of the issue stage, and has the 63 * IQ try to issue instructions each cycle. The execute latency is 64 * actually tied into the issue latency to allow the IQ to be able to 65 * do back-to-back scheduling without having to speculatively schedule 66 * instructions. This happens by having the IQ have access to the 67 * functional units, and the IQ gets the execution latencies from the 68 * FUs when it issues instructions. Instructions reach the execute 69 * stage on the last cycle of their execution, which is when the IQ 70 * knows to wake up any dependent instructions, allowing back to back 71 * scheduling. The execute portion of IEW separates memory 72 * instructions from non-memory instructions, either telling the LSQ 73 * to execute the instruction, or executing the instruction directly. 74 * The writeback portion of IEW completes the instructions by waking 75 * up any dependents, and marking the register ready on the 76 * scoreboard. 77 */ 78template<class Impl> 79class DefaultIEW 80{ 81 private: 82 //Typedefs from Impl 83 typedef typename Impl::CPUPol CPUPol; 84 typedef typename Impl::DynInstPtr DynInstPtr; 85 typedef typename Impl::O3CPU O3CPU; 86 87 typedef typename CPUPol::IQ IQ; 88 typedef typename CPUPol::RenameMap RenameMap; 89 typedef typename CPUPol::LSQ LSQ; 90 91 typedef typename CPUPol::TimeStruct TimeStruct; 92 typedef typename CPUPol::IEWStruct IEWStruct; 93 typedef typename CPUPol::RenameStruct RenameStruct; 94 typedef typename CPUPol::IssueStruct IssueStruct; 95 96 public: 97 /** Overall IEW stage status. Used to determine if the CPU can 98 * deschedule itself due to a lack of activity. 99 */ 100 enum Status { 101 Active, 102 Inactive 103 }; 104 105 /** Status for Issue, Execute, and Writeback stages. */ 106 enum StageStatus { 107 Running, 108 Blocked, 109 Idle, 110 StartSquash, 111 Squashing, 112 Unblocking 113 }; 114 115 private: 116 /** Overall stage status. */ 117 Status _status; 118 /** Dispatch status. */ 119 StageStatus dispatchStatus[Impl::MaxThreads]; 120 /** Execute status. */ 121 StageStatus exeStatus; 122 /** Writeback status. */ 123 StageStatus wbStatus; 124 125 public: 126 /** Constructs a DefaultIEW with the given parameters. */ 127 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 128 129 /** Returns the name of the DefaultIEW stage. */ 130 std::string name() const; 131 132 /** Registers statistics. */ 133 void regStats(); 134 135 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 136 void startupStage(); 137 138 /** Sets main time buffer used for backwards communication. */ 139 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 140 141 /** Sets time buffer for getting instructions coming from rename. */ 142 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 143 144 /** Sets time buffer to pass on instructions to commit. */ 145 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 146 147 /** Sets pointer to list of active threads. */ 148 void setActiveThreads(std::list<ThreadID> *at_ptr); 149 150 /** Sets pointer to the scoreboard. */ 151 void setScoreboard(Scoreboard *sb_ptr); 152 153 /** Perform sanity checks after a drain. */ 154 void drainSanityCheck() const; 155 156 /** Has the stage drained? */ 157 bool isDrained() const; 158 159 /** Takes over from another CPU's thread. */ 160 void takeOverFrom(); 161 162 /** Squashes instructions in IEW for a specific thread. */ 163 void squash(ThreadID tid); 164 165 /** Wakes all dependents of a completed instruction. */ 166 void wakeDependents(DynInstPtr &inst); 167 168 /** Tells memory dependence unit that a memory instruction needs to be 169 * rescheduled. It will re-execute once replayMemInst() is called. 170 */ 171 void rescheduleMemInst(DynInstPtr &inst); 172 173 /** Re-executes all rescheduled memory instructions. */ 174 void replayMemInst(DynInstPtr &inst); 175 176 /** Sends an instruction to commit through the time buffer. */ 177 void instToCommit(DynInstPtr &inst); 178 179 /** Inserts unused instructions of a thread into the skid buffer. */ 180 void skidInsert(ThreadID tid); 181 182 /** Returns the max of the number of entries in all of the skid buffers. */ 183 int skidCount(); 184 185 /** Returns if all of the skid buffers are empty. */ 186 bool skidsEmpty(); 187 188 /** Updates overall IEW status based on all of the stages' statuses. */ 189 void updateStatus(); 190 191 /** Resets entries of the IQ and the LSQ. */ 192 void resetEntries(); 193 194 /** Tells the CPU to wakeup if it has descheduled itself due to no 195 * activity. Used mainly by the LdWritebackEvent. 196 */ 197 void wakeCPU(); 198 199 /** Reports to the CPU that there is activity this cycle. */ 200 void activityThisCycle(); 201 202 /** Tells CPU that the IEW stage is active and running. */ 203 inline void activateStage(); 204 205 /** Tells CPU that the IEW stage is inactive and idle. */ 206 inline void deactivateStage(); 207 208 /** Returns if the LSQ has any stores to writeback. */ 209 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 210 211 /** Returns if the LSQ has any stores to writeback. */ 212 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 213 214 void incrWb(InstSeqNum &sn) 215 { 216 ++wbOutstanding; 217 if (wbOutstanding == wbMax) 218 ableToIssue = false; 219 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 220 assert(wbOutstanding <= wbMax); 221#ifdef DEBUG 222 wbList.insert(sn); 223#endif 224 } 225 226 void decrWb(InstSeqNum &sn) 227 { 228 if (wbOutstanding == wbMax) 229 ableToIssue = true; 230 wbOutstanding--; 231 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 232 assert(wbOutstanding >= 0); 233#ifdef DEBUG 234 assert(wbList.find(sn) != wbList.end()); 235 wbList.erase(sn); 236#endif 237 } 238 239#ifdef DEBUG 240 std::set<InstSeqNum> wbList; 241 242 void dumpWb() 243 { 244 std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 245 while (wb_it != wbList.end()) { 246 cprintf("[sn:%lli]\n", 247 (*wb_it)); 248 wb_it++; 249 } 250 } 251#endif 252 253 bool canIssue() { return ableToIssue; } 254 255 bool ableToIssue; 256 257 /** Check misprediction */ 258 void checkMisprediction(DynInstPtr &inst); 259 260 private: 261 /** Sends commit proper information for a squash due to a branch 262 * mispredict. 263 */ 264 void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 265 266 /** Sends commit proper information for a squash due to a memory order 267 * violation. 268 */ 269 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 270 271 /** Sends commit proper information for a squash due to memory becoming 272 * blocked (younger issued instructions must be retried). 273 */ 274 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 275 276 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 277 void block(ThreadID tid); 278 279 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 280 * other stages to unblock. 281 */ 282 void unblock(ThreadID tid); 283 284 /** Determines proper actions to take given Dispatch's status. */ 285 void dispatch(ThreadID tid); 286 287 /** Dispatches instructions to IQ and LSQ. */ 288 void dispatchInsts(ThreadID tid); 289 290 /** Executes instructions. In the case of memory operations, it informs the 291 * LSQ to execute the instructions. Also handles any redirects that occur 292 * due to the executed instructions. 293 */ 294 void executeInsts(); 295 296 /** Writebacks instructions. In our model, the instruction's execute() 297 * function atomically reads registers, executes, and writes registers. 298 * Thus this writeback only wakes up dependent instructions, and informs 299 * the scoreboard of registers becoming ready. 300 */ 301 void writebackInsts(); 302 303 /** Returns the number of valid, non-squashed instructions coming from 304 * rename to dispatch. 305 */ 306 unsigned validInstsFromRename(); 307 308 /** Reads the stall signals. */ 309 void readStallSignals(ThreadID tid); 310 311 /** Checks if any of the stall conditions are currently true. */ 312 bool checkStall(ThreadID tid); 313 314 /** Processes inputs and changes state accordingly. */ 315 void checkSignalsAndUpdate(ThreadID tid); 316 317 /** Removes instructions from rename from a thread's instruction list. */ 318 void emptyRenameInsts(ThreadID tid); 319 320 /** Sorts instructions coming from rename into lists separated by thread. */ 321 void sortInsts(); 322 323 public: 324 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 325 * Writeback to run for one cycle. 326 */ 327 void tick(); 328 329 private: 330 /** Updates execution stats based on the instruction. */ 331 void updateExeInstStats(DynInstPtr &inst); 332 333 /** Pointer to main time buffer used for backwards communication. */ 334 TimeBuffer<TimeStruct> *timeBuffer; 335 336 /** Wire to write information heading to previous stages. */ 337 typename TimeBuffer<TimeStruct>::wire toFetch; 338 339 /** Wire to get commit's output from backwards time buffer. */ 340 typename TimeBuffer<TimeStruct>::wire fromCommit; 341 342 /** Wire to write information heading to previous stages. */ 343 typename TimeBuffer<TimeStruct>::wire toRename; 344 345 /** Rename instruction queue interface. */ 346 TimeBuffer<RenameStruct> *renameQueue; 347 348 /** Wire to get rename's output from rename queue. */ 349 typename TimeBuffer<RenameStruct>::wire fromRename; 350 351 /** Issue stage queue. */ 352 TimeBuffer<IssueStruct> issueToExecQueue; 353 354 /** Wire to read information from the issue stage time queue. */ 355 typename TimeBuffer<IssueStruct>::wire fromIssue; 356 357 /** 358 * IEW stage time buffer. Holds ROB indices of instructions that 359 * can be marked as completed. 360 */ 361 TimeBuffer<IEWStruct> *iewQueue; 362 363 /** Wire to write infromation heading to commit. */ 364 typename TimeBuffer<IEWStruct>::wire toCommit; 365 366 /** Queue of all instructions coming from rename this cycle. */ 367 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 368 369 /** Skid buffer between rename and IEW. */ 370 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 371 372 /** Scoreboard pointer. */ 373 Scoreboard* scoreboard; 374 375 private: 376 /** CPU pointer. */ 377 O3CPU *cpu; 378 379 /** Records if IEW has written to the time buffer this cycle, so that the 380 * CPU can deschedule itself if there is no activity. 381 */ 382 bool wroteToTimeBuffer; 383 384 /** Source of possible stalls. */ 385 struct Stalls { 386 bool commit; 387 }; 388 389 /** Stages that are telling IEW to stall. */ 390 Stalls stalls[Impl::MaxThreads]; 391 392 /** Debug function to print instructions that are issued this cycle. */ 393 void printAvailableInsts(); 394 395 public: 396 /** Instruction queue. */ 397 IQ instQueue; 398 399 /** Load / store queue. */ 400 LSQ ldstQueue; 401 402 /** Pointer to the functional unit pool. */ 403 FUPool *fuPool; 404 /** Records if the LSQ needs to be updated on the next cycle, so that 405 * IEW knows if there will be activity on the next cycle. 406 */ 407 bool updateLSQNextCycle; 408 409 private: 410 /** Records if there is a fetch redirect on this cycle for each thread. */ 411 bool fetchRedirect[Impl::MaxThreads]; 412 413 /** Records if the queues have been changed (inserted or issued insts), 414 * so that IEW knows to broadcast the updated amount of free entries. 415 */ 416 bool updatedQueues; 417 418 /** Commit to IEW delay. */ 419 Cycles commitToIEWDelay; 420 421 /** Rename to IEW delay. */ 422 Cycles renameToIEWDelay; 423 424 /** 425 * Issue to execute delay. What this actually represents is 426 * the amount of time it takes for an instruction to wake up, be 427 * scheduled, and sent to a FU for execution. 428 */ 429 Cycles issueToExecuteDelay; 430 431 /** Width of dispatch, in instructions. */ 432 unsigned dispatchWidth; 433 434 /** Width of issue, in instructions. */ 435 unsigned issueWidth; 436 437 /** Index into queue of instructions being written back. */ 438 unsigned wbNumInst; 439 440 /** Cycle number within the queue of instructions being written back. 441 * Used in case there are too many instructions writing back at the current 442 * cycle and writesbacks need to be scheduled for the future. See comments 443 * in instToCommit(). 444 */ 445 unsigned wbCycle; 446 447 /** Number of instructions in flight that will writeback. */ 448 449 /** Number of instructions in flight that will writeback. */ 450 int wbOutstanding; 451 452 /** Writeback width. */ 453 unsigned wbWidth; 454 455 /** Writeback width * writeback depth, where writeback depth is 456 * the number of cycles of writing back instructions that can be 457 * buffered. */ 458 unsigned wbMax; 459 460 /** Number of active threads. */ 461 ThreadID numThreads; 462 463 /** Pointer to list of active threads. */ 464 std::list<ThreadID> *activeThreads; 465 466 /** Maximum size of the skid buffer. */ 467 unsigned skidBufferMax; 468 469 /** Stat for total number of idle cycles. */ 470 Stats::Scalar iewIdleCycles; 471 /** Stat for total number of squashing cycles. */ 472 Stats::Scalar iewSquashCycles; 473 /** Stat for total number of blocking cycles. */ 474 Stats::Scalar iewBlockCycles; 475 /** Stat for total number of unblocking cycles. */ 476 Stats::Scalar iewUnblockCycles; 477 /** Stat for total number of instructions dispatched. */ 478 Stats::Scalar iewDispatchedInsts; 479 /** Stat for total number of squashed instructions dispatch skips. */ 480 Stats::Scalar iewDispSquashedInsts; 481 /** Stat for total number of dispatched load instructions. */ 482 Stats::Scalar iewDispLoadInsts; 483 /** Stat for total number of dispatched store instructions. */ 484 Stats::Scalar iewDispStoreInsts; 485 /** Stat for total number of dispatched non speculative instructions. */ 486 Stats::Scalar iewDispNonSpecInsts; 487 /** Stat for number of times the IQ becomes full. */ 488 Stats::Scalar iewIQFullEvents; 489 /** Stat for number of times the LSQ becomes full. */ 490 Stats::Scalar iewLSQFullEvents; 491 /** Stat for total number of memory ordering violation events. */ 492 Stats::Scalar memOrderViolationEvents; 493 /** Stat for total number of incorrect predicted taken branches. */ 494 Stats::Scalar predictedTakenIncorrect; 495 /** Stat for total number of incorrect predicted not taken branches. */ 496 Stats::Scalar predictedNotTakenIncorrect; 497 /** Stat for total number of mispredicted branches detected at execute. */ 498 Stats::Formula branchMispredicts; 499 500 /** Stat for total number of executed instructions. */ 501 Stats::Scalar iewExecutedInsts; 502 /** Stat for total number of executed load instructions. */ 503 Stats::Vector iewExecLoadInsts; 504 /** Stat for total number of executed store instructions. */ 505// Stats::Scalar iewExecStoreInsts; 506 /** Stat for total number of squashed instructions skipped at execute. */ 507 Stats::Scalar iewExecSquashedInsts; 508 /** Number of executed software prefetches. */ 509 Stats::Vector iewExecutedSwp; 510 /** Number of executed nops. */ 511 Stats::Vector iewExecutedNop; 512 /** Number of executed meomory references. */ 513 Stats::Vector iewExecutedRefs; 514 /** Number of executed branches. */ 515 Stats::Vector iewExecutedBranches; 516 /** Number of executed store instructions. */ 517 Stats::Formula iewExecStoreInsts; 518 /** Number of instructions executed per cycle. */ 519 Stats::Formula iewExecRate; 520 521 /** Number of instructions sent to commit. */ 522 Stats::Vector iewInstsToCommit; 523 /** Number of instructions that writeback. */ 524 Stats::Vector writebackCount; 525 /** Number of instructions that wake consumers. */ 526 Stats::Vector producerInst; 527 /** Number of instructions that wake up from producers. */ 528 Stats::Vector consumerInst; 529 /** Number of instructions that were delayed in writing back due 530 * to resource contention. 531 */ 532 Stats::Vector wbPenalized; 533 /** Number of instructions per cycle written back. */ 534 Stats::Formula wbRate; 535 /** Average number of woken instructions per writeback. */ 536 Stats::Formula wbFanout; 537 /** Number of instructions per cycle delayed in writing back . */ 538 Stats::Formula wbPenalizedRate; 539}; 540 541#endif // __CPU_O3_IEW_HH__ 542