iew.hh revision 9184:a1a8f137b796
1955SN/A/* 2955SN/A * Copyright (c) 2010 ARM Limited 31762SN/A * All rights reserved 4955SN/A * 5955SN/A * The license below extends only to copyright in the software and shall 6955SN/A * not be construed as granting a license to any other intellectual 7955SN/A * property including but not limited to intellectual property relating 8955SN/A * to a hardware implementation of the functionality of the software 9955SN/A * licensed hereunder. You may use the software subject to the license 10955SN/A * terms below provided that you ensure that this notice is replicated 11955SN/A * unmodified and in its entirety in all distributions of the software, 12955SN/A * modified or unmodified, in source code or in binary form. 13955SN/A * 14955SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 15955SN/A * All rights reserved. 16955SN/A * 17955SN/A * Redistribution and use in source and binary forms, with or without 18955SN/A * modification, are permitted provided that the following conditions are 19955SN/A * met: redistributions of source code must retain the above copyright 20955SN/A * notice, this list of conditions and the following disclaimer; 21955SN/A * redistributions in binary form must reproduce the above copyright 22955SN/A * notice, this list of conditions and the following disclaimer in the 23955SN/A * documentation and/or other materials provided with the distribution; 24955SN/A * neither the name of the copyright holders nor the names of its 25955SN/A * contributors may be used to endorse or promote products derived from 26955SN/A * this software without specific prior written permission. 27955SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362632Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39955SN/A * 402632Sstever@eecs.umich.edu * Authors: Kevin Lim 412632Sstever@eecs.umich.edu */ 422761Sstever@eecs.umich.edu 432632Sstever@eecs.umich.edu#ifndef __CPU_O3_IEW_HH__ 442632Sstever@eecs.umich.edu#define __CPU_O3_IEW_HH__ 452632Sstever@eecs.umich.edu 462761Sstever@eecs.umich.edu#include <queue> 472761Sstever@eecs.umich.edu#include <set> 482761Sstever@eecs.umich.edu 492632Sstever@eecs.umich.edu#include "base/statistics.hh" 502632Sstever@eecs.umich.edu#include "cpu/o3/comm.hh" 512761Sstever@eecs.umich.edu#include "cpu/o3/lsq.hh" 522761Sstever@eecs.umich.edu#include "cpu/o3/scoreboard.hh" 532761Sstever@eecs.umich.edu#include "cpu/timebuf.hh" 542761Sstever@eecs.umich.edu#include "debug/IEW.hh" 552761Sstever@eecs.umich.edu 562632Sstever@eecs.umich.edustruct DerivO3CPUParams; 572632Sstever@eecs.umich.educlass FUPool; 582632Sstever@eecs.umich.edu 592632Sstever@eecs.umich.edu/** 602632Sstever@eecs.umich.edu * DefaultIEW handles both single threaded and SMT IEW 612632Sstever@eecs.umich.edu * (issue/execute/writeback). It handles the dispatching of 622632Sstever@eecs.umich.edu * instructions to the LSQ/IQ as part of the issue stage, and has the 63955SN/A * IQ try to issue instructions each cycle. The execute latency is 64955SN/A * actually tied into the issue latency to allow the IQ to be able to 65955SN/A * do back-to-back scheduling without having to speculatively schedule 66955SN/A * instructions. This happens by having the IQ have access to the 67955SN/A * functional units, and the IQ gets the execution latencies from the 68955SN/A * FUs when it issues instructions. Instructions reach the execute 69955SN/A * stage on the last cycle of their execution, which is when the IQ 702656Sstever@eecs.umich.edu * knows to wake up any dependent instructions, allowing back to back 712656Sstever@eecs.umich.edu * scheduling. The execute portion of IEW separates memory 722656Sstever@eecs.umich.edu * instructions from non-memory instructions, either telling the LSQ 732656Sstever@eecs.umich.edu * to execute the instruction, or executing the instruction directly. 742656Sstever@eecs.umich.edu * The writeback portion of IEW completes the instructions by waking 752656Sstever@eecs.umich.edu * up any dependents, and marking the register ready on the 762656Sstever@eecs.umich.edu * scoreboard. 772653Sstever@eecs.umich.edu */ 782653Sstever@eecs.umich.edutemplate<class Impl> 792653Sstever@eecs.umich.educlass DefaultIEW 802653Sstever@eecs.umich.edu{ 812653Sstever@eecs.umich.edu private: 822653Sstever@eecs.umich.edu //Typedefs from Impl 832653Sstever@eecs.umich.edu typedef typename Impl::CPUPol CPUPol; 842653Sstever@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 852653Sstever@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 862653Sstever@eecs.umich.edu 872653Sstever@eecs.umich.edu typedef typename CPUPol::IQ IQ; 881852SN/A typedef typename CPUPol::RenameMap RenameMap; 89955SN/A typedef typename CPUPol::LSQ LSQ; 90955SN/A 91955SN/A typedef typename CPUPol::TimeStruct TimeStruct; 922632Sstever@eecs.umich.edu typedef typename CPUPol::IEWStruct IEWStruct; 932632Sstever@eecs.umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 94955SN/A typedef typename CPUPol::IssueStruct IssueStruct; 951533SN/A 962632Sstever@eecs.umich.edu public: 971533SN/A /** Overall IEW stage status. Used to determine if the CPU can 98955SN/A * deschedule itself due to a lack of activity. 99955SN/A */ 1002632Sstever@eecs.umich.edu enum Status { 1012632Sstever@eecs.umich.edu Active, 102955SN/A Inactive 103955SN/A }; 104955SN/A 105955SN/A /** Status for Issue, Execute, and Writeback stages. */ 1062632Sstever@eecs.umich.edu enum StageStatus { 107955SN/A Running, 1082632Sstever@eecs.umich.edu Blocked, 109955SN/A Idle, 110955SN/A StartSquash, 1112632Sstever@eecs.umich.edu Squashing, 1122632Sstever@eecs.umich.edu Unblocking 1132632Sstever@eecs.umich.edu }; 1142632Sstever@eecs.umich.edu 1152632Sstever@eecs.umich.edu private: 1162632Sstever@eecs.umich.edu /** Overall stage status. */ 1172632Sstever@eecs.umich.edu Status _status; 1182632Sstever@eecs.umich.edu /** Dispatch status. */ 1192632Sstever@eecs.umich.edu StageStatus dispatchStatus[Impl::MaxThreads]; 1202632Sstever@eecs.umich.edu /** Execute status. */ 1212632Sstever@eecs.umich.edu StageStatus exeStatus; 1223053Sstever@eecs.umich.edu /** Writeback status. */ 1233053Sstever@eecs.umich.edu StageStatus wbStatus; 1243053Sstever@eecs.umich.edu 1253053Sstever@eecs.umich.edu public: 1263053Sstever@eecs.umich.edu /** Constructs a DefaultIEW with the given parameters. */ 1273053Sstever@eecs.umich.edu DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 1283053Sstever@eecs.umich.edu 1293053Sstever@eecs.umich.edu /** Returns the name of the DefaultIEW stage. */ 1303053Sstever@eecs.umich.edu std::string name() const; 1313053Sstever@eecs.umich.edu 1323053Sstever@eecs.umich.edu /** Registers statistics. */ 1333053Sstever@eecs.umich.edu void regStats(); 1343053Sstever@eecs.umich.edu 1353053Sstever@eecs.umich.edu /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 1363053Sstever@eecs.umich.edu void initStage(); 1373053Sstever@eecs.umich.edu 1382632Sstever@eecs.umich.edu /** Sets main time buffer used for backwards communication. */ 1392632Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1402632Sstever@eecs.umich.edu 1412632Sstever@eecs.umich.edu /** Sets time buffer for getting instructions coming from rename. */ 1422632Sstever@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1432632Sstever@eecs.umich.edu 1442634Sstever@eecs.umich.edu /** Sets time buffer to pass on instructions to commit. */ 1452634Sstever@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1462632Sstever@eecs.umich.edu 1472638Sstever@eecs.umich.edu /** Sets pointer to list of active threads. */ 1482632Sstever@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 1492632Sstever@eecs.umich.edu 1502632Sstever@eecs.umich.edu /** Sets pointer to the scoreboard. */ 1512632Sstever@eecs.umich.edu void setScoreboard(Scoreboard *sb_ptr); 1522632Sstever@eecs.umich.edu 1532632Sstever@eecs.umich.edu /** Drains IEW stage. */ 1541858SN/A bool drain(); 1552638Sstever@eecs.umich.edu 1562638Sstever@eecs.umich.edu /** Resumes execution after a drain. */ 1572638Sstever@eecs.umich.edu void resume(); 1582638Sstever@eecs.umich.edu 1592638Sstever@eecs.umich.edu /** Completes switch out of IEW stage. */ 1602638Sstever@eecs.umich.edu void switchOut(); 1612638Sstever@eecs.umich.edu 1622638Sstever@eecs.umich.edu /** Takes over from another CPU's thread. */ 1632634Sstever@eecs.umich.edu void takeOverFrom(); 1642634Sstever@eecs.umich.edu 1652634Sstever@eecs.umich.edu /** Returns if IEW is switched out. */ 166955SN/A bool isSwitchedOut() { return switchedOut; } 167955SN/A 168955SN/A /** Squashes instructions in IEW for a specific thread. */ 169955SN/A void squash(ThreadID tid); 170955SN/A 171955SN/A /** Wakes all dependents of a completed instruction. */ 172955SN/A void wakeDependents(DynInstPtr &inst); 173955SN/A 1741858SN/A /** Tells memory dependence unit that a memory instruction needs to be 1751858SN/A * rescheduled. It will re-execute once replayMemInst() is called. 1762632Sstever@eecs.umich.edu */ 177955SN/A void rescheduleMemInst(DynInstPtr &inst); 1782776Sstever@eecs.umich.edu 1791105SN/A /** Re-executes all rescheduled memory instructions. */ 1802667Sstever@eecs.umich.edu void replayMemInst(DynInstPtr &inst); 1812667Sstever@eecs.umich.edu 1822667Sstever@eecs.umich.edu /** Sends an instruction to commit through the time buffer. */ 1832667Sstever@eecs.umich.edu void instToCommit(DynInstPtr &inst); 1842667Sstever@eecs.umich.edu 1852667Sstever@eecs.umich.edu /** Inserts unused instructions of a thread into the skid buffer. */ 1861869SN/A void skidInsert(ThreadID tid); 1871869SN/A 1881869SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 1891869SN/A int skidCount(); 1901869SN/A 1911065SN/A /** Returns if all of the skid buffers are empty. */ 1922632Sstever@eecs.umich.edu bool skidsEmpty(); 1932632Sstever@eecs.umich.edu 194955SN/A /** Updates overall IEW status based on all of the stages' statuses. */ 1951858SN/A void updateStatus(); 1961858SN/A 1971858SN/A /** Resets entries of the IQ and the LSQ. */ 1981858SN/A void resetEntries(); 1991851SN/A 2001851SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 2011858SN/A * activity. Used mainly by the LdWritebackEvent. 2022632Sstever@eecs.umich.edu */ 203955SN/A void wakeCPU(); 2042656Sstever@eecs.umich.edu 2052656Sstever@eecs.umich.edu /** Reports to the CPU that there is activity this cycle. */ 2062656Sstever@eecs.umich.edu void activityThisCycle(); 2072656Sstever@eecs.umich.edu 2082656Sstever@eecs.umich.edu /** Tells CPU that the IEW stage is active and running. */ 2092656Sstever@eecs.umich.edu inline void activateStage(); 2102656Sstever@eecs.umich.edu 2112656Sstever@eecs.umich.edu /** Tells CPU that the IEW stage is inactive and idle. */ 2122656Sstever@eecs.umich.edu inline void deactivateStage(); 2132656Sstever@eecs.umich.edu 2142656Sstever@eecs.umich.edu /** Returns if the LSQ has any stores to writeback. */ 2152656Sstever@eecs.umich.edu bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2162656Sstever@eecs.umich.edu 2172656Sstever@eecs.umich.edu /** Returns if the LSQ has any stores to writeback. */ 2182656Sstever@eecs.umich.edu bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2192656Sstever@eecs.umich.edu 2202655Sstever@eecs.umich.edu void incrWb(InstSeqNum &sn) 2213053Sstever@eecs.umich.edu { 2223053Sstever@eecs.umich.edu if (++wbOutstanding == wbMax) 2233053Sstever@eecs.umich.edu ableToIssue = false; 2243053Sstever@eecs.umich.edu DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 2253053Sstever@eecs.umich.edu assert(wbOutstanding <= wbMax); 2263053Sstever@eecs.umich.edu#ifdef DEBUG 2273053Sstever@eecs.umich.edu wbList.insert(sn); 2283053Sstever@eecs.umich.edu#endif 2293053Sstever@eecs.umich.edu } 2303053Sstever@eecs.umich.edu 2313053Sstever@eecs.umich.edu void decrWb(InstSeqNum &sn) 2323053Sstever@eecs.umich.edu { 2333053Sstever@eecs.umich.edu if (wbOutstanding-- == wbMax) 2343053Sstever@eecs.umich.edu ableToIssue = true; 2353053Sstever@eecs.umich.edu DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 2363053Sstever@eecs.umich.edu assert(wbOutstanding >= 0); 2373053Sstever@eecs.umich.edu#ifdef DEBUG 2383053Sstever@eecs.umich.edu assert(wbList.find(sn) != wbList.end()); 2393053Sstever@eecs.umich.edu wbList.erase(sn); 2402667Sstever@eecs.umich.edu#endif 2412667Sstever@eecs.umich.edu } 2422667Sstever@eecs.umich.edu 2432667Sstever@eecs.umich.edu#ifdef DEBUG 2442667Sstever@eecs.umich.edu std::set<InstSeqNum> wbList; 2452667Sstever@eecs.umich.edu 2462667Sstever@eecs.umich.edu void dumpWb() 2472667Sstever@eecs.umich.edu { 2482667Sstever@eecs.umich.edu std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 2492667Sstever@eecs.umich.edu while (wb_it != wbList.end()) { 2502667Sstever@eecs.umich.edu cprintf("[sn:%lli]\n", 2512667Sstever@eecs.umich.edu (*wb_it)); 2522638Sstever@eecs.umich.edu wb_it++; 2532638Sstever@eecs.umich.edu } 2542638Sstever@eecs.umich.edu } 2552638Sstever@eecs.umich.edu#endif 2562638Sstever@eecs.umich.edu 2571858SN/A bool canIssue() { return ableToIssue; } 2583053Sstever@eecs.umich.edu 2593053Sstever@eecs.umich.edu bool ableToIssue; 2603053Sstever@eecs.umich.edu 2613053Sstever@eecs.umich.edu /** Check misprediction */ 2623053Sstever@eecs.umich.edu void checkMisprediction(DynInstPtr &inst); 2633053Sstever@eecs.umich.edu 2643053Sstever@eecs.umich.edu private: 2653053Sstever@eecs.umich.edu /** Sends commit proper information for a squash due to a branch 2661858SN/A * mispredict. 2671858SN/A */ 2681858SN/A void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 2691858SN/A 2701858SN/A /** Sends commit proper information for a squash due to a memory order 2711858SN/A * violation. 2721859SN/A */ 2731858SN/A void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 2741858SN/A 2751858SN/A /** Sends commit proper information for a squash due to memory becoming 2761859SN/A * blocked (younger issued instructions must be retried). 2771859SN/A */ 2781862SN/A void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 2793053Sstever@eecs.umich.edu 2803053Sstever@eecs.umich.edu /** Sets Dispatch to blocked, and signals back to other stages to block. */ 2813053Sstever@eecs.umich.edu void block(ThreadID tid); 2823053Sstever@eecs.umich.edu 2831859SN/A /** Unblocks Dispatch if the skid buffer is empty, and signals back to 2841859SN/A * other stages to unblock. 2851859SN/A */ 2861859SN/A void unblock(ThreadID tid); 2871859SN/A 2881859SN/A /** Determines proper actions to take given Dispatch's status. */ 2891859SN/A void dispatch(ThreadID tid); 2901859SN/A 2911862SN/A /** Dispatches instructions to IQ and LSQ. */ 2921859SN/A void dispatchInsts(ThreadID tid); 2931859SN/A 2941859SN/A /** Executes instructions. In the case of memory operations, it informs the 2951858SN/A * LSQ to execute the instructions. Also handles any redirects that occur 2961858SN/A * due to the executed instructions. 2972139SN/A */ 2982139SN/A void executeInsts(); 2992139SN/A 3002155SN/A /** Writebacks instructions. In our model, the instruction's execute() 3012623SN/A * function atomically reads registers, executes, and writes registers. 3022817Sksewell@umich.edu * Thus this writeback only wakes up dependent instructions, and informs 3032792Sktlim@umich.edu * the scoreboard of registers becoming ready. 3042155SN/A */ 3051869SN/A void writebackInsts(); 3061869SN/A 3071869SN/A /** Returns the number of valid, non-squashed instructions coming from 3081869SN/A * rename to dispatch. 3091869SN/A */ 3102139SN/A unsigned validInstsFromRename(); 3111869SN/A 3122508SN/A /** Reads the stall signals. */ 3132508SN/A void readStallSignals(ThreadID tid); 3142508SN/A 3152508SN/A /** Checks if any of the stall conditions are currently true. */ 3162635Sstever@eecs.umich.edu bool checkStall(ThreadID tid); 3172635Sstever@eecs.umich.edu 3181869SN/A /** Processes inputs and changes state accordingly. */ 3191869SN/A void checkSignalsAndUpdate(ThreadID tid); 3201869SN/A 3211869SN/A /** Removes instructions from rename from a thread's instruction list. */ 3221869SN/A void emptyRenameInsts(ThreadID tid); 3231869SN/A 3241869SN/A /** Sorts instructions coming from rename into lists separated by thread. */ 3251869SN/A void sortInsts(); 3261965SN/A 3271965SN/A public: 3281965SN/A /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 3291869SN/A * Writeback to run for one cycle. 3301869SN/A */ 3312733Sktlim@umich.edu void tick(); 3321869SN/A 3331884SN/A private: 3341884SN/A /** Updates execution stats based on the instruction. */ 3351884SN/A void updateExeInstStats(DynInstPtr &inst); 3361869SN/A 3371858SN/A /** Pointer to main time buffer used for backwards communication. */ 3381869SN/A TimeBuffer<TimeStruct> *timeBuffer; 3391869SN/A 3401869SN/A /** Wire to write information heading to previous stages. */ 3411869SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 3421869SN/A 3431858SN/A /** Wire to get commit's output from backwards time buffer. */ 3442761Sstever@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire fromCommit; 3451869SN/A 3462733Sktlim@umich.edu /** Wire to write information heading to previous stages. */ 3472733Sktlim@umich.edu typename TimeBuffer<TimeStruct>::wire toRename; 3481869SN/A 3491869SN/A /** Rename instruction queue interface. */ 3501869SN/A TimeBuffer<RenameStruct> *renameQueue; 3511869SN/A 3521869SN/A /** Wire to get rename's output from rename queue. */ 3531869SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3541858SN/A 355955SN/A /** Issue stage queue. */ 356955SN/A TimeBuffer<IssueStruct> issueToExecQueue; 3571869SN/A 3581869SN/A /** Wire to read information from the issue stage time queue. */ 3591869SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 3601869SN/A 3611869SN/A /** 3621869SN/A * IEW stage time buffer. Holds ROB indices of instructions that 3631869SN/A * can be marked as completed. 3641869SN/A */ 3651869SN/A TimeBuffer<IEWStruct> *iewQueue; 3661869SN/A 3671869SN/A /** Wire to write infromation heading to commit. */ 3681869SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 3691869SN/A 3701869SN/A /** Queue of all instructions coming from rename this cycle. */ 3711869SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3721869SN/A 3731869SN/A /** Skid buffer between rename and IEW. */ 3741869SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 3751869SN/A 3761869SN/A /** Scoreboard pointer. */ 3771869SN/A Scoreboard* scoreboard; 3781869SN/A 3791869SN/A private: 3801869SN/A /** CPU pointer. */ 3811869SN/A O3CPU *cpu; 3821869SN/A 3831869SN/A /** Records if IEW has written to the time buffer this cycle, so that the 3841869SN/A * CPU can deschedule itself if there is no activity. 3851869SN/A */ 3861869SN/A bool wroteToTimeBuffer; 3871869SN/A 3881869SN/A /** Source of possible stalls. */ 3891869SN/A struct Stalls { 3901869SN/A bool commit; 3911869SN/A }; 3921869SN/A 3931869SN/A /** Stages that are telling IEW to stall. */ 3941869SN/A Stalls stalls[Impl::MaxThreads]; 3951869SN/A 3962655Sstever@eecs.umich.edu /** Debug function to print instructions that are issued this cycle. */ 3972655Sstever@eecs.umich.edu void printAvailableInsts(); 3982655Sstever@eecs.umich.edu 3992655Sstever@eecs.umich.edu public: 4002655Sstever@eecs.umich.edu /** Instruction queue. */ 4012655Sstever@eecs.umich.edu IQ instQueue; 4022655Sstever@eecs.umich.edu 4032655Sstever@eecs.umich.edu /** Load / store queue. */ 4042655Sstever@eecs.umich.edu LSQ ldstQueue; 4052655Sstever@eecs.umich.edu 4062655Sstever@eecs.umich.edu /** Pointer to the functional unit pool. */ 4072655Sstever@eecs.umich.edu FUPool *fuPool; 4082655Sstever@eecs.umich.edu /** Records if the LSQ needs to be updated on the next cycle, so that 4092655Sstever@eecs.umich.edu * IEW knows if there will be activity on the next cycle. 4102655Sstever@eecs.umich.edu */ 4112655Sstever@eecs.umich.edu bool updateLSQNextCycle; 4122655Sstever@eecs.umich.edu 4132655Sstever@eecs.umich.edu private: 4142655Sstever@eecs.umich.edu /** Records if there is a fetch redirect on this cycle for each thread. */ 4152655Sstever@eecs.umich.edu bool fetchRedirect[Impl::MaxThreads]; 4162655Sstever@eecs.umich.edu 4172655Sstever@eecs.umich.edu /** Records if the queues have been changed (inserted or issued insts), 4182655Sstever@eecs.umich.edu * so that IEW knows to broadcast the updated amount of free entries. 4192655Sstever@eecs.umich.edu */ 4202655Sstever@eecs.umich.edu bool updatedQueues; 4212655Sstever@eecs.umich.edu 4222634Sstever@eecs.umich.edu /** Commit to IEW delay. */ 4232634Sstever@eecs.umich.edu Cycles commitToIEWDelay; 4242634Sstever@eecs.umich.edu 4252634Sstever@eecs.umich.edu /** Rename to IEW delay. */ 4262634Sstever@eecs.umich.edu Cycles renameToIEWDelay; 4272634Sstever@eecs.umich.edu 4282638Sstever@eecs.umich.edu /** 4292638Sstever@eecs.umich.edu * Issue to execute delay. What this actually represents is 4302638Sstever@eecs.umich.edu * the amount of time it takes for an instruction to wake up, be 4312638Sstever@eecs.umich.edu * scheduled, and sent to a FU for execution. 4322638Sstever@eecs.umich.edu */ 4331869SN/A Cycles issueToExecuteDelay; 4341869SN/A 435955SN/A /** Width of dispatch, in instructions. */ 436955SN/A unsigned dispatchWidth; 437955SN/A 438955SN/A /** Width of issue, in instructions. */ 4391858SN/A unsigned issueWidth; 4401858SN/A 4411858SN/A /** Index into queue of instructions being written back. */ 4422632Sstever@eecs.umich.edu unsigned wbNumInst; 4432632Sstever@eecs.umich.edu 4442632Sstever@eecs.umich.edu /** Cycle number within the queue of instructions being written back. 4452632Sstever@eecs.umich.edu * Used in case there are too many instructions writing back at the current 4462632Sstever@eecs.umich.edu * cycle and writesbacks need to be scheduled for the future. See comments 4472634Sstever@eecs.umich.edu * in instToCommit(). 4482638Sstever@eecs.umich.edu */ 4492023SN/A unsigned wbCycle; 4502632Sstever@eecs.umich.edu 4512632Sstever@eecs.umich.edu /** Number of instructions in flight that will writeback. */ 4522632Sstever@eecs.umich.edu 4532632Sstever@eecs.umich.edu /** Number of instructions in flight that will writeback. */ 4542632Sstever@eecs.umich.edu int wbOutstanding; 4552632Sstever@eecs.umich.edu 4562632Sstever@eecs.umich.edu /** Writeback width. */ 4572632Sstever@eecs.umich.edu unsigned wbWidth; 4582632Sstever@eecs.umich.edu 4592632Sstever@eecs.umich.edu /** Writeback width * writeback depth, where writeback depth is 4602632Sstever@eecs.umich.edu * the number of cycles of writing back instructions that can be 4612023SN/A * buffered. */ 4622632Sstever@eecs.umich.edu unsigned wbMax; 4632632Sstever@eecs.umich.edu 4641889SN/A /** Number of active threads. */ 4651889SN/A ThreadID numThreads; 4662632Sstever@eecs.umich.edu 4672632Sstever@eecs.umich.edu /** Pointer to list of active threads. */ 4682632Sstever@eecs.umich.edu std::list<ThreadID> *activeThreads; 4692632Sstever@eecs.umich.edu 4702632Sstever@eecs.umich.edu /** Maximum size of the skid buffer. */ 4712632Sstever@eecs.umich.edu unsigned skidBufferMax; 4722632Sstever@eecs.umich.edu 4732632Sstever@eecs.umich.edu /** Is this stage switched out. */ 4742632Sstever@eecs.umich.edu bool switchedOut; 4752632Sstever@eecs.umich.edu 4762632Sstever@eecs.umich.edu /** Stat for total number of idle cycles. */ 4772632Sstever@eecs.umich.edu Stats::Scalar iewIdleCycles; 4782632Sstever@eecs.umich.edu /** Stat for total number of squashing cycles. */ 4792632Sstever@eecs.umich.edu Stats::Scalar iewSquashCycles; 4801888SN/A /** Stat for total number of blocking cycles. */ 4811888SN/A Stats::Scalar iewBlockCycles; 4821869SN/A /** Stat for total number of unblocking cycles. */ 4831869SN/A Stats::Scalar iewUnblockCycles; 4841858SN/A /** Stat for total number of instructions dispatched. */ 4852598SN/A Stats::Scalar iewDispatchedInsts; 4862598SN/A /** Stat for total number of squashed instructions dispatch skips. */ 4872598SN/A Stats::Scalar iewDispSquashedInsts; 4882598SN/A /** Stat for total number of dispatched load instructions. */ 4892598SN/A Stats::Scalar iewDispLoadInsts; 4901858SN/A /** Stat for total number of dispatched store instructions. */ 4911858SN/A Stats::Scalar iewDispStoreInsts; 4921858SN/A /** Stat for total number of dispatched non speculative instructions. */ 4931858SN/A Stats::Scalar iewDispNonSpecInsts; 4941858SN/A /** Stat for number of times the IQ becomes full. */ 4951858SN/A Stats::Scalar iewIQFullEvents; 4961858SN/A /** Stat for number of times the LSQ becomes full. */ 4971858SN/A Stats::Scalar iewLSQFullEvents; 4981858SN/A /** Stat for total number of memory ordering violation events. */ 4991871SN/A Stats::Scalar memOrderViolationEvents; 5001858SN/A /** Stat for total number of incorrect predicted taken branches. */ 5011858SN/A Stats::Scalar predictedTakenIncorrect; 5021858SN/A /** Stat for total number of incorrect predicted not taken branches. */ 5031858SN/A Stats::Scalar predictedNotTakenIncorrect; 5041858SN/A /** Stat for total number of mispredicted branches detected at execute. */ 5051858SN/A Stats::Formula branchMispredicts; 5061858SN/A 5071858SN/A /** Stat for total number of executed instructions. */ 5081858SN/A Stats::Scalar iewExecutedInsts; 5091858SN/A /** Stat for total number of executed load instructions. */ 5101858SN/A Stats::Vector iewExecLoadInsts; 5111859SN/A /** Stat for total number of executed store instructions. */ 5121859SN/A// Stats::Scalar iewExecStoreInsts; 5131869SN/A /** Stat for total number of squashed instructions skipped at execute. */ 5141888SN/A Stats::Scalar iewExecSquashedInsts; 5152632Sstever@eecs.umich.edu /** Number of executed software prefetches. */ 5161869SN/A Stats::Vector iewExecutedSwp; 5171884SN/A /** Number of executed nops. */ 5181884SN/A Stats::Vector iewExecutedNop; 5191884SN/A /** Number of executed meomory references. */ 5201884SN/A Stats::Vector iewExecutedRefs; 5211884SN/A /** Number of executed branches. */ 5221884SN/A Stats::Vector iewExecutedBranches; 5231965SN/A /** Number of executed store instructions. */ 5241965SN/A Stats::Formula iewExecStoreInsts; 5251965SN/A /** Number of instructions executed per cycle. */ 5262761Sstever@eecs.umich.edu Stats::Formula iewExecRate; 5271869SN/A 5281869SN/A /** Number of instructions sent to commit. */ 5292632Sstever@eecs.umich.edu Stats::Vector iewInstsToCommit; 5302667Sstever@eecs.umich.edu /** Number of instructions that writeback. */ 5311869SN/A Stats::Vector writebackCount; 5321869SN/A /** Number of instructions that wake consumers. */ 5332929Sktlim@umich.edu Stats::Vector producerInst; 5342929Sktlim@umich.edu /** Number of instructions that wake up from producers. */ 5353036Sstever@eecs.umich.edu Stats::Vector consumerInst; 5362929Sktlim@umich.edu /** Number of instructions that were delayed in writing back due 537955SN/A * to resource contention. 5382598SN/A */ 5392598SN/A Stats::Vector wbPenalized; 540955SN/A /** Number of instructions per cycle written back. */ 541955SN/A Stats::Formula wbRate; 542955SN/A /** Average number of woken instructions per writeback. */ 5431530SN/A Stats::Formula wbFanout; 544955SN/A /** Number of instructions per cycle delayed in writing back . */ 545955SN/A Stats::Formula wbPenalizedRate; 546955SN/A}; 547 548#endif // __CPU_O3_IEW_HH__ 549