iew.hh revision 7813:7338bc628489
12SN/A/* 21762SN/A * Copyright (c) 2010 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331110SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 358229Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368229Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372680Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 388229Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392800Ssaidi@eecs.umich.edu * 408780Sgblack@eecs.umich.edu * Authors: Kevin Lim 412SN/A */ 425569Snate@binkert.org 432167SN/A#ifndef __CPU_O3_IEW_HH__ 442203SN/A#define __CPU_O3_IEW_HH__ 452203SN/A 462222SN/A#include <queue> 472166SN/A 482203SN/A#include "base/statistics.hh" 492203SN/A#include "cpu/timebuf.hh" 502222SN/A#include "config/full_system.hh" 512166SN/A#include "cpu/o3/comm.hh" 522147SN/A#include "cpu/o3/scoreboard.hh" 532147SN/A#include "cpu/o3/lsq.hh" 542222SN/A 552147SN/Aclass DerivO3CPUParams; 562147SN/Aclass FUPool; 572147SN/A 582222SN/A/** 592147SN/A * DefaultIEW handles both single threaded and SMT IEW 602147SN/A * (issue/execute/writeback). It handles the dispatching of 612147SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the 622222SN/A * IQ try to issue instructions each cycle. The execute latency is 632147SN/A * actually tied into the issue latency to allow the IQ to be able to 642147SN/A * do back-to-back scheduling without having to speculatively schedule 652147SN/A * instructions. This happens by having the IQ have access to the 662222SN/A * functional units, and the IQ gets the execution latencies from the 672147SN/A * FUs when it issues instructions. Instructions reach the execute 682147SN/A * stage on the last cycle of their execution, which is when the IQ 692147SN/A * knows to wake up any dependent instructions, allowing back to back 702222SN/A * scheduling. The execute portion of IEW separates memory 712147SN/A * instructions from non-memory instructions, either telling the LSQ 728405Sksewell@umich.edu * to execute the instruction, or executing the instruction directly. 732147SN/A * The writeback portion of IEW completes the instructions by waking 742222SN/A * up any dependents, and marking the register ready on the 752147SN/A * scoreboard. 768405Sksewell@umich.edu */ 772147SN/Atemplate<class Impl> 782222SN/Aclass DefaultIEW 792147SN/A{ 802289SN/A private: 812289SN/A //Typedefs from Impl 822289SN/A typedef typename Impl::CPUPol CPUPol; 832289SN/A typedef typename Impl::DynInstPtr DynInstPtr; 842147SN/A typedef typename Impl::O3CPU O3CPU; 852147SN/A 862222SN/A typedef typename CPUPol::IQ IQ; 872147SN/A typedef typename CPUPol::RenameMap RenameMap; 882147SN/A typedef typename CPUPol::LSQ LSQ; 892147SN/A 902222SN/A typedef typename CPUPol::TimeStruct TimeStruct; 912147SN/A typedef typename CPUPol::IEWStruct IEWStruct; 922147SN/A typedef typename CPUPol::RenameStruct RenameStruct; 932147SN/A typedef typename CPUPol::IssueStruct IssueStruct; 942222SN/A 952147SN/A friend class Impl::O3CPU; 962147SN/A friend class CPUPol::IQ; 972147SN/A 982222SN/A public: 992147SN/A /** Overall IEW stage status. Used to determine if the CPU can 1002147SN/A * deschedule itself due to a lack of activity. 1012147SN/A */ 1022222SN/A enum Status { 1032147SN/A Active, 1042147SN/A Inactive 1052147SN/A }; 1062222SN/A 1072147SN/A /** Status for Issue, Execute, and Writeback stages. */ 1085569Snate@binkert.org enum StageStatus { 10910417Sandreas.hansson@arm.com Running, 1102174SN/A Blocked, 1112680Sktlim@umich.edu Idle, 1128780Sgblack@eecs.umich.edu StartSquash, 1138780Sgblack@eecs.umich.edu Squashing, 1142222SN/A Unblocking 1152174SN/A }; 1167720Sgblack@eecs.umich.edu 1177720Sgblack@eecs.umich.edu private: 1182196SN/A /** Overall stage status. */ 1197720Sgblack@eecs.umich.edu Status _status; 1207720Sgblack@eecs.umich.edu /** Dispatch status. */ 1212196SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 1222201SN/A /** Execute status. */ 1232196SN/A StageStatus exeStatus; 1245568Snate@binkert.org /** Writeback status. */ 1255568Snate@binkert.org StageStatus wbStatus; 1262196SN/A 1272196SN/A public: 1287720Sgblack@eecs.umich.edu /** Constructs a DefaultIEW with the given parameters. */ 1297720Sgblack@eecs.umich.edu DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 1302174SN/A 1312174SN/A /** Returns the name of the DefaultIEW stage. */ 1325569Snate@binkert.org std::string name() const; 13310417Sandreas.hansson@arm.com 1342201SN/A /** Registers statistics. */ 1352680Sktlim@umich.edu void regStats(); 1368780Sgblack@eecs.umich.edu 1378780Sgblack@eecs.umich.edu /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 1382201SN/A void initStage(); 1392201SN/A 1402201SN/A /** Returns the dcache port. */ 1415569Snate@binkert.org Port *getDcachePort() { return ldstQueue.getDcachePort(); } 14210417Sandreas.hansson@arm.com 1432289SN/A /** Sets main time buffer used for backwards communication. */ 1448780Sgblack@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1458780Sgblack@eecs.umich.edu 1468780Sgblack@eecs.umich.edu /** Sets time buffer for getting instructions coming from rename. */ 1478780Sgblack@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1488780Sgblack@eecs.umich.edu 1498780Sgblack@eecs.umich.edu /** Sets time buffer to pass on instructions to commit. */ 15010823SAndreas.Sandberg@ARM.com void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1518780Sgblack@eecs.umich.edu 1528780Sgblack@eecs.umich.edu /** Sets pointer to list of active threads. */ 1532289SN/A void setActiveThreads(std::list<ThreadID> *at_ptr); 1548780Sgblack@eecs.umich.edu 1558780Sgblack@eecs.umich.edu /** Sets pointer to the scoreboard. */ 1568780Sgblack@eecs.umich.edu void setScoreboard(Scoreboard *sb_ptr); 1578780Sgblack@eecs.umich.edu 1588780Sgblack@eecs.umich.edu /** Drains IEW stage. */ 1598780Sgblack@eecs.umich.edu bool drain(); 1602289SN/A 1618780Sgblack@eecs.umich.edu /** Resumes execution after a drain. */ 1628780Sgblack@eecs.umich.edu void resume(); 1638780Sgblack@eecs.umich.edu 1648780Sgblack@eecs.umich.edu /** Completes switch out of IEW stage. */ 1652289SN/A void switchOut(); 1662289SN/A 1672680Sktlim@umich.edu /** Takes over from another CPU's thread. */ 1682289SN/A void takeOverFrom(); 1692289SN/A 1705569Snate@binkert.org /** Returns if IEW is switched out. */ 17110417Sandreas.hansson@arm.com bool isSwitchedOut() { return switchedOut; } 1722289SN/A 1738780Sgblack@eecs.umich.edu /** Squashes instructions in IEW for a specific thread. */ 17410664SAli.Saidi@ARM.com void squash(ThreadID tid); 17510664SAli.Saidi@ARM.com 17610664SAli.Saidi@ARM.com /** Wakes all dependents of a completed instruction. */ 1772289SN/A void wakeDependents(DynInstPtr &inst); 1782289SN/A 1792680Sktlim@umich.edu /** Tells memory dependence unit that a memory instruction needs to be 1802289SN/A * rescheduled. It will re-execute once replayMemInst() is called. 1812289SN/A */ 1825569Snate@binkert.org void rescheduleMemInst(DynInstPtr &inst); 18310417Sandreas.hansson@arm.com 1844997Sgblack@eecs.umich.edu /** Re-executes all rescheduled memory instructions. */ 1858780Sgblack@eecs.umich.edu void replayMemInst(DynInstPtr &inst); 1868780Sgblack@eecs.umich.edu 1878806Sgblack@eecs.umich.edu /** Sends an instruction to commit through the time buffer. */ 1888806Sgblack@eecs.umich.edu void instToCommit(DynInstPtr &inst); 1898806Sgblack@eecs.umich.edu 1908806Sgblack@eecs.umich.edu /** Inserts unused instructions of a thread into the skid buffer. */ 1918806Sgblack@eecs.umich.edu void skidInsert(ThreadID tid); 1928806Sgblack@eecs.umich.edu 1938806Sgblack@eecs.umich.edu /** Returns the max of the number of entries in all of the skid buffers. */ 1948806Sgblack@eecs.umich.edu int skidCount(); 1954997Sgblack@eecs.umich.edu 1968806Sgblack@eecs.umich.edu /** Returns if all of the skid buffers are empty. */ 1978806Sgblack@eecs.umich.edu bool skidsEmpty(); 1984997Sgblack@eecs.umich.edu 1994997Sgblack@eecs.umich.edu /** Updates overall IEW status based on all of the stages' statuses. */ 2004997Sgblack@eecs.umich.edu void updateStatus(); 2015569Snate@binkert.org 20210417Sandreas.hansson@arm.com /** Resets entries of the IQ and the LSQ. */ 2034997Sgblack@eecs.umich.edu void resetEntries(); 2048780Sgblack@eecs.umich.edu 2058780Sgblack@eecs.umich.edu /** Tells the CPU to wakeup if it has descheduled itself due to no 2068806Sgblack@eecs.umich.edu * activity. Used mainly by the LdWritebackEvent. 2078806Sgblack@eecs.umich.edu */ 2088806Sgblack@eecs.umich.edu void wakeCPU(); 2098806Sgblack@eecs.umich.edu 2108806Sgblack@eecs.umich.edu /** Reports to the CPU that there is activity this cycle. */ 2118806Sgblack@eecs.umich.edu void activityThisCycle(); 2128806Sgblack@eecs.umich.edu 2138806Sgblack@eecs.umich.edu /** Tells CPU that the IEW stage is active and running. */ 2148806Sgblack@eecs.umich.edu inline void activateStage(); 2158806Sgblack@eecs.umich.edu 2168806Sgblack@eecs.umich.edu /** Tells CPU that the IEW stage is inactive and idle. */ 2178806Sgblack@eecs.umich.edu inline void deactivateStage(); 2184997Sgblack@eecs.umich.edu 2198806Sgblack@eecs.umich.edu /** Returns if the LSQ has any stores to writeback. */ 2204997Sgblack@eecs.umich.edu bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2214997Sgblack@eecs.umich.edu 2224997Sgblack@eecs.umich.edu /** Returns if the LSQ has any stores to writeback. */ 2232167SN/A bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2242167SN/A 225 void incrWb(InstSeqNum &sn) 226 { 227 if (++wbOutstanding == wbMax) 228 ableToIssue = false; 229 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 230 assert(wbOutstanding <= wbMax); 231#ifdef DEBUG 232 wbList.insert(sn); 233#endif 234 } 235 236 void decrWb(InstSeqNum &sn) 237 { 238 if (wbOutstanding-- == wbMax) 239 ableToIssue = true; 240 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 241 assert(wbOutstanding >= 0); 242#ifdef DEBUG 243 assert(wbList.find(sn) != wbList.end()); 244 wbList.erase(sn); 245#endif 246 } 247 248#ifdef DEBUG 249 std::set<InstSeqNum> wbList; 250 251 void dumpWb() 252 { 253 std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 254 while (wb_it != wbList.end()) { 255 cprintf("[sn:%lli]\n", 256 (*wb_it)); 257 wb_it++; 258 } 259 } 260#endif 261 262 bool canIssue() { return ableToIssue; } 263 264 bool ableToIssue; 265 266 /** Check misprediction */ 267 void checkMisprediction(DynInstPtr &inst); 268 269 private: 270 /** Sends commit proper information for a squash due to a branch 271 * mispredict. 272 */ 273 void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 274 275 /** Sends commit proper information for a squash due to a memory order 276 * violation. 277 */ 278 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 279 280 /** Sends commit proper information for a squash due to memory becoming 281 * blocked (younger issued instructions must be retried). 282 */ 283 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 284 285 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 286 void block(ThreadID tid); 287 288 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 289 * other stages to unblock. 290 */ 291 void unblock(ThreadID tid); 292 293 /** Determines proper actions to take given Dispatch's status. */ 294 void dispatch(ThreadID tid); 295 296 /** Dispatches instructions to IQ and LSQ. */ 297 void dispatchInsts(ThreadID tid); 298 299 /** Executes instructions. In the case of memory operations, it informs the 300 * LSQ to execute the instructions. Also handles any redirects that occur 301 * due to the executed instructions. 302 */ 303 void executeInsts(); 304 305 /** Writebacks instructions. In our model, the instruction's execute() 306 * function atomically reads registers, executes, and writes registers. 307 * Thus this writeback only wakes up dependent instructions, and informs 308 * the scoreboard of registers becoming ready. 309 */ 310 void writebackInsts(); 311 312 /** Returns the number of valid, non-squashed instructions coming from 313 * rename to dispatch. 314 */ 315 unsigned validInstsFromRename(); 316 317 /** Reads the stall signals. */ 318 void readStallSignals(ThreadID tid); 319 320 /** Checks if any of the stall conditions are currently true. */ 321 bool checkStall(ThreadID tid); 322 323 /** Processes inputs and changes state accordingly. */ 324 void checkSignalsAndUpdate(ThreadID tid); 325 326 /** Removes instructions from rename from a thread's instruction list. */ 327 void emptyRenameInsts(ThreadID tid); 328 329 /** Sorts instructions coming from rename into lists separated by thread. */ 330 void sortInsts(); 331 332 public: 333 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 334 * Writeback to run for one cycle. 335 */ 336 void tick(); 337 338 private: 339 /** Updates execution stats based on the instruction. */ 340 void updateExeInstStats(DynInstPtr &inst); 341 342 /** Pointer to main time buffer used for backwards communication. */ 343 TimeBuffer<TimeStruct> *timeBuffer; 344 345 /** Wire to write information heading to previous stages. */ 346 typename TimeBuffer<TimeStruct>::wire toFetch; 347 348 /** Wire to get commit's output from backwards time buffer. */ 349 typename TimeBuffer<TimeStruct>::wire fromCommit; 350 351 /** Wire to write information heading to previous stages. */ 352 typename TimeBuffer<TimeStruct>::wire toRename; 353 354 /** Rename instruction queue interface. */ 355 TimeBuffer<RenameStruct> *renameQueue; 356 357 /** Wire to get rename's output from rename queue. */ 358 typename TimeBuffer<RenameStruct>::wire fromRename; 359 360 /** Issue stage queue. */ 361 TimeBuffer<IssueStruct> issueToExecQueue; 362 363 /** Wire to read information from the issue stage time queue. */ 364 typename TimeBuffer<IssueStruct>::wire fromIssue; 365 366 /** 367 * IEW stage time buffer. Holds ROB indices of instructions that 368 * can be marked as completed. 369 */ 370 TimeBuffer<IEWStruct> *iewQueue; 371 372 /** Wire to write infromation heading to commit. */ 373 typename TimeBuffer<IEWStruct>::wire toCommit; 374 375 /** Queue of all instructions coming from rename this cycle. */ 376 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 377 378 /** Skid buffer between rename and IEW. */ 379 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 380 381 /** Scoreboard pointer. */ 382 Scoreboard* scoreboard; 383 384 private: 385 /** CPU pointer. */ 386 O3CPU *cpu; 387 388 /** Records if IEW has written to the time buffer this cycle, so that the 389 * CPU can deschedule itself if there is no activity. 390 */ 391 bool wroteToTimeBuffer; 392 393 /** Source of possible stalls. */ 394 struct Stalls { 395 bool commit; 396 }; 397 398 /** Stages that are telling IEW to stall. */ 399 Stalls stalls[Impl::MaxThreads]; 400 401 /** Debug function to print instructions that are issued this cycle. */ 402 void printAvailableInsts(); 403 404 public: 405 /** Instruction queue. */ 406 IQ instQueue; 407 408 /** Load / store queue. */ 409 LSQ ldstQueue; 410 411 /** Pointer to the functional unit pool. */ 412 FUPool *fuPool; 413 /** Records if the LSQ needs to be updated on the next cycle, so that 414 * IEW knows if there will be activity on the next cycle. 415 */ 416 bool updateLSQNextCycle; 417 418 private: 419 /** Records if there is a fetch redirect on this cycle for each thread. */ 420 bool fetchRedirect[Impl::MaxThreads]; 421 422 /** Records if the queues have been changed (inserted or issued insts), 423 * so that IEW knows to broadcast the updated amount of free entries. 424 */ 425 bool updatedQueues; 426 427 /** Commit to IEW delay, in ticks. */ 428 unsigned commitToIEWDelay; 429 430 /** Rename to IEW delay, in ticks. */ 431 unsigned renameToIEWDelay; 432 433 /** 434 * Issue to execute delay, in ticks. What this actually represents is 435 * the amount of time it takes for an instruction to wake up, be 436 * scheduled, and sent to a FU for execution. 437 */ 438 unsigned issueToExecuteDelay; 439 440 /** Width of dispatch, in instructions. */ 441 unsigned dispatchWidth; 442 443 /** Width of issue, in instructions. */ 444 unsigned issueWidth; 445 446 /** Index into queue of instructions being written back. */ 447 unsigned wbNumInst; 448 449 /** Cycle number within the queue of instructions being written back. 450 * Used in case there are too many instructions writing back at the current 451 * cycle and writesbacks need to be scheduled for the future. See comments 452 * in instToCommit(). 453 */ 454 unsigned wbCycle; 455 456 /** Number of instructions in flight that will writeback. */ 457 458 /** Number of instructions in flight that will writeback. */ 459 int wbOutstanding; 460 461 /** Writeback width. */ 462 unsigned wbWidth; 463 464 /** Writeback width * writeback depth, where writeback depth is 465 * the number of cycles of writing back instructions that can be 466 * buffered. */ 467 unsigned wbMax; 468 469 /** Number of active threads. */ 470 ThreadID numThreads; 471 472 /** Pointer to list of active threads. */ 473 std::list<ThreadID> *activeThreads; 474 475 /** Maximum size of the skid buffer. */ 476 unsigned skidBufferMax; 477 478 /** Is this stage switched out. */ 479 bool switchedOut; 480 481 /** Stat for total number of idle cycles. */ 482 Stats::Scalar iewIdleCycles; 483 /** Stat for total number of squashing cycles. */ 484 Stats::Scalar iewSquashCycles; 485 /** Stat for total number of blocking cycles. */ 486 Stats::Scalar iewBlockCycles; 487 /** Stat for total number of unblocking cycles. */ 488 Stats::Scalar iewUnblockCycles; 489 /** Stat for total number of instructions dispatched. */ 490 Stats::Scalar iewDispatchedInsts; 491 /** Stat for total number of squashed instructions dispatch skips. */ 492 Stats::Scalar iewDispSquashedInsts; 493 /** Stat for total number of dispatched load instructions. */ 494 Stats::Scalar iewDispLoadInsts; 495 /** Stat for total number of dispatched store instructions. */ 496 Stats::Scalar iewDispStoreInsts; 497 /** Stat for total number of dispatched non speculative instructions. */ 498 Stats::Scalar iewDispNonSpecInsts; 499 /** Stat for number of times the IQ becomes full. */ 500 Stats::Scalar iewIQFullEvents; 501 /** Stat for number of times the LSQ becomes full. */ 502 Stats::Scalar iewLSQFullEvents; 503 /** Stat for total number of memory ordering violation events. */ 504 Stats::Scalar memOrderViolationEvents; 505 /** Stat for total number of incorrect predicted taken branches. */ 506 Stats::Scalar predictedTakenIncorrect; 507 /** Stat for total number of incorrect predicted not taken branches. */ 508 Stats::Scalar predictedNotTakenIncorrect; 509 /** Stat for total number of mispredicted branches detected at execute. */ 510 Stats::Formula branchMispredicts; 511 512 /** Stat for total number of executed instructions. */ 513 Stats::Scalar iewExecutedInsts; 514 /** Stat for total number of executed load instructions. */ 515 Stats::Vector iewExecLoadInsts; 516 /** Stat for total number of executed store instructions. */ 517// Stats::Scalar iewExecStoreInsts; 518 /** Stat for total number of squashed instructions skipped at execute. */ 519 Stats::Scalar iewExecSquashedInsts; 520 /** Number of executed software prefetches. */ 521 Stats::Vector iewExecutedSwp; 522 /** Number of executed nops. */ 523 Stats::Vector iewExecutedNop; 524 /** Number of executed meomory references. */ 525 Stats::Vector iewExecutedRefs; 526 /** Number of executed branches. */ 527 Stats::Vector iewExecutedBranches; 528 /** Number of executed store instructions. */ 529 Stats::Formula iewExecStoreInsts; 530 /** Number of instructions executed per cycle. */ 531 Stats::Formula iewExecRate; 532 533 /** Number of instructions sent to commit. */ 534 Stats::Vector iewInstsToCommit; 535 /** Number of instructions that writeback. */ 536 Stats::Vector writebackCount; 537 /** Number of instructions that wake consumers. */ 538 Stats::Vector producerInst; 539 /** Number of instructions that wake up from producers. */ 540 Stats::Vector consumerInst; 541 /** Number of instructions that were delayed in writing back due 542 * to resource contention. 543 */ 544 Stats::Vector wbPenalized; 545 /** Number of instructions per cycle written back. */ 546 Stats::Formula wbRate; 547 /** Average number of woken instructions per writeback. */ 548 Stats::Formula wbFanout; 549 /** Number of instructions per cycle delayed in writing back . */ 550 Stats::Formula wbPenalizedRate; 551}; 552 553#endif // __CPU_O3_IEW_HH__ 554