iew.hh revision 2843:19c4c6c2b5b1
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_IEW_HH__ 32#define __CPU_O3_IEW_HH__ 33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38#include "config/full_system.hh" 39#include "cpu/o3/comm.hh" 40#include "cpu/o3/scoreboard.hh" 41#include "cpu/o3/lsq.hh" 42 43class FUPool; 44 45/** 46 * DefaultIEW handles both single threaded and SMT IEW 47 * (issue/execute/writeback). It handles the dispatching of 48 * instructions to the LSQ/IQ as part of the issue stage, and has the 49 * IQ try to issue instructions each cycle. The execute latency is 50 * actually tied into the issue latency to allow the IQ to be able to 51 * do back-to-back scheduling without having to speculatively schedule 52 * instructions. This happens by having the IQ have access to the 53 * functional units, and the IQ gets the execution latencies from the 54 * FUs when it issues instructions. Instructions reach the execute 55 * stage on the last cycle of their execution, which is when the IQ 56 * knows to wake up any dependent instructions, allowing back to back 57 * scheduling. The execute portion of IEW separates memory 58 * instructions from non-memory instructions, either telling the LSQ 59 * to execute the instruction, or executing the instruction directly. 60 * The writeback portion of IEW completes the instructions by waking 61 * up any dependents, and marking the register ready on the 62 * scoreboard. 63 */ 64template<class Impl> 65class DefaultIEW 66{ 67 private: 68 //Typedefs from Impl 69 typedef typename Impl::CPUPol CPUPol; 70 typedef typename Impl::DynInstPtr DynInstPtr; 71 typedef typename Impl::O3CPU O3CPU; 72 typedef typename Impl::Params Params; 73 74 typedef typename CPUPol::IQ IQ; 75 typedef typename CPUPol::RenameMap RenameMap; 76 typedef typename CPUPol::LSQ LSQ; 77 78 typedef typename CPUPol::TimeStruct TimeStruct; 79 typedef typename CPUPol::IEWStruct IEWStruct; 80 typedef typename CPUPol::RenameStruct RenameStruct; 81 typedef typename CPUPol::IssueStruct IssueStruct; 82 83 friend class Impl::O3CPU; 84 friend class CPUPol::IQ; 85 86 public: 87 /** Overall IEW stage status. Used to determine if the CPU can 88 * deschedule itself due to a lack of activity. 89 */ 90 enum Status { 91 Active, 92 Inactive 93 }; 94 95 /** Status for Issue, Execute, and Writeback stages. */ 96 enum StageStatus { 97 Running, 98 Blocked, 99 Idle, 100 StartSquash, 101 Squashing, 102 Unblocking 103 }; 104 105 private: 106 /** Overall stage status. */ 107 Status _status; 108 /** Dispatch status. */ 109 StageStatus dispatchStatus[Impl::MaxThreads]; 110 /** Execute status. */ 111 StageStatus exeStatus; 112 /** Writeback status. */ 113 StageStatus wbStatus; 114 115 public: 116 /** Constructs a DefaultIEW with the given parameters. */ 117 DefaultIEW(Params *params); 118 119 /** Returns the name of the DefaultIEW stage. */ 120 std::string name() const; 121 122 /** Registers statistics. */ 123 void regStats(); 124 125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 126 void initStage(); 127 128 /** Sets CPU pointer for IEW, IQ, and LSQ. */ 129 void setCPU(O3CPU *cpu_ptr); 130 131 /** Sets main time buffer used for backwards communication. */ 132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 133 134 /** Sets time buffer for getting instructions coming from rename. */ 135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 136 137 /** Sets time buffer to pass on instructions to commit. */ 138 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 139 140 /** Sets pointer to list of active threads. */ 141 void setActiveThreads(std::list<unsigned> *at_ptr); 142 143 /** Sets pointer to the scoreboard. */ 144 void setScoreboard(Scoreboard *sb_ptr); 145 146 /** Drains IEW stage. */ 147 void drain(); 148 149 /** Resumes execution after a drain. */ 150 void resume(); 151 152 /** Completes switch out of IEW stage. */ 153 void switchOut(); 154 155 /** Takes over from another CPU's thread. */ 156 void takeOverFrom(); 157 158 /** Returns if IEW is switched out. */ 159 bool isSwitchedOut() { return switchedOut; } 160 161 /** Squashes instructions in IEW for a specific thread. */ 162 void squash(unsigned tid); 163 164 /** Wakes all dependents of a completed instruction. */ 165 void wakeDependents(DynInstPtr &inst); 166 167 /** Tells memory dependence unit that a memory instruction needs to be 168 * rescheduled. It will re-execute once replayMemInst() is called. 169 */ 170 void rescheduleMemInst(DynInstPtr &inst); 171 172 /** Re-executes all rescheduled memory instructions. */ 173 void replayMemInst(DynInstPtr &inst); 174 175 /** Sends an instruction to commit through the time buffer. */ 176 void instToCommit(DynInstPtr &inst); 177 178 /** Inserts unused instructions of a thread into the skid buffer. */ 179 void skidInsert(unsigned tid); 180 181 /** Returns the max of the number of entries in all of the skid buffers. */ 182 int skidCount(); 183 184 /** Returns if all of the skid buffers are empty. */ 185 bool skidsEmpty(); 186 187 /** Updates overall IEW status based on all of the stages' statuses. */ 188 void updateStatus(); 189 190 /** Resets entries of the IQ and the LSQ. */ 191 void resetEntries(); 192 193 /** Tells the CPU to wakeup if it has descheduled itself due to no 194 * activity. Used mainly by the LdWritebackEvent. 195 */ 196 void wakeCPU(); 197 198 /** Reports to the CPU that there is activity this cycle. */ 199 void activityThisCycle(); 200 201 /** Tells CPU that the IEW stage is active and running. */ 202 inline void activateStage(); 203 204 /** Tells CPU that the IEW stage is inactive and idle. */ 205 inline void deactivateStage(); 206 207 /** Returns if the LSQ has any stores to writeback. */ 208 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 209 210 void incrWb(InstSeqNum &sn) 211 { 212 if (++wbOutstanding == wbMax) 213 ableToIssue = false; 214 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 215#if DEBUG 216 wbList.insert(sn); 217#endif 218 } 219 220 void decrWb(InstSeqNum &sn) 221 { 222 if (wbOutstanding-- == wbMax) 223 ableToIssue = true; 224 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 225#if DEBUG 226 assert(wbList.find(sn) != wbList.end()); 227 wbList.erase(sn); 228#endif 229 } 230 231#if DEBUG 232 std::set<InstSeqNum> wbList; 233 234 void dumpWb() 235 { 236 std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 237 while (wb_it != wbList.end()) { 238 cprintf("[sn:%lli]\n", 239 (*wb_it)); 240 wb_it++; 241 } 242 } 243#endif 244 245 bool canIssue() { return ableToIssue; } 246 247 bool ableToIssue; 248 249 private: 250 /** Sends commit proper information for a squash due to a branch 251 * mispredict. 252 */ 253 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 254 255 /** Sends commit proper information for a squash due to a memory order 256 * violation. 257 */ 258 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 259 260 /** Sends commit proper information for a squash due to memory becoming 261 * blocked (younger issued instructions must be retried). 262 */ 263 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 264 265 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 266 void block(unsigned thread_id); 267 268 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 269 * other stages to unblock. 270 */ 271 void unblock(unsigned thread_id); 272 273 /** Determines proper actions to take given Dispatch's status. */ 274 void dispatch(unsigned tid); 275 276 /** Dispatches instructions to IQ and LSQ. */ 277 void dispatchInsts(unsigned tid); 278 279 /** Executes instructions. In the case of memory operations, it informs the 280 * LSQ to execute the instructions. Also handles any redirects that occur 281 * due to the executed instructions. 282 */ 283 void executeInsts(); 284 285 /** Writebacks instructions. In our model, the instruction's execute() 286 * function atomically reads registers, executes, and writes registers. 287 * Thus this writeback only wakes up dependent instructions, and informs 288 * the scoreboard of registers becoming ready. 289 */ 290 void writebackInsts(); 291 292 /** Returns the number of valid, non-squashed instructions coming from 293 * rename to dispatch. 294 */ 295 unsigned validInstsFromRename(); 296 297 /** Reads the stall signals. */ 298 void readStallSignals(unsigned tid); 299 300 /** Checks if any of the stall conditions are currently true. */ 301 bool checkStall(unsigned tid); 302 303 /** Processes inputs and changes state accordingly. */ 304 void checkSignalsAndUpdate(unsigned tid); 305 306 /** Removes instructions from rename from a thread's instruction list. */ 307 void emptyRenameInsts(unsigned tid); 308 309 /** Sorts instructions coming from rename into lists separated by thread. */ 310 void sortInsts(); 311 312 public: 313 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 314 * Writeback to run for one cycle. 315 */ 316 void tick(); 317 318 private: 319 /** Updates execution stats based on the instruction. */ 320 void updateExeInstStats(DynInstPtr &inst); 321 322 /** Pointer to main time buffer used for backwards communication. */ 323 TimeBuffer<TimeStruct> *timeBuffer; 324 325 /** Wire to write information heading to previous stages. */ 326 typename TimeBuffer<TimeStruct>::wire toFetch; 327 328 /** Wire to get commit's output from backwards time buffer. */ 329 typename TimeBuffer<TimeStruct>::wire fromCommit; 330 331 /** Wire to write information heading to previous stages. */ 332 typename TimeBuffer<TimeStruct>::wire toRename; 333 334 /** Rename instruction queue interface. */ 335 TimeBuffer<RenameStruct> *renameQueue; 336 337 /** Wire to get rename's output from rename queue. */ 338 typename TimeBuffer<RenameStruct>::wire fromRename; 339 340 /** Issue stage queue. */ 341 TimeBuffer<IssueStruct> issueToExecQueue; 342 343 /** Wire to read information from the issue stage time queue. */ 344 typename TimeBuffer<IssueStruct>::wire fromIssue; 345 346 /** 347 * IEW stage time buffer. Holds ROB indices of instructions that 348 * can be marked as completed. 349 */ 350 TimeBuffer<IEWStruct> *iewQueue; 351 352 /** Wire to write infromation heading to commit. */ 353 typename TimeBuffer<IEWStruct>::wire toCommit; 354 355 /** Queue of all instructions coming from rename this cycle. */ 356 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 357 358 /** Skid buffer between rename and IEW. */ 359 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 360 361 /** Scoreboard pointer. */ 362 Scoreboard* scoreboard; 363 364 public: 365 /** Instruction queue. */ 366 IQ instQueue; 367 368 /** Load / store queue. */ 369 LSQ ldstQueue; 370 371 /** Pointer to the functional unit pool. */ 372 FUPool *fuPool; 373 374 private: 375 /** CPU pointer. */ 376 O3CPU *cpu; 377 378 /** Records if IEW has written to the time buffer this cycle, so that the 379 * CPU can deschedule itself if there is no activity. 380 */ 381 bool wroteToTimeBuffer; 382 383 /** Source of possible stalls. */ 384 struct Stalls { 385 bool commit; 386 }; 387 388 /** Stages that are telling IEW to stall. */ 389 Stalls stalls[Impl::MaxThreads]; 390 391 /** Debug function to print instructions that are issued this cycle. */ 392 void printAvailableInsts(); 393 394 public: 395 /** Records if the LSQ needs to be updated on the next cycle, so that 396 * IEW knows if there will be activity on the next cycle. 397 */ 398 bool updateLSQNextCycle; 399 400 private: 401 /** Records if there is a fetch redirect on this cycle for each thread. */ 402 bool fetchRedirect[Impl::MaxThreads]; 403 404 /** Used to track if all instructions have been dispatched this cycle. 405 * If they have not, then blocking must have occurred, and the instructions 406 * would already be added to the skid buffer. 407 * @todo: Fix this hack. 408 */ 409 bool dispatchedAllInsts; 410 411 /** Records if the queues have been changed (inserted or issued insts), 412 * so that IEW knows to broadcast the updated amount of free entries. 413 */ 414 bool updatedQueues; 415 416 /** Commit to IEW delay, in ticks. */ 417 unsigned commitToIEWDelay; 418 419 /** Rename to IEW delay, in ticks. */ 420 unsigned renameToIEWDelay; 421 422 /** 423 * Issue to execute delay, in ticks. What this actually represents is 424 * the amount of time it takes for an instruction to wake up, be 425 * scheduled, and sent to a FU for execution. 426 */ 427 unsigned issueToExecuteDelay; 428 429 /** Width of dispatch, in instructions. */ 430 unsigned dispatchWidth; 431 432 /** Width of issue, in instructions. */ 433 unsigned issueWidth; 434 435 /** Index into queue of instructions being written back. */ 436 unsigned wbNumInst; 437 438 /** Cycle number within the queue of instructions being written back. 439 * Used in case there are too many instructions writing back at the current 440 * cycle and writesbacks need to be scheduled for the future. See comments 441 * in instToCommit(). 442 */ 443 unsigned wbCycle; 444 445 /** Number of instructions in flight that will writeback. */ 446 unsigned wbOutstanding; 447 448 /** Writeback width. */ 449 unsigned wbWidth; 450 451 /** Writeback width * writeback depth, where writeback depth is 452 * the number of cycles of writing back instructions that can be 453 * buffered. */ 454 unsigned wbMax; 455 456 /** Number of active threads. */ 457 unsigned numThreads; 458 459 /** Pointer to list of active threads. */ 460 std::list<unsigned> *activeThreads; 461 462 /** Maximum size of the skid buffer. */ 463 unsigned skidBufferMax; 464 465 /** Is this stage switched out. */ 466 bool switchedOut; 467 468 /** Stat for total number of idle cycles. */ 469 Stats::Scalar<> iewIdleCycles; 470 /** Stat for total number of squashing cycles. */ 471 Stats::Scalar<> iewSquashCycles; 472 /** Stat for total number of blocking cycles. */ 473 Stats::Scalar<> iewBlockCycles; 474 /** Stat for total number of unblocking cycles. */ 475 Stats::Scalar<> iewUnblockCycles; 476 /** Stat for total number of instructions dispatched. */ 477 Stats::Scalar<> iewDispatchedInsts; 478 /** Stat for total number of squashed instructions dispatch skips. */ 479 Stats::Scalar<> iewDispSquashedInsts; 480 /** Stat for total number of dispatched load instructions. */ 481 Stats::Scalar<> iewDispLoadInsts; 482 /** Stat for total number of dispatched store instructions. */ 483 Stats::Scalar<> iewDispStoreInsts; 484 /** Stat for total number of dispatched non speculative instructions. */ 485 Stats::Scalar<> iewDispNonSpecInsts; 486 /** Stat for number of times the IQ becomes full. */ 487 Stats::Scalar<> iewIQFullEvents; 488 /** Stat for number of times the LSQ becomes full. */ 489 Stats::Scalar<> iewLSQFullEvents; 490 /** Stat for total number of memory ordering violation events. */ 491 Stats::Scalar<> memOrderViolationEvents; 492 /** Stat for total number of incorrect predicted taken branches. */ 493 Stats::Scalar<> predictedTakenIncorrect; 494 /** Stat for total number of incorrect predicted not taken branches. */ 495 Stats::Scalar<> predictedNotTakenIncorrect; 496 /** Stat for total number of mispredicted branches detected at execute. */ 497 Stats::Formula branchMispredicts; 498 499 /** Stat for total number of executed instructions. */ 500 Stats::Scalar<> iewExecutedInsts; 501 /** Stat for total number of executed load instructions. */ 502 Stats::Vector<> iewExecLoadInsts; 503 /** Stat for total number of squashed instructions skipped at execute. */ 504 Stats::Scalar<> iewExecSquashedInsts; 505 /** Number of executed software prefetches. */ 506 Stats::Vector<> iewExecutedSwp; 507 /** Number of executed nops. */ 508 Stats::Vector<> iewExecutedNop; 509 /** Number of executed meomory references. */ 510 Stats::Vector<> iewExecutedRefs; 511 /** Number of executed branches. */ 512 Stats::Vector<> iewExecutedBranches; 513 /** Number of executed store instructions. */ 514 Stats::Formula iewExecStoreInsts; 515 /** Number of instructions executed per cycle. */ 516 Stats::Formula iewExecRate; 517 518 /** Number of instructions sent to commit. */ 519 Stats::Vector<> iewInstsToCommit; 520 /** Number of instructions that writeback. */ 521 Stats::Vector<> writebackCount; 522 /** Number of instructions that wake consumers. */ 523 Stats::Vector<> producerInst; 524 /** Number of instructions that wake up from producers. */ 525 Stats::Vector<> consumerInst; 526 /** Number of instructions that were delayed in writing back due 527 * to resource contention. 528 */ 529 Stats::Vector<> wbPenalized; 530 /** Number of instructions per cycle written back. */ 531 Stats::Formula wbRate; 532 /** Average number of woken instructions per writeback. */ 533 Stats::Formula wbFanout; 534 /** Number of instructions per cycle delayed in writing back . */ 535 Stats::Formula wbPenalizedRate; 536}; 537 538#endif // __CPU_O3_IEW_HH__ 539