iew.hh revision 2820:7fde0b0f8f78
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_IEW_HH__ 32#define __CPU_O3_IEW_HH__ 33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38#include "config/full_system.hh" 39#include "cpu/o3/comm.hh" 40#include "cpu/o3/scoreboard.hh" 41#include "cpu/o3/lsq.hh" 42 43class FUPool; 44 45/** 46 * DefaultIEW handles both single threaded and SMT IEW 47 * (issue/execute/writeback). It handles the dispatching of 48 * instructions to the LSQ/IQ as part of the issue stage, and has the 49 * IQ try to issue instructions each cycle. The execute latency is 50 * actually tied into the issue latency to allow the IQ to be able to 51 * do back-to-back scheduling without having to speculatively schedule 52 * instructions. This happens by having the IQ have access to the 53 * functional units, and the IQ gets the execution latencies from the 54 * FUs when it issues instructions. Instructions reach the execute 55 * stage on the last cycle of their execution, which is when the IQ 56 * knows to wake up any dependent instructions, allowing back to back 57 * scheduling. The execute portion of IEW separates memory 58 * instructions from non-memory instructions, either telling the LSQ 59 * to execute the instruction, or executing the instruction directly. 60 * The writeback portion of IEW completes the instructions by waking 61 * up any dependents, and marking the register ready on the 62 * scoreboard. 63 */ 64template<class Impl> 65class DefaultIEW 66{ 67 private: 68 //Typedefs from Impl 69 typedef typename Impl::CPUPol CPUPol; 70 typedef typename Impl::DynInstPtr DynInstPtr; 71 typedef typename Impl::O3CPU O3CPU; 72 typedef typename Impl::Params Params; 73 74 typedef typename CPUPol::IQ IQ; 75 typedef typename CPUPol::RenameMap RenameMap; 76 typedef typename CPUPol::LSQ LSQ; 77 78 typedef typename CPUPol::TimeStruct TimeStruct; 79 typedef typename CPUPol::IEWStruct IEWStruct; 80 typedef typename CPUPol::RenameStruct RenameStruct; 81 typedef typename CPUPol::IssueStruct IssueStruct; 82 83 friend class Impl::O3CPU; 84 friend class CPUPol::IQ; 85 86 public: 87 /** Overall IEW stage status. Used to determine if the CPU can 88 * deschedule itself due to a lack of activity. 89 */ 90 enum Status { 91 Active, 92 Inactive 93 }; 94 95 /** Status for Issue, Execute, and Writeback stages. */ 96 enum StageStatus { 97 Running, 98 Blocked, 99 Idle, 100 StartSquash, 101 Squashing, 102 Unblocking 103 }; 104 105 private: 106 /** Overall stage status. */ 107 Status _status; 108 /** Dispatch status. */ 109 StageStatus dispatchStatus[Impl::MaxThreads]; 110 /** Execute status. */ 111 StageStatus exeStatus; 112 /** Writeback status. */ 113 StageStatus wbStatus; 114 115 public: 116 /** Constructs a DefaultIEW with the given parameters. */ 117 DefaultIEW(Params *params); 118 119 /** Returns the name of the DefaultIEW stage. */ 120 std::string name() const; 121 122 /** Registers statistics. */ 123 void regStats(); 124 125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 126 void initStage(); 127 128 /** Sets CPU pointer for IEW, IQ, and LSQ. */ 129 void setCPU(O3CPU *cpu_ptr); 130 131 /** Sets main time buffer used for backwards communication. */ 132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 133 134 /** Sets time buffer for getting instructions coming from rename. */ 135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 136 137 /** Sets time buffer to pass on instructions to commit. */ 138 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 139 140 /** Sets pointer to list of active threads. */ 141 void setActiveThreads(std::list<unsigned> *at_ptr); 142 143 /** Sets pointer to the scoreboard. */ 144 void setScoreboard(Scoreboard *sb_ptr); 145 146 /** Starts switch out of IEW stage. */ 147 void switchOut(); 148 149 /** Completes switch out of IEW stage. */ 150 void doSwitchOut(); 151 152 /** Takes over from another CPU's thread. */ 153 void takeOverFrom(); 154 155 /** Returns if IEW is switched out. */ 156 bool isSwitchedOut() { return switchedOut; } 157 158 /** Squashes instructions in IEW for a specific thread. */ 159 void squash(unsigned tid); 160 161 /** Wakes all dependents of a completed instruction. */ 162 void wakeDependents(DynInstPtr &inst); 163 164 /** Tells memory dependence unit that a memory instruction needs to be 165 * rescheduled. It will re-execute once replayMemInst() is called. 166 */ 167 void rescheduleMemInst(DynInstPtr &inst); 168 169 /** Re-executes all rescheduled memory instructions. */ 170 void replayMemInst(DynInstPtr &inst); 171 172 /** Sends an instruction to commit through the time buffer. */ 173 void instToCommit(DynInstPtr &inst); 174 175 /** Inserts unused instructions of a thread into the skid buffer. */ 176 void skidInsert(unsigned tid); 177 178 /** Returns the max of the number of entries in all of the skid buffers. */ 179 int skidCount(); 180 181 /** Returns if all of the skid buffers are empty. */ 182 bool skidsEmpty(); 183 184 /** Updates overall IEW status based on all of the stages' statuses. */ 185 void updateStatus(); 186 187 /** Resets entries of the IQ and the LSQ. */ 188 void resetEntries(); 189 190 /** Tells the CPU to wakeup if it has descheduled itself due to no 191 * activity. Used mainly by the LdWritebackEvent. 192 */ 193 void wakeCPU(); 194 195 /** Reports to the CPU that there is activity this cycle. */ 196 void activityThisCycle(); 197 198 /** Tells CPU that the IEW stage is active and running. */ 199 inline void activateStage(); 200 201 /** Tells CPU that the IEW stage is inactive and idle. */ 202 inline void deactivateStage(); 203 204 /** Returns if the LSQ has any stores to writeback. */ 205 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 206 207 void incrWb(InstSeqNum &sn) 208 { 209 if (++wbOutstanding == wbMax) 210 ableToIssue = false; 211 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 212#if DEBUG 213 wbList.insert(sn); 214#endif 215 } 216 217 void decrWb(InstSeqNum &sn) 218 { 219 if (wbOutstanding-- == wbMax) 220 ableToIssue = true; 221 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 222#if DEBUG 223 assert(wbList.find(sn) != wbList.end()); 224 wbList.erase(sn); 225#endif 226 } 227 228#if DEBUG 229 std::set<InstSeqNum> wbList; 230 231 void dumpWb() 232 { 233 std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 234 while (wb_it != wbList.end()) { 235 cprintf("[sn:%lli]\n", 236 (*wb_it)); 237 wb_it++; 238 } 239 } 240#endif 241 242 bool canIssue() { return ableToIssue; } 243 244 bool ableToIssue; 245 246 private: 247 /** Sends commit proper information for a squash due to a branch 248 * mispredict. 249 */ 250 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 251 252 /** Sends commit proper information for a squash due to a memory order 253 * violation. 254 */ 255 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 256 257 /** Sends commit proper information for a squash due to memory becoming 258 * blocked (younger issued instructions must be retried). 259 */ 260 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 261 262 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 263 void block(unsigned thread_id); 264 265 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 266 * other stages to unblock. 267 */ 268 void unblock(unsigned thread_id); 269 270 /** Determines proper actions to take given Dispatch's status. */ 271 void dispatch(unsigned tid); 272 273 /** Dispatches instructions to IQ and LSQ. */ 274 void dispatchInsts(unsigned tid); 275 276 /** Executes instructions. In the case of memory operations, it informs the 277 * LSQ to execute the instructions. Also handles any redirects that occur 278 * due to the executed instructions. 279 */ 280 void executeInsts(); 281 282 /** Writebacks instructions. In our model, the instruction's execute() 283 * function atomically reads registers, executes, and writes registers. 284 * Thus this writeback only wakes up dependent instructions, and informs 285 * the scoreboard of registers becoming ready. 286 */ 287 void writebackInsts(); 288 289 /** Returns the number of valid, non-squashed instructions coming from 290 * rename to dispatch. 291 */ 292 unsigned validInstsFromRename(); 293 294 /** Reads the stall signals. */ 295 void readStallSignals(unsigned tid); 296 297 /** Checks if any of the stall conditions are currently true. */ 298 bool checkStall(unsigned tid); 299 300 /** Processes inputs and changes state accordingly. */ 301 void checkSignalsAndUpdate(unsigned tid); 302 303 /** Removes instructions from rename from a thread's instruction list. */ 304 void emptyRenameInsts(unsigned tid); 305 306 /** Sorts instructions coming from rename into lists separated by thread. */ 307 void sortInsts(); 308 309 public: 310 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 311 * Writeback to run for one cycle. 312 */ 313 void tick(); 314 315 private: 316 /** Updates execution stats based on the instruction. */ 317 void updateExeInstStats(DynInstPtr &inst); 318 319 /** Pointer to main time buffer used for backwards communication. */ 320 TimeBuffer<TimeStruct> *timeBuffer; 321 322 /** Wire to write information heading to previous stages. */ 323 typename TimeBuffer<TimeStruct>::wire toFetch; 324 325 /** Wire to get commit's output from backwards time buffer. */ 326 typename TimeBuffer<TimeStruct>::wire fromCommit; 327 328 /** Wire to write information heading to previous stages. */ 329 typename TimeBuffer<TimeStruct>::wire toRename; 330 331 /** Rename instruction queue interface. */ 332 TimeBuffer<RenameStruct> *renameQueue; 333 334 /** Wire to get rename's output from rename queue. */ 335 typename TimeBuffer<RenameStruct>::wire fromRename; 336 337 /** Issue stage queue. */ 338 TimeBuffer<IssueStruct> issueToExecQueue; 339 340 /** Wire to read information from the issue stage time queue. */ 341 typename TimeBuffer<IssueStruct>::wire fromIssue; 342 343 /** 344 * IEW stage time buffer. Holds ROB indices of instructions that 345 * can be marked as completed. 346 */ 347 TimeBuffer<IEWStruct> *iewQueue; 348 349 /** Wire to write infromation heading to commit. */ 350 typename TimeBuffer<IEWStruct>::wire toCommit; 351 352 /** Queue of all instructions coming from rename this cycle. */ 353 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 354 355 /** Skid buffer between rename and IEW. */ 356 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 357 358 /** Scoreboard pointer. */ 359 Scoreboard* scoreboard; 360 361 public: 362 /** Instruction queue. */ 363 IQ instQueue; 364 365 /** Load / store queue. */ 366 LSQ ldstQueue; 367 368 /** Pointer to the functional unit pool. */ 369 FUPool *fuPool; 370 371 private: 372 /** CPU pointer. */ 373 O3CPU *cpu; 374 375 /** Records if IEW has written to the time buffer this cycle, so that the 376 * CPU can deschedule itself if there is no activity. 377 */ 378 bool wroteToTimeBuffer; 379 380 /** Source of possible stalls. */ 381 struct Stalls { 382 bool commit; 383 }; 384 385 /** Stages that are telling IEW to stall. */ 386 Stalls stalls[Impl::MaxThreads]; 387 388 /** Debug function to print instructions that are issued this cycle. */ 389 void printAvailableInsts(); 390 391 public: 392 /** Records if the LSQ needs to be updated on the next cycle, so that 393 * IEW knows if there will be activity on the next cycle. 394 */ 395 bool updateLSQNextCycle; 396 397 private: 398 /** Records if there is a fetch redirect on this cycle for each thread. */ 399 bool fetchRedirect[Impl::MaxThreads]; 400 401 /** Used to track if all instructions have been dispatched this cycle. 402 * If they have not, then blocking must have occurred, and the instructions 403 * would already be added to the skid buffer. 404 * @todo: Fix this hack. 405 */ 406 bool dispatchedAllInsts; 407 408 /** Records if the queues have been changed (inserted or issued insts), 409 * so that IEW knows to broadcast the updated amount of free entries. 410 */ 411 bool updatedQueues; 412 413 /** Commit to IEW delay, in ticks. */ 414 unsigned commitToIEWDelay; 415 416 /** Rename to IEW delay, in ticks. */ 417 unsigned renameToIEWDelay; 418 419 /** 420 * Issue to execute delay, in ticks. What this actually represents is 421 * the amount of time it takes for an instruction to wake up, be 422 * scheduled, and sent to a FU for execution. 423 */ 424 unsigned issueToExecuteDelay; 425 426 /** Width of dispatch, in instructions. */ 427 unsigned dispatchWidth; 428 429 /** Width of issue, in instructions. */ 430 unsigned issueWidth; 431 432 /** Index into queue of instructions being written back. */ 433 unsigned wbNumInst; 434 435 /** Cycle number within the queue of instructions being written back. 436 * Used in case there are too many instructions writing back at the current 437 * cycle and writesbacks need to be scheduled for the future. See comments 438 * in instToCommit(). 439 */ 440 unsigned wbCycle; 441 442 /** Number of instructions in flight that will writeback. */ 443 unsigned wbOutstanding; 444 445 /** Writeback width. */ 446 unsigned wbWidth; 447 448 /** Writeback width * writeback depth, where writeback depth is 449 * the number of cycles of writing back instructions that can be 450 * buffered. */ 451 unsigned wbMax; 452 453 /** Number of active threads. */ 454 unsigned numThreads; 455 456 /** Pointer to list of active threads. */ 457 std::list<unsigned> *activeThreads; 458 459 /** Maximum size of the skid buffer. */ 460 unsigned skidBufferMax; 461 462 /** Is this stage switched out. */ 463 bool switchedOut; 464 465 /** Stat for total number of idle cycles. */ 466 Stats::Scalar<> iewIdleCycles; 467 /** Stat for total number of squashing cycles. */ 468 Stats::Scalar<> iewSquashCycles; 469 /** Stat for total number of blocking cycles. */ 470 Stats::Scalar<> iewBlockCycles; 471 /** Stat for total number of unblocking cycles. */ 472 Stats::Scalar<> iewUnblockCycles; 473 /** Stat for total number of instructions dispatched. */ 474 Stats::Scalar<> iewDispatchedInsts; 475 /** Stat for total number of squashed instructions dispatch skips. */ 476 Stats::Scalar<> iewDispSquashedInsts; 477 /** Stat for total number of dispatched load instructions. */ 478 Stats::Scalar<> iewDispLoadInsts; 479 /** Stat for total number of dispatched store instructions. */ 480 Stats::Scalar<> iewDispStoreInsts; 481 /** Stat for total number of dispatched non speculative instructions. */ 482 Stats::Scalar<> iewDispNonSpecInsts; 483 /** Stat for number of times the IQ becomes full. */ 484 Stats::Scalar<> iewIQFullEvents; 485 /** Stat for number of times the LSQ becomes full. */ 486 Stats::Scalar<> iewLSQFullEvents; 487 /** Stat for total number of memory ordering violation events. */ 488 Stats::Scalar<> memOrderViolationEvents; 489 /** Stat for total number of incorrect predicted taken branches. */ 490 Stats::Scalar<> predictedTakenIncorrect; 491 /** Stat for total number of incorrect predicted not taken branches. */ 492 Stats::Scalar<> predictedNotTakenIncorrect; 493 /** Stat for total number of mispredicted branches detected at execute. */ 494 Stats::Formula branchMispredicts; 495 496 /** Stat for total number of executed instructions. */ 497 Stats::Scalar<> iewExecutedInsts; 498 /** Stat for total number of executed load instructions. */ 499 Stats::Vector<> iewExecLoadInsts; 500 /** Stat for total number of squashed instructions skipped at execute. */ 501 Stats::Scalar<> iewExecSquashedInsts; 502 /** Number of executed software prefetches. */ 503 Stats::Vector<> iewExecutedSwp; 504 /** Number of executed nops. */ 505 Stats::Vector<> iewExecutedNop; 506 /** Number of executed meomory references. */ 507 Stats::Vector<> iewExecutedRefs; 508 /** Number of executed branches. */ 509 Stats::Vector<> iewExecutedBranches; 510 /** Number of executed store instructions. */ 511 Stats::Formula iewExecStoreInsts; 512 /** Number of instructions executed per cycle. */ 513 Stats::Formula iewExecRate; 514 515 /** Number of instructions sent to commit. */ 516 Stats::Vector<> iewInstsToCommit; 517 /** Number of instructions that writeback. */ 518 Stats::Vector<> writebackCount; 519 /** Number of instructions that wake consumers. */ 520 Stats::Vector<> producerInst; 521 /** Number of instructions that wake up from producers. */ 522 Stats::Vector<> consumerInst; 523 /** Number of instructions that were delayed in writing back due 524 * to resource contention. 525 */ 526 Stats::Vector<> wbPenalized; 527 /** Number of instructions per cycle written back. */ 528 Stats::Formula wbRate; 529 /** Average number of woken instructions per writeback. */ 530 Stats::Formula wbFanout; 531 /** Number of instructions per cycle delayed in writing back . */ 532 Stats::Formula wbPenalizedRate; 533}; 534 535#endif // __CPU_O3_IEW_HH__ 536