iew.hh revision 2348
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_IEW_HH__ 30#define __CPU_O3_IEW_HH__ 31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36#include "config/full_system.hh" 37#include "cpu/o3/comm.hh" 38#include "cpu/o3/scoreboard.hh" 39#include "cpu/o3/lsq.hh" 40 41class FUPool; 42 43/** 44 * DefaultIEW handles both single threaded and SMT IEW 45 * (issue/execute/writeback). It handles the dispatching of 46 * instructions to the LSQ/IQ as part of the issue stage, and has the 47 * IQ try to issue instructions each cycle. The execute latency is 48 * actually tied into the issue latency to allow the IQ to be able to 49 * do back-to-back scheduling without having to speculatively schedule 50 * instructions. This happens by having the IQ have access to the 51 * functional units, and the IQ gets the execution latencies from the 52 * FUs when it issues instructions. Instructions reach the execute 53 * stage on the last cycle of their execution, which is when the IQ 54 * knows to wake up any dependent instructions, allowing back to back 55 * scheduling. The execute portion of IEW separates memory 56 * instructions from non-memory instructions, either telling the LSQ 57 * to execute the instruction, or executing the instruction directly. 58 * The writeback portion of IEW completes the instructions by waking 59 * up any dependents, and marking the register ready on the 60 * scoreboard. 61 */ 62template<class Impl> 63class DefaultIEW 64{ 65 private: 66 //Typedefs from Impl 67 typedef typename Impl::CPUPol CPUPol; 68 typedef typename Impl::DynInstPtr DynInstPtr; 69 typedef typename Impl::FullCPU FullCPU; 70 typedef typename Impl::Params Params; 71 72 typedef typename CPUPol::IQ IQ; 73 typedef typename CPUPol::RenameMap RenameMap; 74 typedef typename CPUPol::LSQ LSQ; 75 76 typedef typename CPUPol::TimeStruct TimeStruct; 77 typedef typename CPUPol::IEWStruct IEWStruct; 78 typedef typename CPUPol::RenameStruct RenameStruct; 79 typedef typename CPUPol::IssueStruct IssueStruct; 80 81 friend class Impl::FullCPU; 82 friend class CPUPol::IQ; 83 84 public: 85 /** Overall IEW stage status. Used to determine if the CPU can 86 * deschedule itself due to a lack of activity. 87 */ 88 enum Status { 89 Active, 90 Inactive 91 }; 92 93 /** Status for Issue, Execute, and Writeback stages. */ 94 enum StageStatus { 95 Running, 96 Blocked, 97 Idle, 98 StartSquash, 99 Squashing, 100 Unblocking 101 }; 102 103 private: 104 /** Overall stage status. */ 105 Status _status; 106 /** Dispatch status. */ 107 StageStatus dispatchStatus[Impl::MaxThreads]; 108 /** Execute status. */ 109 StageStatus exeStatus; 110 /** Writeback status. */ 111 StageStatus wbStatus; 112 113 public: 114 /** LdWriteback event for a load completion. */ 115 class LdWritebackEvent : public Event { 116 private: 117 /** Instruction that is writing back data to the register file. */ 118 DynInstPtr inst; 119 /** Pointer to IEW stage. */ 120 DefaultIEW<Impl> *iewStage; 121 122 public: 123 /** Constructs a load writeback event. */ 124 LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew); 125 126 /** Processes writeback event. */ 127 virtual void process(); 128 /** Returns the description of the writeback event. */ 129 virtual const char *description(); 130 }; 131 132 public: 133 /** Constructs a DefaultIEW with the given parameters. */ 134 DefaultIEW(Params *params); 135 136 /** Returns the name of the DefaultIEW stage. */ 137 std::string name() const; 138 139 /** Registers statistics. */ 140 void regStats(); 141 142 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 143 void initStage(); 144 145 /** Sets CPU pointer for IEW, IQ, and LSQ. */ 146 void setCPU(FullCPU *cpu_ptr); 147 148 /** Sets main time buffer used for backwards communication. */ 149 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 150 151 /** Sets time buffer for getting instructions coming from rename. */ 152 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 153 154 /** Sets time buffer to pass on instructions to commit. */ 155 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 156 157 /** Sets pointer to list of active threads. */ 158 void setActiveThreads(std::list<unsigned> *at_ptr); 159 160 /** Sets pointer to the scoreboard. */ 161 void setScoreboard(Scoreboard *sb_ptr); 162 163 /** Starts switch out of IEW stage. */ 164 void switchOut(); 165 166 /** Completes switch out of IEW stage. */ 167 void doSwitchOut(); 168 169 /** Takes over from another CPU's thread. */ 170 void takeOverFrom(); 171 172 /** Returns if IEW is switched out. */ 173 bool isSwitchedOut() { return switchedOut; } 174 175 /** Sets page table pointer within LSQ. */ 176// void setPageTable(PageTable *pt_ptr); 177 178 /** Squashes instructions in IEW for a specific thread. */ 179 void squash(unsigned tid); 180 181 /** Wakes all dependents of a completed instruction. */ 182 void wakeDependents(DynInstPtr &inst); 183 184 /** Tells memory dependence unit that a memory instruction needs to be 185 * rescheduled. It will re-execute once replayMemInst() is called. 186 */ 187 void rescheduleMemInst(DynInstPtr &inst); 188 189 /** Re-executes all rescheduled memory instructions. */ 190 void replayMemInst(DynInstPtr &inst); 191 192 /** Sends an instruction to commit through the time buffer. */ 193 void instToCommit(DynInstPtr &inst); 194 195 /** Inserts unused instructions of a thread into the skid buffer. */ 196 void skidInsert(unsigned tid); 197 198 /** Returns the max of the number of entries in all of the skid buffers. */ 199 int skidCount(); 200 201 /** Returns if all of the skid buffers are empty. */ 202 bool skidsEmpty(); 203 204 /** Updates overall IEW status based on all of the stages' statuses. */ 205 void updateStatus(); 206 207 /** Resets entries of the IQ and the LSQ. */ 208 void resetEntries(); 209 210 /** Tells the CPU to wakeup if it has descheduled itself due to no 211 * activity. Used mainly by the LdWritebackEvent. 212 */ 213 void wakeCPU(); 214 215 /** Reports to the CPU that there is activity this cycle. */ 216 void activityThisCycle(); 217 218 /** Tells CPU that the IEW stage is active and running. */ 219 inline void activateStage(); 220 221 /** Tells CPU that the IEW stage is inactive and idle. */ 222 inline void deactivateStage(); 223 224 /** Returns if the LSQ has any stores to writeback. */ 225 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 226 227 private: 228 /** Sends commit proper information for a squash due to a branch 229 * mispredict. 230 */ 231 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 232 233 /** Sends commit proper information for a squash due to a memory order 234 * violation. 235 */ 236 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 237 238 /** Sends commit proper information for a squash due to memory becoming 239 * blocked (younger issued instructions must be retried). 240 */ 241 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 242 243 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 244 void block(unsigned thread_id); 245 246 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 247 * other stages to unblock. 248 */ 249 void unblock(unsigned thread_id); 250 251 /** Determines proper actions to take given Dispatch's status. */ 252 void dispatch(unsigned tid); 253 254 /** Dispatches instructions to IQ and LSQ. */ 255 void dispatchInsts(unsigned tid); 256 257 /** Executes instructions. In the case of memory operations, it informs the 258 * LSQ to execute the instructions. Also handles any redirects that occur 259 * due to the executed instructions. 260 */ 261 void executeInsts(); 262 263 /** Writebacks instructions. In our model, the instruction's execute() 264 * function atomically reads registers, executes, and writes registers. 265 * Thus this writeback only wakes up dependent instructions, and informs 266 * the scoreboard of registers becoming ready. 267 */ 268 void writebackInsts(); 269 270 /** Returns the number of valid, non-squashed instructions coming from 271 * rename to dispatch. 272 */ 273 unsigned validInstsFromRename(); 274 275 /** Reads the stall signals. */ 276 void readStallSignals(unsigned tid); 277 278 /** Checks if any of the stall conditions are currently true. */ 279 bool checkStall(unsigned tid); 280 281 /** Processes inputs and changes state accordingly. */ 282 void checkSignalsAndUpdate(unsigned tid); 283 284 /** Sorts instructions coming from rename into lists separated by thread. */ 285 void sortInsts(); 286 287 public: 288 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 289 * Writeback to run for one cycle. 290 */ 291 void tick(); 292 293 private: 294 /** Updates execution stats based on the instruction. */ 295 void updateExeInstStats(DynInstPtr &inst); 296 297 /** Pointer to main time buffer used for backwards communication. */ 298 TimeBuffer<TimeStruct> *timeBuffer; 299 300 /** Wire to write information heading to previous stages. */ 301 typename TimeBuffer<TimeStruct>::wire toFetch; 302 303 /** Wire to get commit's output from backwards time buffer. */ 304 typename TimeBuffer<TimeStruct>::wire fromCommit; 305 306 /** Wire to write information heading to previous stages. */ 307 typename TimeBuffer<TimeStruct>::wire toRename; 308 309 /** Rename instruction queue interface. */ 310 TimeBuffer<RenameStruct> *renameQueue; 311 312 /** Wire to get rename's output from rename queue. */ 313 typename TimeBuffer<RenameStruct>::wire fromRename; 314 315 /** Issue stage queue. */ 316 TimeBuffer<IssueStruct> issueToExecQueue; 317 318 /** Wire to read information from the issue stage time queue. */ 319 typename TimeBuffer<IssueStruct>::wire fromIssue; 320 321 /** 322 * IEW stage time buffer. Holds ROB indices of instructions that 323 * can be marked as completed. 324 */ 325 TimeBuffer<IEWStruct> *iewQueue; 326 327 /** Wire to write infromation heading to commit. */ 328 typename TimeBuffer<IEWStruct>::wire toCommit; 329 330 /** Queue of all instructions coming from rename this cycle. */ 331 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 332 333 /** Skid buffer between rename and IEW. */ 334 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 335 336 /** Scoreboard pointer. */ 337 Scoreboard* scoreboard; 338 339 public: 340 /** Instruction queue. */ 341 IQ instQueue; 342 343 /** Load / store queue. */ 344 LSQ ldstQueue; 345 346 /** Pointer to the functional unit pool. */ 347 FUPool *fuPool; 348 349 private: 350 /** CPU pointer. */ 351 FullCPU *cpu; 352 353 /** Records if IEW has written to the time buffer this cycle, so that the 354 * CPU can deschedule itself if there is no activity. 355 */ 356 bool wroteToTimeBuffer; 357 358 /** Source of possible stalls. */ 359 struct Stalls { 360 bool commit; 361 }; 362 363 /** Stages that are telling IEW to stall. */ 364 Stalls stalls[Impl::MaxThreads]; 365 366 /** Debug function to print instructions that are issued this cycle. */ 367 void printAvailableInsts(); 368 369 public: 370 /** Records if the LSQ needs to be updated on the next cycle, so that 371 * IEW knows if there will be activity on the next cycle. 372 */ 373 bool updateLSQNextCycle; 374 375 private: 376 /** Records if there is a fetch redirect on this cycle for each thread. */ 377 bool fetchRedirect[Impl::MaxThreads]; 378 379 /** Used to track if all instructions have been dispatched this cycle. 380 * If they have not, then blocking must have occurred, and the instructions 381 * would already be added to the skid buffer. 382 * @todo: Fix this hack. 383 */ 384 bool dispatchedAllInsts; 385 386 /** Records if the queues have been changed (inserted or issued insts), 387 * so that IEW knows to broadcast the updated amount of free entries. 388 */ 389 bool updatedQueues; 390 391 /** Commit to IEW delay, in ticks. */ 392 unsigned commitToIEWDelay; 393 394 /** Rename to IEW delay, in ticks. */ 395 unsigned renameToIEWDelay; 396 397 /** 398 * Issue to execute delay, in ticks. What this actually represents is 399 * the amount of time it takes for an instruction to wake up, be 400 * scheduled, and sent to a FU for execution. 401 */ 402 unsigned issueToExecuteDelay; 403 404 /** Width of issue's read path, in instructions. The read path is both 405 * the skid buffer and the rename instruction queue. 406 * Note to self: is this really different than issueWidth? 407 */ 408 unsigned issueReadWidth; 409 410 /** Width of issue, in instructions. */ 411 unsigned issueWidth; 412 413 /** Width of execute, in instructions. Might make more sense to break 414 * down into FP vs int. 415 */ 416 unsigned executeWidth; 417 418 /** Index into queue of instructions being written back. */ 419 unsigned wbNumInst; 420 421 /** Cycle number within the queue of instructions being written back. 422 * Used in case there are too many instructions writing back at the current 423 * cycle and writesbacks need to be scheduled for the future. See comments 424 * in instToCommit(). 425 */ 426 unsigned wbCycle; 427 428 /** Number of active threads. */ 429 unsigned numThreads; 430 431 /** Pointer to list of active threads. */ 432 std::list<unsigned> *activeThreads; 433 434 /** Maximum size of the skid buffer. */ 435 unsigned skidBufferMax; 436 437 /** Is this stage switched out. */ 438 bool switchedOut; 439 440 /** Stat for total number of idle cycles. */ 441 Stats::Scalar<> iewIdleCycles; 442 /** Stat for total number of squashing cycles. */ 443 Stats::Scalar<> iewSquashCycles; 444 /** Stat for total number of blocking cycles. */ 445 Stats::Scalar<> iewBlockCycles; 446 /** Stat for total number of unblocking cycles. */ 447 Stats::Scalar<> iewUnblockCycles; 448 /** Stat for total number of instructions dispatched. */ 449 Stats::Scalar<> iewDispatchedInsts; 450 /** Stat for total number of squashed instructions dispatch skips. */ 451 Stats::Scalar<> iewDispSquashedInsts; 452 /** Stat for total number of dispatched load instructions. */ 453 Stats::Scalar<> iewDispLoadInsts; 454 /** Stat for total number of dispatched store instructions. */ 455 Stats::Scalar<> iewDispStoreInsts; 456 /** Stat for total number of dispatched non speculative instructions. */ 457 Stats::Scalar<> iewDispNonSpecInsts; 458 /** Stat for number of times the IQ becomes full. */ 459 Stats::Scalar<> iewIQFullEvents; 460 /** Stat for number of times the LSQ becomes full. */ 461 Stats::Scalar<> iewLSQFullEvents; 462 /** Stat for total number of executed instructions. */ 463 Stats::Scalar<> iewExecutedInsts; 464 /** Stat for total number of executed load instructions. */ 465 Stats::Vector<> iewExecLoadInsts; 466 /** Stat for total number of executed store instructions. */ 467// Stats::Scalar<> iewExecStoreInsts; 468 /** Stat for total number of squashed instructions skipped at execute. */ 469 Stats::Scalar<> iewExecSquashedInsts; 470 /** Stat for total number of memory ordering violation events. */ 471 Stats::Scalar<> memOrderViolationEvents; 472 /** Stat for total number of incorrect predicted taken branches. */ 473 Stats::Scalar<> predictedTakenIncorrect; 474 /** Stat for total number of incorrect predicted not taken branches. */ 475 Stats::Scalar<> predictedNotTakenIncorrect; 476 /** Stat for total number of mispredicted branches detected at execute. */ 477 Stats::Formula branchMispredicts; 478 479 /** Number of executed software prefetches. */ 480 Stats::Vector<> exeSwp; 481 /** Number of executed nops. */ 482 Stats::Vector<> exeNop; 483 /** Number of executed meomory references. */ 484 Stats::Vector<> exeRefs; 485 /** Number of executed branches. */ 486 Stats::Vector<> exeBranches; 487 488// Stats::Vector<> issued_ops; 489/* 490 Stats::Vector<> stat_fu_busy; 491 Stats::Vector2d<> stat_fuBusy; 492 Stats::Vector<> dist_unissued; 493 Stats::Vector2d<> stat_issued_inst_type; 494*/ 495 /** Number of instructions issued per cycle. */ 496 Stats::Formula issueRate; 497 /** Number of executed store instructions. */ 498 Stats::Formula iewExecStoreInsts; 499// Stats::Formula issue_op_rate; 500// Stats::Formula fu_busy_rate; 501 /** Number of instructions sent to commit. */ 502 Stats::Vector<> iewInstsToCommit; 503 /** Number of instructions that writeback. */ 504 Stats::Vector<> writebackCount; 505 /** Number of instructions that wake consumers. */ 506 Stats::Vector<> producerInst; 507 /** Number of instructions that wake up from producers. */ 508 Stats::Vector<> consumerInst; 509 /** Number of instructions that were delayed in writing back due 510 * to resource contention. 511 */ 512 Stats::Vector<> wbPenalized; 513 514 /** Number of instructions per cycle written back. */ 515 Stats::Formula wbRate; 516 /** Average number of woken instructions per writeback. */ 517 Stats::Formula wbFanout; 518 /** Number of instructions per cycle delayed in writing back . */ 519 Stats::Formula wbPenalizedRate; 520}; 521 522#endif // __CPU_O3_IEW_HH__ 523