iew.hh revision 10333:6be8945d226b
1/* 2 * Copyright (c) 2010-2012, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_IEW_HH__ 44#define __CPU_O3_IEW_HH__ 45 46#include <queue> 47#include <set> 48 49#include "base/statistics.hh" 50#include "cpu/o3/comm.hh" 51#include "cpu/o3/lsq.hh" 52#include "cpu/o3/scoreboard.hh" 53#include "cpu/timebuf.hh" 54#include "debug/IEW.hh" 55#include "sim/probe/probe.hh" 56 57struct DerivO3CPUParams; 58class FUPool; 59 60/** 61 * DefaultIEW handles both single threaded and SMT IEW 62 * (issue/execute/writeback). It handles the dispatching of 63 * instructions to the LSQ/IQ as part of the issue stage, and has the 64 * IQ try to issue instructions each cycle. The execute latency is 65 * actually tied into the issue latency to allow the IQ to be able to 66 * do back-to-back scheduling without having to speculatively schedule 67 * instructions. This happens by having the IQ have access to the 68 * functional units, and the IQ gets the execution latencies from the 69 * FUs when it issues instructions. Instructions reach the execute 70 * stage on the last cycle of their execution, which is when the IQ 71 * knows to wake up any dependent instructions, allowing back to back 72 * scheduling. The execute portion of IEW separates memory 73 * instructions from non-memory instructions, either telling the LSQ 74 * to execute the instruction, or executing the instruction directly. 75 * The writeback portion of IEW completes the instructions by waking 76 * up any dependents, and marking the register ready on the 77 * scoreboard. 78 */ 79template<class Impl> 80class DefaultIEW 81{ 82 private: 83 //Typedefs from Impl 84 typedef typename Impl::CPUPol CPUPol; 85 typedef typename Impl::DynInstPtr DynInstPtr; 86 typedef typename Impl::O3CPU O3CPU; 87 88 typedef typename CPUPol::IQ IQ; 89 typedef typename CPUPol::RenameMap RenameMap; 90 typedef typename CPUPol::LSQ LSQ; 91 92 typedef typename CPUPol::TimeStruct TimeStruct; 93 typedef typename CPUPol::IEWStruct IEWStruct; 94 typedef typename CPUPol::RenameStruct RenameStruct; 95 typedef typename CPUPol::IssueStruct IssueStruct; 96 97 public: 98 /** Overall IEW stage status. Used to determine if the CPU can 99 * deschedule itself due to a lack of activity. 100 */ 101 enum Status { 102 Active, 103 Inactive 104 }; 105 106 /** Status for Issue, Execute, and Writeback stages. */ 107 enum StageStatus { 108 Running, 109 Blocked, 110 Idle, 111 StartSquash, 112 Squashing, 113 Unblocking 114 }; 115 116 private: 117 /** Overall stage status. */ 118 Status _status; 119 /** Dispatch status. */ 120 StageStatus dispatchStatus[Impl::MaxThreads]; 121 /** Execute status. */ 122 StageStatus exeStatus; 123 /** Writeback status. */ 124 StageStatus wbStatus; 125 126 /** Probe points. */ 127 ProbePointArg<DynInstPtr> *ppMispredict; 128 ProbePointArg<DynInstPtr> *ppDispatch; 129 130 public: 131 /** Constructs a DefaultIEW with the given parameters. */ 132 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 133 134 /** Returns the name of the DefaultIEW stage. */ 135 std::string name() const; 136 137 /** Registers statistics. */ 138 void regStats(); 139 140 /** Registers probes. */ 141 void regProbePoints(); 142 143 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 144 void startupStage(); 145 146 /** Sets main time buffer used for backwards communication. */ 147 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 148 149 /** Sets time buffer for getting instructions coming from rename. */ 150 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 151 152 /** Sets time buffer to pass on instructions to commit. */ 153 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 154 155 /** Sets pointer to list of active threads. */ 156 void setActiveThreads(std::list<ThreadID> *at_ptr); 157 158 /** Sets pointer to the scoreboard. */ 159 void setScoreboard(Scoreboard *sb_ptr); 160 161 /** Perform sanity checks after a drain. */ 162 void drainSanityCheck() const; 163 164 /** Has the stage drained? */ 165 bool isDrained() const; 166 167 /** Takes over from another CPU's thread. */ 168 void takeOverFrom(); 169 170 /** Squashes instructions in IEW for a specific thread. */ 171 void squash(ThreadID tid); 172 173 /** Wakes all dependents of a completed instruction. */ 174 void wakeDependents(DynInstPtr &inst); 175 176 /** Tells memory dependence unit that a memory instruction needs to be 177 * rescheduled. It will re-execute once replayMemInst() is called. 178 */ 179 void rescheduleMemInst(DynInstPtr &inst); 180 181 /** Re-executes all rescheduled memory instructions. */ 182 void replayMemInst(DynInstPtr &inst); 183 184 /** Moves memory instruction onto the list of cache blocked instructions */ 185 void blockMemInst(DynInstPtr &inst); 186 187 /** Notifies that the cache has become unblocked */ 188 void cacheUnblocked(); 189 190 /** Sends an instruction to commit through the time buffer. */ 191 void instToCommit(DynInstPtr &inst); 192 193 /** Inserts unused instructions of a thread into the skid buffer. */ 194 void skidInsert(ThreadID tid); 195 196 /** Returns the max of the number of entries in all of the skid buffers. */ 197 int skidCount(); 198 199 /** Returns if all of the skid buffers are empty. */ 200 bool skidsEmpty(); 201 202 /** Updates overall IEW status based on all of the stages' statuses. */ 203 void updateStatus(); 204 205 /** Resets entries of the IQ and the LSQ. */ 206 void resetEntries(); 207 208 /** Tells the CPU to wakeup if it has descheduled itself due to no 209 * activity. Used mainly by the LdWritebackEvent. 210 */ 211 void wakeCPU(); 212 213 /** Reports to the CPU that there is activity this cycle. */ 214 void activityThisCycle(); 215 216 /** Tells CPU that the IEW stage is active and running. */ 217 inline void activateStage(); 218 219 /** Tells CPU that the IEW stage is inactive and idle. */ 220 inline void deactivateStage(); 221 222 /** Returns if the LSQ has any stores to writeback. */ 223 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 224 225 /** Returns if the LSQ has any stores to writeback. */ 226 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 227 228 /** Check misprediction */ 229 void checkMisprediction(DynInstPtr &inst); 230 231 private: 232 /** Sends commit proper information for a squash due to a branch 233 * mispredict. 234 */ 235 void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 236 237 /** Sends commit proper information for a squash due to a memory order 238 * violation. 239 */ 240 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 241 242 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 243 void block(ThreadID tid); 244 245 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 246 * other stages to unblock. 247 */ 248 void unblock(ThreadID tid); 249 250 /** Determines proper actions to take given Dispatch's status. */ 251 void dispatch(ThreadID tid); 252 253 /** Dispatches instructions to IQ and LSQ. */ 254 void dispatchInsts(ThreadID tid); 255 256 /** Executes instructions. In the case of memory operations, it informs the 257 * LSQ to execute the instructions. Also handles any redirects that occur 258 * due to the executed instructions. 259 */ 260 void executeInsts(); 261 262 /** Writebacks instructions. In our model, the instruction's execute() 263 * function atomically reads registers, executes, and writes registers. 264 * Thus this writeback only wakes up dependent instructions, and informs 265 * the scoreboard of registers becoming ready. 266 */ 267 void writebackInsts(); 268 269 /** Returns the number of valid, non-squashed instructions coming from 270 * rename to dispatch. 271 */ 272 unsigned validInstsFromRename(); 273 274 /** Checks if any of the stall conditions are currently true. */ 275 bool checkStall(ThreadID tid); 276 277 /** Processes inputs and changes state accordingly. */ 278 void checkSignalsAndUpdate(ThreadID tid); 279 280 /** Removes instructions from rename from a thread's instruction list. */ 281 void emptyRenameInsts(ThreadID tid); 282 283 /** Sorts instructions coming from rename into lists separated by thread. */ 284 void sortInsts(); 285 286 public: 287 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 288 * Writeback to run for one cycle. 289 */ 290 void tick(); 291 292 private: 293 /** Updates execution stats based on the instruction. */ 294 void updateExeInstStats(DynInstPtr &inst); 295 296 /** Pointer to main time buffer used for backwards communication. */ 297 TimeBuffer<TimeStruct> *timeBuffer; 298 299 /** Wire to write information heading to previous stages. */ 300 typename TimeBuffer<TimeStruct>::wire toFetch; 301 302 /** Wire to get commit's output from backwards time buffer. */ 303 typename TimeBuffer<TimeStruct>::wire fromCommit; 304 305 /** Wire to write information heading to previous stages. */ 306 typename TimeBuffer<TimeStruct>::wire toRename; 307 308 /** Rename instruction queue interface. */ 309 TimeBuffer<RenameStruct> *renameQueue; 310 311 /** Wire to get rename's output from rename queue. */ 312 typename TimeBuffer<RenameStruct>::wire fromRename; 313 314 /** Issue stage queue. */ 315 TimeBuffer<IssueStruct> issueToExecQueue; 316 317 /** Wire to read information from the issue stage time queue. */ 318 typename TimeBuffer<IssueStruct>::wire fromIssue; 319 320 /** 321 * IEW stage time buffer. Holds ROB indices of instructions that 322 * can be marked as completed. 323 */ 324 TimeBuffer<IEWStruct> *iewQueue; 325 326 /** Wire to write infromation heading to commit. */ 327 typename TimeBuffer<IEWStruct>::wire toCommit; 328 329 /** Queue of all instructions coming from rename this cycle. */ 330 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 331 332 /** Skid buffer between rename and IEW. */ 333 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 334 335 /** Scoreboard pointer. */ 336 Scoreboard* scoreboard; 337 338 private: 339 /** CPU pointer. */ 340 O3CPU *cpu; 341 342 /** Records if IEW has written to the time buffer this cycle, so that the 343 * CPU can deschedule itself if there is no activity. 344 */ 345 bool wroteToTimeBuffer; 346 347 /** Debug function to print instructions that are issued this cycle. */ 348 void printAvailableInsts(); 349 350 public: 351 /** Instruction queue. */ 352 IQ instQueue; 353 354 /** Load / store queue. */ 355 LSQ ldstQueue; 356 357 /** Pointer to the functional unit pool. */ 358 FUPool *fuPool; 359 /** Records if the LSQ needs to be updated on the next cycle, so that 360 * IEW knows if there will be activity on the next cycle. 361 */ 362 bool updateLSQNextCycle; 363 364 private: 365 /** Records if there is a fetch redirect on this cycle for each thread. */ 366 bool fetchRedirect[Impl::MaxThreads]; 367 368 /** Records if the queues have been changed (inserted or issued insts), 369 * so that IEW knows to broadcast the updated amount of free entries. 370 */ 371 bool updatedQueues; 372 373 /** Commit to IEW delay. */ 374 Cycles commitToIEWDelay; 375 376 /** Rename to IEW delay. */ 377 Cycles renameToIEWDelay; 378 379 /** 380 * Issue to execute delay. What this actually represents is 381 * the amount of time it takes for an instruction to wake up, be 382 * scheduled, and sent to a FU for execution. 383 */ 384 Cycles issueToExecuteDelay; 385 386 /** Width of dispatch, in instructions. */ 387 unsigned dispatchWidth; 388 389 /** Width of issue, in instructions. */ 390 unsigned issueWidth; 391 392 /** Index into queue of instructions being written back. */ 393 unsigned wbNumInst; 394 395 /** Cycle number within the queue of instructions being written back. 396 * Used in case there are too many instructions writing back at the current 397 * cycle and writesbacks need to be scheduled for the future. See comments 398 * in instToCommit(). 399 */ 400 unsigned wbCycle; 401 402 /** Writeback width. */ 403 unsigned wbWidth; 404 405 /** Number of active threads. */ 406 ThreadID numThreads; 407 408 /** Pointer to list of active threads. */ 409 std::list<ThreadID> *activeThreads; 410 411 /** Maximum size of the skid buffer. */ 412 unsigned skidBufferMax; 413 414 /** Stat for total number of idle cycles. */ 415 Stats::Scalar iewIdleCycles; 416 /** Stat for total number of squashing cycles. */ 417 Stats::Scalar iewSquashCycles; 418 /** Stat for total number of blocking cycles. */ 419 Stats::Scalar iewBlockCycles; 420 /** Stat for total number of unblocking cycles. */ 421 Stats::Scalar iewUnblockCycles; 422 /** Stat for total number of instructions dispatched. */ 423 Stats::Scalar iewDispatchedInsts; 424 /** Stat for total number of squashed instructions dispatch skips. */ 425 Stats::Scalar iewDispSquashedInsts; 426 /** Stat for total number of dispatched load instructions. */ 427 Stats::Scalar iewDispLoadInsts; 428 /** Stat for total number of dispatched store instructions. */ 429 Stats::Scalar iewDispStoreInsts; 430 /** Stat for total number of dispatched non speculative instructions. */ 431 Stats::Scalar iewDispNonSpecInsts; 432 /** Stat for number of times the IQ becomes full. */ 433 Stats::Scalar iewIQFullEvents; 434 /** Stat for number of times the LSQ becomes full. */ 435 Stats::Scalar iewLSQFullEvents; 436 /** Stat for total number of memory ordering violation events. */ 437 Stats::Scalar memOrderViolationEvents; 438 /** Stat for total number of incorrect predicted taken branches. */ 439 Stats::Scalar predictedTakenIncorrect; 440 /** Stat for total number of incorrect predicted not taken branches. */ 441 Stats::Scalar predictedNotTakenIncorrect; 442 /** Stat for total number of mispredicted branches detected at execute. */ 443 Stats::Formula branchMispredicts; 444 445 /** Stat for total number of executed instructions. */ 446 Stats::Scalar iewExecutedInsts; 447 /** Stat for total number of executed load instructions. */ 448 Stats::Vector iewExecLoadInsts; 449 /** Stat for total number of executed store instructions. */ 450// Stats::Scalar iewExecStoreInsts; 451 /** Stat for total number of squashed instructions skipped at execute. */ 452 Stats::Scalar iewExecSquashedInsts; 453 /** Number of executed software prefetches. */ 454 Stats::Vector iewExecutedSwp; 455 /** Number of executed nops. */ 456 Stats::Vector iewExecutedNop; 457 /** Number of executed meomory references. */ 458 Stats::Vector iewExecutedRefs; 459 /** Number of executed branches. */ 460 Stats::Vector iewExecutedBranches; 461 /** Number of executed store instructions. */ 462 Stats::Formula iewExecStoreInsts; 463 /** Number of instructions executed per cycle. */ 464 Stats::Formula iewExecRate; 465 466 /** Number of instructions sent to commit. */ 467 Stats::Vector iewInstsToCommit; 468 /** Number of instructions that writeback. */ 469 Stats::Vector writebackCount; 470 /** Number of instructions that wake consumers. */ 471 Stats::Vector producerInst; 472 /** Number of instructions that wake up from producers. */ 473 Stats::Vector consumerInst; 474 /** Number of instructions that were delayed in writing back due 475 * to resource contention. 476 */ 477 Stats::Vector wbPenalized; 478 /** Number of instructions per cycle written back. */ 479 Stats::Formula wbRate; 480 /** Average number of woken instructions per writeback. */ 481 Stats::Formula wbFanout; 482 /** Number of instructions per cycle delayed in writing back . */ 483 Stats::Formula wbPenalizedRate; 484}; 485 486#endif // __CPU_O3_IEW_HH__ 487