iew.hh revision 9184
11689SN/A/* 27782Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37782Sminkyu.jeong@arm.com * All rights reserved 47782Sminkyu.jeong@arm.com * 57782Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67782Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77782Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87782Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97782Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107782Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117782Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127782Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137782Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 432292SN/A#ifndef __CPU_O3_IEW_HH__ 442292SN/A#define __CPU_O3_IEW_HH__ 451060SN/A 461060SN/A#include <queue> 478230Snate@binkert.org#include <set> 481060SN/A 491461SN/A#include "base/statistics.hh" 501717SN/A#include "cpu/o3/comm.hh" 518229Snate@binkert.org#include "cpu/o3/lsq.hh" 522292SN/A#include "cpu/o3/scoreboard.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 548232Snate@binkert.org#include "debug/IEW.hh" 551060SN/A 568737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 572292SN/Aclass FUPool; 582292SN/A 592292SN/A/** 602326SN/A * DefaultIEW handles both single threaded and SMT IEW 612326SN/A * (issue/execute/writeback). It handles the dispatching of 622326SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the 632326SN/A * IQ try to issue instructions each cycle. The execute latency is 642326SN/A * actually tied into the issue latency to allow the IQ to be able to 652292SN/A * do back-to-back scheduling without having to speculatively schedule 662326SN/A * instructions. This happens by having the IQ have access to the 672326SN/A * functional units, and the IQ gets the execution latencies from the 682326SN/A * FUs when it issues instructions. Instructions reach the execute 692326SN/A * stage on the last cycle of their execution, which is when the IQ 702326SN/A * knows to wake up any dependent instructions, allowing back to back 712326SN/A * scheduling. The execute portion of IEW separates memory 722326SN/A * instructions from non-memory instructions, either telling the LSQ 732326SN/A * to execute the instruction, or executing the instruction directly. 742326SN/A * The writeback portion of IEW completes the instructions by waking 752326SN/A * up any dependents, and marking the register ready on the 762326SN/A * scoreboard. 772292SN/A */ 781681SN/Atemplate<class Impl> 792292SN/Aclass DefaultIEW 801060SN/A{ 811060SN/A private: 821060SN/A //Typedefs from Impl 831061SN/A typedef typename Impl::CPUPol CPUPol; 841061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 852733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 861060SN/A 871681SN/A typedef typename CPUPol::IQ IQ; 881061SN/A typedef typename CPUPol::RenameMap RenameMap; 892292SN/A typedef typename CPUPol::LSQ LSQ; 901060SN/A 911061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 921061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 931061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 941061SN/A typedef typename CPUPol::IssueStruct IssueStruct; 951060SN/A 961060SN/A public: 972292SN/A /** Overall IEW stage status. Used to determine if the CPU can 982292SN/A * deschedule itself due to a lack of activity. 992292SN/A */ 1001060SN/A enum Status { 1012292SN/A Active, 1022292SN/A Inactive 1032292SN/A }; 1042292SN/A 1052292SN/A /** Status for Issue, Execute, and Writeback stages. */ 1062292SN/A enum StageStatus { 1071060SN/A Running, 1081060SN/A Blocked, 1091060SN/A Idle, 1102292SN/A StartSquash, 1111060SN/A Squashing, 1121060SN/A Unblocking 1131060SN/A }; 1141060SN/A 1151060SN/A private: 1162292SN/A /** Overall stage status. */ 1171060SN/A Status _status; 1182292SN/A /** Dispatch status. */ 1192292SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 1202292SN/A /** Execute status. */ 1212292SN/A StageStatus exeStatus; 1222292SN/A /** Writeback status. */ 1232292SN/A StageStatus wbStatus; 1241060SN/A 1251060SN/A public: 1262292SN/A /** Constructs a DefaultIEW with the given parameters. */ 1275529Snate@binkert.org DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 1281060SN/A 1292292SN/A /** Returns the name of the DefaultIEW stage. */ 1302292SN/A std::string name() const; 1311062SN/A 1322292SN/A /** Registers statistics. */ 1332632Sstever@eecs.umich.edu void regStats(); 1342632Sstever@eecs.umich.edu 1352292SN/A /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 1362292SN/A void initStage(); 1372292SN/A 1382292SN/A /** Sets main time buffer used for backwards communication. */ 1392632Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1402632Sstever@eecs.umich.edu 1412292SN/A /** Sets time buffer for getting instructions coming from rename. */ 1422632Sstever@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1432632Sstever@eecs.umich.edu 1442292SN/A /** Sets time buffer to pass on instructions to commit. */ 1452632Sstever@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1462632Sstever@eecs.umich.edu 1472292SN/A /** Sets pointer to list of active threads. */ 1486221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1492632Sstever@eecs.umich.edu 1502292SN/A /** Sets pointer to the scoreboard. */ 1512292SN/A void setScoreboard(Scoreboard *sb_ptr); 1522632Sstever@eecs.umich.edu 1532843Sktlim@umich.edu /** Drains IEW stage. */ 1542863Sktlim@umich.edu bool drain(); 1552843Sktlim@umich.edu 1562843Sktlim@umich.edu /** Resumes execution after a drain. */ 1572843Sktlim@umich.edu void resume(); 1582632Sstever@eecs.umich.edu 1592348SN/A /** Completes switch out of IEW stage. */ 1602843Sktlim@umich.edu void switchOut(); 1612632Sstever@eecs.umich.edu 1622348SN/A /** Takes over from another CPU's thread. */ 1632307SN/A void takeOverFrom(); 1642632Sstever@eecs.umich.edu 1652348SN/A /** Returns if IEW is switched out. */ 1662307SN/A bool isSwitchedOut() { return switchedOut; } 1672632Sstever@eecs.umich.edu 1682292SN/A /** Squashes instructions in IEW for a specific thread. */ 1696221Snate@binkert.org void squash(ThreadID tid); 1702107SN/A 1712292SN/A /** Wakes all dependents of a completed instruction. */ 1722632Sstever@eecs.umich.edu void wakeDependents(DynInstPtr &inst); 1732632Sstever@eecs.umich.edu 1742292SN/A /** Tells memory dependence unit that a memory instruction needs to be 1752292SN/A * rescheduled. It will re-execute once replayMemInst() is called. 1762292SN/A */ 1772292SN/A void rescheduleMemInst(DynInstPtr &inst); 1782292SN/A 1792292SN/A /** Re-executes all rescheduled memory instructions. */ 1802292SN/A void replayMemInst(DynInstPtr &inst); 1812292SN/A 1822292SN/A /** Sends an instruction to commit through the time buffer. */ 1832632Sstever@eecs.umich.edu void instToCommit(DynInstPtr &inst); 1842632Sstever@eecs.umich.edu 1852292SN/A /** Inserts unused instructions of a thread into the skid buffer. */ 1866221Snate@binkert.org void skidInsert(ThreadID tid); 1872292SN/A 1882292SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 1892292SN/A int skidCount(); 1902292SN/A 1912292SN/A /** Returns if all of the skid buffers are empty. */ 1922292SN/A bool skidsEmpty(); 1932292SN/A 1942292SN/A /** Updates overall IEW status based on all of the stages' statuses. */ 1952292SN/A void updateStatus(); 1962292SN/A 1972292SN/A /** Resets entries of the IQ and the LSQ. */ 1982292SN/A void resetEntries(); 1992292SN/A 2002292SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 2012292SN/A * activity. Used mainly by the LdWritebackEvent. 2022292SN/A */ 2032292SN/A void wakeCPU(); 2042292SN/A 2052292SN/A /** Reports to the CPU that there is activity this cycle. */ 2062292SN/A void activityThisCycle(); 2072292SN/A 2082292SN/A /** Tells CPU that the IEW stage is active and running. */ 2092292SN/A inline void activateStage(); 2102292SN/A 2112292SN/A /** Tells CPU that the IEW stage is inactive and idle. */ 2122292SN/A inline void deactivateStage(); 2132292SN/A 2142292SN/A /** Returns if the LSQ has any stores to writeback. */ 2152292SN/A bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2162292SN/A 2175557Sktlim@umich.edu /** Returns if the LSQ has any stores to writeback. */ 2186221Snate@binkert.org bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2195557Sktlim@umich.edu 2202820Sktlim@umich.edu void incrWb(InstSeqNum &sn) 2212820Sktlim@umich.edu { 2222820Sktlim@umich.edu if (++wbOutstanding == wbMax) 2232820Sktlim@umich.edu ableToIssue = false; 2248315Sgeoffrey.blake@arm.com DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 2252353SN/A assert(wbOutstanding <= wbMax); 2262926Sktlim@umich.edu#ifdef DEBUG 2272820Sktlim@umich.edu wbList.insert(sn); 2282820Sktlim@umich.edu#endif 2292820Sktlim@umich.edu } 2302820Sktlim@umich.edu 2312820Sktlim@umich.edu void decrWb(InstSeqNum &sn) 2322820Sktlim@umich.edu { 2332820Sktlim@umich.edu if (wbOutstanding-- == wbMax) 2342820Sktlim@umich.edu ableToIssue = true; 2357782Sminkyu.jeong@arm.com DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 2362353SN/A assert(wbOutstanding >= 0); 2372926Sktlim@umich.edu#ifdef DEBUG 2382820Sktlim@umich.edu assert(wbList.find(sn) != wbList.end()); 2392820Sktlim@umich.edu wbList.erase(sn); 2402820Sktlim@umich.edu#endif 2412820Sktlim@umich.edu } 2422820Sktlim@umich.edu 2432926Sktlim@umich.edu#ifdef DEBUG 2442820Sktlim@umich.edu std::set<InstSeqNum> wbList; 2452820Sktlim@umich.edu 2462820Sktlim@umich.edu void dumpWb() 2472820Sktlim@umich.edu { 2482820Sktlim@umich.edu std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 2492820Sktlim@umich.edu while (wb_it != wbList.end()) { 2502820Sktlim@umich.edu cprintf("[sn:%lli]\n", 2512820Sktlim@umich.edu (*wb_it)); 2522820Sktlim@umich.edu wb_it++; 2532820Sktlim@umich.edu } 2542820Sktlim@umich.edu } 2552820Sktlim@umich.edu#endif 2562820Sktlim@umich.edu 2572820Sktlim@umich.edu bool canIssue() { return ableToIssue; } 2582820Sktlim@umich.edu 2592820Sktlim@umich.edu bool ableToIssue; 2602820Sktlim@umich.edu 2617598Sminkyu.jeong@arm.com /** Check misprediction */ 2627598Sminkyu.jeong@arm.com void checkMisprediction(DynInstPtr &inst); 2637598Sminkyu.jeong@arm.com 2642632Sstever@eecs.umich.edu private: 2652292SN/A /** Sends commit proper information for a squash due to a branch 2662292SN/A * mispredict. 2672292SN/A */ 2686221Snate@binkert.org void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 2692632Sstever@eecs.umich.edu 2702292SN/A /** Sends commit proper information for a squash due to a memory order 2712292SN/A * violation. 2722292SN/A */ 2736221Snate@binkert.org void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 2742292SN/A 2752292SN/A /** Sends commit proper information for a squash due to memory becoming 2762292SN/A * blocked (younger issued instructions must be retried). 2772292SN/A */ 2786221Snate@binkert.org void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 2792292SN/A 2802292SN/A /** Sets Dispatch to blocked, and signals back to other stages to block. */ 2816221Snate@binkert.org void block(ThreadID tid); 2822292SN/A 2832292SN/A /** Unblocks Dispatch if the skid buffer is empty, and signals back to 2842292SN/A * other stages to unblock. 2852292SN/A */ 2866221Snate@binkert.org void unblock(ThreadID tid); 2872292SN/A 2882292SN/A /** Determines proper actions to take given Dispatch's status. */ 2896221Snate@binkert.org void dispatch(ThreadID tid); 2902292SN/A 2912292SN/A /** Dispatches instructions to IQ and LSQ. */ 2926221Snate@binkert.org void dispatchInsts(ThreadID tid); 2932292SN/A 2942292SN/A /** Executes instructions. In the case of memory operations, it informs the 2952292SN/A * LSQ to execute the instructions. Also handles any redirects that occur 2962292SN/A * due to the executed instructions. 2972292SN/A */ 2982632Sstever@eecs.umich.edu void executeInsts(); 2992632Sstever@eecs.umich.edu 3002292SN/A /** Writebacks instructions. In our model, the instruction's execute() 3012292SN/A * function atomically reads registers, executes, and writes registers. 3022292SN/A * Thus this writeback only wakes up dependent instructions, and informs 3032292SN/A * the scoreboard of registers becoming ready. 3042292SN/A */ 3052292SN/A void writebackInsts(); 3062292SN/A 3072292SN/A /** Returns the number of valid, non-squashed instructions coming from 3082292SN/A * rename to dispatch. 3092292SN/A */ 3102292SN/A unsigned validInstsFromRename(); 3112292SN/A 3122292SN/A /** Reads the stall signals. */ 3136221Snate@binkert.org void readStallSignals(ThreadID tid); 3142292SN/A 3152292SN/A /** Checks if any of the stall conditions are currently true. */ 3166221Snate@binkert.org bool checkStall(ThreadID tid); 3172292SN/A 3182292SN/A /** Processes inputs and changes state accordingly. */ 3196221Snate@binkert.org void checkSignalsAndUpdate(ThreadID tid); 3202292SN/A 3212702Sktlim@umich.edu /** Removes instructions from rename from a thread's instruction list. */ 3226221Snate@binkert.org void emptyRenameInsts(ThreadID tid); 3232702Sktlim@umich.edu 3242292SN/A /** Sorts instructions coming from rename into lists separated by thread. */ 3252292SN/A void sortInsts(); 3261060SN/A 3271060SN/A public: 3282292SN/A /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 3292292SN/A * Writeback to run for one cycle. 3302292SN/A */ 3312632Sstever@eecs.umich.edu void tick(); 3321060SN/A 3331060SN/A private: 3342348SN/A /** Updates execution stats based on the instruction. */ 3352301SN/A void updateExeInstStats(DynInstPtr &inst); 3361062SN/A 3372292SN/A /** Pointer to main time buffer used for backwards communication. */ 3382632Sstever@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 3391062SN/A 3402292SN/A /** Wire to write information heading to previous stages. */ 3412292SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 3421060SN/A 3431060SN/A /** Wire to get commit's output from backwards time buffer. */ 3441060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3451060SN/A 3461060SN/A /** Wire to write information heading to previous stages. */ 3471060SN/A typename TimeBuffer<TimeStruct>::wire toRename; 3481060SN/A 3491060SN/A /** Rename instruction queue interface. */ 3501060SN/A TimeBuffer<RenameStruct> *renameQueue; 3511060SN/A 3521060SN/A /** Wire to get rename's output from rename queue. */ 3531060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3541060SN/A 3551060SN/A /** Issue stage queue. */ 3561060SN/A TimeBuffer<IssueStruct> issueToExecQueue; 3571060SN/A 3581060SN/A /** Wire to read information from the issue stage time queue. */ 3591060SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 3601060SN/A 3611060SN/A /** 3621060SN/A * IEW stage time buffer. Holds ROB indices of instructions that 3631060SN/A * can be marked as completed. 3641060SN/A */ 3651060SN/A TimeBuffer<IEWStruct> *iewQueue; 3661060SN/A 3671060SN/A /** Wire to write infromation heading to commit. */ 3681060SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 3691060SN/A 3702292SN/A /** Queue of all instructions coming from rename this cycle. */ 3712292SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3722292SN/A 3731060SN/A /** Skid buffer between rename and IEW. */ 3742292SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 3751060SN/A 3762292SN/A /** Scoreboard pointer. */ 3772292SN/A Scoreboard* scoreboard; 3782292SN/A 3791681SN/A private: 3802292SN/A /** CPU pointer. */ 3812733Sktlim@umich.edu O3CPU *cpu; 3821060SN/A 3832292SN/A /** Records if IEW has written to the time buffer this cycle, so that the 3842292SN/A * CPU can deschedule itself if there is no activity. 3852292SN/A */ 3862292SN/A bool wroteToTimeBuffer; 3872292SN/A 3882292SN/A /** Source of possible stalls. */ 3892292SN/A struct Stalls { 3902292SN/A bool commit; 3912292SN/A }; 3922292SN/A 3932292SN/A /** Stages that are telling IEW to stall. */ 3942292SN/A Stalls stalls[Impl::MaxThreads]; 3952292SN/A 3962292SN/A /** Debug function to print instructions that are issued this cycle. */ 3972292SN/A void printAvailableInsts(); 3982292SN/A 3992292SN/A public: 4004329Sktlim@umich.edu /** Instruction queue. */ 4014329Sktlim@umich.edu IQ instQueue; 4024329Sktlim@umich.edu 4034329Sktlim@umich.edu /** Load / store queue. */ 4044329Sktlim@umich.edu LSQ ldstQueue; 4054329Sktlim@umich.edu 4064329Sktlim@umich.edu /** Pointer to the functional unit pool. */ 4074329Sktlim@umich.edu FUPool *fuPool; 4082292SN/A /** Records if the LSQ needs to be updated on the next cycle, so that 4092292SN/A * IEW knows if there will be activity on the next cycle. 4102292SN/A */ 4112292SN/A bool updateLSQNextCycle; 4122292SN/A 4131060SN/A private: 4142292SN/A /** Records if there is a fetch redirect on this cycle for each thread. */ 4152292SN/A bool fetchRedirect[Impl::MaxThreads]; 4162292SN/A 4172292SN/A /** Records if the queues have been changed (inserted or issued insts), 4182292SN/A * so that IEW knows to broadcast the updated amount of free entries. 4192292SN/A */ 4202292SN/A bool updatedQueues; 4212292SN/A 4229184Sandreas.hansson@arm.com /** Commit to IEW delay. */ 4239184Sandreas.hansson@arm.com Cycles commitToIEWDelay; 4241060SN/A 4259184Sandreas.hansson@arm.com /** Rename to IEW delay. */ 4269184Sandreas.hansson@arm.com Cycles renameToIEWDelay; 4271060SN/A 4281060SN/A /** 4299184Sandreas.hansson@arm.com * Issue to execute delay. What this actually represents is 4301060SN/A * the amount of time it takes for an instruction to wake up, be 4311060SN/A * scheduled, and sent to a FU for execution. 4321060SN/A */ 4339184Sandreas.hansson@arm.com Cycles issueToExecuteDelay; 4341060SN/A 4352820Sktlim@umich.edu /** Width of dispatch, in instructions. */ 4362820Sktlim@umich.edu unsigned dispatchWidth; 4371060SN/A 4381060SN/A /** Width of issue, in instructions. */ 4391060SN/A unsigned issueWidth; 4401060SN/A 4412292SN/A /** Index into queue of instructions being written back. */ 4422292SN/A unsigned wbNumInst; 4432292SN/A 4442292SN/A /** Cycle number within the queue of instructions being written back. 4452292SN/A * Used in case there are too many instructions writing back at the current 4462292SN/A * cycle and writesbacks need to be scheduled for the future. See comments 4472292SN/A * in instToCommit(). 4481060SN/A */ 4492292SN/A unsigned wbCycle; 4501060SN/A 4512820Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4523125Sktlim@umich.edu 4533125Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4542353SN/A int wbOutstanding; 4552820Sktlim@umich.edu 4562820Sktlim@umich.edu /** Writeback width. */ 4572820Sktlim@umich.edu unsigned wbWidth; 4582820Sktlim@umich.edu 4592820Sktlim@umich.edu /** Writeback width * writeback depth, where writeback depth is 4602820Sktlim@umich.edu * the number of cycles of writing back instructions that can be 4612820Sktlim@umich.edu * buffered. */ 4622820Sktlim@umich.edu unsigned wbMax; 4632820Sktlim@umich.edu 4642292SN/A /** Number of active threads. */ 4656221Snate@binkert.org ThreadID numThreads; 4662292SN/A 4672292SN/A /** Pointer to list of active threads. */ 4686221Snate@binkert.org std::list<ThreadID> *activeThreads; 4692292SN/A 4702292SN/A /** Maximum size of the skid buffer. */ 4712292SN/A unsigned skidBufferMax; 4722292SN/A 4732348SN/A /** Is this stage switched out. */ 4742307SN/A bool switchedOut; 4752307SN/A 4762292SN/A /** Stat for total number of idle cycles. */ 4775999Snate@binkert.org Stats::Scalar iewIdleCycles; 4782292SN/A /** Stat for total number of squashing cycles. */ 4795999Snate@binkert.org Stats::Scalar iewSquashCycles; 4802292SN/A /** Stat for total number of blocking cycles. */ 4815999Snate@binkert.org Stats::Scalar iewBlockCycles; 4822292SN/A /** Stat for total number of unblocking cycles. */ 4835999Snate@binkert.org Stats::Scalar iewUnblockCycles; 4842292SN/A /** Stat for total number of instructions dispatched. */ 4855999Snate@binkert.org Stats::Scalar iewDispatchedInsts; 4862292SN/A /** Stat for total number of squashed instructions dispatch skips. */ 4875999Snate@binkert.org Stats::Scalar iewDispSquashedInsts; 4882292SN/A /** Stat for total number of dispatched load instructions. */ 4895999Snate@binkert.org Stats::Scalar iewDispLoadInsts; 4902292SN/A /** Stat for total number of dispatched store instructions. */ 4915999Snate@binkert.org Stats::Scalar iewDispStoreInsts; 4922292SN/A /** Stat for total number of dispatched non speculative instructions. */ 4935999Snate@binkert.org Stats::Scalar iewDispNonSpecInsts; 4942292SN/A /** Stat for number of times the IQ becomes full. */ 4955999Snate@binkert.org Stats::Scalar iewIQFullEvents; 4962292SN/A /** Stat for number of times the LSQ becomes full. */ 4975999Snate@binkert.org Stats::Scalar iewLSQFullEvents; 4982292SN/A /** Stat for total number of memory ordering violation events. */ 4995999Snate@binkert.org Stats::Scalar memOrderViolationEvents; 5002292SN/A /** Stat for total number of incorrect predicted taken branches. */ 5015999Snate@binkert.org Stats::Scalar predictedTakenIncorrect; 5022292SN/A /** Stat for total number of incorrect predicted not taken branches. */ 5035999Snate@binkert.org Stats::Scalar predictedNotTakenIncorrect; 5042292SN/A /** Stat for total number of mispredicted branches detected at execute. */ 5052292SN/A Stats::Formula branchMispredicts; 5062301SN/A 5072727Sktlim@umich.edu /** Stat for total number of executed instructions. */ 5085999Snate@binkert.org Stats::Scalar iewExecutedInsts; 5092727Sktlim@umich.edu /** Stat for total number of executed load instructions. */ 5105999Snate@binkert.org Stats::Vector iewExecLoadInsts; 5112353SN/A /** Stat for total number of executed store instructions. */ 5125999Snate@binkert.org// Stats::Scalar iewExecStoreInsts; 5132727Sktlim@umich.edu /** Stat for total number of squashed instructions skipped at execute. */ 5145999Snate@binkert.org Stats::Scalar iewExecSquashedInsts; 5152348SN/A /** Number of executed software prefetches. */ 5165999Snate@binkert.org Stats::Vector iewExecutedSwp; 5172348SN/A /** Number of executed nops. */ 5185999Snate@binkert.org Stats::Vector iewExecutedNop; 5192348SN/A /** Number of executed meomory references. */ 5205999Snate@binkert.org Stats::Vector iewExecutedRefs; 5212348SN/A /** Number of executed branches. */ 5225999Snate@binkert.org Stats::Vector iewExecutedBranches; 5232348SN/A /** Number of executed store instructions. */ 5242301SN/A Stats::Formula iewExecStoreInsts; 5252727Sktlim@umich.edu /** Number of instructions executed per cycle. */ 5262727Sktlim@umich.edu Stats::Formula iewExecRate; 5272727Sktlim@umich.edu 5282348SN/A /** Number of instructions sent to commit. */ 5295999Snate@binkert.org Stats::Vector iewInstsToCommit; 5302348SN/A /** Number of instructions that writeback. */ 5315999Snate@binkert.org Stats::Vector writebackCount; 5322348SN/A /** Number of instructions that wake consumers. */ 5335999Snate@binkert.org Stats::Vector producerInst; 5342348SN/A /** Number of instructions that wake up from producers. */ 5355999Snate@binkert.org Stats::Vector consumerInst; 5362348SN/A /** Number of instructions that were delayed in writing back due 5372348SN/A * to resource contention. 5382348SN/A */ 5395999Snate@binkert.org Stats::Vector wbPenalized; 5402348SN/A /** Number of instructions per cycle written back. */ 5412326SN/A Stats::Formula wbRate; 5422348SN/A /** Average number of woken instructions per writeback. */ 5432326SN/A Stats::Formula wbFanout; 5442348SN/A /** Number of instructions per cycle delayed in writing back . */ 5452326SN/A Stats::Formula wbPenalizedRate; 5461060SN/A}; 5471060SN/A 5482292SN/A#endif // __CPU_O3_IEW_HH__ 549