iew.hh revision 7782
11689SN/A/* 27782Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37782Sminkyu.jeong@arm.com * All rights reserved 47782Sminkyu.jeong@arm.com * 57782Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67782Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77782Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87782Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97782Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107782Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117782Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127782Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137782Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 432292SN/A#ifndef __CPU_O3_IEW_HH__ 442292SN/A#define __CPU_O3_IEW_HH__ 451060SN/A 461060SN/A#include <queue> 471060SN/A 481461SN/A#include "base/statistics.hh" 491060SN/A#include "base/timebuf.hh" 506221Snate@binkert.org#include "config/full_system.hh" 511717SN/A#include "cpu/o3/comm.hh" 522292SN/A#include "cpu/o3/scoreboard.hh" 532292SN/A#include "cpu/o3/lsq.hh" 541060SN/A 555529Snate@binkert.orgclass DerivO3CPUParams; 562292SN/Aclass FUPool; 572292SN/A 582292SN/A/** 592326SN/A * DefaultIEW handles both single threaded and SMT IEW 602326SN/A * (issue/execute/writeback). It handles the dispatching of 612326SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the 622326SN/A * IQ try to issue instructions each cycle. The execute latency is 632326SN/A * actually tied into the issue latency to allow the IQ to be able to 642292SN/A * do back-to-back scheduling without having to speculatively schedule 652326SN/A * instructions. This happens by having the IQ have access to the 662326SN/A * functional units, and the IQ gets the execution latencies from the 672326SN/A * FUs when it issues instructions. Instructions reach the execute 682326SN/A * stage on the last cycle of their execution, which is when the IQ 692326SN/A * knows to wake up any dependent instructions, allowing back to back 702326SN/A * scheduling. The execute portion of IEW separates memory 712326SN/A * instructions from non-memory instructions, either telling the LSQ 722326SN/A * to execute the instruction, or executing the instruction directly. 732326SN/A * The writeback portion of IEW completes the instructions by waking 742326SN/A * up any dependents, and marking the register ready on the 752326SN/A * scoreboard. 762292SN/A */ 771681SN/Atemplate<class Impl> 782292SN/Aclass DefaultIEW 791060SN/A{ 801060SN/A private: 811060SN/A //Typedefs from Impl 821061SN/A typedef typename Impl::CPUPol CPUPol; 831061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 842733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 851060SN/A 861681SN/A typedef typename CPUPol::IQ IQ; 871061SN/A typedef typename CPUPol::RenameMap RenameMap; 882292SN/A typedef typename CPUPol::LSQ LSQ; 891060SN/A 901061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 911061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 921061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 931061SN/A typedef typename CPUPol::IssueStruct IssueStruct; 941060SN/A 952733Sktlim@umich.edu friend class Impl::O3CPU; 962292SN/A friend class CPUPol::IQ; 972292SN/A 981060SN/A public: 992292SN/A /** Overall IEW stage status. Used to determine if the CPU can 1002292SN/A * deschedule itself due to a lack of activity. 1012292SN/A */ 1021060SN/A enum Status { 1032292SN/A Active, 1042292SN/A Inactive 1052292SN/A }; 1062292SN/A 1072292SN/A /** Status for Issue, Execute, and Writeback stages. */ 1082292SN/A enum StageStatus { 1091060SN/A Running, 1101060SN/A Blocked, 1111060SN/A Idle, 1122292SN/A StartSquash, 1131060SN/A Squashing, 1141060SN/A Unblocking 1151060SN/A }; 1161060SN/A 1171060SN/A private: 1182292SN/A /** Overall stage status. */ 1191060SN/A Status _status; 1202292SN/A /** Dispatch status. */ 1212292SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 1222292SN/A /** Execute status. */ 1232292SN/A StageStatus exeStatus; 1242292SN/A /** Writeback status. */ 1252292SN/A StageStatus wbStatus; 1261060SN/A 1271060SN/A public: 1282292SN/A /** Constructs a DefaultIEW with the given parameters. */ 1295529Snate@binkert.org DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 1301060SN/A 1312292SN/A /** Returns the name of the DefaultIEW stage. */ 1322292SN/A std::string name() const; 1331062SN/A 1342292SN/A /** Registers statistics. */ 1352632Sstever@eecs.umich.edu void regStats(); 1362632Sstever@eecs.umich.edu 1372292SN/A /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 1382292SN/A void initStage(); 1392292SN/A 1402871Sktlim@umich.edu /** Returns the dcache port. */ 1412871Sktlim@umich.edu Port *getDcachePort() { return ldstQueue.getDcachePort(); } 1422871Sktlim@umich.edu 1432292SN/A /** Sets main time buffer used for backwards communication. */ 1442632Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1452632Sstever@eecs.umich.edu 1462292SN/A /** Sets time buffer for getting instructions coming from rename. */ 1472632Sstever@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1482632Sstever@eecs.umich.edu 1492292SN/A /** Sets time buffer to pass on instructions to commit. */ 1502632Sstever@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1512632Sstever@eecs.umich.edu 1522292SN/A /** Sets pointer to list of active threads. */ 1536221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1542632Sstever@eecs.umich.edu 1552292SN/A /** Sets pointer to the scoreboard. */ 1562292SN/A void setScoreboard(Scoreboard *sb_ptr); 1572632Sstever@eecs.umich.edu 1582843Sktlim@umich.edu /** Drains IEW stage. */ 1592863Sktlim@umich.edu bool drain(); 1602843Sktlim@umich.edu 1612843Sktlim@umich.edu /** Resumes execution after a drain. */ 1622843Sktlim@umich.edu void resume(); 1632632Sstever@eecs.umich.edu 1642348SN/A /** Completes switch out of IEW stage. */ 1652843Sktlim@umich.edu void switchOut(); 1662632Sstever@eecs.umich.edu 1672348SN/A /** Takes over from another CPU's thread. */ 1682307SN/A void takeOverFrom(); 1692632Sstever@eecs.umich.edu 1702348SN/A /** Returns if IEW is switched out. */ 1712307SN/A bool isSwitchedOut() { return switchedOut; } 1722632Sstever@eecs.umich.edu 1732292SN/A /** Squashes instructions in IEW for a specific thread. */ 1746221Snate@binkert.org void squash(ThreadID tid); 1752107SN/A 1762292SN/A /** Wakes all dependents of a completed instruction. */ 1772632Sstever@eecs.umich.edu void wakeDependents(DynInstPtr &inst); 1782632Sstever@eecs.umich.edu 1792292SN/A /** Tells memory dependence unit that a memory instruction needs to be 1802292SN/A * rescheduled. It will re-execute once replayMemInst() is called. 1812292SN/A */ 1822292SN/A void rescheduleMemInst(DynInstPtr &inst); 1832292SN/A 1842292SN/A /** Re-executes all rescheduled memory instructions. */ 1852292SN/A void replayMemInst(DynInstPtr &inst); 1862292SN/A 1872292SN/A /** Sends an instruction to commit through the time buffer. */ 1882632Sstever@eecs.umich.edu void instToCommit(DynInstPtr &inst); 1892632Sstever@eecs.umich.edu 1902292SN/A /** Inserts unused instructions of a thread into the skid buffer. */ 1916221Snate@binkert.org void skidInsert(ThreadID tid); 1922292SN/A 1932292SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 1942292SN/A int skidCount(); 1952292SN/A 1962292SN/A /** Returns if all of the skid buffers are empty. */ 1972292SN/A bool skidsEmpty(); 1982292SN/A 1992292SN/A /** Updates overall IEW status based on all of the stages' statuses. */ 2002292SN/A void updateStatus(); 2012292SN/A 2022292SN/A /** Resets entries of the IQ and the LSQ. */ 2032292SN/A void resetEntries(); 2042292SN/A 2052292SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 2062292SN/A * activity. Used mainly by the LdWritebackEvent. 2072292SN/A */ 2082292SN/A void wakeCPU(); 2092292SN/A 2102292SN/A /** Reports to the CPU that there is activity this cycle. */ 2112292SN/A void activityThisCycle(); 2122292SN/A 2132292SN/A /** Tells CPU that the IEW stage is active and running. */ 2142292SN/A inline void activateStage(); 2152292SN/A 2162292SN/A /** Tells CPU that the IEW stage is inactive and idle. */ 2172292SN/A inline void deactivateStage(); 2182292SN/A 2192292SN/A /** Returns if the LSQ has any stores to writeback. */ 2202292SN/A bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2212292SN/A 2225557Sktlim@umich.edu /** Returns if the LSQ has any stores to writeback. */ 2236221Snate@binkert.org bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2245557Sktlim@umich.edu 2252820Sktlim@umich.edu void incrWb(InstSeqNum &sn) 2262820Sktlim@umich.edu { 2272820Sktlim@umich.edu if (++wbOutstanding == wbMax) 2282820Sktlim@umich.edu ableToIssue = false; 2292820Sktlim@umich.edu DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 2302353SN/A assert(wbOutstanding <= wbMax); 2312926Sktlim@umich.edu#ifdef DEBUG 2322820Sktlim@umich.edu wbList.insert(sn); 2332820Sktlim@umich.edu#endif 2342820Sktlim@umich.edu } 2352820Sktlim@umich.edu 2362820Sktlim@umich.edu void decrWb(InstSeqNum &sn) 2372820Sktlim@umich.edu { 2382820Sktlim@umich.edu if (wbOutstanding-- == wbMax) 2392820Sktlim@umich.edu ableToIssue = true; 2407782Sminkyu.jeong@arm.com DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 2412353SN/A assert(wbOutstanding >= 0); 2422926Sktlim@umich.edu#ifdef DEBUG 2432820Sktlim@umich.edu assert(wbList.find(sn) != wbList.end()); 2442820Sktlim@umich.edu wbList.erase(sn); 2452820Sktlim@umich.edu#endif 2462820Sktlim@umich.edu } 2472820Sktlim@umich.edu 2482926Sktlim@umich.edu#ifdef DEBUG 2492820Sktlim@umich.edu std::set<InstSeqNum> wbList; 2502820Sktlim@umich.edu 2512820Sktlim@umich.edu void dumpWb() 2522820Sktlim@umich.edu { 2532820Sktlim@umich.edu std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 2542820Sktlim@umich.edu while (wb_it != wbList.end()) { 2552820Sktlim@umich.edu cprintf("[sn:%lli]\n", 2562820Sktlim@umich.edu (*wb_it)); 2572820Sktlim@umich.edu wb_it++; 2582820Sktlim@umich.edu } 2592820Sktlim@umich.edu } 2602820Sktlim@umich.edu#endif 2612820Sktlim@umich.edu 2622820Sktlim@umich.edu bool canIssue() { return ableToIssue; } 2632820Sktlim@umich.edu 2642820Sktlim@umich.edu bool ableToIssue; 2652820Sktlim@umich.edu 2667598Sminkyu.jeong@arm.com /** Check misprediction */ 2677598Sminkyu.jeong@arm.com void checkMisprediction(DynInstPtr &inst); 2687598Sminkyu.jeong@arm.com 2692632Sstever@eecs.umich.edu private: 2702292SN/A /** Sends commit proper information for a squash due to a branch 2712292SN/A * mispredict. 2722292SN/A */ 2736221Snate@binkert.org void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 2742632Sstever@eecs.umich.edu 2752292SN/A /** Sends commit proper information for a squash due to a memory order 2762292SN/A * violation. 2772292SN/A */ 2786221Snate@binkert.org void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 2792292SN/A 2802292SN/A /** Sends commit proper information for a squash due to memory becoming 2812292SN/A * blocked (younger issued instructions must be retried). 2822292SN/A */ 2836221Snate@binkert.org void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 2842292SN/A 2852292SN/A /** Sets Dispatch to blocked, and signals back to other stages to block. */ 2866221Snate@binkert.org void block(ThreadID tid); 2872292SN/A 2882292SN/A /** Unblocks Dispatch if the skid buffer is empty, and signals back to 2892292SN/A * other stages to unblock. 2902292SN/A */ 2916221Snate@binkert.org void unblock(ThreadID tid); 2922292SN/A 2932292SN/A /** Determines proper actions to take given Dispatch's status. */ 2946221Snate@binkert.org void dispatch(ThreadID tid); 2952292SN/A 2962292SN/A /** Dispatches instructions to IQ and LSQ. */ 2976221Snate@binkert.org void dispatchInsts(ThreadID tid); 2982292SN/A 2992292SN/A /** Executes instructions. In the case of memory operations, it informs the 3002292SN/A * LSQ to execute the instructions. Also handles any redirects that occur 3012292SN/A * due to the executed instructions. 3022292SN/A */ 3032632Sstever@eecs.umich.edu void executeInsts(); 3042632Sstever@eecs.umich.edu 3052292SN/A /** Writebacks instructions. In our model, the instruction's execute() 3062292SN/A * function atomically reads registers, executes, and writes registers. 3072292SN/A * Thus this writeback only wakes up dependent instructions, and informs 3082292SN/A * the scoreboard of registers becoming ready. 3092292SN/A */ 3102292SN/A void writebackInsts(); 3112292SN/A 3122292SN/A /** Returns the number of valid, non-squashed instructions coming from 3132292SN/A * rename to dispatch. 3142292SN/A */ 3152292SN/A unsigned validInstsFromRename(); 3162292SN/A 3172292SN/A /** Reads the stall signals. */ 3186221Snate@binkert.org void readStallSignals(ThreadID tid); 3192292SN/A 3202292SN/A /** Checks if any of the stall conditions are currently true. */ 3216221Snate@binkert.org bool checkStall(ThreadID tid); 3222292SN/A 3232292SN/A /** Processes inputs and changes state accordingly. */ 3246221Snate@binkert.org void checkSignalsAndUpdate(ThreadID tid); 3252292SN/A 3262702Sktlim@umich.edu /** Removes instructions from rename from a thread's instruction list. */ 3276221Snate@binkert.org void emptyRenameInsts(ThreadID tid); 3282702Sktlim@umich.edu 3292292SN/A /** Sorts instructions coming from rename into lists separated by thread. */ 3302292SN/A void sortInsts(); 3311060SN/A 3321060SN/A public: 3332292SN/A /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 3342292SN/A * Writeback to run for one cycle. 3352292SN/A */ 3362632Sstever@eecs.umich.edu void tick(); 3371060SN/A 3381060SN/A private: 3392348SN/A /** Updates execution stats based on the instruction. */ 3402301SN/A void updateExeInstStats(DynInstPtr &inst); 3411062SN/A 3422292SN/A /** Pointer to main time buffer used for backwards communication. */ 3432632Sstever@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 3441062SN/A 3452292SN/A /** Wire to write information heading to previous stages. */ 3462292SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 3471060SN/A 3481060SN/A /** Wire to get commit's output from backwards time buffer. */ 3491060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3501060SN/A 3511060SN/A /** Wire to write information heading to previous stages. */ 3521060SN/A typename TimeBuffer<TimeStruct>::wire toRename; 3531060SN/A 3541060SN/A /** Rename instruction queue interface. */ 3551060SN/A TimeBuffer<RenameStruct> *renameQueue; 3561060SN/A 3571060SN/A /** Wire to get rename's output from rename queue. */ 3581060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3591060SN/A 3601060SN/A /** Issue stage queue. */ 3611060SN/A TimeBuffer<IssueStruct> issueToExecQueue; 3621060SN/A 3631060SN/A /** Wire to read information from the issue stage time queue. */ 3641060SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 3651060SN/A 3661060SN/A /** 3671060SN/A * IEW stage time buffer. Holds ROB indices of instructions that 3681060SN/A * can be marked as completed. 3691060SN/A */ 3701060SN/A TimeBuffer<IEWStruct> *iewQueue; 3711060SN/A 3721060SN/A /** Wire to write infromation heading to commit. */ 3731060SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 3741060SN/A 3752292SN/A /** Queue of all instructions coming from rename this cycle. */ 3762292SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3772292SN/A 3781060SN/A /** Skid buffer between rename and IEW. */ 3792292SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 3801060SN/A 3812292SN/A /** Scoreboard pointer. */ 3822292SN/A Scoreboard* scoreboard; 3832292SN/A 3841681SN/A private: 3852292SN/A /** CPU pointer. */ 3862733Sktlim@umich.edu O3CPU *cpu; 3871060SN/A 3882292SN/A /** Records if IEW has written to the time buffer this cycle, so that the 3892292SN/A * CPU can deschedule itself if there is no activity. 3902292SN/A */ 3912292SN/A bool wroteToTimeBuffer; 3922292SN/A 3932292SN/A /** Source of possible stalls. */ 3942292SN/A struct Stalls { 3952292SN/A bool commit; 3962292SN/A }; 3972292SN/A 3982292SN/A /** Stages that are telling IEW to stall. */ 3992292SN/A Stalls stalls[Impl::MaxThreads]; 4002292SN/A 4012292SN/A /** Debug function to print instructions that are issued this cycle. */ 4022292SN/A void printAvailableInsts(); 4032292SN/A 4042292SN/A public: 4054329Sktlim@umich.edu /** Instruction queue. */ 4064329Sktlim@umich.edu IQ instQueue; 4074329Sktlim@umich.edu 4084329Sktlim@umich.edu /** Load / store queue. */ 4094329Sktlim@umich.edu LSQ ldstQueue; 4104329Sktlim@umich.edu 4114329Sktlim@umich.edu /** Pointer to the functional unit pool. */ 4124329Sktlim@umich.edu FUPool *fuPool; 4132292SN/A /** Records if the LSQ needs to be updated on the next cycle, so that 4142292SN/A * IEW knows if there will be activity on the next cycle. 4152292SN/A */ 4162292SN/A bool updateLSQNextCycle; 4172292SN/A 4181060SN/A private: 4192292SN/A /** Records if there is a fetch redirect on this cycle for each thread. */ 4202292SN/A bool fetchRedirect[Impl::MaxThreads]; 4212292SN/A 4222292SN/A /** Records if the queues have been changed (inserted or issued insts), 4232292SN/A * so that IEW knows to broadcast the updated amount of free entries. 4242292SN/A */ 4252292SN/A bool updatedQueues; 4262292SN/A 4271060SN/A /** Commit to IEW delay, in ticks. */ 4281060SN/A unsigned commitToIEWDelay; 4291060SN/A 4301060SN/A /** Rename to IEW delay, in ticks. */ 4311060SN/A unsigned renameToIEWDelay; 4321060SN/A 4331060SN/A /** 4341060SN/A * Issue to execute delay, in ticks. What this actually represents is 4351060SN/A * the amount of time it takes for an instruction to wake up, be 4361060SN/A * scheduled, and sent to a FU for execution. 4371060SN/A */ 4381060SN/A unsigned issueToExecuteDelay; 4391060SN/A 4402820Sktlim@umich.edu /** Width of dispatch, in instructions. */ 4412820Sktlim@umich.edu unsigned dispatchWidth; 4421060SN/A 4431060SN/A /** Width of issue, in instructions. */ 4441060SN/A unsigned issueWidth; 4451060SN/A 4462292SN/A /** Index into queue of instructions being written back. */ 4472292SN/A unsigned wbNumInst; 4482292SN/A 4492292SN/A /** Cycle number within the queue of instructions being written back. 4502292SN/A * Used in case there are too many instructions writing back at the current 4512292SN/A * cycle and writesbacks need to be scheduled for the future. See comments 4522292SN/A * in instToCommit(). 4531060SN/A */ 4542292SN/A unsigned wbCycle; 4551060SN/A 4562820Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4573125Sktlim@umich.edu 4583125Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4592353SN/A int wbOutstanding; 4602820Sktlim@umich.edu 4612820Sktlim@umich.edu /** Writeback width. */ 4622820Sktlim@umich.edu unsigned wbWidth; 4632820Sktlim@umich.edu 4642820Sktlim@umich.edu /** Writeback width * writeback depth, where writeback depth is 4652820Sktlim@umich.edu * the number of cycles of writing back instructions that can be 4662820Sktlim@umich.edu * buffered. */ 4672820Sktlim@umich.edu unsigned wbMax; 4682820Sktlim@umich.edu 4692292SN/A /** Number of active threads. */ 4706221Snate@binkert.org ThreadID numThreads; 4712292SN/A 4722292SN/A /** Pointer to list of active threads. */ 4736221Snate@binkert.org std::list<ThreadID> *activeThreads; 4742292SN/A 4752292SN/A /** Maximum size of the skid buffer. */ 4762292SN/A unsigned skidBufferMax; 4772292SN/A 4782348SN/A /** Is this stage switched out. */ 4792307SN/A bool switchedOut; 4802307SN/A 4812292SN/A /** Stat for total number of idle cycles. */ 4825999Snate@binkert.org Stats::Scalar iewIdleCycles; 4832292SN/A /** Stat for total number of squashing cycles. */ 4845999Snate@binkert.org Stats::Scalar iewSquashCycles; 4852292SN/A /** Stat for total number of blocking cycles. */ 4865999Snate@binkert.org Stats::Scalar iewBlockCycles; 4872292SN/A /** Stat for total number of unblocking cycles. */ 4885999Snate@binkert.org Stats::Scalar iewUnblockCycles; 4892292SN/A /** Stat for total number of instructions dispatched. */ 4905999Snate@binkert.org Stats::Scalar iewDispatchedInsts; 4912292SN/A /** Stat for total number of squashed instructions dispatch skips. */ 4925999Snate@binkert.org Stats::Scalar iewDispSquashedInsts; 4932292SN/A /** Stat for total number of dispatched load instructions. */ 4945999Snate@binkert.org Stats::Scalar iewDispLoadInsts; 4952292SN/A /** Stat for total number of dispatched store instructions. */ 4965999Snate@binkert.org Stats::Scalar iewDispStoreInsts; 4972292SN/A /** Stat for total number of dispatched non speculative instructions. */ 4985999Snate@binkert.org Stats::Scalar iewDispNonSpecInsts; 4992292SN/A /** Stat for number of times the IQ becomes full. */ 5005999Snate@binkert.org Stats::Scalar iewIQFullEvents; 5012292SN/A /** Stat for number of times the LSQ becomes full. */ 5025999Snate@binkert.org Stats::Scalar iewLSQFullEvents; 5032292SN/A /** Stat for total number of memory ordering violation events. */ 5045999Snate@binkert.org Stats::Scalar memOrderViolationEvents; 5052292SN/A /** Stat for total number of incorrect predicted taken branches. */ 5065999Snate@binkert.org Stats::Scalar predictedTakenIncorrect; 5072292SN/A /** Stat for total number of incorrect predicted not taken branches. */ 5085999Snate@binkert.org Stats::Scalar predictedNotTakenIncorrect; 5092292SN/A /** Stat for total number of mispredicted branches detected at execute. */ 5102292SN/A Stats::Formula branchMispredicts; 5112301SN/A 5122727Sktlim@umich.edu /** Stat for total number of executed instructions. */ 5135999Snate@binkert.org Stats::Scalar iewExecutedInsts; 5142727Sktlim@umich.edu /** Stat for total number of executed load instructions. */ 5155999Snate@binkert.org Stats::Vector iewExecLoadInsts; 5162353SN/A /** Stat for total number of executed store instructions. */ 5175999Snate@binkert.org// Stats::Scalar iewExecStoreInsts; 5182727Sktlim@umich.edu /** Stat for total number of squashed instructions skipped at execute. */ 5195999Snate@binkert.org Stats::Scalar iewExecSquashedInsts; 5202348SN/A /** Number of executed software prefetches. */ 5215999Snate@binkert.org Stats::Vector iewExecutedSwp; 5222348SN/A /** Number of executed nops. */ 5235999Snate@binkert.org Stats::Vector iewExecutedNop; 5242348SN/A /** Number of executed meomory references. */ 5255999Snate@binkert.org Stats::Vector iewExecutedRefs; 5262348SN/A /** Number of executed branches. */ 5275999Snate@binkert.org Stats::Vector iewExecutedBranches; 5282348SN/A /** Number of executed store instructions. */ 5292301SN/A Stats::Formula iewExecStoreInsts; 5302727Sktlim@umich.edu /** Number of instructions executed per cycle. */ 5312727Sktlim@umich.edu Stats::Formula iewExecRate; 5322727Sktlim@umich.edu 5332348SN/A /** Number of instructions sent to commit. */ 5345999Snate@binkert.org Stats::Vector iewInstsToCommit; 5352348SN/A /** Number of instructions that writeback. */ 5365999Snate@binkert.org Stats::Vector writebackCount; 5372348SN/A /** Number of instructions that wake consumers. */ 5385999Snate@binkert.org Stats::Vector producerInst; 5392348SN/A /** Number of instructions that wake up from producers. */ 5405999Snate@binkert.org Stats::Vector consumerInst; 5412348SN/A /** Number of instructions that were delayed in writing back due 5422348SN/A * to resource contention. 5432348SN/A */ 5445999Snate@binkert.org Stats::Vector wbPenalized; 5452348SN/A /** Number of instructions per cycle written back. */ 5462326SN/A Stats::Formula wbRate; 5472348SN/A /** Average number of woken instructions per writeback. */ 5482326SN/A Stats::Formula wbFanout; 5492348SN/A /** Number of instructions per cycle delayed in writing back . */ 5502326SN/A Stats::Formula wbPenalizedRate; 5511060SN/A}; 5521060SN/A 5532292SN/A#endif // __CPU_O3_IEW_HH__ 554