iew.hh revision 6221
114039Sstacze01@arm.com/*
214039Sstacze01@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan
314039Sstacze01@arm.com * All rights reserved.
414039Sstacze01@arm.com *
514039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without
614039Sstacze01@arm.com * modification, are permitted provided that the following conditions are
714039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright
814039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer;
914039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright
1014039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the
1114039Sstacze01@arm.com * documentation and/or other materials provided with the distribution;
1214039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its
1314039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from
1414039Sstacze01@arm.com * this software without specific prior written permission.
1514039Sstacze01@arm.com *
1614039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1714039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1814039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1914039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2014039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2114039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2214039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2314039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2414039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2514039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2614039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2714039Sstacze01@arm.com *
2814039Sstacze01@arm.com * Authors: Kevin Lim
2914039Sstacze01@arm.com */
3014039Sstacze01@arm.com
3114039Sstacze01@arm.com#ifndef __CPU_O3_IEW_HH__
3214039Sstacze01@arm.com#define __CPU_O3_IEW_HH__
3314039Sstacze01@arm.com
3414039Sstacze01@arm.com#include <queue>
3514039Sstacze01@arm.com
3614039Sstacze01@arm.com#include "base/statistics.hh"
3714039Sstacze01@arm.com#include "base/timebuf.hh"
3814039Sstacze01@arm.com#include "config/full_system.hh"
3914039Sstacze01@arm.com#include "cpu/o3/comm.hh"
4014039Sstacze01@arm.com#include "cpu/o3/scoreboard.hh"
4114039Sstacze01@arm.com#include "cpu/o3/lsq.hh"
4214039Sstacze01@arm.com
4314039Sstacze01@arm.comclass DerivO3CPUParams;
4414039Sstacze01@arm.comclass FUPool;
4514039Sstacze01@arm.com
4614039Sstacze01@arm.com/**
4714039Sstacze01@arm.com * DefaultIEW handles both single threaded and SMT IEW
4814039Sstacze01@arm.com * (issue/execute/writeback).  It handles the dispatching of
4914039Sstacze01@arm.com * instructions to the LSQ/IQ as part of the issue stage, and has the
5014039Sstacze01@arm.com * IQ try to issue instructions each cycle. The execute latency is
5114252Sgabeblack@google.com * actually tied into the issue latency to allow the IQ to be able to
5214039Sstacze01@arm.com * do back-to-back scheduling without having to speculatively schedule
5314039Sstacze01@arm.com * instructions. This happens by having the IQ have access to the
5414039Sstacze01@arm.com * functional units, and the IQ gets the execution latencies from the
5514039Sstacze01@arm.com * FUs when it issues instructions. Instructions reach the execute
5614039Sstacze01@arm.com * stage on the last cycle of their execution, which is when the IQ
5714252Sgabeblack@google.com * knows to wake up any dependent instructions, allowing back to back
5814039Sstacze01@arm.com * scheduling. The execute portion of IEW separates memory
5914064Sadrian.herrera@arm.com * instructions from non-memory instructions, either telling the LSQ
6014064Sadrian.herrera@arm.com * to execute the instruction, or executing the instruction directly.
6114064Sadrian.herrera@arm.com * The writeback portion of IEW completes the instructions by waking
6214039Sstacze01@arm.com * up any dependents, and marking the register ready on the
6314039Sstacze01@arm.com * scoreboard.
6414039Sstacze01@arm.com */
6514039Sstacze01@arm.comtemplate<class Impl>
6614039Sstacze01@arm.comclass DefaultIEW
6714039Sstacze01@arm.com{
6814039Sstacze01@arm.com  private:
6914039Sstacze01@arm.com    //Typedefs from Impl
7014039Sstacze01@arm.com    typedef typename Impl::CPUPol CPUPol;
7114039Sstacze01@arm.com    typedef typename Impl::DynInstPtr DynInstPtr;
7214039Sstacze01@arm.com    typedef typename Impl::O3CPU O3CPU;
7314039Sstacze01@arm.com
7414039Sstacze01@arm.com    typedef typename CPUPol::IQ IQ;
7514039Sstacze01@arm.com    typedef typename CPUPol::RenameMap RenameMap;
7614039Sstacze01@arm.com    typedef typename CPUPol::LSQ LSQ;
7714039Sstacze01@arm.com
7814039Sstacze01@arm.com    typedef typename CPUPol::TimeStruct TimeStruct;
7914039Sstacze01@arm.com    typedef typename CPUPol::IEWStruct IEWStruct;
8014039Sstacze01@arm.com    typedef typename CPUPol::RenameStruct RenameStruct;
8114039Sstacze01@arm.com    typedef typename CPUPol::IssueStruct IssueStruct;
8214039Sstacze01@arm.com
8314039Sstacze01@arm.com    friend class Impl::O3CPU;
8414039Sstacze01@arm.com    friend class CPUPol::IQ;
8514039Sstacze01@arm.com
8614223Sgiacomo.travaglini@arm.com  public:
8714039Sstacze01@arm.com    /** Overall IEW stage status. Used to determine if the CPU can
8814039Sstacze01@arm.com     * deschedule itself due to a lack of activity.
8914039Sstacze01@arm.com     */
9014039Sstacze01@arm.com    enum Status {
9114039Sstacze01@arm.com        Active,
9214039Sstacze01@arm.com        Inactive
9314039Sstacze01@arm.com    };
9414039Sstacze01@arm.com
9514039Sstacze01@arm.com    /** Status for Issue, Execute, and Writeback stages. */
9614039Sstacze01@arm.com    enum StageStatus {
9714039Sstacze01@arm.com        Running,
9814039Sstacze01@arm.com        Blocked,
9914039Sstacze01@arm.com        Idle,
10014039Sstacze01@arm.com        StartSquash,
10114039Sstacze01@arm.com        Squashing,
10214039Sstacze01@arm.com        Unblocking
10314039Sstacze01@arm.com    };
10414039Sstacze01@arm.com
10514039Sstacze01@arm.com  private:
10614039Sstacze01@arm.com    /** Overall stage status. */
10714039Sstacze01@arm.com    Status _status;
10814039Sstacze01@arm.com    /** Dispatch status. */
10914039Sstacze01@arm.com    StageStatus dispatchStatus[Impl::MaxThreads];
11014039Sstacze01@arm.com    /** Execute status. */
11114039Sstacze01@arm.com    StageStatus exeStatus;
11214039Sstacze01@arm.com    /** Writeback status. */
11314039Sstacze01@arm.com    StageStatus wbStatus;
11414039Sstacze01@arm.com
11514039Sstacze01@arm.com  public:
11614039Sstacze01@arm.com    /** Constructs a DefaultIEW with the given parameters. */
11714039Sstacze01@arm.com    DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
11814039Sstacze01@arm.com
11914039Sstacze01@arm.com    /** Returns the name of the DefaultIEW stage. */
12014092Smatteo.andreozzi@arm.com    std::string name() const;
12114039Sstacze01@arm.com
12214039Sstacze01@arm.com    /** Registers statistics. */
12314039Sstacze01@arm.com    void regStats();
12414039Sstacze01@arm.com
12514039Sstacze01@arm.com    /** Initializes stage; sends back the number of free IQ and LSQ entries. */
12614039Sstacze01@arm.com    void initStage();
12714039Sstacze01@arm.com
12814039Sstacze01@arm.com    /** Returns the dcache port. */
12914039Sstacze01@arm.com    Port *getDcachePort() { return ldstQueue.getDcachePort(); }
13014039Sstacze01@arm.com
13114064Sadrian.herrera@arm.com    /** Sets main time buffer used for backwards communication. */
13214064Sadrian.herrera@arm.com    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
13314064Sadrian.herrera@arm.com
13414064Sadrian.herrera@arm.com    /** Sets time buffer for getting instructions coming from rename. */
13514064Sadrian.herrera@arm.com    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
13614064Sadrian.herrera@arm.com
13714064Sadrian.herrera@arm.com    /** Sets time buffer to pass on instructions to commit. */
13814064Sadrian.herrera@arm.com    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
13914039Sstacze01@arm.com
14014039Sstacze01@arm.com    /** Sets pointer to list of active threads. */
14114039Sstacze01@arm.com    void setActiveThreads(std::list<ThreadID> *at_ptr);
14214039Sstacze01@arm.com
14314039Sstacze01@arm.com    /** Sets pointer to the scoreboard. */
144    void setScoreboard(Scoreboard *sb_ptr);
145
146    /** Drains IEW stage. */
147    bool drain();
148
149    /** Resumes execution after a drain. */
150    void resume();
151
152    /** Completes switch out of IEW stage. */
153    void switchOut();
154
155    /** Takes over from another CPU's thread. */
156    void takeOverFrom();
157
158    /** Returns if IEW is switched out. */
159    bool isSwitchedOut() { return switchedOut; }
160
161    /** Squashes instructions in IEW for a specific thread. */
162    void squash(ThreadID tid);
163
164    /** Wakes all dependents of a completed instruction. */
165    void wakeDependents(DynInstPtr &inst);
166
167    /** Tells memory dependence unit that a memory instruction needs to be
168     * rescheduled. It will re-execute once replayMemInst() is called.
169     */
170    void rescheduleMemInst(DynInstPtr &inst);
171
172    /** Re-executes all rescheduled memory instructions. */
173    void replayMemInst(DynInstPtr &inst);
174
175    /** Sends an instruction to commit through the time buffer. */
176    void instToCommit(DynInstPtr &inst);
177
178    /** Inserts unused instructions of a thread into the skid buffer. */
179    void skidInsert(ThreadID tid);
180
181    /** Returns the max of the number of entries in all of the skid buffers. */
182    int skidCount();
183
184    /** Returns if all of the skid buffers are empty. */
185    bool skidsEmpty();
186
187    /** Updates overall IEW status based on all of the stages' statuses. */
188    void updateStatus();
189
190    /** Resets entries of the IQ and the LSQ. */
191    void resetEntries();
192
193    /** Tells the CPU to wakeup if it has descheduled itself due to no
194     * activity. Used mainly by the LdWritebackEvent.
195     */
196    void wakeCPU();
197
198    /** Reports to the CPU that there is activity this cycle. */
199    void activityThisCycle();
200
201    /** Tells CPU that the IEW stage is active and running. */
202    inline void activateStage();
203
204    /** Tells CPU that the IEW stage is inactive and idle. */
205    inline void deactivateStage();
206
207    /** Returns if the LSQ has any stores to writeback. */
208    bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
209
210    /** Returns if the LSQ has any stores to writeback. */
211    bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
212
213    void incrWb(InstSeqNum &sn)
214    {
215        if (++wbOutstanding == wbMax)
216            ableToIssue = false;
217        DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
218        assert(wbOutstanding <= wbMax);
219#ifdef DEBUG
220        wbList.insert(sn);
221#endif
222    }
223
224    void decrWb(InstSeqNum &sn)
225    {
226        if (wbOutstanding-- == wbMax)
227            ableToIssue = true;
228        DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
229        assert(wbOutstanding >= 0);
230#ifdef DEBUG
231        assert(wbList.find(sn) != wbList.end());
232        wbList.erase(sn);
233#endif
234    }
235
236#ifdef DEBUG
237    std::set<InstSeqNum> wbList;
238
239    void dumpWb()
240    {
241        std::set<InstSeqNum>::iterator wb_it = wbList.begin();
242        while (wb_it != wbList.end()) {
243            cprintf("[sn:%lli]\n",
244                    (*wb_it));
245            wb_it++;
246        }
247    }
248#endif
249
250    bool canIssue() { return ableToIssue; }
251
252    bool ableToIssue;
253
254  private:
255    /** Sends commit proper information for a squash due to a branch
256     * mispredict.
257     */
258    void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
259
260    /** Sends commit proper information for a squash due to a memory order
261     * violation.
262     */
263    void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
264
265    /** Sends commit proper information for a squash due to memory becoming
266     * blocked (younger issued instructions must be retried).
267     */
268    void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
269
270    /** Sets Dispatch to blocked, and signals back to other stages to block. */
271    void block(ThreadID tid);
272
273    /** Unblocks Dispatch if the skid buffer is empty, and signals back to
274     * other stages to unblock.
275     */
276    void unblock(ThreadID tid);
277
278    /** Determines proper actions to take given Dispatch's status. */
279    void dispatch(ThreadID tid);
280
281    /** Dispatches instructions to IQ and LSQ. */
282    void dispatchInsts(ThreadID tid);
283
284    /** Executes instructions. In the case of memory operations, it informs the
285     * LSQ to execute the instructions. Also handles any redirects that occur
286     * due to the executed instructions.
287     */
288    void executeInsts();
289
290    /** Writebacks instructions. In our model, the instruction's execute()
291     * function atomically reads registers, executes, and writes registers.
292     * Thus this writeback only wakes up dependent instructions, and informs
293     * the scoreboard of registers becoming ready.
294     */
295    void writebackInsts();
296
297    /** Returns the number of valid, non-squashed instructions coming from
298     * rename to dispatch.
299     */
300    unsigned validInstsFromRename();
301
302    /** Reads the stall signals. */
303    void readStallSignals(ThreadID tid);
304
305    /** Checks if any of the stall conditions are currently true. */
306    bool checkStall(ThreadID tid);
307
308    /** Processes inputs and changes state accordingly. */
309    void checkSignalsAndUpdate(ThreadID tid);
310
311    /** Removes instructions from rename from a thread's instruction list. */
312    void emptyRenameInsts(ThreadID tid);
313
314    /** Sorts instructions coming from rename into lists separated by thread. */
315    void sortInsts();
316
317  public:
318    /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
319     * Writeback to run for one cycle.
320     */
321    void tick();
322
323  private:
324    /** Updates execution stats based on the instruction. */
325    void updateExeInstStats(DynInstPtr &inst);
326
327    /** Pointer to main time buffer used for backwards communication. */
328    TimeBuffer<TimeStruct> *timeBuffer;
329
330    /** Wire to write information heading to previous stages. */
331    typename TimeBuffer<TimeStruct>::wire toFetch;
332
333    /** Wire to get commit's output from backwards time buffer. */
334    typename TimeBuffer<TimeStruct>::wire fromCommit;
335
336    /** Wire to write information heading to previous stages. */
337    typename TimeBuffer<TimeStruct>::wire toRename;
338
339    /** Rename instruction queue interface. */
340    TimeBuffer<RenameStruct> *renameQueue;
341
342    /** Wire to get rename's output from rename queue. */
343    typename TimeBuffer<RenameStruct>::wire fromRename;
344
345    /** Issue stage queue. */
346    TimeBuffer<IssueStruct> issueToExecQueue;
347
348    /** Wire to read information from the issue stage time queue. */
349    typename TimeBuffer<IssueStruct>::wire fromIssue;
350
351    /**
352     * IEW stage time buffer.  Holds ROB indices of instructions that
353     * can be marked as completed.
354     */
355    TimeBuffer<IEWStruct> *iewQueue;
356
357    /** Wire to write infromation heading to commit. */
358    typename TimeBuffer<IEWStruct>::wire toCommit;
359
360    /** Queue of all instructions coming from rename this cycle. */
361    std::queue<DynInstPtr> insts[Impl::MaxThreads];
362
363    /** Skid buffer between rename and IEW. */
364    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
365
366    /** Scoreboard pointer. */
367    Scoreboard* scoreboard;
368
369  private:
370    /** CPU pointer. */
371    O3CPU *cpu;
372
373    /** Records if IEW has written to the time buffer this cycle, so that the
374     * CPU can deschedule itself if there is no activity.
375     */
376    bool wroteToTimeBuffer;
377
378    /** Source of possible stalls. */
379    struct Stalls {
380        bool commit;
381    };
382
383    /** Stages that are telling IEW to stall. */
384    Stalls stalls[Impl::MaxThreads];
385
386    /** Debug function to print instructions that are issued this cycle. */
387    void printAvailableInsts();
388
389  public:
390    /** Instruction queue. */
391    IQ instQueue;
392
393    /** Load / store queue. */
394    LSQ ldstQueue;
395
396    /** Pointer to the functional unit pool. */
397    FUPool *fuPool;
398    /** Records if the LSQ needs to be updated on the next cycle, so that
399     * IEW knows if there will be activity on the next cycle.
400     */
401    bool updateLSQNextCycle;
402
403  private:
404    /** Records if there is a fetch redirect on this cycle for each thread. */
405    bool fetchRedirect[Impl::MaxThreads];
406
407    /** Records if the queues have been changed (inserted or issued insts),
408     * so that IEW knows to broadcast the updated amount of free entries.
409     */
410    bool updatedQueues;
411
412    /** Commit to IEW delay, in ticks. */
413    unsigned commitToIEWDelay;
414
415    /** Rename to IEW delay, in ticks. */
416    unsigned renameToIEWDelay;
417
418    /**
419     * Issue to execute delay, in ticks.  What this actually represents is
420     * the amount of time it takes for an instruction to wake up, be
421     * scheduled, and sent to a FU for execution.
422     */
423    unsigned issueToExecuteDelay;
424
425    /** Width of dispatch, in instructions. */
426    unsigned dispatchWidth;
427
428    /** Width of issue, in instructions. */
429    unsigned issueWidth;
430
431    /** Index into queue of instructions being written back. */
432    unsigned wbNumInst;
433
434    /** Cycle number within the queue of instructions being written back.
435     * Used in case there are too many instructions writing back at the current
436     * cycle and writesbacks need to be scheduled for the future. See comments
437     * in instToCommit().
438     */
439    unsigned wbCycle;
440
441    /** Number of instructions in flight that will writeback. */
442
443    /** Number of instructions in flight that will writeback. */
444    int wbOutstanding;
445
446    /** Writeback width. */
447    unsigned wbWidth;
448
449    /** Writeback width * writeback depth, where writeback depth is
450     * the number of cycles of writing back instructions that can be
451     * buffered. */
452    unsigned wbMax;
453
454    /** Number of active threads. */
455    ThreadID numThreads;
456
457    /** Pointer to list of active threads. */
458    std::list<ThreadID> *activeThreads;
459
460    /** Maximum size of the skid buffer. */
461    unsigned skidBufferMax;
462
463    /** Is this stage switched out. */
464    bool switchedOut;
465
466    /** Stat for total number of idle cycles. */
467    Stats::Scalar iewIdleCycles;
468    /** Stat for total number of squashing cycles. */
469    Stats::Scalar iewSquashCycles;
470    /** Stat for total number of blocking cycles. */
471    Stats::Scalar iewBlockCycles;
472    /** Stat for total number of unblocking cycles. */
473    Stats::Scalar iewUnblockCycles;
474    /** Stat for total number of instructions dispatched. */
475    Stats::Scalar iewDispatchedInsts;
476    /** Stat for total number of squashed instructions dispatch skips. */
477    Stats::Scalar iewDispSquashedInsts;
478    /** Stat for total number of dispatched load instructions. */
479    Stats::Scalar iewDispLoadInsts;
480    /** Stat for total number of dispatched store instructions. */
481    Stats::Scalar iewDispStoreInsts;
482    /** Stat for total number of dispatched non speculative instructions. */
483    Stats::Scalar iewDispNonSpecInsts;
484    /** Stat for number of times the IQ becomes full. */
485    Stats::Scalar iewIQFullEvents;
486    /** Stat for number of times the LSQ becomes full. */
487    Stats::Scalar iewLSQFullEvents;
488    /** Stat for total number of memory ordering violation events. */
489    Stats::Scalar memOrderViolationEvents;
490    /** Stat for total number of incorrect predicted taken branches. */
491    Stats::Scalar predictedTakenIncorrect;
492    /** Stat for total number of incorrect predicted not taken branches. */
493    Stats::Scalar predictedNotTakenIncorrect;
494    /** Stat for total number of mispredicted branches detected at execute. */
495    Stats::Formula branchMispredicts;
496
497    /** Stat for total number of executed instructions. */
498    Stats::Scalar iewExecutedInsts;
499    /** Stat for total number of executed load instructions. */
500    Stats::Vector iewExecLoadInsts;
501    /** Stat for total number of executed store instructions. */
502//    Stats::Scalar iewExecStoreInsts;
503    /** Stat for total number of squashed instructions skipped at execute. */
504    Stats::Scalar iewExecSquashedInsts;
505    /** Number of executed software prefetches. */
506    Stats::Vector iewExecutedSwp;
507    /** Number of executed nops. */
508    Stats::Vector iewExecutedNop;
509    /** Number of executed meomory references. */
510    Stats::Vector iewExecutedRefs;
511    /** Number of executed branches. */
512    Stats::Vector iewExecutedBranches;
513    /** Number of executed store instructions. */
514    Stats::Formula iewExecStoreInsts;
515    /** Number of instructions executed per cycle. */
516    Stats::Formula iewExecRate;
517
518    /** Number of instructions sent to commit. */
519    Stats::Vector iewInstsToCommit;
520    /** Number of instructions that writeback. */
521    Stats::Vector writebackCount;
522    /** Number of instructions that wake consumers. */
523    Stats::Vector producerInst;
524    /** Number of instructions that wake up from producers. */
525    Stats::Vector consumerInst;
526    /** Number of instructions that were delayed in writing back due
527     * to resource contention.
528     */
529    Stats::Vector wbPenalized;
530    /** Number of instructions per cycle written back. */
531    Stats::Formula wbRate;
532    /** Average number of woken instructions per writeback. */
533    Stats::Formula wbFanout;
534    /** Number of instructions per cycle delayed in writing back . */
535    Stats::Formula wbPenalizedRate;
536};
537
538#endif // __CPU_O3_IEW_HH__
539