iew.hh revision 6221
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#ifndef __CPU_O3_IEW_HH__ 322292SN/A#define __CPU_O3_IEW_HH__ 331060SN/A 341060SN/A#include <queue> 351060SN/A 361461SN/A#include "base/statistics.hh" 371060SN/A#include "base/timebuf.hh" 386221Snate@binkert.org#include "config/full_system.hh" 391717SN/A#include "cpu/o3/comm.hh" 402292SN/A#include "cpu/o3/scoreboard.hh" 412292SN/A#include "cpu/o3/lsq.hh" 421060SN/A 435529Snate@binkert.orgclass DerivO3CPUParams; 442292SN/Aclass FUPool; 452292SN/A 462292SN/A/** 472326SN/A * DefaultIEW handles both single threaded and SMT IEW 482326SN/A * (issue/execute/writeback). It handles the dispatching of 492326SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the 502326SN/A * IQ try to issue instructions each cycle. The execute latency is 512326SN/A * actually tied into the issue latency to allow the IQ to be able to 522292SN/A * do back-to-back scheduling without having to speculatively schedule 532326SN/A * instructions. This happens by having the IQ have access to the 542326SN/A * functional units, and the IQ gets the execution latencies from the 552326SN/A * FUs when it issues instructions. Instructions reach the execute 562326SN/A * stage on the last cycle of their execution, which is when the IQ 572326SN/A * knows to wake up any dependent instructions, allowing back to back 582326SN/A * scheduling. The execute portion of IEW separates memory 592326SN/A * instructions from non-memory instructions, either telling the LSQ 602326SN/A * to execute the instruction, or executing the instruction directly. 612326SN/A * The writeback portion of IEW completes the instructions by waking 622326SN/A * up any dependents, and marking the register ready on the 632326SN/A * scoreboard. 642292SN/A */ 651681SN/Atemplate<class Impl> 662292SN/Aclass DefaultIEW 671060SN/A{ 681060SN/A private: 691060SN/A //Typedefs from Impl 701061SN/A typedef typename Impl::CPUPol CPUPol; 711061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 722733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 731060SN/A 741681SN/A typedef typename CPUPol::IQ IQ; 751061SN/A typedef typename CPUPol::RenameMap RenameMap; 762292SN/A typedef typename CPUPol::LSQ LSQ; 771060SN/A 781061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 791061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 801061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 811061SN/A typedef typename CPUPol::IssueStruct IssueStruct; 821060SN/A 832733Sktlim@umich.edu friend class Impl::O3CPU; 842292SN/A friend class CPUPol::IQ; 852292SN/A 861060SN/A public: 872292SN/A /** Overall IEW stage status. Used to determine if the CPU can 882292SN/A * deschedule itself due to a lack of activity. 892292SN/A */ 901060SN/A enum Status { 912292SN/A Active, 922292SN/A Inactive 932292SN/A }; 942292SN/A 952292SN/A /** Status for Issue, Execute, and Writeback stages. */ 962292SN/A enum StageStatus { 971060SN/A Running, 981060SN/A Blocked, 991060SN/A Idle, 1002292SN/A StartSquash, 1011060SN/A Squashing, 1021060SN/A Unblocking 1031060SN/A }; 1041060SN/A 1051060SN/A private: 1062292SN/A /** Overall stage status. */ 1071060SN/A Status _status; 1082292SN/A /** Dispatch status. */ 1092292SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 1102292SN/A /** Execute status. */ 1112292SN/A StageStatus exeStatus; 1122292SN/A /** Writeback status. */ 1132292SN/A StageStatus wbStatus; 1141060SN/A 1151060SN/A public: 1162292SN/A /** Constructs a DefaultIEW with the given parameters. */ 1175529Snate@binkert.org DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 1181060SN/A 1192292SN/A /** Returns the name of the DefaultIEW stage. */ 1202292SN/A std::string name() const; 1211062SN/A 1222292SN/A /** Registers statistics. */ 1232632Sstever@eecs.umich.edu void regStats(); 1242632Sstever@eecs.umich.edu 1252292SN/A /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 1262292SN/A void initStage(); 1272292SN/A 1282871Sktlim@umich.edu /** Returns the dcache port. */ 1292871Sktlim@umich.edu Port *getDcachePort() { return ldstQueue.getDcachePort(); } 1302871Sktlim@umich.edu 1312292SN/A /** Sets main time buffer used for backwards communication. */ 1322632Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1332632Sstever@eecs.umich.edu 1342292SN/A /** Sets time buffer for getting instructions coming from rename. */ 1352632Sstever@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1362632Sstever@eecs.umich.edu 1372292SN/A /** Sets time buffer to pass on instructions to commit. */ 1382632Sstever@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1392632Sstever@eecs.umich.edu 1402292SN/A /** Sets pointer to list of active threads. */ 1416221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1422632Sstever@eecs.umich.edu 1432292SN/A /** Sets pointer to the scoreboard. */ 1442292SN/A void setScoreboard(Scoreboard *sb_ptr); 1452632Sstever@eecs.umich.edu 1462843Sktlim@umich.edu /** Drains IEW stage. */ 1472863Sktlim@umich.edu bool drain(); 1482843Sktlim@umich.edu 1492843Sktlim@umich.edu /** Resumes execution after a drain. */ 1502843Sktlim@umich.edu void resume(); 1512632Sstever@eecs.umich.edu 1522348SN/A /** Completes switch out of IEW stage. */ 1532843Sktlim@umich.edu void switchOut(); 1542632Sstever@eecs.umich.edu 1552348SN/A /** Takes over from another CPU's thread. */ 1562307SN/A void takeOverFrom(); 1572632Sstever@eecs.umich.edu 1582348SN/A /** Returns if IEW is switched out. */ 1592307SN/A bool isSwitchedOut() { return switchedOut; } 1602632Sstever@eecs.umich.edu 1612292SN/A /** Squashes instructions in IEW for a specific thread. */ 1626221Snate@binkert.org void squash(ThreadID tid); 1632107SN/A 1642292SN/A /** Wakes all dependents of a completed instruction. */ 1652632Sstever@eecs.umich.edu void wakeDependents(DynInstPtr &inst); 1662632Sstever@eecs.umich.edu 1672292SN/A /** Tells memory dependence unit that a memory instruction needs to be 1682292SN/A * rescheduled. It will re-execute once replayMemInst() is called. 1692292SN/A */ 1702292SN/A void rescheduleMemInst(DynInstPtr &inst); 1712292SN/A 1722292SN/A /** Re-executes all rescheduled memory instructions. */ 1732292SN/A void replayMemInst(DynInstPtr &inst); 1742292SN/A 1752292SN/A /** Sends an instruction to commit through the time buffer. */ 1762632Sstever@eecs.umich.edu void instToCommit(DynInstPtr &inst); 1772632Sstever@eecs.umich.edu 1782292SN/A /** Inserts unused instructions of a thread into the skid buffer. */ 1796221Snate@binkert.org void skidInsert(ThreadID tid); 1802292SN/A 1812292SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 1822292SN/A int skidCount(); 1832292SN/A 1842292SN/A /** Returns if all of the skid buffers are empty. */ 1852292SN/A bool skidsEmpty(); 1862292SN/A 1872292SN/A /** Updates overall IEW status based on all of the stages' statuses. */ 1882292SN/A void updateStatus(); 1892292SN/A 1902292SN/A /** Resets entries of the IQ and the LSQ. */ 1912292SN/A void resetEntries(); 1922292SN/A 1932292SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 1942292SN/A * activity. Used mainly by the LdWritebackEvent. 1952292SN/A */ 1962292SN/A void wakeCPU(); 1972292SN/A 1982292SN/A /** Reports to the CPU that there is activity this cycle. */ 1992292SN/A void activityThisCycle(); 2002292SN/A 2012292SN/A /** Tells CPU that the IEW stage is active and running. */ 2022292SN/A inline void activateStage(); 2032292SN/A 2042292SN/A /** Tells CPU that the IEW stage is inactive and idle. */ 2052292SN/A inline void deactivateStage(); 2062292SN/A 2072292SN/A /** Returns if the LSQ has any stores to writeback. */ 2082292SN/A bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2092292SN/A 2105557Sktlim@umich.edu /** Returns if the LSQ has any stores to writeback. */ 2116221Snate@binkert.org bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2125557Sktlim@umich.edu 2132820Sktlim@umich.edu void incrWb(InstSeqNum &sn) 2142820Sktlim@umich.edu { 2152820Sktlim@umich.edu if (++wbOutstanding == wbMax) 2162820Sktlim@umich.edu ableToIssue = false; 2172820Sktlim@umich.edu DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 2182353SN/A assert(wbOutstanding <= wbMax); 2192926Sktlim@umich.edu#ifdef DEBUG 2202820Sktlim@umich.edu wbList.insert(sn); 2212820Sktlim@umich.edu#endif 2222820Sktlim@umich.edu } 2232820Sktlim@umich.edu 2242820Sktlim@umich.edu void decrWb(InstSeqNum &sn) 2252820Sktlim@umich.edu { 2262820Sktlim@umich.edu if (wbOutstanding-- == wbMax) 2272820Sktlim@umich.edu ableToIssue = true; 2282820Sktlim@umich.edu DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 2292353SN/A assert(wbOutstanding >= 0); 2302926Sktlim@umich.edu#ifdef DEBUG 2312820Sktlim@umich.edu assert(wbList.find(sn) != wbList.end()); 2322820Sktlim@umich.edu wbList.erase(sn); 2332820Sktlim@umich.edu#endif 2342820Sktlim@umich.edu } 2352820Sktlim@umich.edu 2362926Sktlim@umich.edu#ifdef DEBUG 2372820Sktlim@umich.edu std::set<InstSeqNum> wbList; 2382820Sktlim@umich.edu 2392820Sktlim@umich.edu void dumpWb() 2402820Sktlim@umich.edu { 2412820Sktlim@umich.edu std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 2422820Sktlim@umich.edu while (wb_it != wbList.end()) { 2432820Sktlim@umich.edu cprintf("[sn:%lli]\n", 2442820Sktlim@umich.edu (*wb_it)); 2452820Sktlim@umich.edu wb_it++; 2462820Sktlim@umich.edu } 2472820Sktlim@umich.edu } 2482820Sktlim@umich.edu#endif 2492820Sktlim@umich.edu 2502820Sktlim@umich.edu bool canIssue() { return ableToIssue; } 2512820Sktlim@umich.edu 2522820Sktlim@umich.edu bool ableToIssue; 2532820Sktlim@umich.edu 2542632Sstever@eecs.umich.edu private: 2552292SN/A /** Sends commit proper information for a squash due to a branch 2562292SN/A * mispredict. 2572292SN/A */ 2586221Snate@binkert.org void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 2592632Sstever@eecs.umich.edu 2602292SN/A /** Sends commit proper information for a squash due to a memory order 2612292SN/A * violation. 2622292SN/A */ 2636221Snate@binkert.org void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 2642292SN/A 2652292SN/A /** Sends commit proper information for a squash due to memory becoming 2662292SN/A * blocked (younger issued instructions must be retried). 2672292SN/A */ 2686221Snate@binkert.org void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 2692292SN/A 2702292SN/A /** Sets Dispatch to blocked, and signals back to other stages to block. */ 2716221Snate@binkert.org void block(ThreadID tid); 2722292SN/A 2732292SN/A /** Unblocks Dispatch if the skid buffer is empty, and signals back to 2742292SN/A * other stages to unblock. 2752292SN/A */ 2766221Snate@binkert.org void unblock(ThreadID tid); 2772292SN/A 2782292SN/A /** Determines proper actions to take given Dispatch's status. */ 2796221Snate@binkert.org void dispatch(ThreadID tid); 2802292SN/A 2812292SN/A /** Dispatches instructions to IQ and LSQ. */ 2826221Snate@binkert.org void dispatchInsts(ThreadID tid); 2832292SN/A 2842292SN/A /** Executes instructions. In the case of memory operations, it informs the 2852292SN/A * LSQ to execute the instructions. Also handles any redirects that occur 2862292SN/A * due to the executed instructions. 2872292SN/A */ 2882632Sstever@eecs.umich.edu void executeInsts(); 2892632Sstever@eecs.umich.edu 2902292SN/A /** Writebacks instructions. In our model, the instruction's execute() 2912292SN/A * function atomically reads registers, executes, and writes registers. 2922292SN/A * Thus this writeback only wakes up dependent instructions, and informs 2932292SN/A * the scoreboard of registers becoming ready. 2942292SN/A */ 2952292SN/A void writebackInsts(); 2962292SN/A 2972292SN/A /** Returns the number of valid, non-squashed instructions coming from 2982292SN/A * rename to dispatch. 2992292SN/A */ 3002292SN/A unsigned validInstsFromRename(); 3012292SN/A 3022292SN/A /** Reads the stall signals. */ 3036221Snate@binkert.org void readStallSignals(ThreadID tid); 3042292SN/A 3052292SN/A /** Checks if any of the stall conditions are currently true. */ 3066221Snate@binkert.org bool checkStall(ThreadID tid); 3072292SN/A 3082292SN/A /** Processes inputs and changes state accordingly. */ 3096221Snate@binkert.org void checkSignalsAndUpdate(ThreadID tid); 3102292SN/A 3112702Sktlim@umich.edu /** Removes instructions from rename from a thread's instruction list. */ 3126221Snate@binkert.org void emptyRenameInsts(ThreadID tid); 3132702Sktlim@umich.edu 3142292SN/A /** Sorts instructions coming from rename into lists separated by thread. */ 3152292SN/A void sortInsts(); 3161060SN/A 3171060SN/A public: 3182292SN/A /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 3192292SN/A * Writeback to run for one cycle. 3202292SN/A */ 3212632Sstever@eecs.umich.edu void tick(); 3221060SN/A 3231060SN/A private: 3242348SN/A /** Updates execution stats based on the instruction. */ 3252301SN/A void updateExeInstStats(DynInstPtr &inst); 3261062SN/A 3272292SN/A /** Pointer to main time buffer used for backwards communication. */ 3282632Sstever@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 3291062SN/A 3302292SN/A /** Wire to write information heading to previous stages. */ 3312292SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 3321060SN/A 3331060SN/A /** Wire to get commit's output from backwards time buffer. */ 3341060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3351060SN/A 3361060SN/A /** Wire to write information heading to previous stages. */ 3371060SN/A typename TimeBuffer<TimeStruct>::wire toRename; 3381060SN/A 3391060SN/A /** Rename instruction queue interface. */ 3401060SN/A TimeBuffer<RenameStruct> *renameQueue; 3411060SN/A 3421060SN/A /** Wire to get rename's output from rename queue. */ 3431060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3441060SN/A 3451060SN/A /** Issue stage queue. */ 3461060SN/A TimeBuffer<IssueStruct> issueToExecQueue; 3471060SN/A 3481060SN/A /** Wire to read information from the issue stage time queue. */ 3491060SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 3501060SN/A 3511060SN/A /** 3521060SN/A * IEW stage time buffer. Holds ROB indices of instructions that 3531060SN/A * can be marked as completed. 3541060SN/A */ 3551060SN/A TimeBuffer<IEWStruct> *iewQueue; 3561060SN/A 3571060SN/A /** Wire to write infromation heading to commit. */ 3581060SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 3591060SN/A 3602292SN/A /** Queue of all instructions coming from rename this cycle. */ 3612292SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3622292SN/A 3631060SN/A /** Skid buffer between rename and IEW. */ 3642292SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 3651060SN/A 3662292SN/A /** Scoreboard pointer. */ 3672292SN/A Scoreboard* scoreboard; 3682292SN/A 3691681SN/A private: 3702292SN/A /** CPU pointer. */ 3712733Sktlim@umich.edu O3CPU *cpu; 3721060SN/A 3732292SN/A /** Records if IEW has written to the time buffer this cycle, so that the 3742292SN/A * CPU can deschedule itself if there is no activity. 3752292SN/A */ 3762292SN/A bool wroteToTimeBuffer; 3772292SN/A 3782292SN/A /** Source of possible stalls. */ 3792292SN/A struct Stalls { 3802292SN/A bool commit; 3812292SN/A }; 3822292SN/A 3832292SN/A /** Stages that are telling IEW to stall. */ 3842292SN/A Stalls stalls[Impl::MaxThreads]; 3852292SN/A 3862292SN/A /** Debug function to print instructions that are issued this cycle. */ 3872292SN/A void printAvailableInsts(); 3882292SN/A 3892292SN/A public: 3904329Sktlim@umich.edu /** Instruction queue. */ 3914329Sktlim@umich.edu IQ instQueue; 3924329Sktlim@umich.edu 3934329Sktlim@umich.edu /** Load / store queue. */ 3944329Sktlim@umich.edu LSQ ldstQueue; 3954329Sktlim@umich.edu 3964329Sktlim@umich.edu /** Pointer to the functional unit pool. */ 3974329Sktlim@umich.edu FUPool *fuPool; 3982292SN/A /** Records if the LSQ needs to be updated on the next cycle, so that 3992292SN/A * IEW knows if there will be activity on the next cycle. 4002292SN/A */ 4012292SN/A bool updateLSQNextCycle; 4022292SN/A 4031060SN/A private: 4042292SN/A /** Records if there is a fetch redirect on this cycle for each thread. */ 4052292SN/A bool fetchRedirect[Impl::MaxThreads]; 4062292SN/A 4072292SN/A /** Records if the queues have been changed (inserted or issued insts), 4082292SN/A * so that IEW knows to broadcast the updated amount of free entries. 4092292SN/A */ 4102292SN/A bool updatedQueues; 4112292SN/A 4121060SN/A /** Commit to IEW delay, in ticks. */ 4131060SN/A unsigned commitToIEWDelay; 4141060SN/A 4151060SN/A /** Rename to IEW delay, in ticks. */ 4161060SN/A unsigned renameToIEWDelay; 4171060SN/A 4181060SN/A /** 4191060SN/A * Issue to execute delay, in ticks. What this actually represents is 4201060SN/A * the amount of time it takes for an instruction to wake up, be 4211060SN/A * scheduled, and sent to a FU for execution. 4221060SN/A */ 4231060SN/A unsigned issueToExecuteDelay; 4241060SN/A 4252820Sktlim@umich.edu /** Width of dispatch, in instructions. */ 4262820Sktlim@umich.edu unsigned dispatchWidth; 4271060SN/A 4281060SN/A /** Width of issue, in instructions. */ 4291060SN/A unsigned issueWidth; 4301060SN/A 4312292SN/A /** Index into queue of instructions being written back. */ 4322292SN/A unsigned wbNumInst; 4332292SN/A 4342292SN/A /** Cycle number within the queue of instructions being written back. 4352292SN/A * Used in case there are too many instructions writing back at the current 4362292SN/A * cycle and writesbacks need to be scheduled for the future. See comments 4372292SN/A * in instToCommit(). 4381060SN/A */ 4392292SN/A unsigned wbCycle; 4401060SN/A 4412820Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4423125Sktlim@umich.edu 4433125Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4442353SN/A int wbOutstanding; 4452820Sktlim@umich.edu 4462820Sktlim@umich.edu /** Writeback width. */ 4472820Sktlim@umich.edu unsigned wbWidth; 4482820Sktlim@umich.edu 4492820Sktlim@umich.edu /** Writeback width * writeback depth, where writeback depth is 4502820Sktlim@umich.edu * the number of cycles of writing back instructions that can be 4512820Sktlim@umich.edu * buffered. */ 4522820Sktlim@umich.edu unsigned wbMax; 4532820Sktlim@umich.edu 4542292SN/A /** Number of active threads. */ 4556221Snate@binkert.org ThreadID numThreads; 4562292SN/A 4572292SN/A /** Pointer to list of active threads. */ 4586221Snate@binkert.org std::list<ThreadID> *activeThreads; 4592292SN/A 4602292SN/A /** Maximum size of the skid buffer. */ 4612292SN/A unsigned skidBufferMax; 4622292SN/A 4632348SN/A /** Is this stage switched out. */ 4642307SN/A bool switchedOut; 4652307SN/A 4662292SN/A /** Stat for total number of idle cycles. */ 4675999Snate@binkert.org Stats::Scalar iewIdleCycles; 4682292SN/A /** Stat for total number of squashing cycles. */ 4695999Snate@binkert.org Stats::Scalar iewSquashCycles; 4702292SN/A /** Stat for total number of blocking cycles. */ 4715999Snate@binkert.org Stats::Scalar iewBlockCycles; 4722292SN/A /** Stat for total number of unblocking cycles. */ 4735999Snate@binkert.org Stats::Scalar iewUnblockCycles; 4742292SN/A /** Stat for total number of instructions dispatched. */ 4755999Snate@binkert.org Stats::Scalar iewDispatchedInsts; 4762292SN/A /** Stat for total number of squashed instructions dispatch skips. */ 4775999Snate@binkert.org Stats::Scalar iewDispSquashedInsts; 4782292SN/A /** Stat for total number of dispatched load instructions. */ 4795999Snate@binkert.org Stats::Scalar iewDispLoadInsts; 4802292SN/A /** Stat for total number of dispatched store instructions. */ 4815999Snate@binkert.org Stats::Scalar iewDispStoreInsts; 4822292SN/A /** Stat for total number of dispatched non speculative instructions. */ 4835999Snate@binkert.org Stats::Scalar iewDispNonSpecInsts; 4842292SN/A /** Stat for number of times the IQ becomes full. */ 4855999Snate@binkert.org Stats::Scalar iewIQFullEvents; 4862292SN/A /** Stat for number of times the LSQ becomes full. */ 4875999Snate@binkert.org Stats::Scalar iewLSQFullEvents; 4882292SN/A /** Stat for total number of memory ordering violation events. */ 4895999Snate@binkert.org Stats::Scalar memOrderViolationEvents; 4902292SN/A /** Stat for total number of incorrect predicted taken branches. */ 4915999Snate@binkert.org Stats::Scalar predictedTakenIncorrect; 4922292SN/A /** Stat for total number of incorrect predicted not taken branches. */ 4935999Snate@binkert.org Stats::Scalar predictedNotTakenIncorrect; 4942292SN/A /** Stat for total number of mispredicted branches detected at execute. */ 4952292SN/A Stats::Formula branchMispredicts; 4962301SN/A 4972727Sktlim@umich.edu /** Stat for total number of executed instructions. */ 4985999Snate@binkert.org Stats::Scalar iewExecutedInsts; 4992727Sktlim@umich.edu /** Stat for total number of executed load instructions. */ 5005999Snate@binkert.org Stats::Vector iewExecLoadInsts; 5012353SN/A /** Stat for total number of executed store instructions. */ 5025999Snate@binkert.org// Stats::Scalar iewExecStoreInsts; 5032727Sktlim@umich.edu /** Stat for total number of squashed instructions skipped at execute. */ 5045999Snate@binkert.org Stats::Scalar iewExecSquashedInsts; 5052348SN/A /** Number of executed software prefetches. */ 5065999Snate@binkert.org Stats::Vector iewExecutedSwp; 5072348SN/A /** Number of executed nops. */ 5085999Snate@binkert.org Stats::Vector iewExecutedNop; 5092348SN/A /** Number of executed meomory references. */ 5105999Snate@binkert.org Stats::Vector iewExecutedRefs; 5112348SN/A /** Number of executed branches. */ 5125999Snate@binkert.org Stats::Vector iewExecutedBranches; 5132348SN/A /** Number of executed store instructions. */ 5142301SN/A Stats::Formula iewExecStoreInsts; 5152727Sktlim@umich.edu /** Number of instructions executed per cycle. */ 5162727Sktlim@umich.edu Stats::Formula iewExecRate; 5172727Sktlim@umich.edu 5182348SN/A /** Number of instructions sent to commit. */ 5195999Snate@binkert.org Stats::Vector iewInstsToCommit; 5202348SN/A /** Number of instructions that writeback. */ 5215999Snate@binkert.org Stats::Vector writebackCount; 5222348SN/A /** Number of instructions that wake consumers. */ 5235999Snate@binkert.org Stats::Vector producerInst; 5242348SN/A /** Number of instructions that wake up from producers. */ 5255999Snate@binkert.org Stats::Vector consumerInst; 5262348SN/A /** Number of instructions that were delayed in writing back due 5272348SN/A * to resource contention. 5282348SN/A */ 5295999Snate@binkert.org Stats::Vector wbPenalized; 5302348SN/A /** Number of instructions per cycle written back. */ 5312326SN/A Stats::Formula wbRate; 5322348SN/A /** Average number of woken instructions per writeback. */ 5332326SN/A Stats::Formula wbFanout; 5342348SN/A /** Number of instructions per cycle delayed in writing back . */ 5352326SN/A Stats::Formula wbPenalizedRate; 5361060SN/A}; 5371060SN/A 5382292SN/A#endif // __CPU_O3_IEW_HH__ 539