iew.hh revision 2665
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311061SN/A//Todo: Update with statuses. 321060SN/A//Need to handle delaying writes to the writeback bus if it's full at the 331689SN/A//given time. 341060SN/A 351755SN/A#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__ 361755SN/A#define __CPU_O3_CPU_SIMPLE_IEW_HH__ 371060SN/A 381060SN/A#include <queue> 391060SN/A 401858SN/A#include "config/full_system.hh" 411461SN/A#include "base/statistics.hh" 421060SN/A#include "base/timebuf.hh" 431717SN/A#include "cpu/o3/comm.hh" 441060SN/A 451681SN/Atemplate<class Impl> 461060SN/Aclass SimpleIEW 471060SN/A{ 481060SN/A private: 491060SN/A //Typedefs from Impl 501061SN/A typedef typename Impl::CPUPol CPUPol; 511061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 521060SN/A typedef typename Impl::FullCPU FullCPU; 531060SN/A typedef typename Impl::Params Params; 541060SN/A 551681SN/A typedef typename CPUPol::IQ IQ; 561061SN/A typedef typename CPUPol::RenameMap RenameMap; 571061SN/A typedef typename CPUPol::LDSTQ LDSTQ; 581060SN/A 591061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 601061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 611061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 621061SN/A typedef typename CPUPol::IssueStruct IssueStruct; 631060SN/A 641681SN/A friend class Impl::FullCPU; 651060SN/A public: 661060SN/A enum Status { 671060SN/A Running, 681060SN/A Blocked, 691060SN/A Idle, 701060SN/A Squashing, 711060SN/A Unblocking 721060SN/A }; 731060SN/A 741060SN/A private: 751060SN/A Status _status; 761060SN/A Status _issueStatus; 771060SN/A Status _exeStatus; 781060SN/A Status _wbStatus; 791060SN/A 801060SN/A public: 811681SN/A class WritebackEvent : public Event { 821681SN/A private: 831681SN/A DynInstPtr inst; 841681SN/A SimpleIEW<Impl> *iewStage; 851060SN/A 861681SN/A public: 871681SN/A WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew); 881062SN/A 891681SN/A virtual void process(); 901681SN/A virtual const char *description(); 911681SN/A }; 921060SN/A 931060SN/A public: 941060SN/A SimpleIEW(Params ¶ms); 951060SN/A 961062SN/A void regStats(); 971062SN/A 981060SN/A void setCPU(FullCPU *cpu_ptr); 991060SN/A 1001060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1011060SN/A 1021060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1031060SN/A 1041060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1051060SN/A 1061060SN/A void setRenameMap(RenameMap *rm_ptr); 1071060SN/A 1081681SN/A void squash(); 1091681SN/A 1101681SN/A void squashDueToBranch(DynInstPtr &inst); 1111681SN/A 1121681SN/A void squashDueToMem(DynInstPtr &inst); 1131681SN/A 1141681SN/A void block(); 1151681SN/A 1161681SN/A inline void unblock(); 1171681SN/A 1181061SN/A void wakeDependents(DynInstPtr &inst); 1191060SN/A 1201681SN/A void instToCommit(DynInstPtr &inst); 1211060SN/A 1221060SN/A private: 1231062SN/A void dispatchInsts(); 1241062SN/A 1251062SN/A void executeInsts(); 1261062SN/A 1271681SN/A public: 1281681SN/A void tick(); 1291681SN/A 1301681SN/A void iew(); 1311681SN/A 1321060SN/A //Interfaces to objects inside and outside of IEW. 1331060SN/A /** Time buffer interface. */ 1341060SN/A TimeBuffer<TimeStruct> *timeBuffer; 1351060SN/A 1361060SN/A /** Wire to get commit's output from backwards time buffer. */ 1371060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 1381060SN/A 1391060SN/A /** Wire to write information heading to previous stages. */ 1401060SN/A typename TimeBuffer<TimeStruct>::wire toRename; 1411060SN/A 1421060SN/A /** Rename instruction queue interface. */ 1431060SN/A TimeBuffer<RenameStruct> *renameQueue; 1441060SN/A 1451060SN/A /** Wire to get rename's output from rename queue. */ 1461060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 1471060SN/A 1481060SN/A /** Issue stage queue. */ 1491060SN/A TimeBuffer<IssueStruct> issueToExecQueue; 1501060SN/A 1511060SN/A /** Wire to read information from the issue stage time queue. */ 1521060SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 1531060SN/A 1541060SN/A /** 1551060SN/A * IEW stage time buffer. Holds ROB indices of instructions that 1561060SN/A * can be marked as completed. 1571060SN/A */ 1581060SN/A TimeBuffer<IEWStruct> *iewQueue; 1591060SN/A 1601060SN/A /** Wire to write infromation heading to commit. */ 1611060SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 1621060SN/A 1631060SN/A //Will need internal queue to hold onto instructions coming from 1641060SN/A //the rename stage in case of a stall. 1651060SN/A /** Skid buffer between rename and IEW. */ 1661061SN/A std::queue<RenameStruct> skidBuffer; 1671060SN/A 1681681SN/A protected: 1691060SN/A /** Instruction queue. */ 1701060SN/A IQ instQueue; 1711060SN/A 1721061SN/A LDSTQ ldstQueue; 1731061SN/A 1741858SN/A#if !FULL_SYSTEM 1751681SN/A public: 1761681SN/A void lsqWriteback(); 1771681SN/A#endif 1781681SN/A 1791681SN/A private: 1801060SN/A /** Pointer to rename map. Might not want this stage to directly 1811060SN/A * access this though... 1821060SN/A */ 1831060SN/A RenameMap *renameMap; 1841060SN/A 1851060SN/A /** CPU interface. */ 1861060SN/A FullCPU *cpu; 1871060SN/A 1881060SN/A private: 1891060SN/A /** Commit to IEW delay, in ticks. */ 1901060SN/A unsigned commitToIEWDelay; 1911060SN/A 1921060SN/A /** Rename to IEW delay, in ticks. */ 1931060SN/A unsigned renameToIEWDelay; 1941060SN/A 1951060SN/A /** 1961060SN/A * Issue to execute delay, in ticks. What this actually represents is 1971060SN/A * the amount of time it takes for an instruction to wake up, be 1981060SN/A * scheduled, and sent to a FU for execution. 1991060SN/A */ 2001060SN/A unsigned issueToExecuteDelay; 2011060SN/A 2021060SN/A /** Width of issue's read path, in instructions. The read path is both 2031060SN/A * the skid buffer and the rename instruction queue. 2041060SN/A * Note to self: is this really different than issueWidth? 2051060SN/A */ 2061060SN/A unsigned issueReadWidth; 2071060SN/A 2081060SN/A /** Width of issue, in instructions. */ 2091060SN/A unsigned issueWidth; 2101060SN/A 2111060SN/A /** Width of execute, in instructions. Might make more sense to break 2121060SN/A * down into FP vs int. 2131060SN/A */ 2141060SN/A unsigned executeWidth; 2151060SN/A 2161060SN/A /** Number of cycles stage has been squashing. Used so that the stage 2171060SN/A * knows when it can start unblocking, which is when the previous stage 2181060SN/A * has received the stall signal and clears up its outputs. 2191060SN/A */ 2201060SN/A unsigned cyclesSquashing; 2211060SN/A 2221062SN/A Stats::Scalar<> iewIdleCycles; 2231062SN/A Stats::Scalar<> iewSquashCycles; 2241062SN/A Stats::Scalar<> iewBlockCycles; 2251062SN/A Stats::Scalar<> iewUnblockCycles; 2261062SN/A// Stats::Scalar<> iewWBInsts; 2271062SN/A Stats::Scalar<> iewDispatchedInsts; 2281062SN/A Stats::Scalar<> iewDispSquashedInsts; 2291062SN/A Stats::Scalar<> iewDispLoadInsts; 2301062SN/A Stats::Scalar<> iewDispStoreInsts; 2311062SN/A Stats::Scalar<> iewDispNonSpecInsts; 2321062SN/A Stats::Scalar<> iewIQFullEvents; 2331062SN/A Stats::Scalar<> iewExecutedInsts; 2341062SN/A Stats::Scalar<> iewExecLoadInsts; 2351062SN/A Stats::Scalar<> iewExecStoreInsts; 2361062SN/A Stats::Scalar<> iewExecSquashedInsts; 2371062SN/A Stats::Scalar<> memOrderViolationEvents; 2381062SN/A Stats::Scalar<> predictedTakenIncorrect; 2391060SN/A}; 2401060SN/A 2411755SN/A#endif // __CPU_O3_CPU_IEW_HH__ 242