iew.hh revision 2632
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 291061SN/A//Todo: Update with statuses. 301060SN/A//Need to handle delaying writes to the writeback bus if it's full at the 311689SN/A//given time. 321060SN/A 331755SN/A#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__ 341755SN/A#define __CPU_O3_CPU_SIMPLE_IEW_HH__ 351060SN/A 361060SN/A#include <queue> 371060SN/A 381858SN/A#include "config/full_system.hh" 391461SN/A#include "base/statistics.hh" 401060SN/A#include "base/timebuf.hh" 411717SN/A#include "cpu/o3/comm.hh" 421060SN/A 431681SN/Atemplate<class Impl> 441060SN/Aclass SimpleIEW 451060SN/A{ 461060SN/A private: 471060SN/A //Typedefs from Impl 481061SN/A typedef typename Impl::CPUPol CPUPol; 491061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 501060SN/A typedef typename Impl::FullCPU FullCPU; 511060SN/A typedef typename Impl::Params Params; 521060SN/A 531681SN/A typedef typename CPUPol::IQ IQ; 541061SN/A typedef typename CPUPol::RenameMap RenameMap; 551061SN/A typedef typename CPUPol::LDSTQ LDSTQ; 561060SN/A 571061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 581061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 591061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 601061SN/A typedef typename CPUPol::IssueStruct IssueStruct; 611060SN/A 621681SN/A friend class Impl::FullCPU; 631060SN/A public: 641060SN/A enum Status { 651060SN/A Running, 661060SN/A Blocked, 671060SN/A Idle, 681060SN/A Squashing, 691060SN/A Unblocking 701060SN/A }; 711060SN/A 721060SN/A private: 731060SN/A Status _status; 741060SN/A Status _issueStatus; 751060SN/A Status _exeStatus; 761060SN/A Status _wbStatus; 771060SN/A 781060SN/A public: 791681SN/A class WritebackEvent : public Event { 801681SN/A private: 811681SN/A DynInstPtr inst; 821681SN/A SimpleIEW<Impl> *iewStage; 831060SN/A 841681SN/A public: 851681SN/A WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew); 861062SN/A 871681SN/A virtual void process(); 881681SN/A virtual const char *description(); 891681SN/A }; 901060SN/A 911060SN/A public: 921060SN/A SimpleIEW(Params ¶ms); 931060SN/A 941062SN/A void regStats(); 951062SN/A 961060SN/A void setCPU(FullCPU *cpu_ptr); 971060SN/A 981060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 991060SN/A 1001060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1011060SN/A 1021060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1031060SN/A 1041060SN/A void setRenameMap(RenameMap *rm_ptr); 1051060SN/A 1061681SN/A void squash(); 1071681SN/A 1081681SN/A void squashDueToBranch(DynInstPtr &inst); 1091681SN/A 1101681SN/A void squashDueToMem(DynInstPtr &inst); 1111681SN/A 1121681SN/A void block(); 1131681SN/A 1141681SN/A inline void unblock(); 1151681SN/A 1161061SN/A void wakeDependents(DynInstPtr &inst); 1171060SN/A 1181681SN/A void instToCommit(DynInstPtr &inst); 1191060SN/A 1201060SN/A private: 1211062SN/A void dispatchInsts(); 1221062SN/A 1231062SN/A void executeInsts(); 1241062SN/A 1251681SN/A public: 1261681SN/A void tick(); 1271681SN/A 1281681SN/A void iew(); 1291681SN/A 1301060SN/A //Interfaces to objects inside and outside of IEW. 1311060SN/A /** Time buffer interface. */ 1321060SN/A TimeBuffer<TimeStruct> *timeBuffer; 1331060SN/A 1341060SN/A /** Wire to get commit's output from backwards time buffer. */ 1351060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 1361060SN/A 1371060SN/A /** Wire to write information heading to previous stages. */ 1381060SN/A typename TimeBuffer<TimeStruct>::wire toRename; 1391060SN/A 1401060SN/A /** Rename instruction queue interface. */ 1411060SN/A TimeBuffer<RenameStruct> *renameQueue; 1421060SN/A 1431060SN/A /** Wire to get rename's output from rename queue. */ 1441060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 1451060SN/A 1461060SN/A /** Issue stage queue. */ 1471060SN/A TimeBuffer<IssueStruct> issueToExecQueue; 1481060SN/A 1491060SN/A /** Wire to read information from the issue stage time queue. */ 1501060SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 1511060SN/A 1521060SN/A /** 1531060SN/A * IEW stage time buffer. Holds ROB indices of instructions that 1541060SN/A * can be marked as completed. 1551060SN/A */ 1561060SN/A TimeBuffer<IEWStruct> *iewQueue; 1571060SN/A 1581060SN/A /** Wire to write infromation heading to commit. */ 1591060SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 1601060SN/A 1611060SN/A //Will need internal queue to hold onto instructions coming from 1621060SN/A //the rename stage in case of a stall. 1631060SN/A /** Skid buffer between rename and IEW. */ 1641061SN/A std::queue<RenameStruct> skidBuffer; 1651060SN/A 1661681SN/A protected: 1671060SN/A /** Instruction queue. */ 1681060SN/A IQ instQueue; 1691060SN/A 1701061SN/A LDSTQ ldstQueue; 1711061SN/A 1721858SN/A#if !FULL_SYSTEM 1731681SN/A public: 1741681SN/A void lsqWriteback(); 1751681SN/A#endif 1761681SN/A 1771681SN/A private: 1781060SN/A /** Pointer to rename map. Might not want this stage to directly 1791060SN/A * access this though... 1801060SN/A */ 1811060SN/A RenameMap *renameMap; 1821060SN/A 1831060SN/A /** CPU interface. */ 1841060SN/A FullCPU *cpu; 1851060SN/A 1861060SN/A private: 1871060SN/A /** Commit to IEW delay, in ticks. */ 1881060SN/A unsigned commitToIEWDelay; 1891060SN/A 1901060SN/A /** Rename to IEW delay, in ticks. */ 1911060SN/A unsigned renameToIEWDelay; 1921060SN/A 1931060SN/A /** 1941060SN/A * Issue to execute delay, in ticks. What this actually represents is 1951060SN/A * the amount of time it takes for an instruction to wake up, be 1961060SN/A * scheduled, and sent to a FU for execution. 1971060SN/A */ 1981060SN/A unsigned issueToExecuteDelay; 1991060SN/A 2001060SN/A /** Width of issue's read path, in instructions. The read path is both 2011060SN/A * the skid buffer and the rename instruction queue. 2021060SN/A * Note to self: is this really different than issueWidth? 2031060SN/A */ 2041060SN/A unsigned issueReadWidth; 2051060SN/A 2061060SN/A /** Width of issue, in instructions. */ 2071060SN/A unsigned issueWidth; 2081060SN/A 2091060SN/A /** Width of execute, in instructions. Might make more sense to break 2101060SN/A * down into FP vs int. 2111060SN/A */ 2121060SN/A unsigned executeWidth; 2131060SN/A 2141060SN/A /** Number of cycles stage has been squashing. Used so that the stage 2151060SN/A * knows when it can start unblocking, which is when the previous stage 2161060SN/A * has received the stall signal and clears up its outputs. 2171060SN/A */ 2181060SN/A unsigned cyclesSquashing; 2191060SN/A 2201062SN/A Stats::Scalar<> iewIdleCycles; 2211062SN/A Stats::Scalar<> iewSquashCycles; 2221062SN/A Stats::Scalar<> iewBlockCycles; 2231062SN/A Stats::Scalar<> iewUnblockCycles; 2241062SN/A// Stats::Scalar<> iewWBInsts; 2251062SN/A Stats::Scalar<> iewDispatchedInsts; 2261062SN/A Stats::Scalar<> iewDispSquashedInsts; 2271062SN/A Stats::Scalar<> iewDispLoadInsts; 2281062SN/A Stats::Scalar<> iewDispStoreInsts; 2291062SN/A Stats::Scalar<> iewDispNonSpecInsts; 2301062SN/A Stats::Scalar<> iewIQFullEvents; 2311062SN/A Stats::Scalar<> iewExecutedInsts; 2321062SN/A Stats::Scalar<> iewExecLoadInsts; 2331062SN/A Stats::Scalar<> iewExecStoreInsts; 2341062SN/A Stats::Scalar<> iewExecSquashedInsts; 2351062SN/A Stats::Scalar<> memOrderViolationEvents; 2361062SN/A Stats::Scalar<> predictedTakenIncorrect; 2371060SN/A}; 2381060SN/A 2391755SN/A#endif // __CPU_O3_CPU_IEW_HH__ 240