iew.hh revision 2326
16892SBrad.Beckmann@amd.com/* 26892SBrad.Beckmann@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 36892SBrad.Beckmann@amd.com * All rights reserved. 46892SBrad.Beckmann@amd.com * 56892SBrad.Beckmann@amd.com * Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com * modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com * met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com * redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com * documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com * neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com * this software without specific prior written permission. 156892SBrad.Beckmann@amd.com * 166892SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com */ 286892SBrad.Beckmann@amd.com 296892SBrad.Beckmann@amd.com#ifndef __CPU_O3_IEW_HH__ 307564SBrad.Beckmann@amd.com#define __CPU_O3_IEW_HH__ 316892SBrad.Beckmann@amd.com 326892SBrad.Beckmann@amd.com#include <queue> 336892SBrad.Beckmann@amd.com 3412065Snikos.nikoleris@arm.com#include "base/statistics.hh" 3510529Smorr@cs.wisc.edu#include "base/timebuf.hh" 366892SBrad.Beckmann@amd.com#include "config/full_system.hh" 376892SBrad.Beckmann@amd.com#include "cpu/o3/comm.hh" 3811019Sjthestness@gmail.com#include "cpu/o3/scoreboard.hh" 396892SBrad.Beckmann@amd.com#include "cpu/o3/lsq.hh" 4011019Sjthestness@gmail.com 4111019Sjthestness@gmail.comclass FUPool; 426892SBrad.Beckmann@amd.com 4311019Sjthestness@gmail.com/** 446892SBrad.Beckmann@amd.com * DefaultIEW handles both single threaded and SMT IEW 4511019Sjthestness@gmail.com * (issue/execute/writeback). It handles the dispatching of 467564SBrad.Beckmann@amd.com * instructions to the LSQ/IQ as part of the issue stage, and has the 477538SBrad.Beckmann@amd.com * IQ try to issue instructions each cycle. The execute latency is 487561SBrad.Beckmann@amd.com * actually tied into the issue latency to allow the IQ to be able to 497561SBrad.Beckmann@amd.com * do back-to-back scheduling without having to speculatively schedule 507564SBrad.Beckmann@amd.com * instructions. This happens by having the IQ have access to the 517564SBrad.Beckmann@amd.com * functional units, and the IQ gets the execution latencies from the 527904SBrad.Beckmann@amd.com * FUs when it issues instructions. Instructions reach the execute 537904SBrad.Beckmann@amd.com * stage on the last cycle of their execution, which is when the IQ 547904SBrad.Beckmann@amd.com * knows to wake up any dependent instructions, allowing back to back 5510519Snilay@cs.wisc.edu * scheduling. The execute portion of IEW separates memory 568436SBrad.Beckmann@amd.com * instructions from non-memory instructions, either telling the LSQ 576892SBrad.Beckmann@amd.com * to execute the instruction, or executing the instruction directly. 586892SBrad.Beckmann@amd.com * The writeback portion of IEW completes the instructions by waking 596892SBrad.Beckmann@amd.com * up any dependents, and marking the register ready on the 606893SBrad.Beckmann@amd.com * scoreboard. 6110917Sbrandon.potter@amd.com */ 626892SBrad.Beckmann@amd.comtemplate<class Impl> 636892SBrad.Beckmann@amd.comclass DefaultIEW 646892SBrad.Beckmann@amd.com{ 656892SBrad.Beckmann@amd.com private: 666892SBrad.Beckmann@amd.com //Typedefs from Impl 676892SBrad.Beckmann@amd.com typedef typename Impl::CPUPol CPUPol; 686892SBrad.Beckmann@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 696892SBrad.Beckmann@amd.com typedef typename Impl::FullCPU FullCPU; 706892SBrad.Beckmann@amd.com typedef typename Impl::Params Params; 716892SBrad.Beckmann@amd.com 726892SBrad.Beckmann@amd.com typedef typename CPUPol::IQ IQ; 736892SBrad.Beckmann@amd.com typedef typename CPUPol::RenameMap RenameMap; 748180SBrad.Beckmann@amd.com typedef typename CPUPol::LSQ LSQ; 758257SBrad.Beckmann@amd.com 766893SBrad.Beckmann@amd.com typedef typename CPUPol::TimeStruct TimeStruct; 776892SBrad.Beckmann@amd.com typedef typename CPUPol::IEWStruct IEWStruct; 786892SBrad.Beckmann@amd.com typedef typename CPUPol::RenameStruct RenameStruct; 796892SBrad.Beckmann@amd.com typedef typename CPUPol::IssueStruct IssueStruct; 806903SBrad.Beckmann@amd.com 818180SBrad.Beckmann@amd.com friend class Impl::FullCPU; 828653Snilay@cs.wisc.edu friend class CPUPol::IQ; 838653Snilay@cs.wisc.edu 846903SBrad.Beckmann@amd.com public: 858180SBrad.Beckmann@amd.com /** Overall IEW stage status. Used to determine if the CPU can 868180SBrad.Beckmann@amd.com * deschedule itself due to a lack of activity. 876903SBrad.Beckmann@amd.com */ 888180SBrad.Beckmann@amd.com enum Status { 898180SBrad.Beckmann@amd.com Active, 906892SBrad.Beckmann@amd.com Inactive 9111266SBrad.Beckmann@amd.com }; 9211266SBrad.Beckmann@amd.com 9311266SBrad.Beckmann@amd.com /** Status for Issue, Execute, and Writeback stages. */ 9411266SBrad.Beckmann@amd.com enum StageStatus { 9511266SBrad.Beckmann@amd.com Running, 9611266SBrad.Beckmann@amd.com Blocked, 9711266SBrad.Beckmann@amd.com Idle, 9811266SBrad.Beckmann@amd.com StartSquash, 9911266SBrad.Beckmann@amd.com Squashing, 10011266SBrad.Beckmann@amd.com Unblocking 10111266SBrad.Beckmann@amd.com }; 1028322Ssteve.reinhardt@amd.com 10311266SBrad.Beckmann@amd.com private: 10411266SBrad.Beckmann@amd.com /** Overall stage status. */ 10511266SBrad.Beckmann@amd.com Status _status; 10611266SBrad.Beckmann@amd.com /** Dispatch status. */ 10711266SBrad.Beckmann@amd.com StageStatus dispatchStatus[Impl::MaxThreads]; 10811266SBrad.Beckmann@amd.com /** Execute status. */ 10911266SBrad.Beckmann@amd.com StageStatus exeStatus; 11011266SBrad.Beckmann@amd.com /** Writeback status. */ 11111266SBrad.Beckmann@amd.com StageStatus wbStatus; 11211266SBrad.Beckmann@amd.com 11311266SBrad.Beckmann@amd.com public: 11411266SBrad.Beckmann@amd.com /** LdWriteback event for a load completion. */ 1156893SBrad.Beckmann@amd.com class LdWritebackEvent : public Event { 1168322Ssteve.reinhardt@amd.com private: 1177566SBrad.Beckmann@amd.com /** Instruction that is writing back data to the register file. */ 1187566SBrad.Beckmann@amd.com DynInstPtr inst; 1197566SBrad.Beckmann@amd.com /** Pointer to IEW stage. */ 1209468Smalek.musleh@gmail.com DefaultIEW<Impl> *iewStage; 12110311Snilay@cs.wisc.edu 1226893SBrad.Beckmann@amd.com public: 1236893SBrad.Beckmann@amd.com /** Constructs a load writeback event. */ 1246893SBrad.Beckmann@amd.com LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew); 1256893SBrad.Beckmann@amd.com 12610311Snilay@cs.wisc.edu /** Processes writeback event. */ 12710311Snilay@cs.wisc.edu virtual void process(); 12811022Sjthestness@gmail.com /** Returns the description of the writeback event. */ 12911022Sjthestness@gmail.com virtual const char *description(); 13011022Sjthestness@gmail.com }; 13111022Sjthestness@gmail.com 13211022Sjthestness@gmail.com public: 13311022Sjthestness@gmail.com /** Constructs a DefaultIEW with the given parameters. */ 13411022Sjthestness@gmail.com DefaultIEW(Params *params); 13511022Sjthestness@gmail.com 13610311Snilay@cs.wisc.edu /** Returns the name of the DefaultIEW stage. */ 13710311Snilay@cs.wisc.edu std::string name() const; 13811022Sjthestness@gmail.com 13911022Sjthestness@gmail.com /** Registers statistics. */ 14011022Sjthestness@gmail.com void regStats(); 14111022Sjthestness@gmail.com 14211022Sjthestness@gmail.com /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 14310311Snilay@cs.wisc.edu void initStage(); 14410311Snilay@cs.wisc.edu 1457564SBrad.Beckmann@amd.com /** Sets CPU pointer for IEW, IQ, and LSQ. */ 1467564SBrad.Beckmann@amd.com void setCPU(FullCPU *cpu_ptr); 1477564SBrad.Beckmann@amd.com 1487564SBrad.Beckmann@amd.com /** Sets main time buffer used for backwards communication. */ 1497564SBrad.Beckmann@amd.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1507564SBrad.Beckmann@amd.com 1517564SBrad.Beckmann@amd.com /** Sets time buffer for getting instructions coming from rename. */ 1527564SBrad.Beckmann@amd.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1537564SBrad.Beckmann@amd.com 1547564SBrad.Beckmann@amd.com /** Sets time buffer to pass on instructions to commit. */ 1559318Spower.jg@gmail.com void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1567564SBrad.Beckmann@amd.com 1577564SBrad.Beckmann@amd.com /** Sets pointer to list of active threads. */ 1587564SBrad.Beckmann@amd.com void setActiveThreads(std::list<unsigned> *at_ptr); 1597564SBrad.Beckmann@amd.com 1607564SBrad.Beckmann@amd.com /** Sets pointer to the scoreboard. */ 1619318Spower.jg@gmail.com void setScoreboard(Scoreboard *sb_ptr); 1627564SBrad.Beckmann@amd.com 1637564SBrad.Beckmann@amd.com void switchOut(); 1649318Spower.jg@gmail.com 1657564SBrad.Beckmann@amd.com void doSwitchOut(); 1669318Spower.jg@gmail.com 1677564SBrad.Beckmann@amd.com void takeOverFrom(); 1689793Sakash.bagdia@arm.com 1699793Sakash.bagdia@arm.com bool isSwitchedOut() { return switchedOut; } 1709793Sakash.bagdia@arm.com 1719793Sakash.bagdia@arm.com /** Sets page table pointer within LSQ. */ 1729793Sakash.bagdia@arm.com// void setPageTable(PageTable *pt_ptr); 1739793Sakash.bagdia@arm.com 1749793Sakash.bagdia@arm.com /** Squashes instructions in IEW for a specific thread. */ 17512065Snikos.nikoleris@arm.com void squash(unsigned tid); 17612065Snikos.nikoleris@arm.com 17712065Snikos.nikoleris@arm.com /** Wakes all dependents of a completed instruction. */ 1787662SBrad.Beckmann@amd.com void wakeDependents(DynInstPtr &inst); 1797662SBrad.Beckmann@amd.com 1807564SBrad.Beckmann@amd.com /** Tells memory dependence unit that a memory instruction needs to be 18112065Snikos.nikoleris@arm.com * rescheduled. It will re-execute once replayMemInst() is called. 18212065Snikos.nikoleris@arm.com */ 18312065Snikos.nikoleris@arm.com void rescheduleMemInst(DynInstPtr &inst); 1846892SBrad.Beckmann@amd.com 1857566SBrad.Beckmann@amd.com /** Re-executes all rescheduled memory instructions. */ 1867566SBrad.Beckmann@amd.com void replayMemInst(DynInstPtr &inst); 1877566SBrad.Beckmann@amd.com 18810311Snilay@cs.wisc.edu /** Sends an instruction to commit through the time buffer. */ 18911022Sjthestness@gmail.com void instToCommit(DynInstPtr &inst); 19011022Sjthestness@gmail.com 19111022Sjthestness@gmail.com /** Inserts unused instructions of a thread into the skid buffer. */ 19211022Sjthestness@gmail.com void skidInsert(unsigned tid); 19311022Sjthestness@gmail.com 19411022Sjthestness@gmail.com /** Returns the max of the number of entries in all of the skid buffers. */ 19510311Snilay@cs.wisc.edu int skidCount(); 19611022Sjthestness@gmail.com 19711022Sjthestness@gmail.com /** Returns if all of the skid buffers are empty. */ 19811022Sjthestness@gmail.com bool skidsEmpty(); 19911022Sjthestness@gmail.com 20011022Sjthestness@gmail.com /** Updates overall IEW status based on all of the stages' statuses. */ 20111022Sjthestness@gmail.com void updateStatus(); 20211022Sjthestness@gmail.com 20311022Sjthestness@gmail.com /** Resets entries of the IQ and the LSQ. */ 20411022Sjthestness@gmail.com void resetEntries(); 20511022Sjthestness@gmail.com 20611022Sjthestness@gmail.com /** Tells the CPU to wakeup if it has descheduled itself due to no 20710311Snilay@cs.wisc.edu * activity. Used mainly by the LdWritebackEvent. 20810311Snilay@cs.wisc.edu */ 2098929Snilay@cs.wisc.edu void wakeCPU(); 2106893SBrad.Beckmann@amd.com 2116893SBrad.Beckmann@amd.com /** Reports to the CPU that there is activity this cycle. */ 2126893SBrad.Beckmann@amd.com void activityThisCycle(); 2136893SBrad.Beckmann@amd.com 21410519Snilay@cs.wisc.edu /** Tells CPU that the IEW stage is active and running. */ 21510519Snilay@cs.wisc.edu inline void activateStage(); 21610917Sbrandon.potter@amd.com 2176892SBrad.Beckmann@amd.com /** Tells CPU that the IEW stage is inactive and idle. */ 2188477Snilay@cs.wisc.edu inline void deactivateStage(); 2199841Snilay@cs.wisc.edu 2208477Snilay@cs.wisc.edu /** Returns if the LSQ has any stores to writeback. */ 2216892SBrad.Beckmann@amd.com bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2229468Smalek.musleh@gmail.com 2236892SBrad.Beckmann@amd.com private: 2246892SBrad.Beckmann@amd.com /** Sends commit proper information for a squash due to a branch 2257566SBrad.Beckmann@amd.com * mispredict. 2267566SBrad.Beckmann@amd.com */ 2277566SBrad.Beckmann@amd.com void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 22810311Snilay@cs.wisc.edu 22911022Sjthestness@gmail.com /** Sends commit proper information for a squash due to a memory order 23011022Sjthestness@gmail.com * violation. 23111022Sjthestness@gmail.com */ 23211022Sjthestness@gmail.com void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 23311022Sjthestness@gmail.com 23410311Snilay@cs.wisc.edu /** Sends commit proper information for a squash due to memory becoming 23510519Snilay@cs.wisc.edu * blocked (younger issued instructions must be retried). 23610311Snilay@cs.wisc.edu */ 23710519Snilay@cs.wisc.edu void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 23810519Snilay@cs.wisc.edu 23910519Snilay@cs.wisc.edu /** Sets Dispatch to blocked, and signals back to other stages to block. */ 24010519Snilay@cs.wisc.edu void block(unsigned thread_id); 24110519Snilay@cs.wisc.edu 24210519Snilay@cs.wisc.edu /** Unblocks Dispatch if the skid buffer is empty, and signals back to 24310519Snilay@cs.wisc.edu * other stages to unblock. 24410519Snilay@cs.wisc.edu */ 24510519Snilay@cs.wisc.edu void unblock(unsigned thread_id); 24610519Snilay@cs.wisc.edu 24711022Sjthestness@gmail.com /** Determines proper actions to take given Dispatch's status. */ 24811022Sjthestness@gmail.com void dispatch(unsigned tid); 24911022Sjthestness@gmail.com 25011022Sjthestness@gmail.com /** Dispatches instructions to IQ and LSQ. */ 25111022Sjthestness@gmail.com void dispatchInsts(unsigned tid); 25210519Snilay@cs.wisc.edu 25310519Snilay@cs.wisc.edu /** Executes instructions. In the case of memory operations, it informs the 25410519Snilay@cs.wisc.edu * LSQ to execute the instructions. Also handles any redirects that occur 25511065Snilay@cs.wisc.edu * due to the executed instructions. 2569100SBrad.Beckmann@amd.com */ 2579100SBrad.Beckmann@amd.com void executeInsts(); 258 259 /** Writebacks instructions. In our model, the instruction's execute() 260 * function atomically reads registers, executes, and writes registers. 261 * Thus this writeback only wakes up dependent instructions, and informs 262 * the scoreboard of registers becoming ready. 263 */ 264 void writebackInsts(); 265 266 /** Returns the number of valid, non-squashed instructions coming from 267 * rename to dispatch. 268 */ 269 unsigned validInstsFromRename(); 270 271 /** Reads the stall signals. */ 272 void readStallSignals(unsigned tid); 273 274 /** Checks if any of the stall conditions are currently true. */ 275 bool checkStall(unsigned tid); 276 277 /** Processes inputs and changes state accordingly. */ 278 void checkSignalsAndUpdate(unsigned tid); 279 280 /** Sorts instructions coming from rename into lists separated by thread. */ 281 void sortInsts(); 282 283 public: 284 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 285 * Writeback to run for one cycle. 286 */ 287 void tick(); 288 289 private: 290 void updateExeInstStats(DynInstPtr &inst); 291 292 /** Pointer to main time buffer used for backwards communication. */ 293 TimeBuffer<TimeStruct> *timeBuffer; 294 295 /** Wire to write information heading to previous stages. */ 296 typename TimeBuffer<TimeStruct>::wire toFetch; 297 298 /** Wire to get commit's output from backwards time buffer. */ 299 typename TimeBuffer<TimeStruct>::wire fromCommit; 300 301 /** Wire to write information heading to previous stages. */ 302 typename TimeBuffer<TimeStruct>::wire toRename; 303 304 /** Rename instruction queue interface. */ 305 TimeBuffer<RenameStruct> *renameQueue; 306 307 /** Wire to get rename's output from rename queue. */ 308 typename TimeBuffer<RenameStruct>::wire fromRename; 309 310 /** Issue stage queue. */ 311 TimeBuffer<IssueStruct> issueToExecQueue; 312 313 /** Wire to read information from the issue stage time queue. */ 314 typename TimeBuffer<IssueStruct>::wire fromIssue; 315 316 /** 317 * IEW stage time buffer. Holds ROB indices of instructions that 318 * can be marked as completed. 319 */ 320 TimeBuffer<IEWStruct> *iewQueue; 321 322 /** Wire to write infromation heading to commit. */ 323 typename TimeBuffer<IEWStruct>::wire toCommit; 324 325 /** Queue of all instructions coming from rename this cycle. */ 326 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 327 328 /** Skid buffer between rename and IEW. */ 329 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 330 331 /** Scoreboard pointer. */ 332 Scoreboard* scoreboard; 333 334 public: 335 /** Instruction queue. */ 336 IQ instQueue; 337 338 /** Load / store queue. */ 339 LSQ ldstQueue; 340 341 /** Pointer to the functional unit pool. */ 342 FUPool *fuPool; 343 344 private: 345 /** CPU pointer. */ 346 FullCPU *cpu; 347 348 /** Records if IEW has written to the time buffer this cycle, so that the 349 * CPU can deschedule itself if there is no activity. 350 */ 351 bool wroteToTimeBuffer; 352 353 /** Source of possible stalls. */ 354 struct Stalls { 355 bool commit; 356 }; 357 358 /** Stages that are telling IEW to stall. */ 359 Stalls stalls[Impl::MaxThreads]; 360 361 /** Debug function to print instructions that are issued this cycle. */ 362 void printAvailableInsts(); 363 364 public: 365 /** Records if the LSQ needs to be updated on the next cycle, so that 366 * IEW knows if there will be activity on the next cycle. 367 */ 368 bool updateLSQNextCycle; 369 370 private: 371 /** Records if there is a fetch redirect on this cycle for each thread. */ 372 bool fetchRedirect[Impl::MaxThreads]; 373 374 /** Used to track if all instructions have been dispatched this cycle. 375 * If they have not, then blocking must have occurred, and the instructions 376 * would already be added to the skid buffer. 377 * @todo: Fix this hack. 378 */ 379 bool dispatchedAllInsts; 380 381 /** Records if the queues have been changed (inserted or issued insts), 382 * so that IEW knows to broadcast the updated amount of free entries. 383 */ 384 bool updatedQueues; 385 386 /** Commit to IEW delay, in ticks. */ 387 unsigned commitToIEWDelay; 388 389 /** Rename to IEW delay, in ticks. */ 390 unsigned renameToIEWDelay; 391 392 /** 393 * Issue to execute delay, in ticks. What this actually represents is 394 * the amount of time it takes for an instruction to wake up, be 395 * scheduled, and sent to a FU for execution. 396 */ 397 unsigned issueToExecuteDelay; 398 399 /** Width of issue's read path, in instructions. The read path is both 400 * the skid buffer and the rename instruction queue. 401 * Note to self: is this really different than issueWidth? 402 */ 403 unsigned issueReadWidth; 404 405 /** Width of issue, in instructions. */ 406 unsigned issueWidth; 407 408 /** Width of execute, in instructions. Might make more sense to break 409 * down into FP vs int. 410 */ 411 unsigned executeWidth; 412 413 /** Index into queue of instructions being written back. */ 414 unsigned wbNumInst; 415 416 /** Cycle number within the queue of instructions being written back. 417 * Used in case there are too many instructions writing back at the current 418 * cycle and writesbacks need to be scheduled for the future. See comments 419 * in instToCommit(). 420 */ 421 unsigned wbCycle; 422 423 /** Number of active threads. */ 424 unsigned numThreads; 425 426 /** Pointer to list of active threads. */ 427 std::list<unsigned> *activeThreads; 428 429 /** Maximum size of the skid buffer. */ 430 unsigned skidBufferMax; 431 432 bool switchedOut; 433 434 /** Stat for total number of idle cycles. */ 435 Stats::Scalar<> iewIdleCycles; 436 /** Stat for total number of squashing cycles. */ 437 Stats::Scalar<> iewSquashCycles; 438 /** Stat for total number of blocking cycles. */ 439 Stats::Scalar<> iewBlockCycles; 440 /** Stat for total number of unblocking cycles. */ 441 Stats::Scalar<> iewUnblockCycles; 442 /** Stat for total number of instructions dispatched. */ 443 Stats::Scalar<> iewDispatchedInsts; 444 /** Stat for total number of squashed instructions dispatch skips. */ 445 Stats::Scalar<> iewDispSquashedInsts; 446 /** Stat for total number of dispatched load instructions. */ 447 Stats::Scalar<> iewDispLoadInsts; 448 /** Stat for total number of dispatched store instructions. */ 449 Stats::Scalar<> iewDispStoreInsts; 450 /** Stat for total number of dispatched non speculative instructions. */ 451 Stats::Scalar<> iewDispNonSpecInsts; 452 /** Stat for number of times the IQ becomes full. */ 453 Stats::Scalar<> iewIQFullEvents; 454 /** Stat for number of times the LSQ becomes full. */ 455 Stats::Scalar<> iewLSQFullEvents; 456 /** Stat for total number of executed instructions. */ 457 Stats::Scalar<> iewExecutedInsts; 458 /** Stat for total number of executed load instructions. */ 459 Stats::Vector<> iewExecLoadInsts; 460 /** Stat for total number of executed store instructions. */ 461// Stats::Scalar<> iewExecStoreInsts; 462 /** Stat for total number of squashed instructions skipped at execute. */ 463 Stats::Scalar<> iewExecSquashedInsts; 464 /** Stat for total number of memory ordering violation events. */ 465 Stats::Scalar<> memOrderViolationEvents; 466 /** Stat for total number of incorrect predicted taken branches. */ 467 Stats::Scalar<> predictedTakenIncorrect; 468 /** Stat for total number of incorrect predicted not taken branches. */ 469 Stats::Scalar<> predictedNotTakenIncorrect; 470 /** Stat for total number of mispredicted branches detected at execute. */ 471 Stats::Formula branchMispredicts; 472 473 Stats::Vector<> exeSwp; 474 Stats::Vector<> exeNop; 475 Stats::Vector<> exeRefs; 476 Stats::Vector<> exeBranches; 477 478// Stats::Vector<> issued_ops; 479/* 480 Stats::Vector<> stat_fu_busy; 481 Stats::Vector2d<> stat_fuBusy; 482 Stats::Vector<> dist_unissued; 483 Stats::Vector2d<> stat_issued_inst_type; 484*/ 485 Stats::Formula issueRate; 486 Stats::Formula iewExecStoreInsts; 487// Stats::Formula issue_op_rate; 488// Stats::Formula fu_busy_rate; 489 490 Stats::Vector<> iewInstsToCommit; 491 Stats::Vector<> writebackCount; 492 Stats::Vector<> producerInst; 493 Stats::Vector<> consumerInst; 494 Stats::Vector<> wbPenalized; 495 496 Stats::Formula wbRate; 497 Stats::Formula wbFanout; 498 Stats::Formula wbPenalizedRate; 499}; 500 501#endif // __CPU_O3_IEW_HH__ 502