iew.hh revision 2316
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_IEW_HH__ 30#define __CPU_O3_IEW_HH__ 31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36#include "config/full_system.hh" 37#include "cpu/o3/comm.hh" 38#include "cpu/o3/scoreboard.hh" 39#include "cpu/o3/lsq.hh" 40 41class FUPool; 42 43/** 44 * DefaultIEW handles both single threaded and SMT IEW(issue/execute/writeback). 45 * It handles the dispatching of instructions to the LSQ/IQ as part of the issue 46 * stage, and has the IQ try to issue instructions each cycle. The execute 47 * latency is actually tied into the issue latency to allow the IQ to be able to 48 * do back-to-back scheduling without having to speculatively schedule 49 * instructions. This happens by having the IQ have access to the functional 50 * units, and the IQ gets the execution latencies from the FUs when it issues 51 * instructions. Instructions reach the execute stage on the last cycle of 52 * their execution, which is when the IQ knows to wake up any dependent 53 * instructions, allowing back to back scheduling. The execute portion of IEW 54 * separates memory instructions from non-memory instructions, either telling 55 * the LSQ to execute the instruction, or executing the instruction directly. 56 * The writeback portion of IEW completes the instructions by waking up any 57 * dependents, and marking the register ready on the scoreboard. 58 */ 59template<class Impl> 60class DefaultIEW 61{ 62 private: 63 //Typedefs from Impl 64 typedef typename Impl::CPUPol CPUPol; 65 typedef typename Impl::DynInstPtr DynInstPtr; 66 typedef typename Impl::FullCPU FullCPU; 67 typedef typename Impl::Params Params; 68 69 typedef typename CPUPol::IQ IQ; 70 typedef typename CPUPol::RenameMap RenameMap; 71 typedef typename CPUPol::LSQ LSQ; 72 73 typedef typename CPUPol::TimeStruct TimeStruct; 74 typedef typename CPUPol::IEWStruct IEWStruct; 75 typedef typename CPUPol::RenameStruct RenameStruct; 76 typedef typename CPUPol::IssueStruct IssueStruct; 77 78 friend class Impl::FullCPU; 79 friend class CPUPol::IQ; 80 81 public: 82 /** Overall IEW stage status. Used to determine if the CPU can 83 * deschedule itself due to a lack of activity. 84 */ 85 enum Status { 86 Active, 87 Inactive 88 }; 89 90 /** Status for Issue, Execute, and Writeback stages. */ 91 enum StageStatus { 92 Running, 93 Blocked, 94 Idle, 95 StartSquash, 96 Squashing, 97 Unblocking 98 }; 99 100 private: 101 /** Overall stage status. */ 102 Status _status; 103 /** Dispatch status. */ 104 StageStatus dispatchStatus[Impl::MaxThreads]; 105 /** Execute status. */ 106 StageStatus exeStatus; 107 /** Writeback status. */ 108 StageStatus wbStatus; 109 110 public: 111 /** LdWriteback event for a load completion. */ 112 class LdWritebackEvent : public Event { 113 private: 114 /** Instruction that is writing back data to the register file. */ 115 DynInstPtr inst; 116 /** Pointer to IEW stage. */ 117 DefaultIEW<Impl> *iewStage; 118 119 public: 120 /** Constructs a load writeback event. */ 121 LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew); 122 123 /** Processes writeback event. */ 124 virtual void process(); 125 /** Returns the description of the writeback event. */ 126 virtual const char *description(); 127 }; 128 129 public: 130 /** Constructs a DefaultIEW with the given parameters. */ 131 DefaultIEW(Params *params); 132 133 /** Returns the name of the DefaultIEW stage. */ 134 std::string name() const; 135 136 /** Registers statistics. */ 137 void regStats(); 138 139 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 140 void initStage(); 141 142 /** Sets CPU pointer for IEW, IQ, and LSQ. */ 143 void setCPU(FullCPU *cpu_ptr); 144 145 /** Sets main time buffer used for backwards communication. */ 146 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 147 148 /** Sets time buffer for getting instructions coming from rename. */ 149 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 150 151 /** Sets time buffer to pass on instructions to commit. */ 152 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 153 154 /** Sets pointer to list of active threads. */ 155 void setActiveThreads(std::list<unsigned> *at_ptr); 156 157 /** Sets pointer to the scoreboard. */ 158 void setScoreboard(Scoreboard *sb_ptr); 159 160 void switchOut(); 161 162 void doSwitchOut(); 163 164 void takeOverFrom(); 165 166 bool isSwitchedOut() { return switchedOut; } 167 168 /** Sets page table pointer within LSQ. */ 169// void setPageTable(PageTable *pt_ptr); 170 171 /** Squashes instructions in IEW for a specific thread. */ 172 void squash(unsigned tid); 173 174 /** Wakes all dependents of a completed instruction. */ 175 void wakeDependents(DynInstPtr &inst); 176 177 /** Tells memory dependence unit that a memory instruction needs to be 178 * rescheduled. It will re-execute once replayMemInst() is called. 179 */ 180 void rescheduleMemInst(DynInstPtr &inst); 181 182 /** Re-executes all rescheduled memory instructions. */ 183 void replayMemInst(DynInstPtr &inst); 184 185 /** Sends an instruction to commit through the time buffer. */ 186 void instToCommit(DynInstPtr &inst); 187 188 /** Inserts unused instructions of a thread into the skid buffer. */ 189 void skidInsert(unsigned tid); 190 191 /** Returns the max of the number of entries in all of the skid buffers. */ 192 int skidCount(); 193 194 /** Returns if all of the skid buffers are empty. */ 195 bool skidsEmpty(); 196 197 /** Updates overall IEW status based on all of the stages' statuses. */ 198 void updateStatus(); 199 200 /** Resets entries of the IQ and the LSQ. */ 201 void resetEntries(); 202 203 /** Tells the CPU to wakeup if it has descheduled itself due to no 204 * activity. Used mainly by the LdWritebackEvent. 205 */ 206 void wakeCPU(); 207 208 /** Reports to the CPU that there is activity this cycle. */ 209 void activityThisCycle(); 210 211 /** Tells CPU that the IEW stage is active and running. */ 212 inline void activateStage(); 213 214 /** Tells CPU that the IEW stage is inactive and idle. */ 215 inline void deactivateStage(); 216 217//#if !FULL_SYSTEM 218 /** Returns if the LSQ has any stores to writeback. */ 219 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 220//#endif 221 222 private: 223 /** Sends commit proper information for a squash due to a branch 224 * mispredict. 225 */ 226 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 227 228 /** Sends commit proper information for a squash due to a memory order 229 * violation. 230 */ 231 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 232 233 /** Sends commit proper information for a squash due to memory becoming 234 * blocked (younger issued instructions must be retried). 235 */ 236 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 237 238 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 239 void block(unsigned thread_id); 240 241 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 242 * other stages to unblock. 243 */ 244 void unblock(unsigned thread_id); 245 246 /** Determines proper actions to take given Dispatch's status. */ 247 void dispatch(unsigned tid); 248 249 /** Dispatches instructions to IQ and LSQ. */ 250 void dispatchInsts(unsigned tid); 251 252 /** Executes instructions. In the case of memory operations, it informs the 253 * LSQ to execute the instructions. Also handles any redirects that occur 254 * due to the executed instructions. 255 */ 256 void executeInsts(); 257 258 /** Writebacks instructions. In our model, the instruction's execute() 259 * function atomically reads registers, executes, and writes registers. 260 * Thus this writeback only wakes up dependent instructions, and informs 261 * the scoreboard of registers becoming ready. 262 */ 263 void writebackInsts(); 264 265 /** Returns the number of valid, non-squashed instructions coming from 266 * rename to dispatch. 267 */ 268 unsigned validInstsFromRename(); 269 270 /** Reads the stall signals. */ 271 void readStallSignals(unsigned tid); 272 273 /** Checks if any of the stall conditions are currently true. */ 274 bool checkStall(unsigned tid); 275 276 /** Processes inputs and changes state accordingly. */ 277 void checkSignalsAndUpdate(unsigned tid); 278 279 /** Sorts instructions coming from rename into lists separated by thread. */ 280 void sortInsts(); 281 282 public: 283 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 284 * Writeback to run for one cycle. 285 */ 286 void tick(); 287 288 private: 289 void updateExeInstStats(DynInstPtr &inst); 290 291 /** Pointer to main time buffer used for backwards communication. */ 292 TimeBuffer<TimeStruct> *timeBuffer; 293 294 /** Wire to write information heading to previous stages. */ 295 typename TimeBuffer<TimeStruct>::wire toFetch; 296 297 /** Wire to get commit's output from backwards time buffer. */ 298 typename TimeBuffer<TimeStruct>::wire fromCommit; 299 300 /** Wire to write information heading to previous stages. */ 301 typename TimeBuffer<TimeStruct>::wire toRename; 302 303 /** Rename instruction queue interface. */ 304 TimeBuffer<RenameStruct> *renameQueue; 305 306 /** Wire to get rename's output from rename queue. */ 307 typename TimeBuffer<RenameStruct>::wire fromRename; 308 309 /** Issue stage queue. */ 310 TimeBuffer<IssueStruct> issueToExecQueue; 311 312 /** Wire to read information from the issue stage time queue. */ 313 typename TimeBuffer<IssueStruct>::wire fromIssue; 314 315 /** 316 * IEW stage time buffer. Holds ROB indices of instructions that 317 * can be marked as completed. 318 */ 319 TimeBuffer<IEWStruct> *iewQueue; 320 321 /** Wire to write infromation heading to commit. */ 322 typename TimeBuffer<IEWStruct>::wire toCommit; 323 324 /** Queue of all instructions coming from rename this cycle. */ 325 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 326 327 /** Skid buffer between rename and IEW. */ 328 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 329 330 /** Scoreboard pointer. */ 331 Scoreboard* scoreboard; 332 333 public: 334 /** Instruction queue. */ 335 IQ instQueue; 336 337 /** Load / store queue. */ 338 LSQ ldstQueue; 339 340 /** Pointer to the functional unit pool. */ 341 FUPool *fuPool; 342 343 private: 344 /** CPU pointer. */ 345 FullCPU *cpu; 346 347 /** Records if IEW has written to the time buffer this cycle, so that the 348 * CPU can deschedule itself if there is no activity. 349 */ 350 bool wroteToTimeBuffer; 351 352 /** Source of possible stalls. */ 353 struct Stalls { 354 bool commit; 355 }; 356 357 /** Stages that are telling IEW to stall. */ 358 Stalls stalls[Impl::MaxThreads]; 359 360 /** Debug function to print instructions that are issued this cycle. */ 361 void printAvailableInsts(); 362 363 public: 364 /** Records if the LSQ needs to be updated on the next cycle, so that 365 * IEW knows if there will be activity on the next cycle. 366 */ 367 bool updateLSQNextCycle; 368 369 private: 370 /** Records if there is a fetch redirect on this cycle for each thread. */ 371 bool fetchRedirect[Impl::MaxThreads]; 372 373 /** Used to track if all instructions have been dispatched this cycle. 374 * If they have not, then blocking must have occurred, and the instructions 375 * would already be added to the skid buffer. 376 * @todo: Fix this hack. 377 */ 378 bool dispatchedAllInsts; 379 380 /** Records if the queues have been changed (inserted or issued insts), 381 * so that IEW knows to broadcast the updated amount of free entries. 382 */ 383 bool updatedQueues; 384 385 /** Commit to IEW delay, in ticks. */ 386 unsigned commitToIEWDelay; 387 388 /** Rename to IEW delay, in ticks. */ 389 unsigned renameToIEWDelay; 390 391 /** 392 * Issue to execute delay, in ticks. What this actually represents is 393 * the amount of time it takes for an instruction to wake up, be 394 * scheduled, and sent to a FU for execution. 395 */ 396 unsigned issueToExecuteDelay; 397 398 /** Width of issue's read path, in instructions. The read path is both 399 * the skid buffer and the rename instruction queue. 400 * Note to self: is this really different than issueWidth? 401 */ 402 unsigned issueReadWidth; 403 404 /** Width of issue, in instructions. */ 405 unsigned issueWidth; 406 407 /** Width of execute, in instructions. Might make more sense to break 408 * down into FP vs int. 409 */ 410 unsigned executeWidth; 411 412 /** Index into queue of instructions being written back. */ 413 unsigned wbNumInst; 414 415 /** Cycle number within the queue of instructions being written back. 416 * Used in case there are too many instructions writing back at the current 417 * cycle and writesbacks need to be scheduled for the future. See comments 418 * in instToCommit(). 419 */ 420 unsigned wbCycle; 421 422 /** Number of active threads. */ 423 unsigned numThreads; 424 425 /** Pointer to list of active threads. */ 426 std::list<unsigned> *activeThreads; 427 428 /** Maximum size of the skid buffer. */ 429 unsigned skidBufferMax; 430 431 bool switchedOut; 432 433 /** Stat for total number of idle cycles. */ 434 Stats::Scalar<> iewIdleCycles; 435 /** Stat for total number of squashing cycles. */ 436 Stats::Scalar<> iewSquashCycles; 437 /** Stat for total number of blocking cycles. */ 438 Stats::Scalar<> iewBlockCycles; 439 /** Stat for total number of unblocking cycles. */ 440 Stats::Scalar<> iewUnblockCycles; 441 /** Stat for total number of instructions dispatched. */ 442 Stats::Scalar<> iewDispatchedInsts; 443 /** Stat for total number of squashed instructions dispatch skips. */ 444 Stats::Scalar<> iewDispSquashedInsts; 445 /** Stat for total number of dispatched load instructions. */ 446 Stats::Scalar<> iewDispLoadInsts; 447 /** Stat for total number of dispatched store instructions. */ 448 Stats::Scalar<> iewDispStoreInsts; 449 /** Stat for total number of dispatched non speculative instructions. */ 450 Stats::Scalar<> iewDispNonSpecInsts; 451 /** Stat for number of times the IQ becomes full. */ 452 Stats::Scalar<> iewIQFullEvents; 453 /** Stat for number of times the LSQ becomes full. */ 454 Stats::Scalar<> iewLSQFullEvents; 455 /** Stat for total number of executed instructions. */ 456 Stats::Scalar<> iewExecutedInsts; 457 /** Stat for total number of executed load instructions. */ 458 Stats::Vector<> iewExecLoadInsts; 459 /** Stat for total number of executed store instructions. */ 460// Stats::Scalar<> iewExecStoreInsts; 461 /** Stat for total number of squashed instructions skipped at execute. */ 462 Stats::Scalar<> iewExecSquashedInsts; 463 /** Stat for total number of memory ordering violation events. */ 464 Stats::Scalar<> memOrderViolationEvents; 465 /** Stat for total number of incorrect predicted taken branches. */ 466 Stats::Scalar<> predictedTakenIncorrect; 467 /** Stat for total number of incorrect predicted not taken branches. */ 468 Stats::Scalar<> predictedNotTakenIncorrect; 469 /** Stat for total number of mispredicted branches detected at execute. */ 470 Stats::Formula branchMispredicts; 471 472 Stats::Vector<> exe_swp; 473 Stats::Vector<> exe_nop; 474 Stats::Vector<> exe_refs; 475 Stats::Vector<> exe_branches; 476 477// Stats::Vector<> issued_ops; 478/* 479 Stats::Vector<> stat_fu_busy; 480 Stats::Vector2d<> stat_fuBusy; 481 Stats::Vector<> dist_unissued; 482 Stats::Vector2d<> stat_issued_inst_type; 483*/ 484 Stats::Formula issue_rate; 485 Stats::Formula iewExecStoreInsts; 486// Stats::Formula issue_op_rate; 487// Stats::Formula fu_busy_rate; 488 489 Stats::Vector<> iewInstsToCommit; 490 Stats::Vector<> writeback_count; 491 Stats::Vector<> producer_inst; 492 Stats::Vector<> consumer_inst; 493 Stats::Vector<> wb_penalized; 494 495 Stats::Formula wb_rate; 496 Stats::Formula wb_fanout; 497 Stats::Formula wb_penalized_rate; 498}; 499 500#endif // __CPU_O3_IEW_HH__ 501