iew.hh revision 2307
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_IEW_HH__ 30#define __CPU_O3_IEW_HH__ 31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36#include "config/full_system.hh" 37#include "cpu/o3/comm.hh" 38#include "cpu/o3/scoreboard.hh" 39#include "cpu/o3/lsq.hh" 40 41class FUPool; 42 43/** 44 * DefaultIEW handles both single threaded and SMT IEW(issue/execute/writeback). 45 * It handles the dispatching of instructions to the LSQ/IQ as part of the issue 46 * stage, and has the IQ try to issue instructions each cycle. The execute 47 * latency is actually tied into the issue latency to allow the IQ to be able to 48 * do back-to-back scheduling without having to speculatively schedule 49 * instructions. This happens by having the IQ have access to the functional 50 * units, and the IQ gets the execution latencies from the FUs when it issues 51 * instructions. Instructions reach the execute stage on the last cycle of 52 * their execution, which is when the IQ knows to wake up any dependent 53 * instructions, allowing back to back scheduling. The execute portion of IEW 54 * separates memory instructions from non-memory instructions, either telling 55 * the LSQ to execute the instruction, or executing the instruction directly. 56 * The writeback portion of IEW completes the instructions by waking up any 57 * dependents, and marking the register ready on the scoreboard. 58 */ 59template<class Impl> 60class DefaultIEW 61{ 62 private: 63 //Typedefs from Impl 64 typedef typename Impl::CPUPol CPUPol; 65 typedef typename Impl::DynInstPtr DynInstPtr; 66 typedef typename Impl::FullCPU FullCPU; 67 typedef typename Impl::Params Params; 68 69 typedef typename CPUPol::IQ IQ; 70 typedef typename CPUPol::RenameMap RenameMap; 71 typedef typename CPUPol::LSQ LSQ; 72 73 typedef typename CPUPol::TimeStruct TimeStruct; 74 typedef typename CPUPol::IEWStruct IEWStruct; 75 typedef typename CPUPol::RenameStruct RenameStruct; 76 typedef typename CPUPol::IssueStruct IssueStruct; 77 78 friend class Impl::FullCPU; 79 friend class CPUPol::IQ; 80 81 public: 82 /** Overall IEW stage status. Used to determine if the CPU can 83 * deschedule itself due to a lack of activity. 84 */ 85 enum Status { 86 Active, 87 Inactive 88 }; 89 90 /** Status for Issue, Execute, and Writeback stages. */ 91 enum StageStatus { 92 Running, 93 Blocked, 94 Idle, 95 StartSquash, 96 Squashing, 97 Unblocking 98 }; 99 100 private: 101 /** Overall stage status. */ 102 Status _status; 103 /** Dispatch status. */ 104 StageStatus dispatchStatus[Impl::MaxThreads]; 105 /** Execute status. */ 106 StageStatus exeStatus; 107 /** Writeback status. */ 108 StageStatus wbStatus; 109 110 public: 111 /** LdWriteback event for a load completion. */ 112 class LdWritebackEvent : public Event { 113 private: 114 /** Instruction that is writing back data to the register file. */ 115 DynInstPtr inst; 116 /** Pointer to IEW stage. */ 117 DefaultIEW<Impl> *iewStage; 118 119 public: 120 /** Constructs a load writeback event. */ 121 LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew); 122 123 /** Processes writeback event. */ 124 virtual void process(); 125 /** Returns the description of the writeback event. */ 126 virtual const char *description(); 127 }; 128 129 public: 130 /** Constructs a DefaultIEW with the given parameters. */ 131 DefaultIEW(Params *params); 132 133 /** Returns the name of the DefaultIEW stage. */ 134 std::string name() const; 135 136 /** Registers statistics. */ 137 void regStats(); 138 139 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 140 void initStage(); 141 142 /** Sets CPU pointer for IEW, IQ, and LSQ. */ 143 void setCPU(FullCPU *cpu_ptr); 144 145 /** Sets main time buffer used for backwards communication. */ 146 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 147 148 /** Sets time buffer for getting instructions coming from rename. */ 149 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 150 151 /** Sets time buffer to pass on instructions to commit. */ 152 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 153 154 /** Sets pointer to list of active threads. */ 155 void setActiveThreads(std::list<unsigned> *at_ptr); 156 157 /** Sets pointer to the scoreboard. */ 158 void setScoreboard(Scoreboard *sb_ptr); 159 160 void switchOut(); 161 162 void takeOverFrom(); 163 164 bool isSwitchedOut() { return switchedOut; } 165 166 /** Sets page table pointer within LSQ. */ 167// void setPageTable(PageTable *pt_ptr); 168 169 /** Squashes instructions in IEW for a specific thread. */ 170 void squash(unsigned tid); 171 172 /** Wakes all dependents of a completed instruction. */ 173 void wakeDependents(DynInstPtr &inst); 174 175 /** Tells memory dependence unit that a memory instruction needs to be 176 * rescheduled. It will re-execute once replayMemInst() is called. 177 */ 178 void rescheduleMemInst(DynInstPtr &inst); 179 180 /** Re-executes all rescheduled memory instructions. */ 181 void replayMemInst(DynInstPtr &inst); 182 183 /** Sends an instruction to commit through the time buffer. */ 184 void instToCommit(DynInstPtr &inst); 185 186 /** Inserts unused instructions of a thread into the skid buffer. */ 187 void skidInsert(unsigned tid); 188 189 /** Returns the max of the number of entries in all of the skid buffers. */ 190 int skidCount(); 191 192 /** Returns if all of the skid buffers are empty. */ 193 bool skidsEmpty(); 194 195 /** Updates overall IEW status based on all of the stages' statuses. */ 196 void updateStatus(); 197 198 /** Resets entries of the IQ and the LSQ. */ 199 void resetEntries(); 200 201 /** Tells the CPU to wakeup if it has descheduled itself due to no 202 * activity. Used mainly by the LdWritebackEvent. 203 */ 204 void wakeCPU(); 205 206 /** Reports to the CPU that there is activity this cycle. */ 207 void activityThisCycle(); 208 209 /** Tells CPU that the IEW stage is active and running. */ 210 inline void activateStage(); 211 212 /** Tells CPU that the IEW stage is inactive and idle. */ 213 inline void deactivateStage(); 214 215//#if !FULL_SYSTEM 216 /** Returns if the LSQ has any stores to writeback. */ 217 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 218//#endif 219 220 private: 221 /** Sends commit proper information for a squash due to a branch 222 * mispredict. 223 */ 224 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 225 226 /** Sends commit proper information for a squash due to a memory order 227 * violation. 228 */ 229 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 230 231 /** Sends commit proper information for a squash due to memory becoming 232 * blocked (younger issued instructions must be retried). 233 */ 234 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 235 236 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 237 void block(unsigned thread_id); 238 239 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 240 * other stages to unblock. 241 */ 242 void unblock(unsigned thread_id); 243 244 /** Determines proper actions to take given Dispatch's status. */ 245 void dispatch(unsigned tid); 246 247 /** Dispatches instructions to IQ and LSQ. */ 248 void dispatchInsts(unsigned tid); 249 250 /** Executes instructions. In the case of memory operations, it informs the 251 * LSQ to execute the instructions. Also handles any redirects that occur 252 * due to the executed instructions. 253 */ 254 void executeInsts(); 255 256 /** Writebacks instructions. In our model, the instruction's execute() 257 * function atomically reads registers, executes, and writes registers. 258 * Thus this writeback only wakes up dependent instructions, and informs 259 * the scoreboard of registers becoming ready. 260 */ 261 void writebackInsts(); 262 263 /** Returns the number of valid, non-squashed instructions coming from 264 * rename to dispatch. 265 */ 266 unsigned validInstsFromRename(); 267 268 /** Reads the stall signals. */ 269 void readStallSignals(unsigned tid); 270 271 /** Checks if any of the stall conditions are currently true. */ 272 bool checkStall(unsigned tid); 273 274 /** Processes inputs and changes state accordingly. */ 275 void checkSignalsAndUpdate(unsigned tid); 276 277 /** Sorts instructions coming from rename into lists separated by thread. */ 278 void sortInsts(); 279 280 public: 281 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 282 * Writeback to run for one cycle. 283 */ 284 void tick(); 285 286 private: 287 void updateExeInstStats(DynInstPtr &inst); 288 289 /** Pointer to main time buffer used for backwards communication. */ 290 TimeBuffer<TimeStruct> *timeBuffer; 291 292 /** Wire to write information heading to previous stages. */ 293 typename TimeBuffer<TimeStruct>::wire toFetch; 294 295 /** Wire to get commit's output from backwards time buffer. */ 296 typename TimeBuffer<TimeStruct>::wire fromCommit; 297 298 /** Wire to write information heading to previous stages. */ 299 typename TimeBuffer<TimeStruct>::wire toRename; 300 301 /** Rename instruction queue interface. */ 302 TimeBuffer<RenameStruct> *renameQueue; 303 304 /** Wire to get rename's output from rename queue. */ 305 typename TimeBuffer<RenameStruct>::wire fromRename; 306 307 /** Issue stage queue. */ 308 TimeBuffer<IssueStruct> issueToExecQueue; 309 310 /** Wire to read information from the issue stage time queue. */ 311 typename TimeBuffer<IssueStruct>::wire fromIssue; 312 313 /** 314 * IEW stage time buffer. Holds ROB indices of instructions that 315 * can be marked as completed. 316 */ 317 TimeBuffer<IEWStruct> *iewQueue; 318 319 /** Wire to write infromation heading to commit. */ 320 typename TimeBuffer<IEWStruct>::wire toCommit; 321 322 /** Queue of all instructions coming from rename this cycle. */ 323 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 324 325 /** Skid buffer between rename and IEW. */ 326 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 327 328 /** Scoreboard pointer. */ 329 Scoreboard* scoreboard; 330 331 public: 332 /** Instruction queue. */ 333 IQ instQueue; 334 335 /** Load / store queue. */ 336 LSQ ldstQueue; 337 338 /** Pointer to the functional unit pool. */ 339 FUPool *fuPool; 340 341 private: 342 /** CPU pointer. */ 343 FullCPU *cpu; 344 345 /** Records if IEW has written to the time buffer this cycle, so that the 346 * CPU can deschedule itself if there is no activity. 347 */ 348 bool wroteToTimeBuffer; 349 350 /** Source of possible stalls. */ 351 struct Stalls { 352 bool commit; 353 }; 354 355 /** Stages that are telling IEW to stall. */ 356 Stalls stalls[Impl::MaxThreads]; 357 358 /** Debug function to print instructions that are issued this cycle. */ 359 void printAvailableInsts(); 360 361 public: 362 /** Records if the LSQ needs to be updated on the next cycle, so that 363 * IEW knows if there will be activity on the next cycle. 364 */ 365 bool updateLSQNextCycle; 366 367 private: 368 /** Records if there is a fetch redirect on this cycle for each thread. */ 369 bool fetchRedirect[Impl::MaxThreads]; 370 371 /** Used to track if all instructions have been dispatched this cycle. 372 * If they have not, then blocking must have occurred, and the instructions 373 * would already be added to the skid buffer. 374 * @todo: Fix this hack. 375 */ 376 bool dispatchedAllInsts; 377 378 /** Records if the queues have been changed (inserted or issued insts), 379 * so that IEW knows to broadcast the updated amount of free entries. 380 */ 381 bool updatedQueues; 382 383 /** Commit to IEW delay, in ticks. */ 384 unsigned commitToIEWDelay; 385 386 /** Rename to IEW delay, in ticks. */ 387 unsigned renameToIEWDelay; 388 389 /** 390 * Issue to execute delay, in ticks. What this actually represents is 391 * the amount of time it takes for an instruction to wake up, be 392 * scheduled, and sent to a FU for execution. 393 */ 394 unsigned issueToExecuteDelay; 395 396 /** Width of issue's read path, in instructions. The read path is both 397 * the skid buffer and the rename instruction queue. 398 * Note to self: is this really different than issueWidth? 399 */ 400 unsigned issueReadWidth; 401 402 /** Width of issue, in instructions. */ 403 unsigned issueWidth; 404 405 /** Width of execute, in instructions. Might make more sense to break 406 * down into FP vs int. 407 */ 408 unsigned executeWidth; 409 410 /** Index into queue of instructions being written back. */ 411 unsigned wbNumInst; 412 413 /** Cycle number within the queue of instructions being written back. 414 * Used in case there are too many instructions writing back at the current 415 * cycle and writesbacks need to be scheduled for the future. See comments 416 * in instToCommit(). 417 */ 418 unsigned wbCycle; 419 420 /** Number of active threads. */ 421 unsigned numThreads; 422 423 /** Pointer to list of active threads. */ 424 std::list<unsigned> *activeThreads; 425 426 /** Maximum size of the skid buffer. */ 427 unsigned skidBufferMax; 428 429 bool switchedOut; 430 431 /** Stat for total number of idle cycles. */ 432 Stats::Scalar<> iewIdleCycles; 433 /** Stat for total number of squashing cycles. */ 434 Stats::Scalar<> iewSquashCycles; 435 /** Stat for total number of blocking cycles. */ 436 Stats::Scalar<> iewBlockCycles; 437 /** Stat for total number of unblocking cycles. */ 438 Stats::Scalar<> iewUnblockCycles; 439 /** Stat for total number of instructions dispatched. */ 440 Stats::Scalar<> iewDispatchedInsts; 441 /** Stat for total number of squashed instructions dispatch skips. */ 442 Stats::Scalar<> iewDispSquashedInsts; 443 /** Stat for total number of dispatched load instructions. */ 444 Stats::Scalar<> iewDispLoadInsts; 445 /** Stat for total number of dispatched store instructions. */ 446 Stats::Scalar<> iewDispStoreInsts; 447 /** Stat for total number of dispatched non speculative instructions. */ 448 Stats::Scalar<> iewDispNonSpecInsts; 449 /** Stat for number of times the IQ becomes full. */ 450 Stats::Scalar<> iewIQFullEvents; 451 /** Stat for number of times the LSQ becomes full. */ 452 Stats::Scalar<> iewLSQFullEvents; 453 /** Stat for total number of executed instructions. */ 454 Stats::Scalar<> iewExecutedInsts; 455 /** Stat for total number of executed load instructions. */ 456 Stats::Vector<> iewExecLoadInsts; 457 /** Stat for total number of executed store instructions. */ 458// Stats::Scalar<> iewExecStoreInsts; 459 /** Stat for total number of squashed instructions skipped at execute. */ 460 Stats::Scalar<> iewExecSquashedInsts; 461 /** Stat for total number of memory ordering violation events. */ 462 Stats::Scalar<> memOrderViolationEvents; 463 /** Stat for total number of incorrect predicted taken branches. */ 464 Stats::Scalar<> predictedTakenIncorrect; 465 /** Stat for total number of incorrect predicted not taken branches. */ 466 Stats::Scalar<> predictedNotTakenIncorrect; 467 /** Stat for total number of mispredicted branches detected at execute. */ 468 Stats::Formula branchMispredicts; 469 470 Stats::Vector<> exe_swp; 471 Stats::Vector<> exe_nop; 472 Stats::Vector<> exe_refs; 473 Stats::Vector<> exe_branches; 474 475// Stats::Vector<> issued_ops; 476/* 477 Stats::Vector<> stat_fu_busy; 478 Stats::Vector2d<> stat_fuBusy; 479 Stats::Vector<> dist_unissued; 480 Stats::Vector2d<> stat_issued_inst_type; 481*/ 482 Stats::Formula issue_rate; 483 Stats::Formula iewExecStoreInsts; 484// Stats::Formula issue_op_rate; 485// Stats::Formula fu_busy_rate; 486 487 Stats::Vector<> iewInstsToCommit; 488 Stats::Vector<> writeback_count; 489 Stats::Vector<> producer_inst; 490 Stats::Vector<> consumer_inst; 491 Stats::Vector<> wb_penalized; 492 493 Stats::Formula wb_rate; 494 Stats::Formula wb_fanout; 495 Stats::Formula wb_penalized_rate; 496}; 497 498#endif // __CPU_O3_IEW_HH__ 499